PCI Enhancements: AGP

 AGP – Advanced Graphics Port

 Called a port, not a bus because it only connects 2
devices

References:
Computer Architecture and Organization Retrieved at,
https://nitsri.ac.in/Department/Electronics%20&%20Communication

COM 4: COMPUTER
%20Engineering/Chapter1-Introduction.pdf

ORGANI ZATION AND

ARCHITECTURE

Prepared by:

MARRYLYN A. ARCIGA
ECT Instructor
UNIT I. INTRODUCTION  public domain, initially developed by Intel to
support Pentium-based systems
1.1 COMPUTER ARCHITECTURE AND ORGANIZATION
 supports a variety of microprocessor-based
Computer Architecture refers to those attributes of a system that configurations, including multiple processors
have a direct impact on the logical execution of a program.  uses synchronous timing and centralized
arbitration
Examples: PCI Bus Lines
o the instruction set
 Systems lines
o the number of bits used to represent various data types
 Including clock and reset
o I/O mechanisms
 Address & Data
o memory addressing techniques
 32 time mux lines for address/data
Computer Organization refers to the operational units and their  Interrupt & validate lines
interconnections that realize the architectural specifications.  Interface Control
 Arbitration
Examples are things that are transparent to the programmer:
 Not shared
o control signals
 Direct connection to PCI bus arbiter
o interfaces between computer and peripherals
 Error lines
o the memory technology being used
 Interrupt lines
o Not shared
 So, for example, the fact that a multiply instruction is available
 Cache support
is a computer architecture issue. How that multiply is
 64-bit Bus Extension
implemented is a computer organization issue.
o Additional 32 lines
Architecture is those attributes visible to the programmer o Time multiplexed
o Instruction set, number of bits used for data representation, I/O o 2 lines to enable devices to agree to use 64-bit
mechanisms, addressing techniques. transfer
o e.g. Is there a multiply instruction?  JTAG/Boundary Scan
o For testing procedures
Organization is how features are implemented
o Control signals, interfaces, memory technology. PCI Commands
o e.g. Is there a hardware multiply unit or is it done by repeated  Transaction between initiator (master) and target
addition?  Master claims bus
 All Intel x86 family share the same basic architecture  Determine type of transaction
 The IBM System/370 family share the same basic architecture  e.g. I/O read/write
 This gives code compatibility  Address phase
At least backwards  One or more data phases
 o Usually sync on leading edge  Organization differs between different versions
o Usually a single cycle for an event
1.2 STRUCTURE AND FUNCTION
 Bus Width Structure is the way in which components relate to each other
 Address: Width of address bus has an impact on system Function is the operation of individual components as part of the
capacity i.e. wider bus means greater the range of locations structure
that can be transferred.
 Data: width of data bus has an impact on system All computer functions are:
performance i.e. wider bus means number of bits  Data processing: Computer must be able to process data
transferred at one time. which may take a wide variety of forms and the range of
processing.
 Data Transfer Type  Data storage: Computer stores data either temporarily or
 Read permanently.
 Write  Data movement: Computer must be able to move data
 Read-modify-write between itself and the outside world.
 Read-after-write  Control: There must be a control of the above three functions.
 Block
Four main structural components:
1.7 PERIPHERAL COMPONENT INTERCONNECT (PCI)  Central processing unit (CPU)
 PCI is a popular high bandwidth, processor independent bus  Main memory
that can function as mezzanine or peripheral bus.  I/O
 PCI delivers better system performance for high speed I/O  System interconnections
subsystems (graphic display adapters, network interface CPU structural components:
controllers, disk controllers etc.)  Control unit
 PCI is designed to support a variety of microprocessor based  Arithmetic and logic unit (ALU)
configurations including both single and multiple processor  Registers
system.  CPU interconnections
 It makes use of synchronous timing and centralized arbitration
scheme. 1.3 COMPUTER COMPONENTS
 PCI may be configured as a 32 or 64-bit bus. 1. The Control Unit (CU) and the Arithmetic and Logic Unit
 Current Standard (ALU) constitute the Central Processing Unit (CPU)
 up to 64 data lines at 33Mhz 2. Data and instructions need to get into the system and results
 requires few chips to implement supports other need to get out
buses attached to PCI bus o Input/output (I/O module)
3. Temporary storage of code and results is needed
 o Main memory (RAM) o Data transfer between CPU and I/O module
4. Program Concept  Data processing
o Hardwired systems are inflexible o Some arithmetic or logical operation on data
o General purpose hardware can do different tasks, given o buffers data transfers between system bus and I/O
correct control signals controllers on expansion bus
o Instead of re-wiring, supply a new set of control signals o insulates memory-to-processor traffic from I/O traffic

1.4 COMPUTER FUNCTION Elements of Bus Design

The basic function p rformed by a computer is execution of a program, BUS TYPES
which consists of a set of instructions stored in memory.  Dedicated
 Two steps of Instructions Cycle:  Separate data & address lines
o Fetch  Multiplexed
o Execute  Shared lines
 Address valid or data valid control line
 Advantage - fewer lines
 Disadvantages
 More complex control
 Ultimate performance
 Bus Arbitration
 More than one module controlling the bus
Fig 1. Basic Instruction Cycle o e.g. CPU and DMA controller
Fetch Cycle  Only one module may control bus at one time
 Program Counter (PC) holds address of next instruction to  Arbitration may be centralized or distributed
fetch  Centralized Arbitration
 Processor fetches instruction from memory location pointed to  Single hardware device controlling bus access
by PC o Bus Controller
 Increment PC o Arbiter
o Unless told otherwise  May be part of CPU or separate
 Instruction loaded into Instruction Register (IR)  Distributed Arbitration
 Each module may claim the bus
Execute Cycle  Control logic on all modules
Processor interprets instruction and performs required actions, such as:  Timing
 Processor – memory  Co-ordination of events on bus
o data transfer between CPU and main memory  Synchronous
 Processor - I/O o Events determined by clock signals
 o Control Bus includes clock line o Use of a cache structure insulates CPU from frequent accesses
o A single 1-0 is a bus cycle to main memory
All devices can read clock line o Main memory can be moved off local bus to a system bus
o Expansion bus interface
Address Bus
 Identify the source or destination of data
 e.g. CPU needs to read an instruction (data) from a given  Control
location in memory o Alteration of sequence of operations
 Bus width determines maximum memory capacity of system o e.g. jump
o e.g. 8080 has 16 bit address bus giving 64k address space  Combination of above

Control Bus 1.5 INTERCONNECTION STRUCTURES

 Control and timing information The collection of paths connecting the various modules is called the
 Memory read interconnecting structure.
 Memory write  All the units must be connected
 I/O read  Different type of connection for different type of unit
 I/O write o Memory
 Transfer ACK o Input/Output
 Bus request o CPU
 Bus grant Memory Connection
 Interrupt request  Receives and sends data
 Interrupt ACK
 Receives addresses (of locations)
 Clock
 Receives control signals
 Reset
o Read
o Write
Multiple Bus Hierarchies
o Timing
 A great number of devices on a bus will cause performance to
suffer
o Propagation delay - the time it takes for devices to coordinate
the use of the bus
o The bus may become a bottleneck as the aggregate data
transfer demand approaches the capacity of the bus (in
available transfer cycles/second)
 Traditional Hierarchical Bus Architecture
 o e.g. port number to identify peripheral
 Send interrupt signals (control)

Fig 3. I/O Module

CPU Connection
 Reads instruction and data
 Writes out data (after processing)
 Sends control signals to other units
Fig 2. Memory Module  Receives (& acts on) interrupts

I/O Connection
 Similar to memory from computer’s viewpoint
 Output
o Receive data from computer

o Send data to peripheral

 Input
o Receive data from peripheral Fig 4. CPU Module

o Send data to computer

1.6 BUS INTERCONNECTION
 Receive control signals from computer
 A bus is a communication pathway connecting two or more
 Send control signals to peripherals
devices
o e.g. spin disk
 Usually broadcast (all components see signal)
 Receive
 Often grouped
addresses
o A number of channels in one bus
from
o e.g. 32 bit data bus is 32 separate single bit channels
computer
 Power lines may not be shown
  There are a number of possible interconnection systems
 Single and multiple BUS structures are most common
 e.g. Control/Address/Data bus (PC)
 e.g. Unibus (DEC-PDP)
 Lots of devices on one bus leads to:
o Propagation delays
o Long data paths mean that co-ordination of bus use can
adversely affect performance
o If aggregate data transfer approaches bus capacity
 Most systems use multiple buses to overcome these problems

Fig 5. Bus Interconnection Scheme

Data Bus
 Carries data
o Remember that there is no difference between “data” and
“instruction” at this level
 Width is a key determinant of performance
o 8, 16, 32, 64 bit