SIFANG CSC-326EB V2.00 Transformer Protection IED Manual 2020-09

CSC-326
Transformer Protection IED

Manual
CSC-326 系列数字式变压器保护装置
说明书
(英文)
编制:杨帆
校核:秦嗣友
标准化审查:刘晓丰
审定:张恒祥
版本号: V2.00
文件代号: 0000189070
出版日期: 2020.09
Version: V2.00
Doc. Code: 0000189070
Issued Date: 2020.09
Copyright owner: Beijing Sifang Automation Co., Ltd
Note: the company keeps the right to perfect the instruction. If equipment
does not agree with the instruction at anywhere, please contact our
company in time. We will provide you with corresponding service.
®
is registered trademark of Beijing Sifang Automation Co., Ltd.
We reserve all rights to this document, even in the event that a patent is issued and a
different commercial proprietary right is registered. Improper use, in particular reproduction
and dissemination to third parties, is not permitted.
This document has been carefully checked. If the user nevertheless detects any errors, he
is asked to notify us as soon as possible.
The data contained in this manual is intended solely for the product description and is not to
be deemed to be a statement of guaranteed properties. In the interests of our customers,
we constantly seek to ensure that our products are developed to the latest technological
standards as a result; it is possible that there may be some differences between the
hardware/software product and this information product.
Manufacturer: Beijing Sifang Automation Co., Ltd.

Email: [email protected]
Website: http://www.sf-auto.com
Add: No.9, Shangdi 4th Street, Haidian District, Beijing, P.R.C.100085
Preface
Purpose of this manual
This manual describes the functions, operation, installation, and placing
into service of IED CSC-326. In particular, one will find:
 Information on how to configure the IED scope and a description of the
IED functions and setting options;
 Instructions for mounting and commissioning;
 Compilation of the technical specifications;
 A compilation of the most significant data for experienced users in the
Appendix.
Target audience
This manual mainly face to installation engineer, commissioning engineer
and operation engineer with perfessional electric and electrical knowledge,
rich experience in protection function, using protection IED, test IED,
responsible for the installation, commissioning, maintenance and taking
the protection IED in and out of normal service.
Applicability of this manual

This manual is valid for V1.02 CSC-326 transformer protection IED.
Note: the password for this device is 8888.
Technical support
In case of further questions concerning the CSC family, please contact
Sifang company or your local Sifang representative.
We provide the users with protection function and test training, the
warranty period is 5 years.
Safety information
Strictly follow the company and international safety regulations.

Working in a high voltage environment requires serious approch
to aviod human injuries and damage to equipment
Do not touch any circuitry during operation. Potentially lethal

voltages and currents are present
Avoid to touching the circuitry when covers are removed. The IED
contains electirc circuits which can be damaged if exposed to
static electricity. Lethal high voltage circuits are also exposed
when covers are removed
I
Using the isolated test pins when measuring signals in open
circuitry. Potentially lethal voltages and currents are present
Never connect or disconnect wire and/or linker to or from IED

during normal operation. Dangerous voltages and currents are
present. Operation may be interrupted and IED and measuring
circuitry may be damaged
Always connect the IED to protective earth regardless of the

operating conditions. Operating the IED without proper earthing
may damage both IED and measuring circuitry and may cause
injuries in case of an accident
Do not disconnect the secondary connection of current

transformer without short-circuiting the transformer’s secondary
winding. Operating a current transformer with the secondary
winding open will cause a high voltage that may damage the
transformer and may cause injuries to humans
Do not remove the screw from a powered IED or from an IED

connected to power circuitry. Potentially lethal voltages and
currents are present
Using the certified conductive bags to transport PCBs (modules).

Handling modules with a conductive wrist strap connected to
protective earth and on an antistatic surface. Electrostatic
discharge may cause damage to the module due to electronic
circuits are sensitive to this phenomenon
Do not connect live wires to the IED, internal circuitry may be

damaged
When replacing modules using a conductive wrist strap

connected to protective earth. Electrostatic discharge may
damage the modules and IED circuitry
When installing and commissioning, take care to avoid electrical

shock if accessing wiring and connection IEDs
Changing the setting value group will inevitably change the IEDs
operation. Be careful and check regulations before making the
change
II
Contents
Chapter 1 Introduction.............................................................................................................1
1 IED overview..................................................................................................................2
2 IED characteristic ...........................................................................................................2
3 Basic function.................................................................................................................3
3.1 Protection function ..................................................................................................3
3.2 Control function ......................................................................................................7
3.3 Measurement function ............................................................................................7
3.4 Monitoring function .................................................................................................8
3.5 Communication mode .............................................................................................8
Chapter 2 Common functions ..................................................................................................9
1 Event record and analysis ............................................................................................ 10
1.1 Overview .............................................................................................................. 10
1.2 Fault record .......................................................................................................... 10
1.3 Waveform record .................................................................................................. 10
1.4 Sequence of event (SOE) ..................................................................................... 10
1.5 Operation record ................................................................................................... 11
2 Diagnostic function ....................................................................................................... 11
2.1 Overview .............................................................................................................. 11
2.2 Diagnostic principle............................................................................................... 11
3 Time synchronization function ...................................................................................... 11
3.1 Overview .............................................................................................................. 11
3.2 Synchronization principle ...................................................................................... 12
3.3 IRIG-B code synchronization mode ....................................................................... 12
3.4 PPS synchronization mode ................................................................................... 12
3.5 SNTP synchronization mode ................................................................................. 13
3.6 1588 synchronization mode .................................................................................. 13
4 Authorization ................................................................................................................ 13
Chapter 3 Fault phase selection component ...................................................................... 15
1 Overview...................................................................................................................... 16
2 Function module description......................................................................................... 16
3 Detailed description...................................................................................................... 17
3.1 Protection principle ............................................................................................... 17
3.1.1 Steady state component phase selector ............................................................ 17
3.1.2 Undervoltage phase selection component ......................................................... 17
Chapter 4 Basic protection component .............................................................................. 19
1 Startup component ....................................................................................................... 20
1.1 Overview .............................................................................................................. 20
1.2 Current sudden-change startup component........................................................... 20
1.3 Differential current startup component ................................................................... 20
2 Report .......................................................................................................................... 20
Chapter 5 Differential protection (87T) ............................................................................... 21
1 Overview...................................................................................................................... 22
3.1.1 Differential and restraint current calculation ....................................................... 25
3.1.2 Automatic Ratio compensation .......................................................................... 26
3.1.3 Automatic Vector group and zero sequence current compensation .................... 29
3.1.4 Instantaneous differential protection characteristic ............................................. 34
3.1.5 Treble slope percent differential protection characteristic ................................... 34
3.1.6 CT failure supervision........................................................................................ 40
3.1.7 CT Saturation supervision ................................................................................. 41
3.1.8 Differential current supervision .......................................................................... 42
3.1.9 Differential protection of variables...................................................................... 43
3.2 Setting list ............................................................................................................. 44
3.3 Report list ............................................................................................................. 45
3.4 Technical parameter.............................................................................................. 46
Chapter 6 Restricted earth fault protection (87REF) ........................................................... 47
1 Overview...................................................................................................................... 48
III
2Function module description......................................................................................... 48
3Detailed description...................................................................................................... 48
3.1.1 Differential and restraint current calculation ....................................................... 51
3.1.2 Automatic Ratio compensation .......................................................................... 53
3.1.3 Positive sequence current blocking ................................................................... 54
3.1.4 Restricted earth fault current alarm .................................................................... 54
3.2 Setting list ............................................................................................................. 55
3.3 Report list ............................................................................................................. 56
Chapter 7 Impedance protection (21)................................................................................. 59
1 Overview...................................................................................................................... 60
3.2 Logic diagram ....................................................................................................... 63
3.3 Setting list ............................................................................................................. 64
3.4 Report list ............................................................................................................. 69
Chapter 8 Interturn protection (16) ..................................................................................... 71
1 Overview...................................................................................................................... 72
3.2 Logic diagram ....................................................................................................... 74
3.3 Setting list ............................................................................................................. 74
3.4 Report list ............................................................................................................. 74
Chapter 9 Overcurrent Protection (50, 51, 67) ................................................................... 75
1 Overview...................................................................................................................... 76
3.1.1 Inrush blocking components .............................................................................. 78
3.1.2 Compound voltage blocking unit ........................................................................ 79
3.1.3 Directional component....................................................................................... 81
3.1.4 Definite time ...................................................................................................... 82
3.1.5 Inverse time ...................................................................................................... 83
3.1.6 Trip characteristic .............................................................................................. 84
3.1.7 Logic diagram ................................................................................................... 84
3.2 Setting list ............................................................................................................. 85
3.3 Report list ........................................................................................................... 100
3.4 Technical parameter............................................................................................ 103
Chapter 10 Emergency overcurrent protection(50,51) ........................................................ 105
1 Overview.................................................................................................................... 106
2 Function module description....................................................................................... 106
3 Detailed description.................................................................................................... 107
3.1 Protection principle ............................................................................................. 107
3.1.1 Inrush blocking components ............................................................................ 107
3.1.2 Definite time .................................................................................................... 108
3.1.3 Inverse time .................................................................................................... 108
3.1.4 Trip characteristic ............................................................................................ 109
3.1.5 Logic diagram ................................................................................................. 110
3.2 Setting list ........................................................................................................... 110
3.3 Report list ........................................................................................................... 114
Chapter 11 Earth fault protection (50N, 51N, 67N) ............................................................. 117
1 Overview.................................................................................................................... 118
IV
3.1.2 Directional component..................................................................................... 120
3.1.3 Definite time .................................................................................................... 122
3.1.4 Inverse time .................................................................................................... 122
3.2 Setting list ........................................................................................................... 124
3.3 Report list ........................................................................................................... 141
Chapter 12 Emergency earth fault protection(50N,51N) ..................................................... 145
1 Overview.................................................................................................................... 146
3.1.2 Definite time .................................................................................................... 147
3.1.3 Inverse time .................................................................................................... 148
3.1.5 Logic diagram ................................................................................................. 149
3.2 Setting list ........................................................................................................... 150
3.3 Report list ........................................................................................................... 153
Chapter 13 Negative sequence current protection (46) ...................................................... 155
1 Overview.................................................................................................................... 156
3.1.1 Definite time .................................................................................................... 157
3.1.2 Inverse time .................................................................................................... 157
3.2 Setting list ........................................................................................................... 159
3.3 Report list ........................................................................................................... 167
Chapter 14 Overvoltage protection (59) ............................................................................. 169
1 Overview.................................................................................................................... 170
3.1.1 Definite time .................................................................................................... 171
3.1.2 Inverse time .................................................................................................... 171
3.1.4 Logic diagram ................................................................................................. 173
3.2 Setting list ........................................................................................................... 173
3.3 Report list ........................................................................................................... 177
Chapter 15 Zero sequence voltage protection (64) ............................................................ 179
1 Overview.................................................................................................................... 180
3.1.1 Definite time .................................................................................................... 181
3.1.2 Inverse time .................................................................................................... 181
3.2 Setting list ........................................................................................................... 183
3.3 Report list ........................................................................................................... 187
Chapter 16 Negative sequence voltage protection (47) ...................................................... 189
1 Overview.................................................................................................................... 190
V
3.1.1 Definite time .................................................................................................... 191
3.1.2 Inverse time .................................................................................................... 191
3.2 Setting list ........................................................................................................... 192
3.3 Report list ........................................................................................................... 196
Chapter 17 Undervoltage protection (27) ........................................................................... 197
1 Overview.................................................................................................................... 198
3.1.1 Blocking condition ........................................................................................... 199
3.1.2 Definite time .................................................................................................... 200
3.1.3 Inverse time .................................................................................................... 200
3.1.5 Logic diagram ................................................................................................. 202
3.2 Setting list ........................................................................................................... 203
3.3 Report list ........................................................................................................... 205
Chapter 18 Thermal overload protection (49) ..................................................................... 207
1 Overview.................................................................................................................... 208
3.2 Setting list ........................................................................................................... 210
3.3 Report list ........................................................................................................... 211
Chapter 19 Circuit Breaker Failure protection (50BF) ......................................................... 213
1 Overview.................................................................................................................... 214
3.1 Protection function .............................................................................................. 215
3.1.1 Current check.................................................................................................. 216
3.1.2 Breaker auxiliary contacts check ..................................................................... 216
3.1.3 CBF protection trip logic .................................................................................. 217
3.2 Setting list ........................................................................................................... 217
3.3 Report list ........................................................................................................... 219
3.4 Parameters ......................................................................................................... 220
Chapter 20 Dead zone protection (50DZ) .......................................................................... 221
1 Overview.................................................................................................................... 222
3.2 Setting list ........................................................................................................... 226
3.3 Report list ........................................................................................................... 226
Chapter 21 Stub protection (50STUB) ............................................................................... 227
1 Overview.................................................................................................................... 228
3.2 Setting list ........................................................................................................... 230
3.3 Report list ........................................................................................................... 230
Chapter 22 Pole discrepancy protection (62PD)................................................................. 233
1 Overview.................................................................................................................... 234
VI
3.2 Logic diagram ..................................................................................................... 235
3.3 Setting list ........................................................................................................... 236
3.4 Report list ........................................................................................................... 237
Chapter 23 Overexcitation protection (24).......................................................................... 239
1 Overview.................................................................................................................... 240
3.2 Setting list ........................................................................................................... 244
3.3 Report list ........................................................................................................... 245
Chapter 24 Underfrequency Protection (81UF) .................................................................. 247
1 Overview.................................................................................................................... 248
3.1.1 Protection function introduction ....................................................................... 249
3.1.2 Logic diagram ................................................................................................. 250
3.2 Setting list ........................................................................................................... 250
3.3 Report list ........................................................................................................... 251
Chapter 25 Overfrequency protection (81OF) .................................................................... 253
1 Overview.................................................................................................................... 254
3.1.1 Protection function introduction ....................................................................... 255
3.1.2 Logic diagram ................................................................................................. 256
3.2 Setting list ........................................................................................................... 256
3.3 Report list ........................................................................................................... 257
Chapter 26 Non-electric protection .................................................................................... 259
1 Overview.................................................................................................................... 260
3.2 Setting list ........................................................................................................... 260
3.3 Report list ........................................................................................................... 261
Chapter 27 Side differential protection ............................................................................... 263
1 Overview.................................................................................................................... 264
3.1.1 Differential and restraint current calculation ..................................................... 266
3.1.2 Automatic Ratio compensation ........................................................................ 267
3.1.3 CT failure supervision...................................................................................... 268
3.1.4 Side differential CT Saturation supervision ...................................................... 269
3.1.5 Side differential current supervision ................................................................. 270
3.2 Setting list ........................................................................................................... 271
3.3 Report list ........................................................................................................... 271
Chapter 28 Secondary circuit supervision .......................................................................... 273
1 Overview.................................................................................................................... 274
3.1.1. Protection function introduction ....................................................................... 275
3.1.2. Logic diagram ................................................................................................. 275
3.2 Setting list ........................................................................................................... 277
VII
3.3 Report list ........................................................................................................... 278
Chapter 29 Gap protection ................................................................................................ 281
1 Overview.................................................................................................................... 282
3.2 Setting list ........................................................................................................... 283
3.3 Report list ........................................................................................................... 284
Chapter 30 Overload protection ......................................................................................... 287
1 Overview.................................................................................................................... 288
3.2 Configuration specification of BO module ............................................................ 289
3.3 Setting list ........................................................................................................... 290
3.4 Report list ........................................................................................................... 292
Chapter 31 User-defined function ...................................................................................... 293
1 Overview.................................................................................................................... 294
2 User-defined configuration ......................................................................................... 294
2.1 Open project ....................................................................................................... 294
2.2 Binary input configuration.................................................................................... 294
2.3 Binary output configuration ................................................................................. 295
2.4 LED configuration ............................................................................................... 297
2.5 IO Matrix configuration ........................................................................................ 298
2.5.1 IO Matrix channel configuration ....................................................................... 298
2.5.2 IO Matrix function configuration ....................................................................... 298
2.6 Binary input switch setting group ......................................................................... 299
2.6.1 Function description ........................................................................................ 299
2.6.2 Setting list ....................................................................................................... 300
2.7 Configuration startup........................................................................................... 300
2.8 Other configuration ............................................................................................. 301
2.9 Defined logic....................................................................................................... 302
2.10 Connector attribute change ................................................................................. 302
Chapter 32 Control function ............................................................................................... 305
1 CB/Isolator control...................................................................................................... 306
1.1 Introduction......................................................................................................... 306
1.2 Function module description ............................................................................... 306
1.3 Detailed description ............................................................................................ 306
2 Direct control .............................................................................................................. 307
2.1 Introduction......................................................................................................... 307
2.2 Function module description ............................................................................... 307
3 Tap control ................................................................................................................. 307
3.1 Overview ............................................................................................................ 307
3.2 Description of function module ............................................................................ 307
4 Report list .................................................................................................................. 308
Chapter 33 Substation communication .............................................................................. 309
1 Overview.................................................................................................................... 310
2 Communication protocol ............................................................................................. 310
2.1 IEC 61850-8-1 communication protocol............................................................... 310
2.2 IEC 60870-5-103 communication protocol ........................................................... 310
3 Communication port ................................................................................................... 310
3.1 Front plate communication port ........................................................................... 310
3.2 RS485 communication port ................................................................................. 310
3.3 Ethernet communication port .............................................................................. 310
4 Technical parameter ................................................................................................... 311
5 Typical substation communication mode..................................................................... 312
6 Typical clock synchronization mode............................................................................ 312
VIII
Chapter 34 Man-machine interface (MMI) and operation.................................................... 313
1 Overview.................................................................................................................... 314
2 Function description ................................................................................................... 314
2.1 Liquid crystal display(LCD).................................................................................. 314
2.2 Man-machine interface (MMI) ............................................................................. 314
2.3 Menu structure.................................................................................................... 316
Chapter 35 IED hardware .................................................................................................. 323
1 Overview.................................................................................................................... 324
1.1 IED structure....................................................................................................... 324
1.1.1 4U, 19 2 inch device ...................................................................................... 324
1.1.2 4U, 19inch device............................................................................................ 325
1.2 Module arrangement diagram ............................................................................. 326
1.2.1 4U, 19 2 inch device ...................................................................................... 326
1.2.2 4U, 19inch device............................................................................................ 326
2 Analog input module .................................................................................................. 326
2.1 Overview ............................................................................................................ 326
2.2 Analog input module introduction ........................................................................ 327
2.3 Technical parameter ........................................................................................... 327
3 BI modules ................................................................................................................. 328
3.1 Introduction......................................................................................................... 328
3.2 BI Module description ......................................................................................... 328
4 BO modules ............................................................................................................... 330
4.1 Introduction......................................................................................................... 330
4.2 BO Module description........................................................................................ 330
5 BIO module ................................................................................................................ 332
5.1 Overview ............................................................................................................ 332
5.2 BIO module introduction...................................................................................... 332
6 CPU module .............................................................................................................. 334
6.1 Overview ............................................................................................................ 334
6.2 CPU module terminal diagram ............................................................................ 334
7 Power supply module ................................................................................................. 338
7.1 Overview ............................................................................................................ 338
7.2 Power supply module terminals diagram ............................................................. 338
8 TCS Module ............................................................................................................... 340
8.1 Overview ............................................................................................................ 340
8.2 TCS Module instructions ..................................................................................... 340
9 Test ............................................................................................................................ 344
10 Structural design ........................................................................................................ 346
11 CE Certification .......................................................................................................... 346
Chapter 36 Appendix......................................................................................................... 347
1 IED parameter............................................................................................................ 348
2 Common setting ......................................................................................................... 349
3 Report list .................................................................................................................. 350
3.1 Alarm report ........................................................................................................ 350
3.2 Operation Report ................................................................................................ 351
4 Analog list .................................................................................................................. 352
5 Connector list ............................................................................................................. 356
6 Typical wiring ............................................................................................................. 358
7 Inverse time characteristic .......................................................................................... 361
7.1 Twelve types of IEC and ANSI time inverse property curve ................................. 361
7.2 Definable properties by the user.......................................................................... 361
8 CT requirements ........................................................................................................ 362
8.1 Overview ............................................................................................................ 362
IX
8.2 Current transformer classification ........................................................................ 362
8.3 Abbreviations (based on IEC 60044-1, IEC 60044-6 standard) ............................ 363
8.4 Basic current transformer requirements............................................................... 363
8.4.1 Protection check current .................................................................................. 363
8.4.2 CT classification .............................................................................................. 364
8.4.3 Precision level ................................................................................................. 365
8.4.4 CT ratio ........................................................................................................... 366
8.4.5 Rated secondary current ................................................................................. 366
8.4.6 Secondary load ............................................................................................... 366
8.4.7 Rated equivalent secondary electromotive force requirements......................... 366
9 Abbreviation comparison table ................................................................................... 368
X
Chapter 1Chapter 1 Introduction
Chapter 1 Introduction
About this chapter

This chapter describes CSC-326 series transformer
protection IED.
1
1 IED overview
It is selective, reliable and high speed IED (Intelligent Electronic Device)
for transformer protection with powerful capabilities, which is suitable for
large and medium two- or three-winding transformers, and can be the
complicated application as main protection unit or full functions unit and
the communication with station automation system. The integrated and
flexible logic makes IED suitable for all winding connection mode.
Table 1 CSC-326 Application description
Type Sub-type Description
CSC-326-EB 4U, 19 2 inches, two-windings, three-winding protection
CSC-326 and BCU scheme

4U, 19 inches, two-windings, three-winding protection and
CSC-326-EBL
BCU scheme.
This series of IEDs use the new design concept, all the IEDs are
established in a general hardware and software platform. All functions are
modulized designed and at the same time diagnosis and debugging tools
are also provided. According to the actual needs of the field, through the
visual chart logic, users can customize all kinds of protection and control
logic. The equipment is highly reliable, flexible and maintainable and can be
adapted to the different site conditions.
2 IED characteristic
CSC-326 series transformer protection IED contains selectivity, reliability
and speed, application range is as bellow:
1) Integrated protection function and monitor and control function;
2) Meeting demands for three-phase tripping in transmission and
distribution grid;
3) Adopt corresponding type for different bay;
a) It is applicable to low voltage side with branch of three-winding
transformer and equipped with differential and three-side backup
protection.
b) Differential protection picks up current IH1 from high voltage side,
IH2 from high voltage side 2, IM1 from medium side, IM2 from
medium side, IL1 from low voltage side 1, IL2 from low voltage
side 2 and IL3 from low voltage side 3, the branch current is
selected, according to the different branch number of high,
medium and low voltage side.
c) Backup protection of high voltage side acquiescently picks up the
sum current of IH1 and IH2, backup protection of high voltage
side acquiescently picks up the sum current of IM1 and IM2,
backup protection of low voltage side 1, side 2 and side 3
acquiescently picks up current of IL1, IL2 and IL3 respectively.
d) It is equipped with overcurrent protection scheme of IEC 61850
GOOSE message.
4) It is equipped with breaker position monitoring function;
2
5) The device is equipped with module self-diagnosis function;

6) The device can provide complete report records, including operation
report, alarm report, start-up report and tripping report. All reports
could store no less than 2000 items and are able to store during power
disruption;
7) Up to two electric/optical Ethernet ports and capable of
communicating with substation automation system through TCP103
protocol;
8) RS485 is provided to communicate with substation automatic system
by protocol IEC 60870-5-103;
9) It supports PRP protocol based on IEC 62439-3, the device can be set
to PRP mode, and the dual network ports adopt redundant mode to
send and receive information in parallel;
10) Simple network time protocol (SNTP), pulse, IRIG-B synchronizing
modes can be selected to synchronize time;
11) A friendly MMI;
12) IEDs could be installed on screen, separately on switch panel or in
outdoor switch panel.
3 Basic function
3.1 Protection function
Functions supported by CSC-326-EB(L) and its typical application are as
follows, the optional functions can be selected, according to the ordering
code.
Table 2 Typical application configuration
IEC 61850
Description ANSI code Remark
Logic node name
Three-winding
87T PDIF
differential
Two-winding
87T PDIF
differential
Split side differential 87T PDIF
Restricted earth
87N REFPDIF HV/MV/LV
fault protection
Impedance
21 HV/MV
protection
Overcurrent
50,51 PTOC HV/MV/LV1/LV2/LV3
protection
Directional
overcurrent 51V, 67 PTOC HV/MV/LV1/LV2/LV3
protection
Emergency
overcurrent 50, 51 PTOC HV/MV
protection
Self-produced
zero-sequence 50N, 51N PEFM HV/MV/LV1/LV2/LV3
current protection
External earth fault
50G, 51G PEFM HV/MV1/LV2/LV3
protection
3
IEC 61850
Description ANSI code Remark
Logic node name
Direction earth fault
67N PEFM HV/MV1/LV2/LV3
protection
Emergency earth
50N, 51N PEFM HV/MV
fault protection
Negative sequence
46 PPBR HV/MV/LV1/LV2/LV3
current protection
Overvoltage
59 PTOV HV/MV
protection
Zero sequence
64 LV1
voltage protection
Negative sequence
47 PPBV HV/MV
voltage protection
Undervoltage
27 PTUV HV/MV
protection
Thermal overload
49 PTTR HV
protection
CBF protection 50BF RBRF HV/MV/LV1/LV2
Gap protection HV/MV

Dead zone
50SH-Z LV1
protection
Stub protection 50STUB PTOC HV/MV
Three-phase
discordance 62PD LV1
protection
Overexcitation
24 HV
protection
Underfrequency
81UF PTUF HV
protection
Overfrequency
81OF PTOF HV
protection
Start fan
Blocking voltage
adjustment
Overload 16
Interturn protection
Non-electric
(BI-BO)
protection
CT failure HV/MV/LV
VT failure 97FF HV/MV/LV1/LV2
4
Application 1 is shown as below:
59N
220kV
21
50/51/51V
*
50BF 50BF
49 49
● ● 87N
50N/51N
87T
87N ●
*
●
*
50N/51N
21
50/51/51V
*
59N
110kV
Busbar 1
Busbar 2
50/51
*
10kV
Figure 1 Application 1
5
59N
110kV
21
50/51/51V
50BF
49
● ● 87N
50N/51N
87T
● 87N
*
●
*
50N/51N
50BF
49
21
50/51/51V
59N
Meter
*
35kV
6

Bus I Bus II
* *
500kV
21
50/51/51V 50BF
50N/51N
87T
220kV
24 87N 87T
Bus I Bus II
*
ComWinding
* *
*
*
21
50/51/51V
50N/51N
50BF
50/51/51V CT4
50N/51N
64 *
35kV
3.2 Control function

Table 3 Control function
Description
Circuit breaker, disconnector and other switching devices control
3.3 Measurement function

Measurement is acquired through the dedicated measurement channels.
Table 4 Measurement function
Description
Current: Ia, Ib, Ic
Voltage: Ua, Ub, Uc, Uab, Ubc, Uca
Active power: P, Pa, Pb, Pc
Reactive power: Q, Qa, Qb, Qc
Power factor: COSφ
Frequency: F
7
3.4 Monitoring function

Table 5 Measurement function
Description
Position of circuit breaker, disconnector and other switching devices monitoring
Position of circuit breaker monitoring
Auxiliary contacts of circuit breaker monitoring
Self-diagnosis function
Disturbance and fault record
3.5 Communication mode

Table 6 Communication mode
Communication port on the front plate
RJ45 Ethernet communication port
Communication port on the rear plate
Isolated electrical RS485 communication port
Ethernet electrical/optical communication port
Time synchronization port
Communication protocol
IEC61850 Protocol
IEC60870-5-103 Protocol
DNP3.0
MODBUS
8
Chapter 2 Chapter 1Common functions
Chapter 2 Common functions
About this chapter

The chapter describes the general IED functions
9
1 Event record and analysis

1.1 Overview
To get fast, complete and reliable information about fault current, voltage,
binary signal and other disturbances in the power system is very important.
Through record function of fault data, operators can make better analysis
about the related primary and secondary devices during and after the fault.
Operational personnel can acquire valuable information to explain the
cause of the fault and modify the IED configuration in accordance with the
conclusion to improve IED reliability.
Disturbance data includes devices samples and calculated analogs, BI
and BO signals.
1.2 Fault record

IED can save the latest 40 times disturbance and fault records (which will
not loss during power failures). The records can be viewed through
operation interface of device, communication port or debugging software.
The types of reports include startup report, trip reports, alarm report and
operation report and BI change position report.
Main information of fault records include:
1) Fault time: Date and time
2) Time list: Trip component and time
3) Operation data: Current, voltage, frequency and phase
1.3 Waveform record

Disturbance and fault record function is used to capture the sampling data,
analog data and state data of predefined length before and after an event
(analog data is only applicable for the intermediate node, mid file), and
replay the protected equipment running track before and after the event.
Any logic component and BIO of the device can be used to trigger
recording function.
Recording contains analog channel, digital channel (BI, BO and protection
component states) as well as time standard sequence information.
IED makes data record, according to each cycle. Each record total length
can reach up to 20s and the latest 16 protection trip and 16 times startup,
total 32 records can be saved.
Disturbance and fault record file can be exported through the Ethernet
debugging port by using the debugging tool software (COMTRADE type),
it can also be uploaded to engineer station through the substation
communication network and used to analyze IED trip.
1.4 Sequence of event (SOE)

IED makes real-time monitor and record of trip event, alarm, BI, BO and
connector on or off, a total of 2000 state change events, recording event
time scale, reason and present state, and these real-time data are
transferred to the station control center through communication port. IED
can save more than 10 latest startup and operation event records and
SOE records can be viewed through debugging tools and software.
10
1.5 Operation record

IED records the latest 2000 times of important operating parameters
modification and remote trip and close operation. The operation object,
operation time, data modifications or operational reasons will be recorded
and provide the basis for the accident tracing.
Operation information is saved in operation record of the IED. User can
view these report information through MMI or export them by using
debugging software.
2 Diagnostic function
2.1 Overview
The device realizes the hardware and software self-checking and
monitoring of the device by means of energizing self-diagnosis and
operation self-monitoring to ensure the high reliability of the operation of
the device. Self-checking objects include key components of hardware
(such as analog sampling circuit, BIO output circuit, RAM and ROM) and
hardware accessories (such as backup battery, communication interface)
and important running parameters (such as settings, soft connectors), in
addition, the embedded two level software monitor can be used to monitor
the operation conditions of the software. When the device detects any
abnormal conditions, the device will record the abnormal events and drive
signal node and LED lights. For the key abnormal conditions, the device
will block the protection function and the important output circuit to prevent
the device from malfunctions.
The user can also check the important hardware circuit of the device
through the test command provided by the device, such as the AC circuit,
BI circuit and BO circuit, etc..
In order to cooperate automation system engineering implementation, the
device provides remote point test function, so the local SCADA and remote
master database can be checked, so the complicated manual point check
operation between the SCADA operator and remote operator is avoided.
Mainly includes the telesignalisation point check, telemetry point check.
2.2 Diagnostic principle

1) Measurement device power
2) Check zero drift and zero drift out-of-limits
3) Confirm alarm circuit
4) Check setting and parameter
3 Time synchronization function

3.1 Overview
The IED, as a part of the protection system, can be time synchronized by
time synchronization source. In the security automation intelligent system,
through the time synchronization, IED and other devices in the system
have the same clock source. When the system fault or abnormal, there is a
unified clock reference between the various devices.
11
3.2 Synchronization principle

Definition of time
The error of a clock is the difference between the actual time and the
synchronized clock. The rate accuracy of a clock is normally called the
clock accuracy. When the clock deviation is too large, the clock will
re-synchronize to ensure clock accuracy is within the set range.
Synchronization principle
Generally speaking, synchronization can be seen as a hierarchical
structure. A module is synchronized from a higher level and provides
synchronization to lower levels.
Synchronization from a higher level
Module
Optional synchronization of modules at

a lower level
Figure 4 Synchronization principle diagram

A module of the system is synchronized when it receives synchronization
signal from a higher level and this module is time synchronization module.
The less the clock synchronization level, the higher the final time
synchronization accuracy is. The same module may have several options
of time synchronization sources with different errors, this module can
choose the best time source and adjust the internal clock, according to the
time synchronization source. The maximum error of a clock can be defined
as:
1) The maximum error of the last synchronization information;
2) The calculated time from last time synchronization information;
3) The rate accuracy of the internal clock in the module.
Time synchronization system provides three synchronization methods:
IRIG-B code, IEEE1588 and net synchronization and second pulse
synchronization.
3.3 IRIG-B code synchronization mode

CPU module of the device supports RS485 level IRIG-B (DC) code
synchronization.
3.4 PPS synchronization mode

CPU module of the device supports RS485 level PPS signal. If the
substation time is not synchronized with the standard time, the present
12
time of the substation will be regarded as valid time and the IED time is
synchronized with it. After receiving the pulse signal, the CPU can
automatically adapt to the positive and negative pulses.
3.5 SNTP synchronization mode

Synchronization via SNTP is implemented on a request-response basis
The IED sends a synchronization request message to a SNTP server. The
SNTP server resets time message after handling transmission delay, and
then sends the time information to the device through Ethernet. In order to
ensure SNTP synchronization is normal, one SNTP server must be set, it
is suggested that one server can be set at one substation. SNTP
synchronization accuracy is 1ms for binary inputs. The IED itself can be
set as a SNTP synchronization server.
3.6 1588 synchronization mode

It supports IEEE1588 high precision network synchronization.
4 Authorization
To safeguard the interests of customers, accesses to the IED and the
debugging software are restricted in terms of authorization. In practice,
attention should be paid to the following aspects in the use of the IED and
associated debugging software:
1) There are two types of access to the IED:
a) Local, through the local HMI
b) Remote, through the communication ports
2) Different users have different authority to access to or operate device
or test the software
13
Chapter 3 Chapter 1Fault phase selection component
Chapter 3 Fault phase selection

component
About this chapter

This chapter describes the basic protection component, fault
phase selection component.
15
1 Overview
The fault phase selector component can distinguish the fault phase, and
make use of various phase selection principles to judge the different fault
conditions, so as to meet the requirements of trip phase selection.
The fault uses steady-status sequence component to judge the phase, for
power supply, terminal fault small current or no current, the low voltage
phase selector is used to judge the phase.
When the local side over-current protection trips, the fault phase selection
is triggered, which is only used to judge the fault current generated by the
local side fault.
Phase selection function can be blocked by external binary input, VT
failure and CT failure.
If the voltage connector of local side is disabled, the fault phase selection
function of local side will be disabled.
2 Function module description

The I/O signals described herein only reflect the visible engineering part.
The input and output signals of fault phase selection module function are
shown as follows:
Faulty Phase Selection

1 1
BIBlk FaultPhase
2 2
VTFailBlk FaultA
3 3
CTFailBlk FaultB
4 4
Ena_*Voltage FaultC
Figure 5 Input and output signal diagram of fault phase selector component function
Table 7 Parameter description
Function Key Description

Input:
BIBlk BI blocking BO
VTFailBlk VT failure blocking signs
CTFailBlk CT failure blocking sign

FltPh Output:
FaultPhase Fault phase
FaultA Phase A fault

FaultB Fault of phase B
FaultC Phase C fault
"HVSideVoltConn": Ena_HVoltage,the corresponding hard
connector is Ena_HVoltage_5
"MVSideVoltConn": Ena_MVoltage,the corresponding hard
ENA_*Voltage Ena_*Voltage
connector is Ena_MVoltage_5
"MVSideVoltConn": Ena_MVoltage,the corresponding hard
16
3 Detailed description
3.1 Protection principle
3.1.1 Steady state component phase selector
The steady status component phase selector selects the phase through
the angle between zero sequence current component and negative
sequence current components, and the phase impedance is used to
confirm whether the phase selection is correct.
The analysis shows that the angle between the zero sequence current
component and negative sequence current component of the fault current
can be used to select the fault phase, the analysis is shown in the following
figure:
I0a
0 0
+30 AN,BCN -30
ABN BCN
0 0
+90 -90
CN,ABN BN,CAN
0 0
+150 CAN -150
Figure 6 Relationship diagram between zero sequence current component and

negative sequence current component angle of various faults
Table 8 Steady status component phase selector table
Phase area Angle range Phase selection results
1 +30°~-30° AN or BCN
2 +90°~ +30° ABN
3 +150°~ +90° CN or ABN
4 -150°~ +150° CAN
5 -90°~ -150° BN or CAN
6 -30°~ -90° BCN
For example, the angle between the negative sequence component and
the zero sequence components is between -30 degrees and +30 degrees,
and the fault type is a phase grounding or fault between phase B and C or
grounding fault between phase B and C.
As shown in the table above, area 2, 4, and 6 directly reflect the relative
fault type, but area 1, 3, and 5 may reflect the existence of two types of
fault, at this point, it is distinguished through phase impedance calculation.
If the phase impedance is larger than that of the phase impedance setting
value, the possibility of phase fault is eliminated, and it is judged to the
corresponding single-phase grounding fault, or it is judged to the
corresponding phase fault.
3.1.2 Undervoltage phase selection component
The steady status component phase selector is not reliable in the weak
17
feedback system, and the low voltage phase selector is applied to the
weak feedback system.
Discriminant formula for single phase fault and interphase fault is as
follows:
Upe<k×Upe_Secondary
or
Upp <k×Upp_Secondary
Where:
1) Upe and Upp are phase-to-earth voltage and phase-to-phase voltage
respectively
2) U_Secondary is system secondary rated voltage value
3) k is internal coefficient
For example, if only A phase voltage is low, it is judged to be A phase fault;
if only the AB phase-to-earth voltage is low, it is judged to be AB phase
fault; if AB, BC and CA phase-to-earth voltage are all low, then it is judged
to be three-phase fault.
18
Chapter 4 Basic protection component
Chapter 4 Basic protection

component
About this chapter

This chapter describes basic protection components
including startup components and directional components.
19
Chapter 4 Basic protection component
1 Startup component
1.1 Overview
Startup component is used to detect faults in power system and initiate
related programs to selectively remove faults. The main startup
components of CSC-326 are abrupt-change current component and
differential startup component.
Startup component includes:
1) Current sudden-change startup component;
2) Differential current startup component.
1.2 Current sudden-change startup component

The abrupt-change current component is main startup component; it can
detect sensitively most faults. Criteria are as follows:
i  I _ startup

i  i (t )  2  i (t  T )  i (t  2T )
Where:
I_startup is fixed threshold value (when secondary value of CT is 1A,
I_startup=0.2A; when secondary value of CT is 5A, I_startup =1A).
1.3 Differential current startup component

 I d max  I _ diff startup

 I d max  Max I d ,  a, b, c

 I _ diff startup  0.8I _ percent diff
Where:
I_diff startup is differential protection startup threshold, I_Percent Diff is
differential protection value, Idφ is phase differential current.
2 Report
Table 9 Report list
Report Description
IED startup IED startup
20
Chapter 5 Differential protection(87T)
Chapter 5 Differential protection

(87T)
About this chapter

This chapter describes the protection principle, input and
output signals, parameter, IED report and technical
parameter for differential protection function.
21
Chapter 5 Differential protection (87T)
1 Overview
The numerical current differential protection represents the main protection
function of the IED. It provides a fast short-circuit protection for power
transformers. The protected zone is selectively limited by the CTs at its
ends. The device is able to perform this function on 2 or 3 winding
transformers in a variety of voltage levels and protected object types.
The protective function can be disabled through the function connector.
The connector properties can be configured as soft connector, hard
connector, soft-hard series, soft-hard parallel, and the default is soft-hard
parallel.
The IED provides numerical differential protection function which can be
used to protect power transformers in various configurations. For example,
it is possible to use it for a two-winding transformer, three-winding
transformer as well as auto-transformer. Examples for some of
applications are illustrated in the below figure.
High voltage side Low voltage side

I A.1 Ia.2
A a
I B.1 Ib .2
B b
I C .1 Ic .2
C c
CSC-326
Figure 7 Application of differential protection on a two-winding Yd transformer

I A.1
A Ia.2
a
IB.1
Ib .2
B
b
IC .1
C Ic .2
c
CSC-326
Figure 8 Application of differential protection on a two-winding Yd transformer
22
High voltage side Low voltage side

I A.1 Ia.2
A a
IB.1 Ib .2
B b
IC .1 Ic .2
C c
CSC-326
Figure 9 Application of differential protection on a two-winding Yd transformer with

earthing transformer inside the protected zone
Middle voltage side

Ia.2
a
Ib .2
b
High voltage side Ic .2
I A.1 c
A
I B.1
B
I C .1 Low voltage side
C Ia.3
a
Ib .3
b
Ic .3
c
CSC-326
Figure 10 Application of differential protection on a three-winding Ydd transformer

The input and output signals of differential protection function diagram are
shown below, left side is input and right side is output:
23
DiffTripBO
1 1
Ena_Diff PerDiffATrip
2
PerDiffBTrip
3
PerDiffCTrip
4
InstDiffATrip
5
InstDiffBTrip
6
InstDiffCTrip
7
CT_Fail
8
Diff_Alm
9
IrushBlkDiff
10
BlkDiff3or5Harm
Figure 11 Transformer differential protection module

Function Identifier Description
Input:
ENA_Function "DiffConn",the corresponding hard connector is
Ena_Diff
Ena_Diff_5
Output:
PerDiffATrip Differential phase A trip

PerDiffBTrip Differential phase B trip
PerDiffCTrip Differential phase C trip
InstDiffATrip Instantaneous differential phase A trip
DiffTripBO InstDiffBTrip Instantaneous differential phase B trip
InstDiffCTrip Instantaneous differential phase C trip
CT_Fail CT failure
Diff_Alm Differential current over limit alarm
IrushBlkDiff Secondary harmonic blocking differential
BlkDiff3or5Harm Blocking differential of third or fifth harmonic
This section describes basic principle of differential protection function.
First, the case of a single phase transformer with two windings is
considered. The basic principle is based on current comparison at two
sides of the protected object. Indeed, the differential protection function
makes use of the fact that a protected object carries always the same
current at its two sides in healthy operation condition. This current flows
into one side of the protected object and leaves it from the other side. A
difference in currents is an indication of a fault within this section. An
24
example of this condition is shown in below figure, when a fault inside the
protected zone causes a current I1prim. + I2prim flowing in from both sides
of the protected object.
IED area
I1-prim. I2-prim.
CT-1 CT-2
Protected
transformer
I1 I2
CSC-326
Figure 12 Basic principle of differential protection for two ends (single phase)
For protected objects with three or more sides, the basic principle is
expanded in that the total of all currents flowing into the protected object is
zero in healthy operation, whereas in case of a fault the total in-flowing
current is equal to the fault current.
When an external fault causes a heavy current to flow through the
protected transformer, differences in the magnetic characteristics of the
current transformers CT-1 and CT-2 under saturation condition may cause
a significant difference in the secondary currents I1+I2 connected to IED. If
the difference is greater than the pickup threshold, the differential
protection function can trip even though no fault occurred in the protected
zone. To prevent the protection function from such erroneous operation, a
restraint (stabilizing) current is brought in. For differential protection IED,
the restraint current is normally derived from the I1 and I2. The next
subsection goes on to demonstrate how the differential and restraint
currents are calculated.
3.1.1 Differential and restraint current calculation
The differential current Idiff and the restraining current Ires are calculated
by the following equation. The following definitions apply for each phase of
the protected object.
 N 
 I diff 

 i 1
Ii
 N 1 
 1 
 I res  2 I j (max) 
 i 1
I i (i  j )
I i Where is the current vector of side i, corresponding to HV, MV and LV

windings; N is total current inputs of the IED. In other words, it is number of
the protected object sides; I j (max) is the maximum current vector among
N 1 
the N current inputs of the IED, suppose it is side j;  I i (i j ) is the sum of
i 1
the other current inputs of the IED, not including side j. Idiff is derived from
the fundamental frequency current and used for the judgment of the
tripping effect, while Ires is used for the judgment of the restraining effect.
25
To clarify the situation, three important operating conditions with ideal and
matched measurement qualities are examined.
1) External fault:
I1 flows into the protected zone,I2 leaves the protected zone, i.e. I2 = –I1.
Idiff = I1 + I2 = I1 – I1 = 0
Ires = 0.5×| I1 - (–I1) | = 0.5×|2I1| = |I1|
No tripping effect (Idiff = 0); the restraint (Ires) corresponds to the external
fault current flowing through the protected object.
2) Internal fault, fed with equal currents from both sides:
that isI2 = I1
Idiff = I1 + I2 = I1 + I1 = 2 I1
Ires = 0.5×| I1 - I1| = 0
Tripping effect (Idiff) corresponds to double the fault current, and restraint
value (Ires) are equal to zero.
3) Internal fault, fed from one side only:
supposeI2 = 0
Idiff = I1 + I2 = I1 + 0 = I1
Ires = 0.5×|I1 - I2| =0.5× |I1 - 0| = 0.5×|I1|=0.5 I1
Tripping quantity (Idiff) and restraint quantity (Ires) are equal and
correspond to the single-sided fault current.
The results show that the device is capable to properly discriminate
internal and external faults by using the definitions proposed for differential
and restraint current. However, the device is still subjected to some
influences that induce differential currents even during normal operation
condition. These influences should be compensated in appropriate
manners. The specific treatments designed to cope with these influences
includes automatic ratio compensation and automatic vector group
compensation which are explored in the next subsections.
3.1.2 Automatic Ratio compensation

Differential protection of power transformers represents some problems in
the application of current transformers. CTs should be matched to the
current rating of each transformer winding, so that normal current through
the power transformer is equal on the secondary side of the CT on different
windings. However, because only standard CT ratios are available, this
matching may not be exact. As a result, the secondary currents of the
current transformers are not generally equal when a current flows through
the power transformer. The difference between the currents flowing
through CTs’ secondary circuit depends on the transformation ratio of the
protected power transformer, as well as the rated currents of the current
transformers. Therefore, the currents should be matched in order to
become comparable. To do so, the input currents of the IED are converted
in relation to the power transformer rated currents. This is achieved by
entering the characteristic values of the power transformer (i.e. rated
apparent power and rated voltages) and primary rated currents of CTs into
the IED by using user-entered settings. As a result, matching to various
power transformer and current transformer ratios is performed purely
26
mathematically inside the device. Therefore, no external matching

transformer is required. In this context, the rated primary current of each
side I1N can be calculated automatically by the following equation.
SN
I 1N 
3U 1N
Where SN is rated apparent power of the transformer and U1N is rated

voltage of the corresponding side.
The rated secondary current of each side I2N can be calculated by the
following equation:
I1N
I 2N 
nCT
Rated secondary current of the high voltage side is then taken as the
reference current. The currents of the other sides are automatically
matched to the rated current of the high voltage side by calculation of
correction factor KCT for MV and LV side, according to below equations,
respectively:
I 2 N  HV I /n S / 3U 1N  HV nCT  MV U 1N  MV nCT  MV
K CT  MV   1N  HV CT  HV  N   
I 2 N  MV I 1N  MV / nCT  MV S N / 3U 1N  MV nCT  HV U 1N  HV nCT  HV
I 2 N  HV I 1N  HV / nCT  HV S N / 3U 1N  HV nCT  LV U 1N  LV nCT  LV
K CT  LV      
I 2 N  LV I 1N  LV / nCT  LV S N / 3U 1N  LV nCT  HV U 1N  HV nCT  HV
Where, KCT-MV is the correction coefficient on the medium voltage side

and KCT-LV is the correction coefficient on the low voltage side.
I1N is the rated primary current of the transformer (I1N-HV is the primary
current of the high voltage side, I1N-MV is the primary current of the
medium voltage side and I1N-LV is the primary current of the low voltage
side).
I2N is the rated secondary current of the transformer (I2N-HV is the
secondary current of the high voltage side, I2N-MV is the secondary
current of the medium voltage side, I2N-LV is the secondary current of the
low voltage side).
nCT is CT ratio of the transformer (nCT-HV is the ratio of the high voltage
side, nCT-MV is of the medium voltage side, nCT-LV is of the low voltage
side).
U1N is rated voltage of the transformer (U1N-HV is the rated voltage of the
high voltage side, U1N-MV is of the medium voltage side, U1N-LV is of the
low voltage side).
As mentioned previously, all of the calculations are automatically
per-formed inside the IED by its CPU. The related settings can be found
under the menu “Test Menu”.
Below figure shows an example of automatic ratio compensation in case of
a two-winding transformer. The rated currents of the high voltage and low
voltage sides, (I1N = 402A, I2N= 1466A) are calculated by the rated
apparent power (160MVA) of the transformer and the rated voltage (230kV
and 63kV) of each side. Since the rated currents of CT is based on the
27
rated current of transformers, the secondary current of low voltage side

shall be multiplied by the correction coefficient KCT-LV. Subsequent to this
matching, equal current magnitudes are achieved at both sides under
nominal conditions of the power transformer.
SN=160MVA
U1N-HV=230kV U1N-LV=63kV
CTRATIO=500/1A CTRATIO=2000/1A
Figure 13 Example of automatic ratio compensation in a three-winding transformer
160MVA
I1N  HV   402 A
3  230
I1N  HV 402
I 2 N  HV    0.804 A
nCT 500
160 MVA
I 1N  LV   1466 A
3  63
1466
I 2 N  LV   0.733 A
2000
0.804
K CT LV   1.097
0.733
Concerning three-winding power transformers, the windings may have

different power ratings. In order to compare secondary currents in an
appropriate manner, all currents are matched to the rated secondary
current of HV winding having highest power rating. This apparent power is
nominated as the rated apparent power of the transformer.
Below figure shows an example of a three-winding power transformer. HV
winding and MV winding are rated for 160MVA. The rated primary and
secondary currents of these windings are calculated as shown in previous
example. However, the LV winding has 25MVA rating (e.g. for auxiliary
supply). The rated current of this winding may result in 721A. However,
differential protection has to process comparable currents. Therefore, the
currents of LV winding should be referred to the rated apparent power of
the transformer, i.e. 160MVA. This results in a rated current of 4619A. This
is the base value of the low voltage side current, which should be
multiplied by the correction coefficient KCT-LV to calculate the differential
protection.
160MVA 160MVA
U1N-HV=230kV U1N-MV=63kV
CTRATIO=500/1A CTRATIO=2000/1A
U1N-LV=20kV 25MVA
CTRATIO=2500/1A
28
Figure 14 Example of automatic ratio compensation in a three-winding transformer

160 MVA
I 1N  LV   4619 A
3  20
I 1N  LV 4619
I 2N  LV    1.848A
nCT 2500
0.804
K CT LV   0.435
1.848
3.1.3 Automatic Vector group and zero sequence current

compensation
Transformers have different vector groups, which cause a shift of the
phase angles between the primary and the secondary side. Without
ad-equate correction, this phase shift would cause a false differential
current. Furthermore, the conditioning of the starpoint(s) of the power
transformer has a great impact on the resulting differential current during
through fault currents.
The IED removes this problem. To do so, all CTs at the power transformer
are connected Wye (polarity markings pointing away from the transformer).
User-entered settings in the relay are then used to characterize the power
transformer and allow the relay to automatically per-form all necessary
phase angles, and zero sequence compensation. This section describes
the procedures that perform this compensation inside the relay and
produce the required calculated quantities for transformer differential
protection. The phase angle compensation as well as zero sequence
current elimination procedure is performed by programmed coefficient
matrices which are capable to simulate the difference in phase angle of
currents flowing through transformer windings. Thus, compensation is
possible for the entire commonly used transformer vector groups. This
simplifies application of the IED in various configurations, if the setting
corresponding to vector Group Angle, “Vet Grp Angle”, is properly entered
into the device, together with the settings for connection type of
transformer windings in each side, “HVSideConnectMode/Y-0 D-1”,
“MVSideVectorGrp/Y-0 D-1”, LVSideVectorGrp/Y-0 D-1”, which could be
set to 1-delta or 0-wye. The basic principle of numerical vector group and
zero-sequence compensation is shown through some examples. A
thorough review of all possible connection groups as well as device
treatment in each case is explored in Appendix.
1) Take example for Yy0 connection, including similar ones of Yy0
(separate or auto-connected windings), YNy0, Yyn0, YNyn0 (separate
or auto-connected windings) and so on. Below figure shows an
example in case of Yy0 connection group with no earthed star point.
The figure shows the windings (left) and the vector diagrams of
symmetrical currents (right).
29
A B C
Yy0 c b
C B
a b c
Figure 15 Vector Group and zero sequence compensation for Yy0 transformer
The equations including the coefficient matrix are as follow:
 I A  1 -1 0  I A 
  1   
 I B    0 1 -1   I B 
I   3
-1 0 1   I C 
 C  
 I a  1 -1 0  Ia 
  1   
 I b    0 1 -1   I b 
I   3 
-1 0 1   I c 
 c  
According to these matrices, if we deduct side one currents I A  IB , the
resulting current I A has the same direction as I A on side two.

Multiplying it with 1 3 , matches the absolute value. The matrices
describe the con-version for all three phases. Using these matrices, the
elimination of zero sequence currents are warranted regardless of star
point earth connection.
As mentioned previously, the two above equations can be used similarly
for auto-transformers, as the auto-connected windings in
auto-transformers can only be connected Y(N)y(n)0. If the star point is
earthed, both the auto-connected HV and LV windings are affected. The
zero sequence components in current flowing through both sides of the
transformer are then coupled because of the common star point. These
zero sequence components are eliminated by the application of the
matrices presented in the above equations.
2) Take example for Yd1 connection, including similar ones of Yd1 and
YNd1 without earthing transformer installed at delta side. Below figure
shows an example in case of Yd1 connection group with no earthed
star point.
30
A B C
A
a
Yd1 c
C b B
a b c
Figure 16 Vector Group compensation for Yd1 transformer

The equation including the coefficient matrix is as follows:
 I A  1 0 -1  I A 
  1   
 I B    -1 1 0    I B 
I   3
0 -1 1   I C 
 C  
If an earthing transformer/reactor is installed inside the protected zone on
delta side, the IED should be informed about it by logic switch
“HVSideDeltaMinus3I0”, “MVSideDeltaMinus3I0” or
“LVSideDeltaMinus3I0”. By taking example for Yd1 connection with
earthing transformer installed at delta side, logic switch
“LVSideDeltaMinus3I0” is enabled, and thus, device performs a zero
sequence current elimination on delta side. In this case, the equations
including the coefficient matrices are as follow:
 I A  1 0 -1  I A 
  1   
 I B    -1 1 0    I B 
I   3
0 -1 1   I C 
 C  
   
I
  I
a
 2  1  1  a 
  1  . I 
     
I b . 1 2 1  b
   3  1  1 2    
 I c    I c 
   
3) Take example for Ydd3 connection, including similar ones of Ydd3 and
YNdd3 without earthing transformer installed at delta sides. Below
figure shows an example in case of Ydd3 connection group with no
earthed star point in Wye side.
31
A B C
A
c(c’)
Ydd3 a(a’)
C b(b’) B
c a b c' a' b'
Figure 17 Vector Group compensation for Ydd3 transformer

 I A  0 1 -1  I A 
  1   
 I B    -1 0 1    I B 
I   3 
1 -1 0   I C 
 C  
4) Take example for Yd5 connection, including similar ones of Yd5 and
YNd5 with earthing transformer installed at delta side. Below figure
shows an example in case of Yd5 connection group with no earthed
star point.
A B C
A
c
Yd5 b
a
C B
c a b
Figure 18 Vector Group compensation for Yd5 transformer

By setting logic switch “LVSideDeltaMinus3I0”, the equations including the
coefficient matrices are as follow:
 I A  -1 1 0  I A 
  1   
 B
I    0 -1 1    I B 
I   3
1 0 -1  I C 
 C  
32
   
I
 a I
 2  1  1  a 
  1

. I 
     
I b . 1 2 1  b
   3  1  1 2    
 I c    I c 
   
5) Take example for Dy1 connection, including similar ones of Dy1 and
Dyn1 without earthing transformer installed at delta side. Below figure
shows an example in case of Dy1 connection group with no earthed
star point.
A B C
Dy1 c
b
C B
a b c
Figure 19 Vector Group compensation for Dy1 transformer

 I a  1 -1 0  I a 
  1   
 I b    0 1 -1   I b 
I   3 
-1 0 1  I c 
 c  
If an earthing transformer/reactor is installed inside the protected zone on
delta side, logic switch “LVSideDeltaMinus3I0” is enabled, and thus,
device performs a zero sequence current elimination on delta side. In this
case, the equations including the coefficient matrices are as follow:
    
I
  I
A
 2  1  1  A 
  1    
 I  B   . 1 2  1. I B 
   3  1  1 2    
 I C    I C 
   
 I a  1 -1 0  I a 
  1   
 I b    0 1 -1   I b 
I   3 
-1 0 1  I c 
 c  
Subsequent to application of the magnitude, vector group and zero
sequence compensation, the IED use the following calculated quantities
(per phase) to discriminate between internal and external faults:
fundamental component of differential and restraint currents together with
instantaneous value, second and 5th harmonic contents of differential
current. The following sections go on to demonstrate the fault recognition
criteria using these derived quantities.
33
3.1.4 Instantaneous differential protection characteristic

An instantaneous (unrestrained) differential characteristic which entails an
overcurrent protection is provided for fast tripping on heavy internal faults.
The function can be enabled or disabled by using logic switch
“InstantaneousDiffOn” and “DiffOn” (1-on, 0-off).
If “InstantaneousDiffOn”and “DiffOn” are set as “1-on”, regardless of the
magnitude of the restraining current, a trip signal will be issued as soon as
the differential current exceeds the threshold ID> (setting "
InstantDiffCurrSet"). The signal is phase splitting trip. And the device will
issue trip reports “InstantDiffPhATrip”, “InstantDiffPhBTrip” or
“InstantDiffPhCTrip” when the calculated differential current in phase A, B
or C exceeds the threshold ID> (setting "InstantDiffCurrentSetting"). The
purpose of this stage of differential protection is extremely fast operation in
case of high magnitude internal fault currents. When the short-circuit
current is higher than IN/Uk%, a fault may occur in the transformer. It
should be noted that the flowing fault current shall be lower than IN/Uk%.
(IN is rated current and UK% is short-circuit voltage of the transformer.)
The logic diagram of instantaneous differential protection is shown in
below figure.
“DiffOn”=1
&
“InstantaneousDiffOn”=1
DiffProttFcnOn=1 &
Instantaneous differential
phase A output
IDA>“InstantDiffCurrSet”
&
phase B output
IDB> “InstantDiffCurrSet”
&
phase C output
IDC> “InstantDiffCurrSet”
Figure 20 Tripping logic of the instantaneous differential protection

As mentioned previously and can be seen from the figure, the stage
operates as an unrestrained protection function. In other words, it is not
inhibited by any of harmonic stabilization features of the percent differential
component as well as the CT failure detection. This means that it can
operate even when, for example, a considerable second harmonic is
present in the differential current, which is caused by current transformer
saturation by a DC component in the fault current, and which could be
interpreted by the inrush inhibit function as an inrush current.
This high current stage evaluates the fundamental component of the
differential current as well as the instantaneous values. Instantaneous
value processing ensures fast tripping even in case the fundamental
component of the current is strongly reduced by current transformer
saturation. Fast trip is shown in Figure 16.
3.1.5 Treble slope percent differential protection
characteristic
The percent differential protection uses a treble-slope dual break-point
34
operating characteristic with magnetizing inrush and overexcitation and CT

failure detection inhibits integrated. The treble slope characteristics can be
enabled or disabled by using logic switch “DiffOn” (1-on, 0-off). If setting
1-on is selected, the stage calculates differential and restraint current
separately in each phase to obtain operating point in each operation
condition. Then the operating point is mapped into Idiff-Ires plane to
examine whether it lies in trip or block area which is defined according to
predefined operating characteristic. The operation characteristic is shown
in below figure.
1 differential Instantaneous
differential trip
Instantaneous area
differential current
Differential currrent
Slope 3
Trip area
Slope 2 Restraint
Slope 1 area
Differential 1 restranit
startup
1 restraint break point 1 1 restraint break point 2 Restraint current
Figure 21 Differential protection characteristics for transformers

In this characteristic, branch 1 represents the sensitivity threshold of the
differential protection. The setting of ID> (the setting is "DiffStartupSet")
defines the minimum differential current required for operation. The setting
is chosen based on the amount of differential current that might be seen
under normal operating conditions which corresponds to constant error
currents such as magnetizing currents and CT errors under no-load
conditions. The setting for slope of branch 1 is applicable for restraint
currents of zero to the first break-point indicated on restraint axis (the
setting is "BreakPoint1CurrSet"). The slope 1(the setting is
“Slope1RatioRestrCoef”) is the ratio of differential current to restraint
current above which is the percent differential protection trip area. The first
break-point on restraint axis defines the end of the slope 1 region and the
start of the second branch region. This setting should be set just above the
maximum operating current level of the transformer. This level is
somewhere between the maximum forced-cooled rated current of the
transformer and the maximum emergency overload current level.
Slope 2 considers current-proportional errors which may result from
transformation errors of the main CTs or the input CTs of the relay. This
may also contain the error caused by the influence of tap changers in
power transformers with voltage control. The setting for slope of branch 2
(the setting is” Slope2RatioRestrCoef”) is applicable for restraint currents
of the first break-point to the second one on restraint axis, and defines the
ratio of differential to restraint current above which the component will
operate. This slope is set to ensure sensitivity to internal faults at normal
operating current levels. This setting should be set to the level at which
any of the protection CTs is probable to saturate. The second break-point
on restraint axis (setting “I_ResPoint2 Diff”) defines the end of the slope 2
35
region and the beginning of the slope 3 region. This setting should be set
to the level at which any of the protection CTs is probable to saturate.
In the range of high through fault currents which may give rise to high
differential currents as a result of CT saturation, branch 3 is applicable to
provide additional stabilization. The setting for the slope 3 (the setting is
“Slope3RatioRestrCoef”) is applicable up to the point at which the branch
intersects the characteristic of instantaneous differential protection.
As a summary of the fault detection using operating characteristics of the
above figure, the calculated differential and restraint currents, IDiff and
IRest, are compared by the differential protection with the operating
characteristic according to the following formula ,
I diff  S1I res  I D  I res  I R1 


I diff  S 2 ( I res  I R1 )  S1  I R1  I D  I R1  I res  I R 2 

I diff  S3 ( I res  I R 2 )  S 2 ( I R 2  I R1 )  S1  I R1  I D  I R 2  I res 
Where, S1 is Slope 1 (the setting is "Slope1RatioRestrCoef");
S2 is Slope 2 (the setting is "Slope2RatioRestrCoef");
S3 is Slope 3 (the setting is "Slope3RatioRestrCoef");
ID> is the threshold value of the differential protection sensitivity (the
setting is “DiffStartupSet”);
IR1 is the first break point setting of restricted current
“BreakPoint1CurrSet”;
IR2 is the second break point setting of restricted current
“BreakPoint2CurrSet t”.
If the operating point calculated from the quantities of differential and
restraint current falls into the trip area, a trip signal is issued by the percent
differential protection. The issued signals are phase selective. They can be
found in event report as “DiffPhATrip”, “DiffPhBTrip” and “DiffPhCTrip”.
This stage cannot operate when there is an inrush or over-excitation
stabilization or a restraint due to CT failure detection. This is illustrated in
below logic diagram.
36
DiffFcnOn=1
&
“DiffOn”=1
I diff  A , I rest  A Phase A Ratio differential

& Phase A output
ID>
Ratio differential
blocking Phase A
Phase B Ratio differential

I diff  B , I rest  B Phase B output
ID>
&
Ratio differential
blocking Phase B
Phase C
I diff C , I rest C Ratio differential
& Phase C output
ID>
Ratio differential
blocking Phase C
“CTFailBlkDiff”=1
&
CT failure
Figure 22 Tripping logic of the percent differential protection

It should be noted that when the IED is delivered, both the instantaneous
and percent differential protection functions are switched off. Setting of
“0-off” is applied for logic switch “InstantaneousDiffOn” and “DiffOn”. This
is because the fact that these protection functions should not be used
before at least the vector group and other essential parameters for each
side is correctly set. Without these settings the equipment may show
unpredictable behavior. (E.g. tripping)
3.1.5.1 Excitation inrush current blocking principle
1) Second harmonic blocking principle
By selecting “1-Block” for control-word “ExcitInrushBlkDiff” and selecting
“1-second harmonic” for logic switch “2ndHRestr”, inrush current is
recognized if the second harmonic content in the differential current
exceeds a selectable threshold. The ratio between the second harmonic
and the fundamental frequency component is decisive to discriminate
inrush conditions from the other operation conditions. The ratio is
calculated by the below equation. As soon as the measured ratio exceeds
the set thresholds, a restraint is applied to the percent differential
protection, in the " Blocking time of the second harmonic " time，blocking
three-phase differential，over "Blocking time of the second harmonic "
time, blocking single-phase differential.
I diff  2
 K 2
I diff 
Where, Idiff-φ2 is the secondary harmonic magnitude of differential current,

Kφ2 is the setting of the secondary harmonic ratio, Idiff-φ is fundamental
wave component of differential current.
37
2) Fuzzy recognition blocking principle

By selecting “1-block” in control-word “ExcitInrushBlkDiff”, and selecting
“0-waveform on” for logic switch “2ndHRestr”, inrush current is detected by
a fuzzy recognition method based on waveform. In this context, differential
current waveform is sampled in each phase by 2n number of samples per
cycle, each of the samples is nominated as I(k), k=1, 2, …, 2n. X(k) is
obtained by the calculation according to the following equation.
I ( k )  I ( k  n)
X (k )  , k  1,2,..., n
I ( k )  I ( k  n)
The smaller values of X(k) represent that the calculated point corresponds
to fault condition with higher confidence level. Alternatively, the larger
values of X(k) gives a picture that there is large content of inrush current in
the waveform. Assume that X(k) belongs to “inrush Fuzzy class” with
membership function of A[X(k)]. Then, the fuzzy similarity coefficient for
the n calculated values of X(k) in one cycle is defined as below equation.
n
N  A[ X (k )] / n
k 1
The derived value of N is used in the IED to assess the differential current
corresponds to inrush condition or not. To do so, the value of N is
compared with a threshold K, and inrush content is recognized in the
current waveform, if N>K.
DiffFcnOn=1
≥1 2ndHBlkDiff
“DiffOn”=1
&
“ExcitInrushBlkDiff”=1
&
“2ndHRestr”=1 ≥1 PerDiffBlockPhaseA
T
I diff  A 2
 K 2
I diff  A
&
T
≥1 PerDiffBlockPhaseB
I diff  B  2
 K 2
I diff  B 
≥1 PerDiffBlockPhaseC
I diff C  2 &
 K 2 T
I diff C 
K 2 ：“2NDHRestrCoef” T：“2ndHCrossBlkTime”
Figure 23 Logic diagram of excitation inrush detected by using the secondary harmonic
mode
38
DiffFcnOn=1
“DiffOn”=1
&
& PerDiffBlockPhaseA
“ExcitInrushBlkDiff”=1
“2ndHRestr”=0
Phase A Fuzzy Recognition
& PerDiffBlockPhaseB
Phase B Fuzzy Recognition
& PerDiffBlockPhaseC
Phase C Fuzzy Recognition
Figure 24 Logic diagram of excitation inrush detected by using fuzzy recognition mode
3.1.5.2 Overexcitation stabilization
Apart from the second harmonic, other harmonic contents can be selected
in the IED to cause stabilization of percent differential protection. This is
because the fact that unwanted differential currents caused by transformer
overexcitation may result in false tripping of the percent differential
protection. Since steady state overexcitation is characterized by odd
harmonics, the third or the fifth harmonic can be selected in the IED to
judge for overexcitation stabilization. If it is desired to impose a blocking
condition to percent differential protection by these harmonics, logic switch
“OEBlkDiff” should be set to “1-on”. By applying this setting, alarm report
entitled “3rd/5thHBlkDiff” is issued whenever third or fifth harmonic
detection impose a blocking condition to differential protection.
It is possible to use logic switch “OE5thHOn” to select whether 3rd or 5th
harmonic detection is utilized for detection of overexcitation condition
(1-5th harmonic, 0-3rd harmonic). It is, however, possible to set the
protection in a way that when any phase detects the third or fifth harmonic
not only the phase with the inrush current, but also the remaining phases
of the percent differential protection are blocked. This is achieved by
cross-blocking the differential protection for a certain period to avoid
spurious tripping. The setting corresponds to "3rd/5thHBlkTime". Within
this time, all three phases are blocked as soon as an 3rd or 5th harmonic is
detected in any one phase. After the timer is expired, only the phase with
3rd or 5th harmonic content is blocked.
The detection method used for 3rd or 5th harmonic is similar to those
applied for 2nd harmonic. However, setting “3rd/5thHRestrCoef” is
decisive in this case. It means that 3rd or 5th harmonic is recognized if the
ratio between third or fifth harmonic and the fundamental frequency
component of the differential current exceeds the setting threshold. The
ratio is calculated by the below equation.
I diff  3 / 5
 K 3 / 5
I diff 
39
Where, Idiff-φ3/5 is the 3rd/5th harmonic magnitude of differential current,

Kφ3/5 is the setting of the 3rd/5th harmonic ratio, Idiff-φ is fundamental
wave component of differential current. Below figure shows logic diagram
of overexcitation stabilization.
DiffFcnOn=1
“DiffOn”=1 &
“OEBlkDiff”=1
“OE5thHOn”=0
“OE5thHOn”=1
≥1 3rd5thHBlkDiff
I diff  A 3 &

 K  3 / 5 &
I diff  A
≥1 ≥1 PerDiffBlockPhaseA
I diff  A 5 &
 K  3 / 5 T
I diff  A
I diff  A 3 &

 K  3 / 5
I diff  A &
≥1 ≥1 PerDiffBlockPhaseB
I diff  A 5 &
 K  3 / 5
I diff  A T
I diff  A 3 &

 K  3 / 5
I diff  A &
≥1 ≥1 PerDiffBlockPhaseC
I diff  A 5 &
 K  3 / 5
I diff  A T
K 3/5 ：3rd/5thHBlkCoef T：3rd/5thHBlkTime
Figure 25 Logic diagram of excitation characteristics
3.1.6 CT failure supervision

During steady-state operation, the CT failure supervision monitors the
transient behavior of the currents flowing through secondary circuit of each
phase and thus registers failures in the secondary circuit of the current
transformers for each side of the power transformer. The function can be
enabled or disabled by using setting “CTFailDetectOn” (1-On, 0-Off). If
setting “1-On” is applied whenever a CT failure is detected, IED issues the
alarm report. The differential protection can be configured as whether the
blocking is through CT failure by the logic switch "CTFailBlkDiff". By setting
blocking through the logic switch, the percent differential protection is
blocked immediately in all phases when CT failure occurs. Blocking
condition is cancelled as soon as the device is again supplied with a
normal current in the relevant faulty phase(s). It should be noted that this
logic switch is not useful if the differential current is very high (more than
1.2 Ie, Ie is the rated current of high voltage side). In other words, blocking
conditions takes place only for treble slope percent differential protection.
This means that the instantaneous differential protection will issue trip if a
differential current is greater than “InstantDiffCurrSet”, even if even if the
differential protection is blocked by CT.
40
The criteria for CT failure check are as follow:

The currents flowing through all three phases of CT secondary are normal
at each side of the protected object. As a result, the differential current is
near to zero. When one or two phase current of one side is decreased to
less than a threshold (half of the memory current), at the same time all
three phase currents in other side(s) are normal, and at least one phase
current is larger than a threshold (>0.3I_Percent Diff), the condition maybe
an indication of CT failure. CT failure check logic is illustrated in below
figure.
CT Failure Function On
Max {Idiff_A, Idiff_B,

Idiff_C}>0.3*“DiffStartupSet”
In {IHV_A, IHV_B, IHV_C}, only one or two

phase reduce.
&
{IMV_A, IMV_B, IMV_C}和 {ILV_A, ILV_B,
ILV_C} All current is unchanged
CT Failure
In {IMV_A, IMV_B, IMV_C}, only one or
two phase reduce. &
≥
& 1
{IHV_A, IHV_B, IHV_C} 和 {ILV_A,
ILV_B, ILV_C} All current is
unchanged
In {ILV_A, ILV_B, ILV_C}, only one or two

phase reduce.
&
{IHV_A, IHV_B, IHV_C} 和 {IMV_A, IMV_B,
IMV_C} All current is unchanged
Figure 26 Logic diagram of CT failure supervision
3.1.7 CT Saturation supervision

When Internal and external faults occurs, it is possible that transient and
steady fault currents induce the CT saturation. CT saturation may lead to
mal-operation of differential protection when an external fault occurs. In
order to avoid mal-operation of protection in such situations, CT saturation
supervision component is integrated in IED.
When transient saturation of CT occurs, the second harmonic content in
the corresponding phase current is dominant. Also whenever steady
saturation of CT occurs, the 3rd harmonic content in the corresponding
phase current is dominant. Both second and 3rd harmonic contents of all
phase currents of each side of the protected transformer are calculated to
judge whether CT saturation occurs or not. Comprehensive harmonic ratio
is calculated by below equation.
41
I 2 I 3
  K har
I I
Where:
Iφ2 is the secondary harmonic of current on each side;
Iφ3 is the third harmonic of current on each side;
Khar is the setting of comprehensive harmonic ratio, and the fixed setting
of software.
If the second and 3rd harmonic contents of any phase current are more
than Khar, then CT satisfies the above formulas and it is saturated. Before
the CT saturation status, there usually is a short time period in which CT
still works in its linear characteristic. By very fast CT saturation detection of
IED, it needs only 4ms before any CT saturation happening to detect the
fault which is internal or external fault. In order to distinguish saturation
caused by internal faults and external faults effectively, percent differential
protection based on sample values is used. If CT saturation is induced by
external fault, differential protection will be blocked. However if CT
saturation is induced by internal fault, differential protection will send its trip
signal.
The typical saturation figure of phase A CT saturation is shown in below
figure.
Figure 27 Typical phase A current transformer Saturation waveform
3.1.8 Differential current supervision

In normal operation condition, zero differential current is assumed in each
phase. The differential current supervision monitors the differential
currents and checks its value to be less than a threshold. An alarm report
is generated as “DiffCurrOverLmtAlarm” after 5s, if the differential current
exceeds the threshold value. The alarm is an indication of miss-connection
in CT secondary windings, and therefore is released to remind user to
detect the faulty connection in secondary circuit and remove it. This
function can be enabled or disabled by the logic switch "DiffOn" (1-on,
0-off). The fixed threshold for releasing alarm is 0.3 “DiffStartupSet”.
However, to avoid incorrect alarm, the threshold value will increase to
0.05A (1A CT) and to 0.25A (5A CT) if 0.3 times of "DiffStartupSet "
<0.05In.
Logic of differential current supervision is shown in below figure.
42
DiffFcnOn =1
“DiffOn”=1
Idiff_A>ID.alarm
Idiff_B>ID.alarm ≥1 & 5s Differential Alarm
Idiff_C>ID.alarm
Figure 28 CT Fail detection logic

DANGER: Before Differential protection is put into operation on site,
polarity of current transformer must have been checked right by an
energizing test of every side of the transformer or a test of simulating an
external fault of the side in primary system. Otherwise a mal-operation
may occur during an external fault.
3.1.9 Differential protection of variables

Variable value differential protection takes the characteristic of percentage
restraint, which can enable or disable by the logic switch “VarDiffOn”. The
calculation of the percentage restraint is different from the percentage
differential and has the characteristics of inrush current, over excitation
and CT bleak blocking.
Calculating methods of differential and restraint current are as follow:
N
I diff = 
i
Ii
1
N
1
Ires =  Ii  Ifd
{ 2 i 1
Idiff is the differential current; Ires is restraint current; Ii is the

I fd
variable value of each side that caused differential protection; is the
floating threshold of current variable value.
The trip characteristic is shown in below figure.
I Differential
Operating area
range
Differential
current
slope2=0.8
slope1=0
Variables Restraint
differential starting area
value
IRestraint
IRestraint inflection point Restraint

1=0.4*I2N-HV Current
Figure 29 Differential protection characteristics for variables
43
As a summary of the fault detection using operating characteristics of the

above figure, the calculated differential and restraint currents, IDiff and
IRest, are compared by the differential protection with the operating
characteristic according to the following formula,
I diff  IT I diff  0.4I 2 N  HV 

I diff  K 2(I res  0.4I 2 N  HV )  IT 0.4I 2 N  HV  I res 
(Variables differential starting value）is Min 0.4I 2 N  HV ， I D ）+ I fd ，

IT
I 2 N  HV , which is Secondary rated current at high voltage side. I D is
“DiffStartupSet“. I fd is floating threshold. The slope of the first broken

line is fixed as 0, the second 0.8.
The detection is in accordance with phase, and when any phase meets
above conditions, variable differential protection trips. This protection is
under inrush current and overexcitation blocking. When choosing
"CTFailBlkDiff", the variable differential protection is blocked after CT
failure. If the differential current is greater than 1.2 I e , the variable
differential protection is unblocked.
Note: Differential variable value protection will only open 2 frequency
current time after break variable and differential start.
This principle protection is free from detection.
3.2 Setting list

Table 11 Differential protection setting
Default
Range
No. Setting name value Unit Remark
(In:5A/1A)
(In:5A/1A)
InstantDiffCurrSet Differential Tripping
1. 0.5In~20In 20 A
Current setting(ID>>)
DiffStartupSet Differential Startup
2. 0.05In~4In 2 A
Current Setting
BreakPoint1CurrSet The current setting of
3. 0.1In~In 0.6 A
first break point (IR1)
BreakPoint2CurrSet The 2nd breakpoint
4. 0.1In~10In 2 A
restraint current (IR2)
Ratio restraint
5. Slope1RatioRestrCoef 0.00~0.2 0.2 coefficient of the first
slope
Ratio restraint
6. Slope2RatioRestrCoef 0.2~0.7 0.5 coefficient of the
second slope
Ratio restraint
7. Slope3RatioRestrCoef 0.25~0.95 0.7 coefficient of the third
slope
2ndHRestrCoef Second
8. 0.05~0.80 0.15
harmonic(HAR) ratio
3rd/5thHRestrCoef Third or fifth
9. 0.05~0.80 0.35
harmonic(HAR) ratio
Within the delay
2ndHCrossBlkTime second harmonic
10. 0.00~20 20 s
block all three phases.
After the delay, then
44
Default
Range
No. Setting name value Unit Remark
(In:5A/1A)
(In:5A/1A)
only the local phase is
blocked.
Within the delay fifth
harmonic block all
11. 3rd/5thHBlkTime 0.00~20 20 s three phases. After the
delay, then only the
local phase is blocked.
Table 12 Differential protection logic switch
Default
No. Logic switch name Set mode Remark
value
DiffOn Enable ratio differential
1. 0/1 0
protection 1-enable, 0-disable
Enable differential
2. InstantaneousDiffOn 0/1 0 instantaneous protection
1-enable, 0-disable
3. CTFailDetectOn 0/1 0 CT failure test is on 1-On, 0-Off
CTFailBlkDiff CT failure blocking differential

4. 0/1 0
1-blocking, 0-unblocking
Inrush blocking differential
5. ExcitInrushBlkDiff 0/1 0 protection
1-block; 0-not block.
Second harmonic restraint
2ndHRestr 1-2nd harmonic restraining on;
6. 0/1 0
0- fuzzy identification restraining
on
OEBlkDiff Overexcitation block differential
7. 0/1 0
protection 1-block; 0-not block.
Overexcitation stabilization
OE5thHOn judgment 3rd or 5th harmonic
8. 0/1 0
(HAR) inhibit on
1-5th harmonic; 0-3rd harmonic.
Eliminate calculated 3I0 when
HVSideDeltaMinus3I0 HV side winding is connected in
9. 0/1 0
Delta mode
1- eliminate; 0-not eliminate
MVSideDeltaMinus3I0 MV side winding is connected in
10. 0/1 0
Delta mode 1- eliminate; 0-not
eliminate
LVSideDeltaMinus3I0 LV side winding is connected in
11. 0/1 0
Delta mode 1- eliminate; 0-not
eliminate
VarDiffOn Differential protection of
12. 0/1 0
variables 1-enable, 0-disable
3.3 Report list

Table 13 Report list
No. Report name Remark

Trip report:
1. DiffPhATrip
Three-slope ratio differential phase A/B/C trip
2. DiffPhBTrip
45
No. Report name Remark

3. DiffPhCTrip
4. InstantDiffPhATrip
Instantaneous Differential protection (ID>>)
5. InstantDiffPhBTrip
trip for phase A/B/C
6. InstantDiffPhCTrip
7. VarDiffPhATrip
8. VarDiffPhBTrip Differential protection of variables trip A/B/C
phrase
9. VarDiffPhCTrip
Alarm report:
1. HVSide1CTFail
2. HVSide2CTFail
3. MVSide1CTFail
4. MVSide2CTFail
5. LVSide1CTFail
6. LVSide2CTFail
7. LVSide3CTFail
8. DiffCurrOverLmtAlarm Imbalance differential current alarm
9. 2ndHBlkDiff
10. 3rd/5thHBlkDiff
3.4 Technical parameter

Note: In is CT rated secondary current, 1A or 5A.
Table 14 Technical parameter for differential protection
Content Range and value Error
Instantaneous differential current 0.5In to 20.00In ≤ ±3% setting or ±0.02In
Percentage differential current 0.05In to 4.00In ≤ ±3% setting or ±0.02In,
Restraint current 1 0.1In to 1In ≤ ±3% setting or ±0.02In
Restraint current 2 0.1In to 10In ≤ ±3% setting or ±0.02In
Slope 1 0.0 to 0.2
Slope 2 0.2 to 0.7
Slope 3 0.25 to 0.95
0.05 to 0.80 fundamental
Second harmonic restraint ratio
wave
Third or fifth harmonic restraint
0.05 to 0.80
ratio
Reset ratio of restrained
About 0.7
differential
it ≤ 30ms when the setting
Operating time of restraint
is in 200% times, and
differential
IDifferential>2IRestraint
Typical trip time is 20ms
Operating time of instantaneous
when the setting is in
differential
200% times
Reset time about 40ms
46
Chapter 6 Chapter 1Restricted earth fault protection
(87REF)
Chapter 6 Restricted earth fault

protection (87REF)
About this chapter

parameter of restricted earth protection.
47
(87REF)
1 Overview
The restricted earth fault protection detects earth faults in power
trans-formers with earthed starpoint or in non-earthed power transformers
with a starpoint former (earthing transformer/reactor) installed inside the
protected zone. A precondition for using this function is that a CT should be
installed in the starpoint connection, i.e. between the starpoint and earth.
The starpoint CT and the phase CTs define the limits of the protected zone
by restricted earth fault protection.
parallel.

The input and output signals of restricted earth fault protection function are
shown as below, the left side is input signals and right side is output
signals:
Restricted Earth-Fault
Differential Protection
1 1
BIBlk Trip
2 2
Ena_*REF Alarm
Figure 30 The input and output signals of restricted earth fault protection function
diagram
Input:
BIBlk BIBlk
REF Output:
Trip Restricted earth fault protection trip
Alarm Restricted earth fault current is over limit
Input:
"HVSideREFConn": Ena_HVREF,the corresponding
hard connector is Ena_HVREF_5
ENA_Function "MVSideREFConn":Ena_MVREF,Hard connector is
Ena_*REF
Ena_MVREF_5
"LVSideREFConn": Ena_LVREF,the corresponding
hard connector is Ena_LVREF_5
The IED provides restricted differential protection function which can be
used independently at various locations. For example, it is possible to use
48
(87REF)
them for both windings of YNyn transformer which is earthed at both
starpoints. Further, one of them can be implemented to protect an earthed
transformer winding and the other for an earthing transformer/reactor. In
case of auto-transformers, one of them is sufficient to protect the
auto-windings. Examples for some of applications are illustrated in the
below figure.
HV LV
I A.2
A a
IB.2
B b
IC .2
C c
3I02  IA.2  IB.2  IC .2

3I01
CSC-326
Figure 31 Application of restricted earth fault protection on an earthed transformer

winding
HV LV
Ia .2
A a
Ib .2
B b
Ic.2
C c
3I01

3I02
  Ia .2  Ib .2  Ic.2
CSC-326
Figure 32 Application of restricted earth fault protection on an earthed transformer

winding
49
(87REF)
HV LV
I A.2
Ia .2
A a
IB.2
Ib .2
B b
IC .2 Ic.2
C c
3I01 3I01

3I02  IA.2  IB.2  IC .2
CSC-326
3I02
  Ia .2  Ib .2  Ic.2
Figure 33 Application of restricted earth fault protection on both sides of transformer
I A.2
A Ia.3
a
IB.2
Ib .3
B
b
IC .2
C Ic .3
c
3I01
3I02  IA.2  IB.2  IC .2

CSC-326
3I03  Ia.3  Ib.3  Ic.3
Figure 34 Application of restricted earth fault protection on an auto-transformer

Under proper operation condition, no neutral point current 3I0 flows
through the neutral point CT. Furthermore, the sum of the phase currents
3I02 =IA.2 + IB.2 + IC.2 which is almost zero. In case of auto-transformer,
both the neutral point currents 3I02 =IA.2 + IB.2 + IC.2 and 3I03 =IA.3 +
IB.3 + IC.3 are zero. With an earth fault inside the protected zone, a
neutral point current 3I01 flows.
Moreover, depending on the earthing conditions of the power system
outside the protected zone, a further earth current may be recognized in
the residual current path of the phase CTs (3I02 and 3I03). Since all the
currents flowing into the protected zone are defined positive, the residual
current from the system (3I02 and 3I03) is more or less in phase with the
neutral point current (3I01). With an earth fault outside the protected zone,
a neutral point current 3I01 flows into the protected zone, together with
equal residual current 3I02 and 3I03 which flows toward outside of the
50
(87REF)
protected zone, through the phase CTs. The direction of the current flowing
into the protection zone is the positive one, the neutral point current is in
phase opposition with 3I02 and 3I03.
With the described situations, it may seem to be simple to discriminate an
internal fault from an external one. With the described situations, it may
seem to be simple to discriminate an internal fault from an external one.
However, there are some difficulties to do so. For instance, when a strong
fault without earth connection occurs outside the protected zone, a
residual current may appear in the residual current path of the phase CTs.
The residual current is caused by different degrees of saturation in phase
CTs and could simulate a fault in the protected zone. Thus, additional
measures should be taken to prevent this current to cause false tripping.
To achieve this objective, the restricted earth fault protection provides a
restraint quantity.
The differential current Idiff0 and restricted current Irest0 are calculated as
the following equation:
 I diff 0  3I01  3I02  3I03




 I rest0  max 3I01 , 3I02 , 3I03 
Idiff0 and Irest0 are compared by the restricted earth fault protection with a
dual-slope operating characteristic defined by below equation and shown
in below figure.
I diff 0  I 0 D
 if I res0  I 0 D / S 0 D
 )
I diff 0  S 0 D  I res0
 if I res0  I 0 D / S 0 D
Where, I0D is the setting of sensitivity threshold of restricted earth fault

protection (the setting is “REFStartupCurr”), and S0D is slope ratio of
restricted earth fault (the setting is "REFRestrCoef”).
This characteristic can be enabled or disabled by using logic switch
(“REFTrip”). If setting “1-on” is selected, a trip signal is issued by restricted
earth fault protection when the operating point lies into tripping area (see
below figure) and the preset time delay is expired.
The trip logic for restricted earth fault protection is shown in below figure.
I Diff0
Trip Area
Slope _ REF
Restraint
Earth Fault Restraint Area
Startup
Current
I Res0
Figure 35 Characteristic of restricted earth fault protection
51
(87REF)
“REFTrip”=1
REFProtFcnOn=1 T1 Restraint Earth Fault

& Trip
“REFAlarm”=1 T2 Restraint Earth Fault

& Trip is over limit
Idiff0 > “REFAlarmCurr”
T1：“REFTripTime” T2：“REFAlarmTime”
Figure 36 Tripping logic of the restricted earth fault protection

To clarify the proper operation during various situations, three important
operating conditions are examined.
External fault under undisturbed conditions:
3I01 flows into protection zone, 3I02 flows out of protection zone,
according to the definition of the positive direction of current, 3I02 shall be
a minus, which means 3I02 = –3I01.
Idiff0 = |3I01 + 3I02| = |3I01 – 3I02|= 0
Ires0 = max {|3I01|, |3I02|} = |3I01|
No differential current (Idiff0 = 0), the restricted current (Irest0) is the
external fault current flowing into the neutral point.
Internal fault, fed only from the starpoint:
In this case, 3I02=0, thus,
Idiff0 = |3I01 + 3I02| = |3I01 + 0| = |3I01|
IIres0 =Max{|3I01|, |3I02|} = |3I01|
Both the tripping (Idiff0) and the restraint (Irest0) quantities correspond to
the fault current flowing through the starpoint.
Internal fault, fed from the starpoint and from the system, e.g. with equal
earth current magnitude:
Both 3I01 and 3I02 flow into the protection zone, they are positive,
therefore, 3I02 = 3I01.
Idiff0 = |3I01 + 3I02 |= |3I01 + 3I02 |= 2 ×|3I01|
Ires0 = max {|3I01|, |3I02|} = |3I01|
Tripping quantity (Idiff0) corresponds to double the fault current flowing
through the starpoint connection, and restraint quantity (Irest0) is equal to
the fault current.
The results show that the device is capable to properly discriminate
internal and external earth faults by using the definitions proposed for
differential and restraint current. However, the device is still subjected to
some influences that induce differential currents even during normal
operation condition. These influences should be compensated in
appropriate manner. The specific treatments designed to cope with these
influences includes automatic ratio compensation which is explored as
52
(87REF)
follows.
Restricted earth fault protection represents some problems in the
application of current transformers regarding to matching between phase
and starpoint CTs. The problem is originated from different ratio of phase
and starpoint CTs. The difference may result in a differential current in
normal operation condition. To remove this problem, the input currents of
the relay from starpoint CTs should be converted according to primary
rated currents of phase and starpoint CTs. In the IED, this objective is
achieved by taking a common reference value and converting all
secondary currents of starpoint CTs into the same reference. The
conversion is per-formed by calculation of ratio compensation factor for
starpoint CTs. The compensation factors are then multiplied by the
secondary current of starpoint CTs to make them comparable with those
current measured at phase CTs. The conversion procedure is performed
inside the device. For ordinary transformers, the corresponding number of
zero differential protection modules are configured according to the
measurement numbers of restricted earth fault protection needed to be
configured. The I3/I4 current input is 0. The ratio compensation factors of
secondary currents of starpoint CTs of ordinary transformers are
calculated as follow:
nStarpo int W 1
K Starpo int W 1  (3)
nPhaseW 1
Where, K Starpo int W 1 is the ratio compensation factor for winding 1
For autotransformer, in addition to the common winding starpoint CT, the

measured current from phase winding of winding 2 (MV winding) should
also be converted to the common reference current. In this context, the
ratio compensation factors are calculated as follow:
nPhaseW 2
KW 2  (4)
nPhaseW 1
nStarpo int
K Starpo int  (5)
nPhaseW 1
Where, KW 2 is the ratio compensation factor for winding 2 (MV winding)

phase CT, K is the ratio compensation factor for common winding
Starpo int
starpoint CT.
53
(87REF)
3.1.3 Positive sequence current blocking
CT2 HV LV
I A.2
A a
IB.2
B b
IC .2
C c
3I02  IA.2  IB.2  IC .2

3I01
CSC-326
Figure 37 Logic program of positive sequence current blocking

When an external fault causes a heavy current to flow through the
protected device, differences in the magnetic characteristics of the current
transformer CT2 under saturation condition may cause a significant
difference in the secondary currents I02 connected to the IED. If the
difference is greater than the pickup threshold, the REF protection function
can trip even though no fault occurred in the protected zone. To prevent
the protection function from such erroneous operation, a restraint
(stabilizing) ratio, zero-sequence current divides positive-sequence current,
is brought in.
I0
 15% (6)
I1
Where, I0 is zero-sequence current, I1 is positive-sequence current.
Only when the ratio is greater than 15% can the REF protection trip.
3.1.4 Restricted earth fault current alarm
In normal operation condition, zero differential current is expected for
restricted earth fault protection. The restricted earth fault current
supervision monitors Idiff0 and detects whether its value is less than the
threshold or not. If the differential current exceeds the setting
“REFAlarmCurr”, then an alarm report “REFCurrOverLmt” will be issued
after the delay time "REFAlarmTime" is up. The alarm is an indication of
miss-connection in phase or starpoint CT secondary windings, and
therefore is released to remind user to detect the faulty connection in
secondary circuit and remove it. The function can be enabled or disabled
by using setting “REFAlarm". Current setting range of restricted earth fault
protection alarm is 0.05In~2In, because the unbalanced current exists in
the operation of the system, if the setting value is too small, there may be a
problem of false alarm.
DANGER: Before earth fault protection is put into operation on site, polarity
of CT of neutral point must has been checked right by an energizing test of
every side of the transformer or a test of simulating an external fault of the
side in primary system. Otherwise a mal-operation may occur during an
external fault.
54
(87REF)
3.2 Setting list
Table 16 Restricted earth fault protection of high voltage side setting
Default
Range
Number Setting name value Unit Remark
(In:5A/1A)
(In:5A/1A)
1. HVSideREFStartupCurr 0.05In~2In 2 A
2. HVSideREFAlarmCurr 0.05In~2In 2 A
3. HVsideREFRestrCoef 0.2~0.95 0.5
4. HVsideREFTripTime 0~60 0.03 s
5. HVsideREFAlarmTime 0~60 0.03 s
Table 17 Restricted earth fault protection of medium voltage side setting

Range Default value
Number Setting name Unit Remark
(In:5A/1A) (In:5A/1A)
1. MVSideREFStartupCurr 0.05In~2In 2 A
2. MVSideREFAlarmCurr 0.05In~2In 2 A
3. MVSideREFRestrCoef 0.2~0.95 0.5
4. MVSideREFTripTime 0~60 0.03 s
5. MVSideREFAlarmTime 0~60 0.03 s
Table 18 Restricted earth fault protection of low voltage side setting

Default
Range
(In:5A/1A)
(In:5A/1A)
1. LVSideREFStartupCurr 0.05In~2In 2 A
2. LVSideREFAlarmCurr 0.05In~2In 2 A
3. LVSideREFRestrCoef 0.2~0.95 0.5
4. LVSideREFTripTime 0~60 0.03 s
5. LVSideREFAlarmTime 0~60 0.03 s
Table 19 Restricted earth fault protection of high voltage side logic switch
Set Default
Number Logic switch name Remark
mode value
Enable restricted earth fault
1. HVSideREFProtTrip 0/1 0 protection of high voltage side trip
1-On, 0-Off
Enable high restricted earth fault
2. HVSideREFAlarm 0/1 0 protection alarm
1-On, 0-Off
CT failure blocking restricted earth
3. CTFailBlkHVSideREF 0/1 0 fault protection
1-On, 0-Off
55
(87REF)
Table 20 Restricted earth fault protection of medium voltage side logic switch
Set Default
mode value
MVSideREFProtTrip protection of medium voltage side
1. 0/1 0
trip
1-On, 0-Off
MVSideREFAlarm protection alarm of medium
2. 0/1 0
voltage side
1-On, 0-Off
CT failure blocking restricted earth
CTFailBlkMVSideRE fault protection of medium voltage
3. 0/1 0
F side
1-On, 0-Off
Table 21 Restricted earth fault protection of low voltage side logic switch
Set Default
mode value
Enable restricted earth fault protection
1. LVSideREFTrip 0/1 0 of low voltage side trip
1-On, 0-Off
Enable restricted earth fault protection
2. LVSideREFAlarm 0/1 0 alarm of low voltage side
1-On, 0-Off
CT failure blocking restricted earth fault
3. CTFailBlkLVSideREF 0/1 0 protection of low voltage side
1-On, 0-Off
3.3 Report list

Number Report name Remark

Trip report:
1. HVSideREFTrip /
2. MVSideREFTrip /
3. LVSideREFTrip /
Alarm report:
1. HVSideREFCurrOverLmt /
2. MVSideREFCurrOverLmt /
3. LVSideREFCurrOverLmt /

Table 23 Restricted earth fault protection technical parameter
Differential current 0.05In to 2.00In ≤±3% setting or 0.02In
Slope 0.2 to 0.95
≤ ±1% setting or +40ms,
Time delay 0.00 to 60.00s, step 0.01s when trip value is set as
200% setting
Reset ratio Approx. 0.7, at tripping
56
(87REF)
≤ 30ms when the setting is in 200%
Trip time
times
Reset time About 40ms
57
Chapter 7 Chapter 1Impedance protection (21)
Chapter 7 Impedance protection (21)
About this chapter

output signals, setting parameters, messages and technical
parameters.
59
1 Overview
The sub-transmission lines are extended, including lots of branches and
different distance lines, so the situations are complicated. This kind of
system has higher requirement for fault isolating, in order to sustain the
stability and safety of power system.
The configuration of impedance protection can meet basic requirements of
transformer and transmission line. This protection function has the
following characteristics:
1) If the voltage connector of local side is disabled, the impedance
protection function of local side will be disabled.
2) It provides phase-to-phase and phase-to-earth impedance protection
of 1 stage 3 times, the fourth stage provides only 1 time.
3) The protective function can be disabled through the function connector.
connector, soft-hard series, soft-hard parallel, and the default is
soft-hard parallel.

The input and output signals of impedance protection function are shown
as below, the left side is input signals and right side is output signals:
Impendance Protection
1 1
BIBlk Dis_PP_Trip1
2 2
Ena_*Dis Dis_PP_Trip2
3 3
Ena_*Voltage Dis_PP_Trip3
4
Dis_PN_Trip1
5
Dis_PN_Trip2
6
Dis_PN_Trip3
Figure 38 The input and output signals of impedance protection function diagram
Input:
BIBlk BIBlk
Output:
DISPP
Dis_PP_Trip1 Phase-to-phase impedance time 1 trip

Input:
DISPN BIBlk BI blocking
Output:
60
Dis_PN_Trip1 phase-to-earth impedance trip 1
Input:
"HVSideImpedConn":Ena_HVDis,the
ENA_Function corresponding hard connector is Ena_HVDis_5
Ena_*Dis
"MVSideImpedConn":Ena_MVDis,the
corresponding hard connector is Ena_HVDis_5
Input:
"HVSideVoltConn":Ena_HVoltage,the
ENA_*Voltage corresponding hard connector is Ena_HVoltage_5
Ena_*Voltage
"MVSideVoltConn":Ena_MVoltage,the
corresponding hard connector is Ena_MVoltage_5
Protection startup component: there are abrupt current startup component
and negative current startup component, where the abrupt current startup
component is equal to the main protection, and the negative current
startup component is as follows:
 I 2  I Qd 2



 I Qd 2＝0.2 I e
Where: I 2 is the effective value of negative current, I Qd 2 is the fixed

threshold, I e rated current for transformer.
Distance measurement component: the action characteristics of
phase-phase impedance protection and phase-to-earth impedance
protection can be fixed as full-impedance characteristics or offset
impedance characteristics.
78°to 90°distance sensitivity angle can be fixed.
Phase-to-phase impedance protection can adopt 0° connection, and the
voltage selects the phase-to-phase voltage, and the current takes the
     
corresponding phase current. For example U  U A  U B , I  I A  I B , are

used to calculate the corresponding AB phase-to-phase distance, and BC
phase-to-phase impedance is similar to CA phase-to-phase impedance.
Phase-to-earth also adopts 0° connection, the AC quantity is taken from
the CT and VT, whose equation is as follows:

U
Z jd   
I   K 3 I 0
  
where: U  is phase-to-earth voltage, I  is phase current, 3 I 0 is
calculated zero sequence current, K is zero sequence compensation
61
coefficient, in which the phase-to-earth impedance zero compensation

coefficient K pointing to the main transformer is fixed as 0, and the
phase-to-earth impedance zero compensation coefficient K pointing to the
busbar can be fixed by the setting.
When the software calculates, it regularly adopts the compensation
coefficient K as 0 to calculate the phase-to-earth impedance, and makes
the compensation for the setting of phase-to-earth impedance pointing to
busbar (whose zero sequence compensation coefficient can be fixed). The
specific implementation is as the following analysis
jX jX
Z1 Z1
φ φ
R R
Z2
Z2P
a) b)
Figure 39 The trip characteristics of impedance components
The operation characteristics of impedance protection is shown as figure
above (φ is the sensitivity angle), in which figure a) is the circular
characteristics corresponding to the impedance setting fixed according to
the actual operation; b) is the impedance circular characteristics. where:
Z1 is the value of phase-to-earth impedance pointing to main transformer,
Z2 is the value of phase-to-earth pointing to busbar, and the both can be
fixed; Z2P is the value after the compensation of phase-to-earth
impedance Z2 pointing to busbar, automatically calculated by the software.
As for phase-to-earth impedance pointing the main transformer, without
considering its protection range extending to the opposite busbar, its
corresponding phase-to-earth impedance do not consider the zero

U
compensation, and the impedance calculated by the equation Z jd  
I
is matched with the actual setting protection value; as for the
phase-to-earth impedance, Z2 is matched with the impedance value

U
calculated by the equation Z jd    ; a conversion relation
I   K 3 I 0
between the equation and the equation used in the actual calculation:
   
U U I I
Z jd   
 
  
 Z jd   
 Z jd  M ,
I  K 3I 0 I I  K 3I 0 I  K 3I 0
62
Corresponding to the use of unified equation, the setting of Z1 remains

unchanged, and Z2 needs to consider to compensation; that is:
  .
I   K 3 I 0
Z 2 P  Z 2 / M  Z 2  
I
In fact, considering that the phase-phase impedance protection can

accurately measure the phase-phase fault and three-phase fault,
phase-to-earth protection need to consider certain compensation, if the
single-phase phase-to-earth needs to be measured correctly, therefore,
phase-to-earth impedance protection as the supplement of phase-phase
impedance protection, is mainly used to detect the single-phase
 
phase-to-earth fault. Because while single-phase is ground, I  ＝ 3 I 0 ,
1 1
then M can be simplified as a real number, that is M  ,  1 K .
1 K M
The influence of VT failure and voltage clamp on the protection
While the local side VT failure happens, the impedance protection
functions of the local side need to be blocked.
Influence of the voltage connector on protection.
If the voltage connector of local side is disabled, the impedance protection
function of local side will be disabled.
Oscillation blocking component
In order to avoid the impedance protection mis-operation during the
oscillation, the impedance protection is equipped with oscillating blocking
component.
Impedance protection can be set as blocked by swing or not by swing
respectively according to time.
When the fault occurs again during the oscillating process, it is equipped
with oscillating blocking opening component and the abrupt startup open
regularly within 150ms in order to ensure the correct operation of
impedance protection; in addition, opening component with asymmetric
fault and symmetric fault are input conditionally.
3.2 Logic diagram

The logic of phase-phase impedance protection and phase-to-earth
impedance protection is the same, and the 1st stage impedance protection
logic is as the figure:
63
Voltage connector of local side=1
“PPZ1On/PEZ1On”=1
I2>0.2Ie ≥1 &
T1 Phase-to-phase/
phase-to-earth
△iφ>0.2IN zone 1 trip
Zφ is within the
area
VT Failure
ImpedProtFcnOn
T：“PPZ1Time/PEZ1Time”
Figure 40 1st stage impedance protection logic diagram
3.3 Setting list

Table 25 Impedance setting on high voltage side
Default
Number Setting name Range Unit Remark
value
1. PPZSensitiveAngle 78~90 80 .
2. HVSidePEZSensitiveAngle 78~90 80 .
3. HVSidePPZ1PointToTransf 0.1~125 10 Ω
7. HVSidePPZ1PointToSystem 0.1~125 10 Ω
11. HVSidePPZ1Time1 0.1~20.0 20 s
13. HVSidePPZ1Time3 0.1~125 10 Ω


20. HVSidePPZ4Time 0.1~20.0 20 s
21. HVSideImpedRstTime 0.02~20.0 0.04 s
22. HVSidePEZ1PointToTransf 0.1~125 10 Ω
64
Default
value
26. HVSidePEZ1PointToSystem 0.1~125 10 Ω
30. HVSidePEZ1K0 0~1 0.67
34. HVSidePEZ1Time1 0.1~20.0 20 s
43. HVSidePEZ4Time 0.1~20.0 20 s
Table 26 Distance protection logic switch

Default
Number Logic switch name Set mode Remark
value
1. HVSidePPZ1Time1On 0/1 0
4. HVSidePPZ1BlkByPowerSwing 0/1 0
65
Default
value
13. HVSidePPZ4On 0/1 0
15. HVSidePEZ1Time1On 0/1 0
18. HVSidePEZ1BlkByPowerSwing 0/1 0
27. HVSidePEZ4On 0/1 0
Table 27 Impedance setting on medium voltage side

Default
value
1. PPZSensitiveAngle 78~90 80 .
2. MVSidePEZSensitiveAngle 78~90 80 .
3. MVSidePPZ1PointToTransf 0.1~125 10 Ω
7. MVSidePPZ1PointToSystem 0.1~125 10 Ω
66
Default
value
11. MVSidePPZ1Time1 0.1~20.0 20 s
13. MVSidePPZ1Time3 0.1~125 10 Ω
20. MVSidePPZ4Time 0.1~20.0 20 s
21. MVSideImpedRstTime 0.02~20.0 0.04 s
22. MVSidePEZ1PointToTransf 0.1~125 10 Ω
26. MVSidePEZ1PointToSystem 0.1~125 10 Ω
30. MVSidePEZ1K0 0~1 0.67
34. MVSidePEZ1Time1 0.1~20.0 20 s
43. MVSidePEZ4Time 0.1~20.0 20 s
67
Table 28 Distance protection logic switch

Default
value
1. MVSidePPZ1Time1On 0/1 0
4. MVSidePPZ1BlkByPowerSwing 0/1 0
13. MVSidePPZ4On 0/1 0
15. MVSidePEZ1Time1On 0/1 0
18. MVSidePEZ1BlkByPowerSwing 0/1 0
27. MVSidePEZ4On 0/1 0
68
3.4 Report list


Trip report:
1. HVSidePPZ1Time1Trip /
10. HVSidePPZ4Trip /
11. HVSidePEZ1Time1Trip /
20. HVSidePEZ4Trip /
21. MVSidePPZ1Time1Trip /
30. MVSidePPZ4Trip /
31. MVSidePEZ1Time1Trip /
40. MVSidePEZ4Trip /
69

Table 30 Distance protection technical parameter
≤± 5.0% static accuracy or ±0.1Ω
0.1Ω～25Ω, step 0.01Ω, when In=5A Condition
Distance setting range
0.5Ω～125Ω, step 0.01Ω, when In=1A Voltage range: 0.01Ur to 1.2Ur
Current range: 0.12In to 20In
≤±1% or+40ms, below the 70%
Time delay 0.00s to 100.00s, step 0.01s
of setting
Dynamic overreaching ≤±5%, when 0.5<SIR<30
70
Chapter8 Chapter 1Interturn protection (16)
Chapter 8 Interturn protection (16)
About this chapter

This chapter describes the interturn protection (Suitable for
reactor) principle, input and output signals, setting
parameters, reports and technical parameter.
71
1 Overview
Interturn short circuit is a common internal fault form of the reactor. The
device adopts the principle of fault-tolerant recovery to adapt interturn
protection principle.
When the voltage connector is disabled, the interturn protection of reactor
will be disabled.
parallel.

The input and output signals of interturn protection function are shown as
below, the left side is input signals and right side is output signals:
InterTurn Protection
1 1
BIBlk Operation
2
Ena_HVoltage
3
Ena_ITURN
Figure 41 The input and output signals of interturn protection function diagram
Input:
BIBlk BIBlk
ITURN
Output:
Operation Interturn protection trip
Input:
ENA_HVoltage "HVSideVoltConn",the corresponding
Ena_HVoltage
hard connector is Ena_HVoltage_5
Input:
ENA_HVoltage "InterturnConn",the corresponding
Ena_ITURN
hard connector is Ena_ITURN_5
Interturn short circuit is a common internal fault form of the reactor. The
device adopts the principle of fault-tolerant recovery to adapt interturn
protection principle.

The protection adopts zero sequence power directional relay consisting of
the zero sequence current at the end of the main reactor and the zero
sequence voltage of the reactor installed at the reactor, and the related
electrical quantities are fault-tolerant. Due to the interturn short circuit in
72
the reactor, the corresponding terminal measurement value always

satisfies the exceeding zero sequence voltage to zero sequence current,
and the zero sequence reactance measurement value is the zero
sequence reactance of the system. When the external fault (systematical
fault)occurs, the corresponding zero sequence voltage lags behind zero
sequence current. The zero sequence reactance is the zero sequence
impedance of the reactor. Therefore, the phase relationship between the
zero sequence current of the terminal of the main reactor and the zero
sequence voltage of the reactor installation is used to distinguish the
interturn short circuit, the internal grounding fault and the external fault of
the reactor. When the number of short circuited turns is very small, the
zero sequence current and zero sequence voltage are very small in the
zero sequence impedance of the system (the zero sequence impedance
of the system is far less than the zero sequence impedance of the reactor).
Therefore, the zero sequence voltage must be compensated in order to
better distinguish the interturn fault of the small turn number. In order to
eliminate the influence of irrelevant zero flow on sensitivity of inter turn
protection during non-full-phase operation, impedance criterion is used.
The forward direction of zero sequence voltage and zero sequence
current is shown below.
PT
System
*
Reactor CT
Figure 42 Zero sequence voltage and zero sequence current positive direction
definition
The action equation of the zero sequence power directional component is:
(3U 0  K  Z  3I02 )
0  Arg  180 
3I
02
The equation of impedance components:

Z  0.66 Z 2 n
Where: Z is the secondary impedance value of the main reactor, which
is calculated in real time and according to phase identification; Z 2n is the
secondary rated impedance of the main reactor.
In order to ensure reliable operation of interturn protection, CT
disconnection and VT breakage detection components are provided.
When the CT or VT is broken, the interturn protection of the main reactor
is withdrawn.
When the voltage connector is disabled, the interturn protection of reactor
will be disabled.
73
3.2 Logic diagram

“HVSideVoltConn”=1
“InterturnProtFcnOn”=1
The criteria of steady-state &

component and abrupt of Each &
electric quantity satisfy conditions Interturn protection trip
(3U 0  K  Z  3I0 )
0  Arg

 180 ≥1
3I0
Z  0 . 66 Z 2 n
VT failure
≥1
CT failure
Figure 43 Logic diagram of interturn protection
3.3 Setting list

Table 32 Interturn protection setting
Default
value
1. Interturn3I0StartupSet 0.05In~40In 40 A
Table 33 Interturn protection logic switch

Logic switch Default
Number Set mode Remark
name value
1. InterturnProtIsOn 0/1 0
3.4 Report list


Trip report:
1. InterturnTrip /

Table 35 Distance protection technical parameter
Zero sequence startup 0.05In～40.00In ≤ ±2.5% setting or
current ±0.02In
TheMaximumSensitiveAngle 90° 5°
Trip range 20°~160°
Intrinsic time delay Using inverse time characteristic,
the fastest action time is no more
than 100ms.
74
Chapter 9 Chapter 1Overcurrent protection (50, 51, 67)
Chapter 9 Overcurrent Protection

(50, 51, 67)
About this chapter

This chapter describes the overcurrent principle, the input
and output signals, setting value parameters, messages and
technical parameters.
75
1 Overview
When the power system fault occurs, the current of the system increases,
and the overcurrent protection can avoid the damage of the fault current to
the equipment. The device provides three-stage of overcurrent protection
of high, middle and low voltage side, each stage provides options of
overcurrent definite time protection or inverse time protection. Each stage
of overcurrent protection has the same logic criterion, and each stage can
be enabled or disabled independently.
Each stage of the overcurrent protection can be selectively input harmonic
blocking component and directional component, and based on the phase
measurement of the current action. In addition, each stage of the
overcurrent definite-time protection can be selectively input the complex
pressure blocking component.
Main characteristics of overcurrent protection:
1) The device provides 3 stages of overcurrent protection on each high,
medium and low voltage side, each stage adopts definite time or 12
IEC and ANSI standard curve of inverse time characteristic, and it
adopts user defined characteristic curve as well;
2) The flow direction sensitive angle can be adjusted to meet different
application occasions;
3) Each stage of the overcurrent protection can be respectively set
whether it inputs direction component, whether the action area is
"forward" or "reverse" action is set by the logic switch;
whether it’s through harmonic locking;
5) Harmonic blocking can lock across;
6) Each stage of the overcurrent protection can be respectively set as
blocked by composited voltage, and the composited voltage can be
selected from each voltage side;
7) The enabled protection with directional component needs to detect
whether the VT failure of secondary circuit. If VT failure occurs, the
protections with directional component or composited voltage
component can be set as disabling protection or unblocking
protection.
soft-hard parallel.

The input and output signals of overcurrent protection function are shown
as below, the left side is input signals and the right side is output signals:
76
Directional / Non-directional Overcurrent Protection

1 1
BIBlk Start
2 2
Ena_*OC Operation
3 3
Ena_HVoltage PhaseA
4 4
Ena_MVoltage PhaseB
5 5
Ena_L1Voltage PhaseC
6
Ena_L2Voltage
Figure 44 The input and output signals of overcurrent protection function diagram
Input:
BIBlk BI blocking
Output:
Start IED startup

OC
Operation IED trip
PhaseA Phase A trip
PhaseB Phase B trip
PhaseC Phase C trip
Input:
HVSideOCConn:Ena_HVOC,Hard connector is
Ena_HVOC_5
MVSideOCConn:Ena_MVOC,Hard connector
is Ena_MVOC_5
ENA_Function "LVSide1OCConn": Ena_LV1OC,the hard
Ena_*OC
connector is Ena_LV1OC_5
"LVSide2OCConn": Ena_LV2OC,the hard
"LVSide3OCConn": Ena_LV3OC,the hard
Input:
ENA_HVoltage "HVSideVoltConn",the hard connector is
Ena_HVoltage
Ena_HVoltage_5
Input:
ENA_MVoltage "MVSideVoltConn",the hard connector is
Ena_MVoltage
Ena_MVoltage_5
Input:
ENA_L1Voltage "LVSide1VoltConn",the hard connector is
Ena_L1Voltage
Ena_L1Voltage_5
Input:
ENA_L2Voltage "LVSide2VoltConn",the hard connector is
Ena_L2Voltage
Ena_L2Voltage_5
IED is equipped with 3 stages overcurrent protection; please refer to the
77
setting list for details.

3.1.1 Inrush blocking components
When "OC1BlkBy2ndH"=1, carrying out inrush check, the inrush criterion
is shown as below:
I∅2
> “OC2ndHI2/I1Ratio”, (∅ = a, b, c)
I∅
When it is detected that the ratio of second harmonic and fundamental
wave is larger than "OC2ndHI2/I1Ratio" and there is a current, then the
inrush condition is satisfied in the phase.
When it is detected that there is inrush condition, within the
"HarmCrossBlkTime", one phase inrush protection fails and three phase
protection; after the "HarmCrossBlkTime", one phase inrush protection
fails and one phase protection; when the inrush criterion returns, release
each blocking.
When the maximum fundamental wave current of the three phases is
larger than "HarmUnblkOCCurr", release each blocking.
The output blocking state of each phase is caused by inrush blocking of
overcurrent stage 1 phase A, phase B and phase C. Schematic diagram is
shown below:
78
Phase A I2/I1 >“OC2ndHI2/I1Ratio”

≥1
&
Phase B I2/I1 >“OC2ndHI2/I1Ratio”
3 Phase Inrush Current Blocking
Phase C I2/I1 >“OC2ndHI2/I1Ratio”
Time<“HarmCrossBlkTime”
3 Phase Inrush Current Blocking &

Overcurrent Stage1-3 Phase Inrush Current Blocking
“OC1BlkBy2ndH”=1
Phase A I2/I1>“OC2ndHI2/I1Ratio” &

&
Overcurrent Stage1- Phase A Inrush Current Blocking
Time>“HarmCrossBlkTime”
Phase B I2/I1>“OC2ndHI2/I1Ratio” &

&
Overcurrent Stage1- Phase B Inrush Current Blocking
Phase C I2/I1>“OC2ndHI2/I1Ratio” &

&
Overcurrent Stage1- Phase C Inrush Current Blocking
Figure 45 Inrush blocking logic diagram
3.1.2 Compound voltage blocking unit

“OCStage1BlkByVolt” =1, check the voltage. The voltage blocking
component is compound voltage component, including undervoltage and
negative sequence voltage components, composite voltage criterion:
min(Uab, Ubc, Uca) < “PPVoltBlkSet” or U2 > “U2BlkSet”
Where:
When “CVCBlkUseHVS”=1, phase-to-phase voltage Uab, Ubc, Uca and
negative sequence voltage U2 use voltage of high voltage side;
When “CVCBlkUseMVS”=1, phase-to-phase voltage Uab, Ubc, Uca and
negative sequence voltage U2 use voltage of medium voltage side;
When “CVCBlkUseLVS1”=1, phase-to-phase voltage Uab, Ubc, Uca and
negative sequence voltage U2 use voltage of branch 1 of low voltage side;
When “CVCBlkUseLVS2”=1, phase-to-phase voltage Uab, Ubc, Uca and
negative sequence voltage U2 use voltage of branch 2 of low voltage side;
The effect of VT failure on composited voltage component:
If there is VT failure in a certain side, only the composited voltage
detection of the failure side voltage is disabled, the composited voltage of
other voltage sides can be selected for composited voltage detection.
79
If there are VT failures in all the voltage sides, the protection trip can be
selected by “H/M/LSideOC VTFailProtOff”. If “H/M/LSideOC
VTFailProtOff”=0, the composited voltage components is diabled, and it
turns into overcurrent protection. If “H/M/LSideOC VTFailProtOff”=1,
composited voltage component does not meet the condition, then block
overcurrent protection.
If there is no voltage is selected for composited voltage detection, then the
composited voltage components will be disabled, (directional) composited
voltage overcurrent protection turns into (directional) overcurrent
protection.
The effect of voltage connector on composited voltage component:
If the voltage connector of composited voltage selection side is disabled,
the composited voltage detection of this side is disabled (the composited
voltage of other voltage sides can be selected for composited voltage
detection).
Composited voltage detection logic diagrams are as follow:
“HVSideCVCBlkUseHVS”=1
&
min(UHab,UHbc,UHca)<“PPVoltBlkSet”
≥1 Composited voltage component of
high voltage side meets condition
High voltage sideU2>“U2BlkSet”
VT failure on high voltage side
“HVSideCVCBlkUseMVS”=1
“MVSideVoltConn”=1
&
min(UMab,UMbc,UMca)<“PPVoltBlkSet”
medium voltage side meets condition
Medium voltage sideU2>“U2BlkSet”
VT failure on medium voltage side
“HVSideCVCBlkUseLVS1”=1
“LVSide1VoltConn”=1
&
min(UL1ab,UL1bc,UL1ca)<“PPVoltBlkSet”
low voltage side 1 meets condition
Low voltage side 1 U2>“U2BlkSet”
VT failure on low voltage side 1
80
“HVSideCVCBlkUseLVS2”=1
“LVSide2VoltConn”=1
&
min(UL2ab,UL2bc,UL2ca)<“PPVoltBlkSet”
Low voltage side 2 U2>“U2BlkSet”
VT failure on low voltage side 2
All VT failure of
composited voltage side &
“H/M/LVS OC VTFailProtOff”=0
Composited voltage component of

high voltage side meets condition

medium voltage side meets condition
≥1
Composited voltage component of Composited voltage component of
low voltage side 1 meets condition overcurrent stage 1 meets condition

“OCStage1BlkByVolt”=0
Disable all voltage

connector of each side
Figure 46 Logic diagram of the characteristics of multi-voltage component
3.1.3 Directional component

"DirOCStage1"=1, check the direction. Directional components are
connected with a 90°angle, the fault phase direction is determined by the
fault phase current and the line voltage of the sound phase.
Table 37 The judgment of the fault phase direction
Phase Current Voltage
A Ia U bc
B Ib U ca
C Ic U ab
When the three-phase fault occurs, there is no sound phase-to-earth
voltage, which is not enough to judge the fault current direction, so
memory voltage is adopted. Diagram of forward and reverse direction
characteristics of phase A current:
81
FWD 90° IA 90° IA
Bisector Bisector
RVD
Φ Φ
0° 0°
U BC_Ref U BC_Ref
5°
-IA -IA 5°
Figure 47 Forward and reverse direction interval graph

Sensitive angle of directional overcurrent  =Angle: Adjustable;
Positive direction overcurrent range: (-85°~ +85°), reverse direction
overcurrent range: (+95°~ +265°);
Direction discrimination logic diagram is shown below:
Local side VT failure &
“H/M/LVSideOC VTFailProtOff”=0
≥1
Local side voltage connector=0 Directional component of
phase A meets the condition
“DirOCStage1”=0
Phase A is in the forward trip area
Figure 48 Direction discrimination logic diagram

The effects of VT failure on directional components:
In the process of direction detection, the VT failure may lead trips or
alarms that are not consistent with the flow direction detection along each
overcurrent protection stage. When VT fails, the action mode is decided
according to "H/M/LVS OCVTFailBlkProt"; if “H/M/LVS OCVTFailBlkProt”
is set to 1, overcurrent protection with directional component is blocked; if
“H/M/LVS OCVTFailBlkProt” is set to 0, directional component exits and
trips in a pure overcurrent mode.
The effects of voltage connector on directional components:
When the local voltage connector is disabled, the directional component
detection is disabled (directional component meets the conditional
automatically).
For the directional component, the voltage of local side is selected, and the
voltage of low voltage side 2 is selected for the current of the low voltage
side 3.
3.1.4 Definite time
When "OCStage1Curve"=0, overvoltage is the definite time characteristic,
82
inverse time function is disabled.

I∅ > “OCStage1CurrSet”, (∅ = 𝑎, 𝑏, 𝑐)
When the phase-to-earth current is greater than "OCStage1CurrSet", timing
component starts and until "OCSatge1Time”, overcurrent protection trips,
when the phase-to-earth current I∅ < Dropout × ”OCStage1CurrSet” ,
Dropout is dropoff coefficient, timing component returns, overcurrent
protection resets.
3.1.5 Inverse time
When "OCStage1Curve"=1~13, inverse time overcurrent characteristic
trips, definite time function is disabled.
 
 
A
t  B  T
  I  P 
   1 
  Iset  
Where:
A: "InvTimeOCStage1CoefA"
P: "InvTimeOCStage1IndexP"
B: "InvTimeOCStage1TimeB"
T: "InvTimeOCStage1ConstT"
Iφ: Phase current value in the system
Iset: "OCStage1CurrSet"
If the phase-to-earth current exceeds "OCStage1CurrSet", the timing
component starts, inverse time characteristic curve is selected by Curve, A,
P, B are determined when the value is from 1 to 12, see the following Table;
when the value is 13, it is user defined characteristics, calculate the trip
delay according to the setting of the A, P, B, T. while timing is up,
overcurrent protection trips. When the delay is less than the
"InvTimeOCMinTime", the component trip according to the
"InvTimeOCMinTime".
Table 38 Curve definition
Curve Inverse time characteristic A P B

0. Definite time
1. IEC INV. 0.14 0.02 0
2. IEC VERY INV. 13.5 1.0 0
3. IEC EXTERMELY INV. 80.0 2.0 0
4. IEC SHORT TIME INV. 0.05 0.04 0
5. IEC LONG TIME INV. 120.0 1.0 0
6. ANSI INV. 8.9341 2.0938 0.17966
7. ANSI SHORT INV. 0.2663 1.2969 0.03393
8. ANSI LONG INV. 5.6143 1 2.18592
9. ANSI MODERATELY INV. 0.0103 0.02 0.0228
83

10. ANSI VERY INV. 3.922 2.0 0.0982
11. ANSI EXTERMELY INV. 5.64 2.0 0.02434
12. ANSI DEFINITE INV. 0.4797 1.5625 0.21359
13. USER DEFINE
3.1.6 Trip characteristic

When overcurrent protection function is enabled (En=1) and no BI blocking,
if the "OCStage1On"=1 , the overcurrent protection of the corresponding
stage is enabled.
If the action conditions are met, time component starts; take stage 1
protection for example, when time is over, "OCStage1Trip" is issued.
When IED trips each phase trip states will be displayed. LED and
protection trip can be configured by AESP.
When "OC1BlkBy2ndH"=1, the harmonic locking component is put into
operation, when the action timer is time out, the inrush current is checked,
and if the current is not locked, unblock overcurrent trip, otherwise it will
output “InrushBlk” report.
When "OCStage1BlkByVolt"=1, the compound voltage locking component
is put into the device. When the protection is started, the device checks the
compound voltage locking condition, unblock overcurrent protection if it
meets the conditions, otherwise the protection is locked.
When "DirOCStage1"=1, overcurrent protection is with the directional
component, and choose the positive or negative direction characteristic
according to"OCStage1FwdDir", when the directional component is not
satisfied, overcurrent protection is blocked.
When the overcurrent component trips, at the same time, 3-phase current
value of Ia, Ib and Ic will also be displayed.
3.1.7 Logic diagram
Taking the Stage1 phase A of the overcurrent definite time logic diagram.
as an example, the logic diagram of definite time is shown below:
84
Ia>“OCStage1CurrSet”
VT Failure Blocking &

≥1
&
Overcurrent Stage1 Phase A Startup
“VTFailProtOff”=1
Overcurrent Stage1 Direction

Component Satisfied
Overcurrent Stage 1 Compound

Voltage Component Satisfied
Overcurrent Protection Function On
Overcurrent Stage1
&
Phase A Startup T1 &
&
Binary Blocking Overcurrent Stage1 Protection Trip
Overcurrent Stage 1
3 Phase Inrush Blocking
“OCStage1On”=1
T1：“OCSatge1Time”
Figure 49 Stage1 of the overcurrent definite time logic diagram
3.2 Setting list

Table 39 Overcurrent setting on high voltage side
Default
value
0: definite time
1: IEC INV.
2: IEC VERY INV.
3:IEC EXTERMELY INV.
4: IEC SHORT TIME INV.
5: IEC LONG TIME INV.
HVSideOCStage1 6:ANSI INV.
1. 0~13 0 7:ANSI SHORT INV.
Curve
8:ANSI LONG INV.
9:ANSI MODERATELY
INV.
10:ANSI VERY INV.
11:ANSI EXTERMELY INV.
12:ANSI DEFINITE INV.
13: User defined
HVSideOCStage1 0.05In~40I
2. 40 A
CurrSet n
HVSideOCSatge1 0.00~100.0
3. 100 s
Time1 0
HVSideInvTimeO 0.025~ 0.0
4. 1.5 25
CStage1ConstT
HVSideInvTimeO 0.001~
5. 10 s
CStage1CoefA 1000
HVSideInvTimeO 0.000~ 100
6. 100.00
CStage1TimeB
7. HVSideInvTimeO 0.01~10.00 10
85
Default
value
C1IndexP
0: definite time
1:IEC INV.
2:IEC VERY INV.
4:IEC SHORT TIME INV.
5:IEC LONG TIME INV.
Curve
8:ANSI LONG INV.
9:ANSI MODERATELY
INV.
10:ANSI VERY INV.
13:User defined
9. 40 A
CurrSet n
HVSideOCSatge2 0.00~100.0
10. 100 s
Time1 0
HVSideInvTimeO 0.025~ 0.0
11. 1.5 25
CStage2ConstT
HVSideInvTimeO
12. 0.01~10.00 10
CStage2CoefA
HVSideInvTimeO 0.000~100.
13. 100
CStage2TimeB 00
HVSideInvTimeO
14. 0.01~10.00 10
C2IndexP
0:definite time
1:IEC INV.
2:IEC VERY INV.
5:IECLONG TIME INV.
Curve
8:ANSI LONG INV.
9:ANSI MODERATELY
INV.
10:ANSI VERY INV.
13:User defined
16. 40 A
CurrSet n
HVSideOCStage3 0.00~100.0
17. 100 s
Time1 0
HVSideInvTimeO
18. 0.025~1.5 0.025
CStage3ConstT
HVSideInvTimeO 0.001~100
19. 10 s
CStage3CoefA 0
HVSideInvTimeO 0.000~100.
20. 100 s
CStage3TimeB 00
HVSideInvTimeO
21. 0.01~10.00 10
C3IndexP
86
Default
value
HVSideDirOCSen
22. 0.00~90.00 30 degree
sitiveAngle
HVSidePPVoltBlk
23. 1.00~120.0 30 V
OCSet
HVSideOCU2Blk
24. 0.05~100.0 3 V U2
OCSet
Overcurrent
harmonic crossing 0.000~100.
25. 100 s
blocking time of 00
high voltage side
HVSideOCRstTim
26. 0.01~100 0.04 s
e
HVInvTimeOCMin 0.10~100 0.1 s
27.
TripTime
HVSideOCSatge1 0.10~100 100 s
28.
Time2
29.
Time3
30.
Time2
31.
Time3
32.
Time2
33.
Time3
Table 40 Overcurrent protection logic switch of high voltage side
Set Default
mode value
1-Enable overcurrent stage 1
time 1 of high voltage side;
1. HVSideOCSatge1Time1On 1/0 0
0-Disable overcurrent stage 1
time 1 of high voltage side.
1-overcurrent stage 1 voltage
on of high voltage side,
2. HVSideOCStage1BlkByVolt 1/0 0
0-Overcurrent stage 1 voltage
off of high voltage side
1-overcurrent stage 1
3. HVSideDirOCStage1 1/0 0 Direction on, 0-Overcurrent
stage 1 Direction off
1-overcurrent stage 1 forward
direction of high voltage side,
4. HVSideOCStage1Fwd 1/0 0
0-overcurrent stage 1 reverse
direction of high voltage side
1-overcurrent stage 1 of high
voltage side secondary
5. HVSideOCStage1BlkBy2ndH 1/0 0 harmonic on, 0-Overcurrent
stage 1 of high voltage side
secondary harmonic off
0-Disable overcurrent time 2
87
Set Default
mode value
11. HVSideOCSatge3Time1On 1/0 0 0-Disable overcurrent time 3

1-VT failure or disabling
voltage connector disables
protection
16. HVSideOCVTFailProtOff 1/0 0
0-VT failure or disabling
voltage connector does not
disable protection
1-composited voltage
blocking overcurrent uses
voltage of high voltage side
17. HVSideCVCBlkUseHVS 1/0 0 0-composited voltage
blocking overcurrent does not
use voltage of high voltage
side
voltage of medium voltage
18. HVSideCVCBlkUseMVS 1/0 0 side
use voltage of medium
88
Set Default
mode value
voltage side
voltage of low voltage side 1
19. HVSideCVCBlkUseLVS1 1/0 0 0-composited voltage
use voltage of low voltage
side 1
voltage of low voltage side 2
20. HVSideCVCBlkUseLVS2 1/0 0 0-composited voltage
use voltage of low voltage
side 2


1-Enab le overcurrent stage 3
Note: Overcurrent protection logic switch of middle and low voltage side
are the same to that of high voltage side
Table 41 Overcurrent setting on medium voltage side
Default
value
0: definite time
MVSideOCStage 1: IEC INV.
1. 0~13 0 2: IEC VERY INV.
1Curve
89
Default
value
6:ANSI INV.
7:ANSI SHORT INV.
8:ANSI LONG INV.
9:ANSI MODERATELY
INV.
10:ANSI VERY INV.
13: User defined
MVSideOCStage 0.05In~40I
2. 40 A
1CurrSet n
MVSideOCSatge 0.00~100.0
3. 100 s
1Time1 0
MVSideInvTimeO 0.025~1.5 0.025
4.
CStage1ConstT
MVSideInvTimeO 0.001~100
5. 10 s
CStage1CoefA 0
MVSideInvTimeO 0.000~100. 100
6. 00
CStage1TimeB
MVSideInvTimeO
7. 0.01~10.00 10
C1IndexP
0: definite time
1:IEC INV.
2:IEC VERY INV.
MVSideOCStage 6:ANSI INV.
8. 7:ANSI SHORT INV.
2Curve
8:ANSI LONG INV.
9:ANSI MODERATELY
INV.
10:ANSI VERY INV.
0~13 0 11:ANSI EXTERMELY INV.
13:User defined
9. 40 A
2CurrSet n
MVSideOCSatge 0.00~100.0
10. 100 s
2Time1 0
MVSideInvTimeO 0.025~1.5 0.025
11.
CStage2ConstT
MVSideInvTimeO
12. 0.01~10.00 10
CStage2CoefA
MVSideInvTimeO 0.000~100.
13. 100
CStage2TimeB 00
MVSideInvTimeO
14. 0.01~10.00 10
C2IndexP
0:definite time
1:IEC INV.
MVSideOCStage 2:IEC VERY INV.
15. 0~13 0
3Curve 3:IEC EXTERMELY INV.
5:IECLONG TIME INV.
90
Default
value
6:ANSI INV.
7:ANSI SHORT INV.
8:ANSI LONG INV.
9:ANSI MODERATELY
INV.
10:ANSI VERY INV.
13:User defined
16. 40 A
3CurrSet n
MVSideOCStage 0.00~100.0
17. 100 s
3Time1 0
MVSideInvTimeO
18. 0.025~1.5 0.025
CStage3ConstT
MVSideInvTimeO 0.001~100
19. 10 s
CStage3CoefA 0
MVSideInvTimeO 0.000~100.
20. 100 s
CStage3TimeB 00
MVSideInvTimeO
21. 0.01~10.00 10
C3IndexP
MVSideDirOCSen
22. 0.00~90.00 30 degree
sitiveAngle
MVSidePPVoltBlk
23. 1.00~120.0 30 V
OCSet
MVSideOCU2Blk
24. 0.05~100.0 3 V U2
OCSet
MVSideHarmCros 0.000~100.
25. 100 s
sBlkOCTime 00
MVSideOCRstTi
26. 0.01~100 0.04 s
me
MVInvTimeOCMi 0.10~100 0.1 s
27.
nTripTime
MVSideOCSatge 0.10~100 100 s
28.
1Time2
29.
1Time3
30.
2Time2
31.
2Time3
32.
3Time2
33.
3Time3
Table 42 Overcurrent protection logic switch of medium voltage side
Set Default
mode value
1. MVSideOCSatge1Time1On 1/0 0
2. MVSideOCStage1BlkByVolt 1/0 0
1-Direction on,
3. MVSideDirOCStage1 1/0 0
0- Direction off
91
Set Default
mode value
4. MVSideOCStage1Fwd 1/0 0
5. MVSideOCStage1BlkBy2ndH 1/0 0
MVSideOCStage2Fwd 1-Direction on,
9. 1/0 0
0- Direction off
1-Direction on,
14. MVSideOCStage3Fwd 1/0 0
0- Direction off
16. MVSideOCVTFailProtOff 1/0 0
17. MVSideCVCBlkUseHVS 1/0 0
18. MVSideCVCBlkUseMVS 1/0 0
19. MVSideCVCBlkUseLVS1 1/0 0
20. MVSideCVCBlkUseLVS2 1/0 0
Table 43 Overcurrent setting on low voltage side1
Default
value
0: definite time
1: IEC INV.
2: IEC VERY INV.
LVSide1OCStage 6:ANSI INV.
1Curve
8:ANSI LONG INV.
9:ANSI MODERATELY
INV.
10:ANSI VERY INV.
13: User defined
LVSide1OCStage 0.05In~40I
2. 40 A
1CurrSet n
LVSide1OCSatge 0.00~100.0
3. 100 s
1Time1 0
LVSide1InvTimeO 0.025~1.5 0.025
4.
CStage1ConstT
LVSide1InvTimeO 0.001~100
5. 10 s
CStage1CoefA 0
LVSide1InvTimeO 0.000~100. 100
6. 00
CStage1TimeB
92
Default
value
LVSide1InvTimeO
7. 0.01~10.00 10
C1IndexP
0: definite time
1:IEC INV.
2:IEC VERY INV.
2Curve
8:ANSI LONG INV.
9:ANSI MODERATELY
INV.
10:ANSI VERY INV.
13:User defined
9. 40 A
2CurrSet n
10. 100 s
2Time1 0
11.
CStage2ConstT
LVSide1InvTimeO
12. 0.01~10.00 10
CStage2CoefA
LVSide1InvTimeO 0.000~100.
13. 100
CStage2TimeB 00
LVSide1InvTimeO
14. 0.01~10.00 10
C2IndexP
0:definite time
1:IEC INV.
2:IEC VERY INV.
5:IECLONG TIME INV.
3Curve
8:ANSI LONG INV.
9:ANSI MODERATELY
INV.
10:ANSI VERY INV.
13:User defined
16. 40 A
3CurrSet n
LVSide1OCStage 0.00~100.0
17. 100 s
3Time 0
LVSide1InvTimeO
18. 0.025~1.5 0.025
CStage3ConstT
19. 10 s
CStage3CoefA 0
20. 100 s
CStage3TimeB 00
21. LVSide1InvTimeO 0.01~10.00 10
93
Default
value
C3IndexP
LVSide1DirOCSe
22. 0.00~90.00 30 degree
nsitiveAngle
LVSide1PPVoltBlk
23. 1.00~120.0 30 V
OCSet
LVSide1OCU2Blk
24. 0.05~100.0 3 V U2
OCSet
LVSide1HarmCro 0.000~100.
25. 100 s
ssBlkOCTime 00
LVSide1OCRstTi
26. 0.01~100 0.04 s
me
LVS1OCInvTime 0.10~100 0.1 s
27.
MinTripTime
LVSide1OCSatge 0.10~100 100 s
28.
1Time2
29.
1Time3
30.
2Time2
31.
2Time3
32.
3Time2
33.
3Time3
Table 44 Overcurrent protection logic switch of low voltage side1
Set Default
mode value
1. LVSide1OCSatge1Time1On 1/0 0
2. LVSide1OCStage1BlkByVolt 1/0 0
1-Direction on,
3. LVSide1DirOCStage1 1/0 0
0- Direction off
4. LVSide1OCStage1Fwd 1/0 0
5. LVSide1OCStage1BlkBy2ndH 1/0 0
1-Direction on,
0- Direction off
1-Direction on,
0- Direction off
16. LVSide1OCVTFailProtOff 1/0 0
17. LVSide1CVCBlkUseHVS 1/0 0
18. LVSide1CVCBlkUseMVS 1/0 0
19. LVSide1CVCBlkUseLVS1 1/0 0
94
Set Default
mode value
Default
value
0: definite time
1: IEC INV.
2: IEC VERY INV.
1Curve
8:ANSI LONG INV.
9:ANSI MODERATELY
INV.
10:ANSI VERY INV.
13: User defined
2. 40 A
1CurrSet n
3. 100 s
1Time1 0
4.
CStage1ConstT
5. 10 s
CStage1CoefA 0
6. 00
CStage1TimeB
LVSide2InvTimeO
7. 0.01~10.00 10
C1IndexP
0: definite time
1:IEC INV.
2:IEC VERY INV.
2Curve
8:ANSI LONG INV.
9:ANSI MODERATELY
INV.
10:ANSI VERY INV.
13:User defined
9. 40 A
2CurrSet n
0.00~100.0
10. LVSide2OCSatge 100 s
0
95
Default
value
2Time1
11.
CStage2ConstT
LVSide2InvTimeO
12. 0.01~10.00 10
CStage2CoefA
13. 100
CStage2TimeB 00
LVSide2InvTimeO
14. 0.01~10.00 10
C2IndexP
0:definite time
1:IEC INV.
2:IEC VERY INV.
5:IECLONG TIME INV.
3Curve
8:ANSI LONG INV.
9:ANSI MODERATELY
INV.
10:ANSI VERY INV.
13:User defined
16. 40 A
3CurrSet n
17. 100 s
3Time 0
LVSide2InvTimeO
18. 0.025~1.5 0.025
CStage3ConstT
19. 10 s
CStage3CoefA 0
20. 100 s
CStage3TimeB 00
LVSide2InvTimeO
21. 0.01~10.00 10
C3IndexP
LVSide2DirOCSe
22. 0.00~90.00 30 degree
nsitiveAngle
LVSide2PPVoltBlk
23. 1.00~120.0 30 V
OCSet
LVSide2OCU2Blk
24. 0.05~100.0 3 V U2
OCSet
25. 100 s
ssBlkOCTime 00
LVSide2OCRstTi
26. 0.01~100 0.04 s
me
27.
MinTripTime
28.
1Time2
29.
1Time3
30. LVSide2OCSatge 0.10~100 100 s
96
Default
value
2Time2
31.
2Time3
32.
3Time2
33.
3Time3
Set Default
mode value
LVSide2DirOCStage1 1-Direction on,
3. 1/0 0
0- Direction off
1-Direction on,
0- Direction off
1-Direction on,
0- Direction off
Default
value
0: definite time
1: IEC INV.
2: IEC VERY INV.
LVSide3OCStage 4: IEC SHORT TIME INV.
1. 0~13 0
1Curve 5: IEC LONG TIME INV.
6:ANSI INV.
7:ANSI SHORT INV.
8:ANSI LONG INV.
9:ANSI MODERATELY
97
Default
value
INV.
10:ANSI VERY INV.
13: User defined
2. 40 A
1CurrSet n
3. 100 s
1Time1 0
4.
CStage1ConstT
5. 10 s
CStage1CoefA 0
6. 00
CStage1TimeB
LVSide3InvTimeO
7. 0.01~10.00 10
C1IndexP
0: definite time
1:IEC INV.
2:IEC VERY INV.
2Curve
8:ANSI LONG INV.
9:ANSI MODERATELY
INV.
10:ANSI VERY INV.
13:User defined
9. 40 A
2CurrSet n
10. 100 s
2Time1 0
LVSide3InvTimeO
11. 0.025~1.5 0.025
CStage2ConstT
LVSide3InvTimeO
12. 0.01~10.00 10
CStage2CoefA
13. 100
CStage2TimeB 00
LVSide3InvTimeO
14. 0.01~10.00 10
C2IndexP
0:definite time
1:IEC INV.
2:IEC VERY INV.
LVSide3OCStage 4:IEC SHORT TIME INV.
15. 0~13 0 5:IECLONG TIME INV.
3Curve
6:ANSI INV.
7:ANSI SHORT INV.
8:ANSI LONG INV.
9:ANSI MODERATELY
INV.
98
Default
value
10:ANSI VERY INV.
13:User defined
16. 40 A
3CurrSet n
17. 100 s
3Time 0
LVSide3InvTimeO
18. 0.025~1.5 0.025
CStage3ConstT
19. 10 s
CStage3CoefA 0
20. 100 s
CStage3TimeB 00
LVSide3InvTimeO
21. 0.01~10.00 10
C3IndexP
LVSide3DirOCSe
22. 0.00~90.00 30 degree
nsitiveAngle
LVSide3PPVoltBlk
23. 1.00~120.0 30 V
OCSet
LVSide3OCU2Blk
24. 0.05~100.0 3 V U2
OCSet
25. 100 s
ssBlkOCTime 00
LVSide3OCRstTi
26. 0.01~100 0.04 s
me
27.
MinTripTime
28.
1Time2
29.
1Time3
30.
2Time2
31.
2Time3
32.
3Time2
33.
3Time3
Set Default
mode value
1-Direction on,
0- Direction off
99
Set Default
mode value
1-Direction on,
0- Direction off
1-Direction on,
0- Direction off
Table 49 Common setting
Number Setting name Range Default Unit Remark
value
1. HVSideHarmUnblkPhCurr 0.05In~40In 40 A
2. HVSideOC2ndHI2/I1Ratio 0.07~0.50 0.07
3. MVSideHarmUnblkPhCurr 0.05In~40In 40 A
4. MVSideOC2ndHI2/I1Ratio 0.07~0.50 0.07
5. LVSideHarmUnblkPhCurr 0.05In~40In 40 A
6. LVSideOC2ndHI2/I1Ratio 0.07~0.50 0.07
3.3 Report list


Trip report:
1. HVSideOCSatge1Time1Trip /
2. HVSideOCStage1PhATrip /
3. HVSideOCStage1PhBTrip /
4. HVSideOCStage1PhCTrip /
100

19. MVSideOCSatge1Time1Trip /
20. MVSideOCStage1PhATrip /
21. MVSideOCStage1PhBTrip /
22. MVSideOCStage1PhCTrip /
37. LVSide1OCSatge1Time1Trip /
38. LVSide1OCStage1PhATrip /
39. LVSide1OCStage1PhBTrip /
40. LVSide1OCStage1PhCTrip /
101

102

Alarm report:
Inrush conditions meet the requirements
1. HVSideOCInrushBlk
of blocking overcurrent protection
2. MVSideOCInrushBlk
3. LVSide1OCInrushBlk

Table 51 Overcurrent protection technical parameter
Definite time characteristics
Current 0.05In～40.00In ≤ ±2.5% setting or ±0.02In
≤ ±1% setting or +40ms
Time delay 0.00s～100.00s, step 0.01s At 2 times of operating
current
Inverse time characteristic
Normal inverse time IEC 60255-151
Very inverse time; ≤ ±5% setting or +40ms
IEC standard
Extreme inverse time Under the condition 2< I  / I set
Long inverse time <20
Inverse time
Short inverse time ANSI/IEEE C37.112
Long inverse time ≤ ±5% setting or +40ms
ANSI Medium inverse time
Under the condition 2< I  / I set
Very inverse time;
Extreme inverse time <20
Definite inverse time
  IEC 60255-151
  ≤ ±5% setting or +40ms
A
t  T
User-defined characteristic
 B
curve   I  P  Under the condition 2< I  / I set
  1 
  Iset   <20
Time coefficient of inverse
0.001~000, step 0.001
time : A
Time delay of inverse time:
0.000～100.00, step 0.01
B
Inverse time index: P 0.01~10.00, step 0.01
Inverse time constant: T 0.025~1.5, step 0.005
Minimum trip time 20ms
Return mode Instantaneous return
Directional component
103

Action angle range 170° ≤±3°,
Sensitive Angle 0°～90°, step 1° When line voltage >2V
Inrush blocking
Maximum current of open
magnetizing inrush current 0.05In ~ 40.00In ≤ ±2.5% setting or ±0.02In
blocking
The ratio of secondary
harmonic and fundamental 0.07～0.5, step 0.01
current
Cross blocking (IL1, IL2,
IL3) (Time setting can be 0.00s～100.00s, step 0.01s ≤ ±1% setting or +40ms,
adjusted)
104
Chapter 10 Chapter 1Emergency overcurrent
protection(50,51)
Chapter 10 Emergency overcurrent

protection(50,51)
About this chapter

This chapter describes the emergency overcurrent
principlethe input and output signals, setting value
parameters, messages and technical parameters.
105
protection(50,51)
1 Overview
When VT failure happens, emergency overcurrent protection enables,and
emergency overcurrent protection is backup overcurrent protection without
direction.
Main characteristics of emergency overcurrent protection:
1) The device provides 2 stages of overcurrent protection on each high,
medium and low voltage side, each stage adopts definite time-lag or
12 IEC and ANSI standard curve of inverse time characteristic, and it
adopts user defined characteristic curve as well.
whether it’s through harmonic locking;
3) Harmonic blocking can lock across;
4) When VT failure happens, emergency overcurrent protection enables;
soft-hard parallel.

Input and output signals of the emergency overcurrent protectionfunction
are shown as follow:
Emergency Overcurrent Protection
1 1
BIBlk Start
2 2
Ena_*OC Operation
3
PhaseA
4
PhaseB
5
PhaseC
Figure 50 The input and output signals of emergency overcurrent protection function
diagram
The left side is the input and the right is the output, parameter description
is shown in the following table.
Function Logo Description
Input:
BIBlk BI blocking function
Output:
EMOC
Start IED startup
Operation Protection trip
PhaseA Phase A trip
106
protection(50,51)
PhaseB Phase B trip
PhaseC Phase C trip
Input:
HVSideOCConn:Ena_HVOC,Hard
ENA_Function connector is Ena_HVOC_5
Ena_*OC
MVSideOCConn:Ena_MVOC,Hard
connector is Ena_MVOC_5
The unit is equipped with two sections of emergency overcurrent
protection at high and medium voltage sides, each with three time periods,
which are detailed in the setting value list.

When “EmOC1BlkBy2ndH”=1, inrush is detected and the criteria are:
I∅2
> “OC2ndHI2/I1Ratio”, (∅ = 𝑎, 𝑏, 𝑐)
I∅
When it is detected that the ratio of second harmonic and fundamental
wave is greater than "OC2ndHI2/I1Ratio" and there is a current, then the
inrush condition is satisfied.
When it is detected that there is inrush condition, within the
"HarmCrossBlkTime", one phase inrush protection fails and three phase
protection; after the "HarmCrossBlkTime", one phase inrush protection
fails and one phase protection; when the inrush criterion returns, release
each blocking.
When the maximum fundamental wave current of the three phases is
greater than "OCHarmUnblkCurr", unblocking
The output blocking state of each phase is caused by inrush blocking of
emergency overcurrent stage 1 phase A, phase B and phase C.
Schematic diagram is shown as follow:
107
protection(50,51)
PhAI2/I1Ratio>OC2ndHI2/I1Ratio
≥1
&
PhBI2/I1Ratio>“OC2ndHI2/I1Ratio
3PhInrushBlk
PhCI2/I1Ratio>“OC2ndHI2/I1Ratio
Time<“HarmCrossBlkTime”
3PhInrushBlk &
EmOCS1 3PhInrushBlk
“EmOC1BlkBy2ndH”=1
PhAI2/I1Ratio>OC2ndHI2/I1Ratio &
&
EmOCS1PhAInrushBlk
PhBI2/I1Ratio>“OC2ndHI2/I1Ratio &
&
EmOCS1PhBInrushBlk
PhCI2/I1Ratio>“OC2ndHI2/I1Ratio &
&
EmOCS1PhCInrushBlk
Figure 51 Inrush blockinglogic diagram
3.1.2 Definite time

When "EmOCStage1Curve"=0, emergency overcurrent is the definite
time characteristic, inverse time function is disabled.
I∅ > “EmOCStage1CurrSet”, (∅ = 𝑎, 𝑏, 𝑐)
When the phase-to-earth current is greater than"EmOCStage1CurrSet",
timing component starts and until "EmOCSatge1Time“, emergency
overcurrent protection trips, when the phase-to-earth current I∅ <
Dropout × “EmOCStage1CurrSet”, Dropout is dropoff coefficient, timing
component returns, emergency overcurrent protection resets.
3.1.3 Inverse time
When "EmOCStage1Curve"=1~13, emergency overcurrent is the inverse
time characteristic, definite time function is disabled.
 
 
A
t  B  T
  I  P 
   1 
  Iset  
108
protection(50,51)
Where:
A:InvTimeEmOCStage1CoefA
P:InvTimeEmOCStage1IndexP
B:InvTimeEmOCStage1TimeB
T:InvTimeEmOCStage1ConstT
Iφ: Phase current value in the system
Iset: "EmOCStg1CurrSet"
If the phase-to-earth current is greater than "EmOCStage1CurrSet", the
timing component starts, inverse time characteristic curve is selected by
"EmOCStage1Curve", A, P, B are determined when the value is from 1 to
12, see the following table; when the value is 13, it is user defined
characteristics, calculate the trip delay according to the setting of the A, P,
B, T. While timing, emergency overcurrent protection trips. When the delay
is less than the "OC1InvTimeMinTime", the component trips according to
the "OV1InvTimeMinTime"
Curve Curve characteristic A P B

0 Definite time
1 IEC INV. 0.14 0.02 0
2 IEC VERY INV. 13.5 1.0 0
3 IEC EXTERMELY INV. 80.0 2.0 0
4 IEC SHORT TIME INV. 0.05 0.04 0
5 IEC LONG TIME INV. 120.0 1.0 0
6 ANSI INV. 8.9341 2.0938 0.17966
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
9 ANSI MODERATELY INV. 0.0103 0.02 0.0228
10 ANSI VERY INV. 3.922 2.0 0.0982
11 ANSI EXTERMELY INV. 5.64 2.0 0.02434
12 ANSI DEFINITE INV. 0.4797 1.5625 0.21359
13 USER DEFINE

Emergency overcurrent satge 1 is taken as an example: When VT failure
and no BI blocking, if the "EmOCStage1On"=1, the emergency overcurrent
stage 1 protection is enabled.
If the trip conditions are met, time component starts until
"EmOCStage1Trip". When IED trips, at the same time, each phase trip
states will be displayed. LED, IED output and others can be configured by
AESP.
When " EmOCStage1BlkBy2ndH"=1, the harmonic locking component is
109
protection(50,51)
put into operation, when the trip timer is time out, the inrush current is
checked, and if the current is not locked, unblock emergency overcurrent
protection trip.
When the emergency overcurrent component trips, at the same time,
three-phase current value of Ia, Ib and Ic will also be displayed.
3.1.5 Logic diagram
Stage1 of the emergency overcurrent definite time logic diagram. definite
time logic diagram.
Ia>“OCStage1CurrSet”
&
VTFailBlk EmOCS1PhAStartup
OCProtOn
EmOCS1PhAStartup &
T1 &
&
BIBlk EmOCStage1Trip
EmOCS1 3PhInrushBlk
“EmOCStage1On”=1
T1：“EmOCSatge1Time”
Figure 52 Stage1 of the emergency overcurrent definite time logic diagram
3.2 Setting list

Table 54 Emergency overcurrent setting on high voltage side
Default
No. SetName Scope Unit Comment
Val
0: Definite time
1:IEC INV.
2:IEC VERY INV.
6:ANSI INV.
HVSideEmOCStage1Cu 7:ANSI SHORT INV.
1. 0~13 0
rve 8:ANSI LONG INV.
9:ANSI MODERATELY
INV.
10:ANSI VERY INV.
11:ANSI EXTERMELY
INV.
13: User defined
HVSideEmOCStage1Cu
2. 0.05In~40In 40 A
rrSet
HVSideEmOCS1Time1
3. 0.00~100.00 100 s
Set
HVSInvTime3U0Stage2
4. 0.025~1.5 0.025
ConstT
HVSideEmOCStage1Co
5. 0.001~1000 10
efA
110
protection(50,51)
Default
Val
HVSideEmOCStage1Ti
6. 0.000~100.00 100
meB
HVSideEmOCStage1In
7. 0.01~10.00 10
dexP
0: Definite time
1:IEC INV.
2:IEC VERY INV.
6:ANSI INV.
HVSideEmOCStage2Cu 7:ANSI SHORT INV.
8. 0~13 0
rve 8:ANSI LONG INV.
9:ANSI MODERATELY
INV.
10:ANSI VERY INV.
11:ANSI EXTERMELY
INV.
13: User defined
HVSideEmOCStage2Cu
9. 0.05In/40In 40 A
rrSet
HVSideEmOCStage2Ti
10. 0.00~100.00 100 s
meSet
HVSInvTime3U0Stage2
11. 0.025~1.5 0.025
ConstT
HVSideEmOCStage2Co
12. 0.001~1000 10
efA
HVSideEmOCStage2Ti
13. 0.000~100.00 100
meB
HVSideEmOCStage2In
14. 0.01~10.00 10
dexP
HVSideHarmCrossBlkO
15. 0.000~100.00 100 s
CTime
16. HVSideOCRstTime 0.01~100 0.04 s
HVInvTimeOCMinTripTi
17. 0.10~100 0.1 s
me
HVSideEmOCStage1Ti
18. 0.10~100 100 s
me2
HVSideEmOCStage1Ti
19. 0.10~100 100 s
me3
HVSideEmOCStage2Ti
20. 0.10~100 100 s
me2
HVSideEmOCStage2Ti
21. 0.10~100 100 s
me3
Table 55 Emergency Overcurrent protection logic switch of high voltage side
Setting
No. LSName DefaultVal Comment
Mode
HVSideEmOCStage1Time
1. 1/0 0
1On
2. HVSideEmOC1BlkBy2nd 1/0 0
111
protection(50,51)
Setting
Mode
3. 1/0 0
1On
4. HVSideEmOC4BlkBy2nd 1/0 0
5. 1/0 0
2On
6. 1/0 0
3On
7. 1/0 0
2On
8. 1/0 0
3On
Table 56 Emergency overcurrent setting on medium voltage side

Default
Val
0: Definite time
1:IEC INV.
2:IEC VERY INV.
6:ANSI INV.
MVSideEmOCStage1C 7:ANSI SHORT INV.
1. 0~13 0
urve 8:ANSI LONG INV.
9:ANSI MODERATELY
INV.
10:ANSI VERY INV.
11:ANSI EXTERMELY
INV.
13: User defined
MVSideEmOCStage1C
2. 0.05In~40In 40 A
urrSet
MVSideEmOCS1Time1
3. 0.00~100.00 100 s
Set
MVSInvTime3U0Stage2
4. 0.025~1.5 0.025
ConstT
MVSideEmOCStage1C
5. 0.001~1000 10
oefA
MVSideEmOCStage1Ti
6. 0.000~100.00 100
meB
MVSideEmOCStage1In
7. 0.01~10.00 10
dexP
0: Definite time
1:IEC INV.
2:IEC VERY INV.
MVSideEmOCStage2C
8. 0~13 0 5:IEC LONG TIME INV.
urve
6:ANSI INV.
7:ANSI SHORT INV.
8:ANSI LONG INV.
9:ANSI MODERATELY
INV.
112
protection(50,51)
Default
Val
10:ANSI VERY INV.
11:ANSI EXTERMELY
INV.
13: User defined
MVSideEmOCStage2C
9. 0.05In/40In 40 A
urrSet
MVSideEmOCStage2Ti
10. 0.00~100.00 100 s
meSet
MVSInvTime3U0Stage2
11. 0.025~1.5 0.025
ConstT
MVSideEmOCStage2C
12. 0.001~1000 10
oefA
MVSideEmOCStage2Ti
13. 0.000~100.00 100
meB
MVSideEmOCStage2In
14. 0.01~10.00 10
dexP
MVSideHarmCrossBlkO
15. 0.000~100.00 100 s
CTime
16. MVSideOCRstTime 0.01~100 0.04 s
MVInvTimeOCMinTripTi
17. 0.10~100 0.1 s
me
MVSideEmOCStage1Ti
18. 0.10~100 100 s
me2
MVSideEmOCStage1Ti
19. 0.10~100 100 s
me3
MVSideEmOCStage2Ti
20. 0.10~100 100 s
me2
MVSideEmOCStage2Ti
21. 0.10~100 100 s
me3
Table 57 Emergency Overcurrent protection logic switch of medium voltage side
Setting
Mode
MVSideEmOCStage1Time
1. 1/0 0
1On
2. MVSideEmOC1BlkBy2nd 1/0 0
3. 1/0 0
1On
4. MVSideEmOC4BlkBy2nd 1/0 0
5. 1/0 0
2On
6. 1/0 0
3On
7. 1/0 0
2On
8. 1/0 0
3On
Table 58 CommonSet
113
protection(50,51)
No. SetName Scope DefaultVal Unit Comment
1. HVSideHarmUnblkPhCurr 0.05In~40 In 40 A
3. MVSideHarmUnblkPhCurr 0.05In~40 In 40 A
3.3 Report list

No. Report name Comment

Trip report:
1. HVSideEmOCS1Time1Trip /
2. HVSideEmOCS1PhATrip /
3. HVSideEmOCS1PhBTrip /
4. HVSideEmOCS1PhCTrip /
8. HVSideEmOCS2PhATrip /
9. HVSideEmOCS2PhBTrip /
10. HVSideEmOCS2PhCTrip /
13. MVSideEmOCS1Time1Trip /
14. MVSideEmOCS1PhATrip /
15. MVSideEmOCS1PhBTrip /
16. MVSideEmOCS1PhCTrip /
20. MVSideEmOCS2PhATrip /
21. MVSideEmOCS2PhBTrip /
22. MVSideEmOCS2PhCTrip /
Alarm report:
114
protection(50,51)
Inrush conditions meet the requirements of blocking

1. HVSideOCInrushBlk
overcurrent protection
2. MVSideOCInrushBlk

Table 60 Emergency overcurrent protection technical parameter
Definite time characteristic
≤ ±1% setting or +40 ms,
Time delay 0.00s～100.00s, step 0.01s
At 2 times of trip current
IEC standard Normal inverse time IEC 60255-151
Very inverse time ≤ ±5% setting or +40 ms,
Extreme inverse time Under the condition 2< I  /
Long inverse time
I set <20
ANSI Inverse time ANSI/IEEE C37.112，
Short inverse time ≤ ±5% setting or +40 ms,
Long inverse time Under the condition 2< I  /
Medium inverse time
Very inverse time I set <20
Extreme inverse time
User defined characteristic   IEC 60255-151
curve   ≤ ±5% setting or +40 ms,
A
t  B  T Under the condition 2< I  /
  I  P 
   1  I set <20
  Iset  
Time coefficient of inverse 0.001~000, step 0.001
time:A
Time delay of inverse time: 0.000～100.00, step 0.01
B
Inverse time index:P 0.01~10.00, step 0.01
Inverse time constant: T 0.025~1.5, step 0.005
Inrush blocking
Maximum current of open 0.05 In～40.00 In
magnetizing inrush current ≤ ±2.5% setting or ±0.02In
blocking
The ratio of secondary 0.07～0.5, step 0.01
harmonic and fundamental
wave current
115
protection(50,51)
Cross blocking 0.00s～100.00s, step 0.01s ≤ ±1% setting or +40 ms
Note: In: CT secondary rated current, 1A or 5A.
116
Chapter 11Chapter 1 Earth fault protection (50N, 51N,
67N)
Chapter 11 Earth fault protection

(50N, 51N, 67N)
About this chapter

This chapter describes the zero sequence current principle,
the input and output signals, setting value parameters,
messages and technical parameters.
117
67N)
1 Overview
Under the condition of high resistance grounding fault in the neutral point
grounding system, the calculated impedance located out of the impedance
zone and the IED maloperate. Therefore, other protection trips are needed
to isolate the fault, earth fault protection can reliably identify high
resistance grounding fault. For example, in the double circuit lines, the
directional earth fault protection simultaneously distinguishes the size and
direction of fault current and cooperates with other protection devices in
the system.
The characteristics of earth fault protection are listed as follow:
1) There are three stages of definite time on each high, medium and low
voltage side of which the definite stage or inverse time can be
selected.(including all inverse time characteristics that stipulated by
IEC/ANSI standard );
2) Direction characteristics of each stage is independent (selectable);
3) Negative sequence directional component(selectable);
4) The inrush blocking feature of each stage is independent ;
5) Inrush locking is distinguished by secondary harmonic currents;
6) The maximum current of open magnetizing inrush blocking can be
adjusted;
7) VT failure blocks directional earth fault protection.
8) The protective function can be disabled through the function
connector. The connector properties can be configured as soft
connector, hard connector, soft-hard series, soft-hard parallel, and the
default is soft-hard parallel.

The input and output signals of earth fault protection function are shown as
below, the left side is input signals and the right side is output signals:
Directional / Non-directional Zero
Overcurrent Protection
1 1
BIBlk Start
2 2
Ena_*EF Operation
3
Ena_*Voltage
Figure 53 The input and output signals diagram of earth fault protection function
Input:
EF
BIBlk BI blocking
118
67N)
Output:
Start IED startup
Operation IED trip
Input:
HVSide3I0Conn:Ena_HVEF,Hard connector is
Ena_HVEF_5
MVSide3I0Conn:Ena_HVEF,Hard connector is
Ena_MVEF_5
ENA_Function "LVSide1 3I0Conn": Ena_LV1EF,the corresponding hard
Ena_*EF
connector is Ena_LV1EF_5
"LVSide2 3I0Conn": Ena_LV2EF,the corresponding hard
"LVSide3 3I0Conn": Ena_LV3EF,the corresponding hard
Input:
"HVSideVoltConn": Ena_HVoltage,the corresponding hard
"MVSideVoltConn": Ena_MVoltage,the corresponding
hard connector is Ena_MVoltage_5
ENA_*Voltage Ena_*Voltage
"LVSide1VoltConn",the corresponding hard connector is
Ena_L1Voltage_5
"LVSide2VoltConn": Ena_L2Voltage, the corresponding
hard connector is Ena_L2Voltage_5
IED is equipped with 3 stages earth fault protection on each high, medium
and low voltage side, please refer to the setting list for details. The
overcurrent protection stage 1 will be taken as an example below and the
principle will be introduced.

When "3I0Stage1BlkBy2ndH"=1, inrush detects. There are two inrush
criteria:
Check phase current harmonics and external zero sequence current
harmonic.
1) Only when "3I0HarmonChkExtrI02/I01"=1, and "Extr3I0Stage1"=1,
zero-sequence current harmonic is detected. When it is detected that
the ratio of second harmonic and fundamental wave is larger than
"3I02ndHI02/I01" and there is zero sequence current, then the zero
sequence inrush condition is satisfied. When the maximum
fundamental wave of zero sequence current is larger than
"3I0UnblkHarmBlkCurr", release each blocking.
2) In addition to the first case, detect the phase current harmonic. When
it is detected that the ratio of second harmonic and fundamental wave
is larger than "OC2ndHI2/I1Ratio" and there is a current, then the
inrush condition is satisfied in the phase. When the maximum
119
67N)
fundamental wave of phase current is larger than "OCHarmUnblkCurr",
release each blocking.
When any of the above two harmonic check method is satisfied, the
secondary harmonic current is high.
3I0>“3I0UnblkHarmBlkCurr” &
&
3I02/3I0>“3I02ndHI02/I01”
“Extr3I0Stage1”=0 & ≥1
High 2nd Harmonic Current
“3I0HarmonChkExtrI02/I01”=1
&
Imax>“HarmUnblkPhCurr”
Ia2/Ia1>“OC2ndHI2/I1Ratio”
≥1
Ib2/Ib1>“OC2ndHI2/I1Ratio”
Ic2/Ic1>“OC2ndHI2/I1Ratio”
3I02/3I0:Zero Sequence 2nd Harmonic/Zero Sequence Basic Wave

Ia2/Ia1：Phase A Current 2nd Harmonic/Phase A Current Basic Wave
Ib2/Ib1：Phase B Current 2nd Harmonic/Phase B Current Basic Wave
Ic2/Ic1：Phase C Current 2nd Harmonic/Phase C Current Basic Wave
Figure 54 Logic diagram of the secondary harmonic blocking of earth fault protection
3.1.2 Directional component

1) Zero sequence directional component
In order to meet the different operating conditions of power system, the
reference voltage can be clockwise rotate 0 to 90° according to the
"3I0DirectSensitiveAngle", this setting influences direction characteristics
of each stage. The reference voltage vector after rotation is closer to the
-3I0 of lag 3U0 angle Φd, which makes the direction distinguishing more
sensitive. Rotate reference voltage vector to define the forward direction
and reverse direction action zone. The direction range of the positive
direction is rotating voltage reference vector for the vertical bisector
between -80 degrees and +80 degrees. If the -3I0 vector is in this zone,
the device is considered to be in the forward direction.
Zero-sequence voltage of zero-sequence direction component can select
calculated zero sequence voltage or external zero sequence voltage.
Zero-sequence current adopts self-produced zero current.
An example is given to illustrate the direction discrimination of A phase
faults. In the figure, 3I0 exceeds 3U0, so the -3I0 lags 3U0, the reference
voltage 3U0 vector rotates "3I0DirectSensitiveAngle", in order to be closer
to the -3I0 vector. In addition, the yellow area in the diagram is a positive
direction.
120
67N)
3I 0 90° 90°
3I 0
Reverse
10°
10°
0° 0°
3 U 0_Ref 3U 0_Ref
Φ0 Φ0
Forward Bisector Bisector
-3 I 0 -3 I 0
Figure 55 Diagram of zero sequence directional component

Where:
0
Zero-sequence directional sensitive angle: the angle is settable,
="Dir3I0SensitiveAngle ";
Zero sequence positive direction overcurrent range: (-80°~ +80°), zero
sequence reverse direction overcurrent range: (+100°~ +260°).
2) Negative sequence directional component
When "ZeroSeqChkU2/I2DirOn"=1, and the zero sequence voltage is
small, then enable the negative sequence directional component. For
example, zero sequence current mutual coupling or uncertain zero
sequence directional impedance happen in the double circuit line. Here, it
is necessary to input the negative sequence directional component to
detect the fault current direction, the logic switch “ZeroSeqChkU2/I2DirOn”
is set to 1. Here, it is still the default input zero sequence direction
discrimination. However, when 3U0 is less than 1V and 3U2 is larger than
2V, it is converted into negative sequence direction discrimination, at this
point negative sequence component is used to discriminate the direction.
Negative sequence directional characteristics diagram:
3I 2 90° 3I 2 90°
Reverse
10°
10°
0° 0°
3 U 2-Ref 3U 2-Ref
Φ2 Φ2
Forward Bisector Bisector
-3 I 2 -3 I 2
Figure 56 Negative-sequence directional characteristic diagram
121
67N)
Where:
Ф2: setting "3I0NSDSensitiveAngle".
Negative sequence positive direction overcurrent range: (-80°~ +80°),
negative sequence reverse direction overcurrent range: (+100°~ +260°).
In the process of direction discrimination, the VT disconnection may lead
actions or alarms that are not consistent with the flow direction
discrimination or the voltage discrimination along overcurrent protection
stages. When VT fails, the action mode is decided according to
"VTFailProtOff"; if “VTFailProtOff” is set to 1, earth fault protection with
voltage or directional component is blocked; if “VTFailProtOff” is set to 0,
voltage blocking component and directional component exit and act in a
pure overcurrent mode.
VT failure blocking
&
& ≥1
Zero sequence forward zone
Forward direction
Calculated zero voltage>1V
&
“ZeroSeqChkU2/I2DirOn”=1
Negative sequence forward zone
Zero sequence forward zone：Calculate as 90°connection，zero sequence current is within the direction zone.
Negative Sequence Forward Zone：Calculate as 90°connection，negative current is within the direction zone.
Figure 57 Zero sequence current direction sensitive angle logic diagram
3.1.3 Definite time

When "3I0Stage1Curve"=0, zero sequence current is the inverse time
characteristic, inverse time function is disabled.
3I0 > “3I0Stage1CurrSet”
When the zero sequence current is greater than "3I0Stage1CurrSet",
timing component starts and until "3I0Satge1Time”, earth fault protection
trips, when the current <Dropout×"3I0Stage1CurrSet", Dropout is dropout
coefficient, timing component returns, earth fault protection resets.
3.1.4 Inverse time
When "3I0Stage1Curve"=1~13, zero sequence current is the definite time
characteristic, definite stage function is disabled.
 
 
 A 
t P
 B T
  3I 0   1 
  3I 0set  
Where:
A: "InvTime3I0Stage1CoefA"
P: "InvTime3I0Stage1IndexP"
B: "InvTime3I0Stage1TimeB"
122
67N)
T: "InvTime3I0Stage1ConstT"
3I 0 : Zero sequence current setting value
3I 0set "3I0Stage1CurrSet"
If the current exceeds "3I0Stage1CurrSet", the timing component starts,
inverse time characteristic curve is selected by "3I0Stage1Curve", A, P, B
are determined when the value is from 1 to 12, see the following Table;
delay according to the setting of the A, P, B, T, while timing is up, earth fault
protection trips. When the calculated delay is less than the minimum trip
delay time "3I0InvTimeMinTripTime", the component trips according to the
"3I0InvTimeMinTripTime".

0 Definite time
1. IEC INV. 0.14 0.02 0
2. IEC VERY INV. 13.5 1.0 0
6. ANSI INV. 8.9341 2.0938 0.17966
7. ANSI SHORT INV. 0.2663 1.2969 0.03393
8. ANSI LONG INV. 5.6143 1 2.18592
10. ANSI VERY INV. 3.922 2.0 0.0982
13. USER DEFINE

When earth fault protection function is enabled and no BI blocking, if the
"3I0Stage1On"=1 , the earth fault protection of the corresponding stage is
enabled.
If the action conditions are met, time component starts; take stage 1
protection for example, when time is over, "3I0Stage1Trip" is issued. LED
and protection trip can be configured by AESP. When IED trips each phase
trip states will be displayed.
When "3I0Stage1BlkBy2ndH"=1, the harmonic locking component is put
into operation, when the action timer is time out, the inrush current is
checked, and if the current is not blocked, unblock overcurrent trip,
otherwise it will output “InrushBlk” report.
When "Dir3I0Stage1"=1, protection is with the directional component, and
choose the positive or negative direction characteristic according to
123
67N)
"3I0Stage1FwdDir", when the directional component is not satisfied, earth
fault protection is blocked.
Component trip triggers action or alarm, meanwhile output analog quantity
of action time, when the component is based on the self-produce zero
sequence current judgment, self-produce zero sequence current is output;
when it is based on the external zero sequence current, external zero
sequence current is output.
3I0>“3I0Stage1CurrSet”
&
T1
Binary input blocking
&
& Zero Sequence Current
Forward Direction Stage 1 Protection Trip
“3I0Stage1FwdDir”=1
“Dir3I0Stage1”=1 ≥1
&
“H/M/LVSideVoltConn”=0
“H/M/LVSideExtr3IO3U0”=0
&
2nd harmonic current is high
“3I0Stage1BlkBy2ndH”=1
“3I0Stage1On”=1
Zero Sequence Overcurrent Stage 1

Protection Function On
T1：“3I0Satge1Time”
Figure 58 Logic diagram of earth fault protection function
3.2 Setting list

Table 63 Zero sequence current setting on high voltage side
Default
value
0: definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
1. HVSide3I0Stage1Curve 0~13 0
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
124
67N)
Default
value
12: ANSI
DEFINITE INV.
13: User
defined
2. HVSide3I0Stage1CurrSet 0.05~200 40 A
3. HVSide3I0Satge1Time1 0.00~100.00 100 s
4. HVSideInvTime3I0Stage1ConstT 0.025~1.5 0.025
5. HVSideInvTime3I0Stage1CoefA 0.001~1000 10
6. HVSideInvTime3I0Stage1TimeB 0.000~100.00 100
7. HVSideInvTime3I0Stage1IndexP 0.01~10.00 10
0: definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
HVSide3I0Stage2Curve SHORT INV.
8. 0~13 0
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
9. HVSide3I0Stage2CurrSet 0.05~200 40 A
10. HVSide3I0Satge2Time1 0.00~100.00 100 s
13. HVSideInvTime3I0 Stage 2TimeB 0.000~100.00 100
0: definite time
1: IEC INV.
2: IEC VERY
15. HVSide3I0Stage3Curve 0~13 0 INV.
3: IEC
EXTERMELY
INV.
125
67N)
Default
value
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
16. HVS3I0Stage3CurrSet 0.05~200 40 A
17. HVSideI3I0Stage3Time1 0.00~100.00 100 s
20. HVSideInvTime3I0 Stage 3TimeB 0.000~100.00 100
22. HVSideDir3I0SensitiveAngle 0.00~90.00 30
23. HVSide3I0NSDSensitiveAngle 0.00~90.00 30
24. HVSide3I0RstTime 0.10~100 0.1 s
25. HVInvTime3I0MinTripTime 0.00~100 0.04 s
26. HVSide3I0Satge1Time2 0.10~100 100 s
Table 64 Earth fault protection of high voltage side logic switch

Set Default
mode value
1-Enable zero sequence
covercurrent stage 1 time 1
of high voltage side;
1. HVSide3I0Stage1Time1On 1/0 0
0-Disable zero sequence
current time 1 time 1 of high
voltage side.
1-3I0 external connection;
2. HVSide3I0Stage1Extr 1/0 0
0-3I0 calculated
3. HVSideDir3I0Stage1 1/0 0 1-zero sequence current
126
67N)
Set Default
mode value
direction on, 0-zero
sequence current stage 1of
high voltage side direction
off
1-Zero sequence current
HVSide3I0Stage1FowardDir forward direction; 0-zero
4. 1/0 0
sequence current stage 1
of high voltage side reverse
direction
1-High zero sequence
current stage 1 secondary
harmonic blocking on, 0-
5. HVSide3I0Stage1BlkBy2ndH 1/0 0
high zero sequence current
stage 1 secondary
harmonic blocking off
6. HVSide3I0Stage2Time1On 1/0 0
voltage side.
7. HVSide3I0Stage2Extr 1/0 0
0-3I0 calculated
1-zero sequence current
8. HVSideDir3I0Satge 1/0 0
sequence current stage 1of
high voltage side direction
off
HVSide3I0Stage2FowardDir forward direction; 0-zero
9. 1/0 0
direction
stage 2 secondary
HVSide3I0Stage3Time1On of high voltage side;
11. 1/0 0
voltage side.
HVSide3I0Stage3Extr 1-3I0 external connection;
12. 1/0 0
0-3I0 calculated
1-zero sequence current
13. HVSideDir3I0Satge3 1/0 0
of high voltage side
direction off
127
67N)
Set Default
mode value
forward direction; 0-zero
14. HVSide3I0Stage3FowardDir 1/0 0
direction
stage 3 secondary
1-3U0 external connection;
16. HVSideExtr3IO3U0 1/0 1
0-3U0 calculated
1-check negative sequence
HVSideZeroSeqChkU2/I2DirOn direction;
17. 1/0 1
0-don't check negative
sequence direction
harmonics checking
external connection I02/I01;
18. HVSide3I0HarmonChkExtrI02/I01 1/0 0
harmonics checking phase
current I2/I1
19. HVSide3I0Satge1Time2On 1/0 0
voltage side.
voltage side.
voltage side.
voltage side.
voltage side.
24. HVSide3I0Satge3Time3On 1/0 0 1-Enable zero sequence
128
67N)
Set Default
mode value
voltage side.
Table 65 Zero sequence current setting on medium voltage side
Default
value
0: definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
1. MVSide3I0Stage1Curve 0~13 0
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
2. MVSide3I0Stage1CurrSet 0.05~200 40 A
3. MVSide3I0Satge1Time1 0.00~100.00 100 s
4. MVSideInvTime3I0Stage1ConstT 0.025~1.5 0.025
5. MVSideInvTime3I0Stage1CoefA 0.001~1000 10
6. MVSideInvTime3I0Stage1TimeB 0.000~100.00 100
7. MVSideInvTime3I0Stage1IndexP 0.01~10.00 10
0: definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
129
67N)
Default
value
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
9. MVSide3I0Stage2CurrSet 0.05~200 40 A
10. MVSide3I0Satge2Time1 0.00~100.00 100 s
0: definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
16. MVS3I0Stage3CurrSet 0.05~200 40 A
17. MVSideI3I0Stage3Time1 0.00~100.00 100 s
130
67N)
Default
value
22. MVSideDir3I0SensitiveAngle 0.00~90.00 30
23. MVSide3I0NSDSensitiveAngle 0.00~90.00 30
24. MVSide3I0RstTime 0.10~100 0.1 s
25. MVInvTime3I0MinTripTime 0.00~100 0.04 s
26. MVSide3I0Satge1Time2 0.10~100 100 s
Table 66 Earth fault protection of medium voltage side logic switch

Setting Default
Mode value
1. MVSide3I0Stage1Time1On 1/0 0
2. MVSide3I0Stage1Extr 1/0 0
0-3I0 calculated
3. MVSideDir3I0Stage1 1/0 0
1- forward direction;
4. MVSide3I0Stage1FowardDir 1/0 0
0- reverse direction
5. MVSide3I0Stage1BlkBy2ndH 1/0 0
7. MVSide3I0Stage2Extr 1/0 0
0-3I0 calculated
8. MVSideDir3I0Satge 1/0 0
MVSide3I0Stage3Extr 1-3I0 external connection;
12. 1/0 0
0-3I0 calculated
13. MVSideDir3I0Satge3 1/0 0
1-3U0 external connection;
16. MVSideExtr3IO3U0 1/0 1
0-3U0 calculated
17. MVSideZeroSeqChkU2/I2DirOn 1/0 1
harmonics checking
external connection
18. MVSide3I0HarmonChkExtrI02/I01 1/0 0 I02/I01; 0-Zero sequence
current harmonics
checking phase current
I2/I1
131
67N)
Setting Default
Mode value
19. MVSide3I0Satge1Time2On 1/0 0
Table 67 Zero sequence current setting on low voltage side1
Default
value
0: definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
1. LVSide1 3I0Stage1Curve 0~13 0
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
2. LVSide1 3I0Stage1CurrSet 0.05~200 40 A
3. LVSide1 3I0Satge1Time1 0.00~100.00 100 s
4. LVSide1InvTime3I0Stage1ConstT 0.025~1.5 0.025
5. LVSide1InvTime3I0Stage1CoefA 0.001~1000 10
6. LVSide1InvTime3I0Stage1TimeB 0.000~100.00 100
7. LVSide1InvTime3I0Stage1IndexP 0.01~10.00 10
0: definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
132
67N)
Default
value
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
13. LVSide1InvTime3I0Stage 2TimeB 0.000~100.00 100
0: definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
16. LVS1 3I0Stage3CurrSet 0.05~200 40 A
133
67N)
Default
value
17. LVSide1 3I0Stage3Time1 0.00~100.00 100 s
22. LVSide1Dir3I0SensitiveAngle 0.00~90.00 30
23. LVSide1 3I0NSDSensitiveAngle 0.00~90.00 30
24. LVSide1 3I0RstTime 0.10~100 0.1 s
25. LVS1InvTime3I0MinTripTime 0.00~100 0.04 s
26. LVSide1 3I0Satge1Time2 0.10~100 100 s
Table 68 Earth fault protection of low voltage side1 logic switch
Setting Default
Mode value
1. LVSide1 3I0Stage1Time1On 1/0 0
1-3I0 external
2. LVSide1 3I0Stage1Extr 1/0 0 connection; 0-3I0
calculated
3. LVSide1Dir3I0Stage1 1/0 0
4. LVSide1 3I0Stage1FowardDir 1/0 0
5. LVSide1 3I0Stage1BlkBy2ndH 1/0 0
1-3I0 external
calculated
8. LVSide1Dir3I0Satge 1/0 0
LVSide1 3I0Stage2FowardDir 1- forward direction;
9. 1/0 0
1-3I0 external
calculated
13. LVSide1Dir3I0Satge3 1/0 0
1-3U0 external
16. LVSide1Extr3IO3U0 1/0 1 connection; 0-3U0
calculated
17. LVSide1ZeroSeqChkU2/I2DirOn 1/0 1
LVSide1 1-Zero sequence current
18. 1/0 0 harmonics checking
3I0HarmonChkExtrI02/I01
external connection
134
67N)
Setting Default
Mode value
I02/I01; 0-Zero sequence
current harmonics
I2/I1
19. LVSide1 3I0Satge1Time2On 1/0 0
Default
value
0: definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
LVSide2 3I0Stage1Curve SHORT INV.
1. 0~13 0
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
0: definite time
1: IEC INV.
8. LVSide2 3I0Stage2Curve 0~13 0 2: IEC VERY
INV.
3: IEC
135
67N)
Default
value
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
0: definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
136
67N)
Default
value
13: User
defined
16. LVS13I0Stage3CurrSet 0.05~200 40 A


Setting Default
Mode value
1-3I0 external
calculated
4. 1/0 0
1-3I0 external
calculated
9. 1/0 0
1-3I0 external
calculated
1-3U0 external
16. LVSide2Extr3IO3U0 1/0 1
connection; 0-3U0
137
67N)
Setting Default
Mode value
calculated
harmonics checking
LVSide2 external connection
18. 1/0 0 I02/I01; 0-Zero sequence
current harmonics
I2/I1
Default
value
0: definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
8. LVSide3 3I0Stage2Curve 0~13 0 0: definite time
138
67N)
Default
value
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
0: definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
15. LVSide3 3I0Stage3Curve 0~13 0 TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
139
67N)
Default
value
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
16. LVS13I0Stage3CurrSet 0.05~200 40 A

Setting Default
Mode value
2. LVSide3 3I0Stage1Extr 1/0 0
0-3I0 calculated
0-3I0 calculated
0-3I0 calculated
1-3U0 external
16. LVSide3Extr3IO3U0 1/0 1
connection; 0-3U0
140
67N)
Setting Default
Mode value
calculated
harmonics checking
LVSide3 external connection
18. 1/0 0 I02/I01; 0-Zero sequence
current harmonics
I2/I1
Default
value
1. HVSideHarmUnblkPhCurr 0.05In~40 In 40 A
5. LVSideHarmUnblkPhCurr 0.05In~40 In 40 A
6. LVSideOC2ndHI2/I1Ratio 0.07~0.50 0.07
7. HVSide3I0HarmUnblkCurr 0.05In~40 In 40 A
8. HVSide3I02ndHI02/I01 0.07~0.50 0.07
9. MVSide3I0HarmUnblkCurr 0.05In~40 In 40 A
10. MVSide3I02ndHI02/I01 0.07~0.50 0.07
11. LVSide3I0HarmUnblkCurr 0.05In~40 In 40 A
12. LVSide3I02ndHI02/I01 0.07~0.50 0.07
Table 74 Common logic switch

Setting Default
Mode value
1-VT failure disables
protection
1. VTFailProtOff 1/0 0
0-VT failure does not
disable protection
3.3 Report list


Trip report:
1. HVSide3I0Stage1Time1Trip /
2. HVSide3I0Satge1Time2Trip /
141
67N)
10. MVSide3I0Stage1Time1Trip /
11. MVSide3I0Satge1Time2Trip /
19. LVSide1 3I0Stage1Time1Trip /
20. LVSide1 3I0Satge1Time2Trip /
Alarm report:
If inrush conditions meet the requirements,
1. HVSide 3I0InrushBlk
blockearth fault protection.
2. MVSide 3I0InrushBlk
3. LVSide1 3I0InrushBlk

Table 76 Earth fault protection technical parameter
142
67N)
≤ ±1% setting or +40ms
Time delay 0.00s～100.00s, step 0.01s At 2 times of operating
current
Very inverse time; ≤ ±5% setting or +40ms
Extreme inverse time Under the condition 2< 3I 0 /
Long inverse time
3I 0set <20
ANSI Inverse time ANSI/IEEE C37.112,
Short inverse time ≤ ±5% setting or +40ms
Long inverse time Under the condition 2< 3I 0 /
Medium inverse time
Very inverse time; 3I 0set <20
User-defined characteristic   IEC 60255-151
curve   ≤ ±5% setting or +40ms
A
t  B  T Under the condition 2< 3I 0 /
  I  P 
  1  3I 0set <20
  Iset  
Time coefficient of inverse 0.005～1000.0, step 0.001
time : A
Time delay of inverse time: B 0.000～100.00, step 0.01
Inverse time index: P 0.01～10.00, step 0.005
Inverse time constant: T 0.025～1.5, step 0.01
Directional component
Zero sequence direction ≤ ±3°, when 3U0≥1V
160°
component action angle range
Directional sensitive angle 0°to 90°, step 1°
Negative sequence direction ≤ ±3°, when 3U2≥2V
160°
component action angle range
Directional sensitive angle 0°to 90°, step 1°
143
Chapter 12 Emergency earth fault protection(50N,51N)
Chapter 12 Emergency earth fault

protection(50N,51N)
About this chapter

This chapter describes the emergency earth fault principle,
the input and output signals, setting parameters, messages
and technical parameters.
145
1 Overview
When VT failure happens, emergency earth fault protection enables,and
emergency earth fault protection is backup overcurrent protection without
direction.
The characteristics of emergency earth fault protection are listed as follow:
1) There are 2 stages on each high and medium voltage side of which the
definite time or inverse time can be selected.(including all inverse time
characteristics that stipulated by IEC/ANSI standard );
2) The inrush locking feature of each stage is independently selectable;
3) Inrush locking is distinguished by secondary harmonic currents;
4) The maximum current of open magnetizing inrush current can be
adjusted;
5) When VT failure happens, emergency earth fault protection enables.
soft-hard parallel.

The input and output signals of emergency earth fault protection function
are shown as follow:
Emergency Zero Overcurrent Protection

1 1
BIBlk Start
2 2
Ena_*EF Operation
Figure 59 The input and output signals diagram ofemergency earth fault protection
function
The input signals are on the left side and the output signals are on the
right.
Input:
BIBlk BI blocking
EF Output:
Start IED startup
Operation Protection trip

ENA_Function Input:
146

HVSide3I0Conn:Ena_HVEF,Hard connector is
Ena_HVEF_5
Ena_*EF
MVSide3I0Conn:Ena_HVEF,Hard connector is
Ena_MVEF_5
IED is equipped with satge 2 emergency earth fault protection, please refer
to the setting list for details. Take emergency earth fault stage 1 protection
as an example to explain the principle.

When "Em3I0Stage1BlkBy2ndH"=1, inrush will be detected. There are two
inrush criteria:
Check phase current harmonics and external zero sequence current
harmonic.
1) Only when "3I0HarmonChkExtrI02/I01"=1, and "EmExtr3I0Stage1"=1,
zero sequence current harmonic is detected. When it is detected that
the ratio of second harmonic and fundamental wave is greater than
"3I02ndHI02/I01" and there is zero sequence current, then the zero
sequence inrush condition is satisfied. When the maximum
fundamental wave zero sequence current is greater than
"3I0HarmUnblkCurr", release each blocking.
2) In addition to the first case, detect the phase current harmonic. When
it is detected that the ratio of second harmonic and fundamental wave
is greater than "OC2ndHI2/I1Ratio" and there is a current, then the
inrush condition is satisfied. When the maximum fundamental wave of
phase current is greater than "HarmUnblkOCCurr", release each
blocking.
Output locking statue when any of the above second harmonic check
method is satisfied, the secondary harmonic current is high.
3I0>“3I0HarmUnblkCurr” &
&
3I02/3I0>“3I02ndHI02/I01Ratio”
Em3I0Stage1Extr=0 &
≥1
secondary harmonic current
is high.
3I0HarmonChkExtrI02/I01=1
&
Imax>“HarmUnblkPhCurr”
Ia2/Ia1>“OC2ndHI2/I1Ratio”
≥1
Ib2/Ib1>“OC2ndHI2/I1Ratio”
Ic2/Ic1>“OC2ndHI2/I1Ratio”
3I02/3I0:3I02ndH/3I0FundWave
Ia2/Ia1:PhACurr2ndH/PhACurrFundWave
Ib2/Ib1:PhBCurr2ndH/PhBCurrFundWave
Ic2/Ic1:PhCCurr2ndH/PhCCurrFundWave
Figure 60 Logic diagram of the secondary harmonic blocking of emergency earth fault
3.1.2 Definite time

When "Em3I0Stg1Curve"=0, emergency earth fault protection is the
147
definite time characteristic, inverse time function is disabled.

3I0 > “Em3I0Stage1CurrSet”
When zero sequence current is greater than "Em3I0Stage1CurrSet",
timing component starts and until "Em3I0Stage1Time“, earth fault
protection trips, when 3I0 _0<Dropout×“3I0Stage1CurrSet”, Dropout is
dropoff coefficient, timing component returns, earth fault protection resets.
3.1.3 Inverse time

When " Em3I0Stage1Curve "=1~13, emergency earth fault is the inverse
 
 
 A 
t P
 B  T
  3 I  
0
1
  3I 0set  
Where:
A:InvTimeEm3I0Stage1CoefA
P:InvTimeEm3I0Stage1IndexP
B:InvTimeEm3I0Stage1TimeB
T:InvTimeEm3I0Stage1ConstT
3I 0 : Zero sequence current setting value
3I 0set Em3I0Stage1CurrSet
If the current exceeds "Em3I0Stage1CurrSet", the timing component starts,
inverse time characteristic curve is selected by "Em3I0Stage1Curve ", A, P,
B are determined when the value is from 1 to 12, See the table below;
delay according to the setting of the A, P, B, T. While timing is up earth
fault protection trips. When the calculated delay is less than the minimum
trip delay time "3I0InvTimeMinTripTime", the component trips according to
the "3I0InvTimeMinTripTime".
Curve Curve Characteristic A P B
0 Definite time
1 IEC INV. 0.14 0.02 0
2 IEC VERY INV. 13.5 1.0 0
3 IEC EXTERMELY INV. 80.0 2.0 0
4 IEC SHORT TIME INV. 0.05 0.04 0
5 IEC LONG TIME INV. 120.0 1.0 0
6 ANSI INV. 8.9341 2.0938 0.17966
148
Curve Curve Characteristic A P B
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
9 ANSI MODERATELY INV. 0.0103 0.02 0.0228
10 ANSI VERY INV. 3.922 2.0 0.0982
11 ANSI EXTERMELY INV. 5.64 2.0 0.02434
12 ANSI DEFINITE INV. 0.4797 1.5625 0.21359
13 USER DEFINE

Take emergency earth fault protection stage 1 as an example. When VT
failure and there is no binary input blocking, if “Em3I0Stage1On”=1, then
emergency earth fault stage 1 is enabled.
If the trip conditions are met, time component starts until "
Em3I0Stage1Trip ". When IED trips, at the same time, each phase trip
states will be displayed. LED, IED output and others can be configured by
AESP.
When " Em3I0Stage1BlkBy2ndH "=1, the harmonic locking component is
put into operation, when the trip timer is time out, the inrush current is
checked, and if the current is not locked, unblock emergency earth fault
protection.
component trip triggers action, meanwhile output analog quantity of trip
time, when the component is based on the self-produce zero sequence
current judgment, self-produce zero sequence current is output; when it is
based on the external zero sequence current, external zero sequence
current is output.
3.1.5 Logic diagram
Logic diagram with the definite time emergency earth fault stage 1 as
example.
VTFailBlk
&
T1
3I0>“Em3I0Stage1CurrSet”
BIBlk
&
Em3I0Stage1Trip
2ndHCurrHigh &
“Em3I0Stage1BlkBy2ndH”=1
“Em3I0Stage1On”=1
Em3I0Stage1ProtOn
T1：“Em3I0Stage1Time”
149
Figure 61 Logic diagram of emergency earth fault protection function
3.2 Setting list

Table 79 Emergency earth fault setting on high voltage side
DefaultV
al
0:Definite time
1:IEC INV.
2:IEC VERY INV.
6:ANSI INV.
HVSideEm3I0Stage1C 7:ANSI SHORT INV.
1. 0~13 0
9:ANSI MODERATELY
INV.
10:ANSI VERY INV.
11:ANSI EXTERMELY
INV.
13:User defined
HVSideEm3I0Stage1C
2. 0.05~200 40 A
urrSet
HVSideEm3I0S1Time1
3. 0.00~100.00 100 s
Set
HVSInvTimeEm3I0S1C
4. 0.025~1.5 0.025
onstT
HVSInvTimeEm3I0S1C
5. 0.001~1000 10
oefA
HVSInvTimeEm3I0S1Ti
6. 0.000~100.00 100
meB
HVSInvTimeEm3I0S1In
7. 0.01~10.00 10
dexP
0:Definite time
1:IEC INV.
2:IEC VERY INV.
6:ANSI INV.
HVSideEm3I0Stage2C 7:ANSI SHORT INV.
8. 0~13 0
9:ANSI MODERATELY
INV.
10:ANSI VERY INV.
11:ANSI EXTERMELY
INV.
13:User defined
HVSideEm3I0Stage2C
9. 0.05~200 40 A
urrSet
HVSideEm3I0Stage2Ti
10. 0.00~100.00 100 s
me1
HVSInvTimeEm3I0S2C
11. 0.025~1.5 0.025
onstT
HVSInvTimeEm3I0S2C
12. 0.001~1000 10
oefA
150
DefaultV
al
HVSInvTimeEm3I0S2Ti
13. 0.000~100.00 100
meB
HVSInvTimeEm3I0S1In
14. 0.01~10.00 10
dexP
15. HVSide3I0RstTime 0.10~100 0.1 s
HVInvTime3I0MinTripTi
16. 0.00~100 0.04 s
me
HVSideEm3I0Stage1Ti
17. 0.10~100 100 s
me1
HVSideEm3I0Stage1Ti
18. 0.10~100 100 s
me3
HVSideEm3I0Stage2Ti
19. 0.10~100 100 s
me2
HVSideEm3I0Stage2Ti
20. 0.10~100 100 s
me3
Table 80 Emergency earth fault protection logic switch
No. LSName Setting Mode DefaultVal Comment

1. HVSideEm3I0S1Time1On 1/0 0 /
2. HVSideEm3I0Stage1Extr 1/0 0 /
3. HVSEm3I0Stage1BlkBy2ndH 1/0 0 /
5. HVSideEm3I0Stage2Extr 1/0 0 /
6. HVSEm3I0Stage2BlkBy2ndH 1/0 0 /
7. HVSide3I0HarmChkExtrI02/I01 1/0 0 /
Table 81 Emergency earth fault setting on medium voltage side
DefaultV
al
0:Definite time
1:IEC INV.
2:IEC VERY INV.
6:ANSI INV.
MVSideEm3I0Stage1C 7:ANSI SHORT INV.
1. 0~13 0
9:ANSI MODERATELY
INV.
10:ANSI VERY INV.
11:ANSI EXTERMELY
INV.
13:User defined
MVSideEm3I0Stage1C
2. 0.05~200 40 A
urrSet
MVSideEm3I0S1Time1
3. 0.00~100.00 100 s
Set
HVSInvTimeEm3I0S1C
4. 0.025~1.5 0.025
onstT
5. HVSInvTimeEm3I0S1C 0.001~1000 10
151
DefaultV
al
oefA
HVSInvTimeEm3I0S1Ti
6. 0.000~100.00 100
meB
HVSInvTimeEm3I0S1In
7. 0.01~10.00 10
dexP
0:Definite time
1:IEC INV.
2:IEC VERY INV.
6:ANSI INV.
MVSideEm3I0Stage2C 7:ANSI SHORT INV.
8. 0~13 0
9:ANSI MODERATELY
INV.
10:ANSI VERY INV.
11:ANSI EXTERMELY
INV.
13:User defined
MVSideEm3I0Stage2C
9. 0.05~200 40 A
urrSet
MVSideEm3I0Stage2Ti
10. 0.00~100.00 100 s
me1
MVSInvTimeEm3I0S2C
11. 0.025~1.5 0.025
onstT
MVSInvTimeEm3I0S2C
12. 0.001~1000 10
oefA
MVSInvTimeEm3I0S2Ti
13. 0.000~100.00 100
meB
MVSInvTimeEm3I0S1In
14. 0.01~10.00 10
dexP
15. MVSide3I0RstTime 0.10~100 0.1 s
MVInvTime3I0MinTripTi
16. 0.00~100 0.04 s
me
MVSideEm3I0Stage1Ti
17. 0.10~100 100 s
me1
MVSideEm3I0Stage1Ti
18. 0.10~100 100 s
me3
MVSideEm3I0Stage2Ti
19. 0.10~100 100 s
me2
MVSideEm3I0Stage2Ti
20. 0.10~100 100 s
me3
Table 82 Emergency earth fault protection logic switch

1. MVSideEm3I0S1Time1On 1/0 0 /
2. MVSideEm3I0Stage1Extr 1/0 0 /
3. MVSEm3I0Stage1BlkBy2ndH 1/0 0 /
5. MVSideEm3I0Stage2Extr 1/0 0 /
6. MVSEm3I0Stage2BlkBy2ndH 1/0 0 /
7. MVSide3I0HarmChkExtrI02/I01 1/0 0 /
152

No. SetName Scope Defau Unit Co

ltVal mm
1. HVSideHarmUnblkPhCurr 0.05In~40 In 40 A ent
6. HVSide3I02ndHI02/I01 0.07~0.50 0.07
7. MVSide3I0HarmUnblkCurr 0.05In~40 In 40 A
8. MVSide3I02ndHI02/I01 0.07~0.50 0.07
3.3 Report list

Table 84 Report list(2 stage is the same as 1 stage)
Trip report:
1. HVSideEm3I0S1Time1Trip /
7. MVSideEm3I0S1Time1Trip /
Alarm report:
If inrush conditions meet the requirements, blockearth fault

1. HVSide3I0InrushBlk
protection
2. MVSide3I0InrushBlk
153

Table 85 Emergency earth fault protection technical parameter
Definite time characteristic
≤ ±1% setting or +40 ms,
Time delay 0.00s～100.00s, step 0.01s
At 2 times of trip current
Very inverse time ≤ ±5% setting or +40 ms,
Extreme inverse time Under the condition 2< 3I 0 /
Long inverse time
3I 0set <20
ANSI Inverse time ANSI/IEEE C37.112,
Short inverse time ≤ ±5% setting or +40 ms,
Long inverse time Under the condition 2< 3I 0 /
Medium inverse time
Very inverse time 3I 0set <20
User defined characteristic   IEC 60255-151
curve   ≤ ±5% setting or +40 ms,
 A  Under the condition 2< 3I 0 /
t P
 B T
  3I 0   1  3I 0set <20
  3I 0set  
Time coefficient of inverse 0.005～1000.0, step 0.001
time:A
Time delay of inverse time: B 0.000～100.00, step 0.01
Inverse time index:P 0.01～10.00, step 0.005
Inverse time constant: T 0.025～1.5, step 0.01
154
Chapter 13 Negative sequence current protection (46)
Chapter 13 Negative sequence

current protection (46)
About this chapter

This chapter describes the negative sequence current
principle, the input and output signals, setting value
parameters, messages and technical parameters.
155
1 Overview
Negative sequence current protection can detect the unbalance of power
system load. When the generator connect unbalanced load, negative
sequence current protection is particularly useful. Because the unbalanced
load will produce a reverse magnetic field in the three-phase induction
motor, resulting in overheating of the rotor end. Secondly, the negative
sequence current protection can also be used to detect the disconnection,
short circuit and polarity of current transformer. Besides, the negative
sequence current protection can also detect the single-phase or two-phase
faults in the system, and the fault statue when the fault current is less than
the load current.
1) The main characteristics of the negative sequence current protection:
offer 3 stages on each high, medium and low voltage side, and definite
time or inverse time can be selected.
soft-hard parallel.

The input and output signals of negative sequence current protection
function are shown as below, the left side is input signals and the right side
is output signals:
Negative Sequence Over Current
1 Protection 1
2 BIBlk Start 2
Ena_*NSOC Operation
Figure 62 The input and output signals diagram of negative sequence current
protection function
Input:
BIBlk BI blocking
NSOC Output:
Start IED startup
Operation IED trip

ENA_Function Input:
“HVSideI2Conn”:Ena_HVNSOC,Hard
connector is Ena_HVNSOC_5
Ena_*NSOC
“MVSideI2Conn":Ena_MVNSOC,Hard
connector is Ena_MVNSOC_5
156

"LVSideI2Conn": Ena_LV1NSOC,the
corresponding hard connector is
Ena_LV1NSOC_5
IED is equipped with 3 stages of negative sequence current protection on
each high, medium and low voltage side, please refer to the setting list for
details. The negative sequence current protection stage 1 will be taken as
an example below and the principle will be introduced.

3.1.1 Definite time
When "3I2Stage1Curve "=0, negative sequence current is the definite time
characteristic, inverse time function is disabled.
The negative sequence current protection action current is calculated by
the three-phase current as follow:
İ2 = İA + a2 İB + aİC
I2 > “3I2Stage1CurrSet”
When the current is greater than "3I2Stage1CurrSet", timing component
starts and until "3I2Stage1Time”, negative sequence current protection
trips, when current I2 < Dropout × ”3I2Stage1CurrSet”, timing component
returns, negative sequence current protection resets.
Where:
I 2 : Negative sequence current;
I 2 set “3I2Stage1CurrSet”
Dropoff: Return coefficient
3.1.2 Inverse time
When "3I2Stage1Curve"=1~13, negative sequence current is the inverse
 
 
 A 
t P
 B T
  I2  1 
  I 2set  
If the negative sequence current exceeds "3I2Stage1CurrSet", the timing

delay according to the setting of the A, P, B, T. While timing is up, earth
fault protection trips. When the calculated delay time is less than the
"InvTimeI2MinTime", the component trips in accordance with the
"InvTimeI2MinTime".
Where:
157
A: "InvTime3I2Stage1CoefA"
P: "InvTime3I2Stage1IndexP"
B: "InvTime3I2Stage1TimeB"
T: "InvTime3I2Stage1ConstT"
I 2 : Negative sequence current;
I 2 set :”3I2Stage1CurrSet”
0. Definite time
1. IEC INV. 0.14 0.02 0
2. IEC VERY INV. 13.5 1.0 0
6. ANSI INV. 8.9341 2.0938 0.17966
7. ANSI SHORT INV. 0.2663 1.2969 0.03393
8. ANSI LONG INV. 5.6143 1 2.18592
10. ANSI VERY INV. 3.922 2.0 0.0982
13. USER DEFINE

When negative sequence current protection function is enabled and no BI
blocking, if the "3I2Stage1On"=1, the negative sequence current
protection of the corresponding stage is enabled.
Negative sequence current protection is tripped, after the starting of
protection trip, if the action conditions are met, timing component starts,
take stage 1 for example, when time is over, "3I2Stage1Trip" is issued.
LED and protection trip can be configured by AESP. When the zero
sequence current component trips negative sequence current value will
also be displayed.
158
Negative Sequence Overcurrent

Stage1 Protection Function On
&
&
“3I2Stage1On”=1 T1 Negative Sequence Overcurrent
Stage1 Protection Trip
3I2>“3I2Stage1CurrSet”
Binary Blocking
T1：“3I2Stage1Time”
Figure 63 Logic diagram of negative sequence current protection function
3.2 Setting list

Table 88 Negative sequence current setting on high voltage side
Default
value
0: definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
1. HVSideI2Stage1Curve 0~13 0
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
2. HVSideI2Stage1CurrSet 0.05In~40 40 A
3. HVSideI2Stage1Time 0.00~100.00 100 s
4. HVSideInvTimeI2Stage1CoefT 0.025~1.5 0.025
5. HVSideInvTimeI2Stage1CoefA 0.001~1000 10
6. HVSideInvTimeI2Stage1CoefB 0.000~100.00 100
7. HVSideInvTimeI2Stage1IndexP 0.01~10.00 10
HVSideI2Stage2Curve 0: definite time

8. 0~13 0
1:IEC INV.
159
Default
value
2:IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
9. HVSideI2Stage2CurrSet 0.05In~40 In 40 A

0: definite time
1:IEC INV.
2:IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
15. HVSideI2Stage3Curve 0~13 0 TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
160
Default
value
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
16. HVSideI2Stage3CurrSet 0.05In~40 In 40 A
22. HVSideI2RstTime 0.00~100.00 0.04 s

23. HVInvTimeI2MinTripTime 0.10~100.00 0.10 s
24. HVSideI2Satge1Time2 0.10~100.00 100 s
Table 89 Negative sequence current protection of high voltage side logic switch
Set Default
mode value
1. HVSideI2Stage1Time1On 1/0 0
Table 90 Negative sequence current setting on medium voltage side

Default
value
0: definite time
1. MVSideI2Stage1Curve 0~13 0 1: IEC INV.
2: IEC VERY
161
Default
value
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
2. MVSideI2Stage1CurrSet 0.05In~40 40 A
3. MVSideI2Stage1Time 0.00~100.00 100 s
4. MVSideInvTimeI2Stage1CoefT 0.025~1.5 0.025
5. MVSideInvTimeI2Stage1CoefA 0.001~1000 10
6. MVSideInvTimeI2Stage1CoefB 0.000~100.00 100
7. MVSideInvTimeI2Stage1IndexP 0.01~10.00 10
0: definite time
1:IEC INV.
2:IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
MVSideI2Stage2Curve TIME INV.
8. 0~13 0
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
162
Default
value
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
9. MVSideI2Stage2CurrSet 0.05In~40 In 40 A

0: definite time
1:IEC INV.
2:IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
15. MVSideI2Stage3Curve 0~13 0
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
16. MVSideI2Stage3CurrSet 0.05In~40 In 40 A
22. MVSideI2RstTime 0.00~100.00 0.04 s
163
Default
value
23. MVInvTimeI2MinTripTime 0.10~100.00 0.10 s
24. MVSideI2Satge1Time2 0.10~100.00 100 s
Table 91 Negative sequence current protection of medium voltage side logic switch
Set Default
mode value
1. MVSideI2Stage1Time1On 1/0 0
Table 92 Negative sequence current setting on low voltage side1

Default
value
0: definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
1. LVSide1I2Stage1Curve 0~13 0 6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
164
Default
value
INV.
12: ANSI
DEFINITE INV.
13: User
defined
2. LVSide1I2Stage1CurrSet 0.05In~40 40 A
3. LVSide1I2Stage1Time 0.00~100.00 100 s
4. LVSide1InvTimeI2Stage1CoefT 0.025~1.5 0.025
5. LVSide1InvTimeI2Stage1CoefA 0.001~1000 10
6. LVSide1InvTimeI2Stage1CoefB 0.000~100.00 100
7. LVSide1InvTimeI2Stage1IndexP 0.01~10.00 10
0: definite time
1:IEC INV.
2:IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8. LVSide1I2Stage2Curve 0~13 0
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
9. LVSide1I2Stage2CurrSet 0.05In~40 In 40 A

0: definite time
1:IEC INV.
15. LVSide1I2Stage3Curve 0~13 0
2:IEC VERY
INV.
165
Default
value
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
16. LVSide1I2Stage3CurrSet 0.05In~40 In 40 A
22. LVSide1I2RstTime 0.00~100.00 0.04 s
23. LVS1InvTimeI2MinTripTime 0.10~100.00 0.10 s
24. LVSide1I2Satge1Time2 0.10~100.00 100 s
Table 93 Negative sequence current protection of low voltage side1 logic switch
Set Default
mode value
1. LVSide1I2Stage1Time1On 1/0 0
166
3.3 Report list


Trip report:
1. HVSideI2Satge1Time1Trip /
4. MVSideI2Satge1Time1Trip /
7. LVSide1I2Satge1Time1Trip /

Table 95 Negative sequence current protection technical parameter
Items Setting range Trip value error
0.05In~40In ≤ ±2.5% setting value or
Current setting
±0.02In
≤ ± 1% times of setting or
Time setting 0.00s～100.00s, step 0.01s +40ms, when trip current is
set as 200% setting
Reset time About 40ms
DropoffCoef About 0.95, when I/In > 0.5
0.05In~40In ≤ ±2.5% setting value or
Current setting
±0.02In
IEC standard curve Normal inverse time; ≤ ±5% setting or +40ms,
Very inverse time; when 2< I 2 / I 2 set <20, it
Extreme inverse time; meets IEC60255-151
Long inverse time; standard
ANSI standard curve Standard inverse time; ≤ ±5% times of setting or
Short inverse time +40ms, when 2< I 2 / I 2 set
Long inverse time; <20, it meets
Normal inverse time; ANSI/IEEEC37.112 standard
Very inverse time;
Extreme inverse time;
User-defined inverse time;
167

User defined curve   ≤ ±5% times of setting or
  +40ms, when 2< I 2 / I 2 set
T= t   A 
 B T
 P <20, it meets IEC 60255-151
  I2  1  standard
  I 2set  
Time coefficient of inverse 0.001~10.0, step0.001
time : A
Time delay of inverse time: 0.000 to 100.00, step 0.01
B
Inverse time index: P 0.01 to 10.00, step 0.005
Inverse time constant :T 0.025 to 1.5, step 0.01
Reset time Approx. 40ms
168
Chapter 14 Overvoltage protection (59)
Chapter 14 Overvoltage protection

(59)
About this chapter

This chapter describes the overvoltage principle, the input
and output signals, setting value parameters, reports and
technical parameters.
169
1 Overview
Overvoltage protection is used to prevent the impact of overvoltage on
electrical equipment. The abnormal overvoltage often occurs in low load,
long transmission line, generator voltage regulation fails in the islanded
system, or the load shedding of the generator in the system. Even if the
compensating capacitor can compensate line capacitance, lower the
overvoltage of the lines, when the compensating capacitor fails,
overvoltage will endanger the line insulation system, here the circuit must
be removed.
Overvoltage protection has the following characteristics:
1) Definite or inverse time can be selected on each 2 stages of
high/medium/low voltage side;
2) Set the alarm or trip in stage;
3) Measured voltage can be phase-to-earth voltage or phase-to-phase
voltage;
4) Dropoff coefficient is adjustable.
5) When the voltage connector of local side is disabled, the overvoltage
protection of local side is also disabled.
soft-hard parallel.

The input and output signals of overvoltage protection function are shown
as below, the left side is input signals and the right side is output signals:
Overvoltage Protection
1 1
BIBlk Start
2 2
Ena_*OV Operation
3 3
Ena_*Voltage PhaseA
4
PhaseB
5
PhaseC
Figure 64 The input and output signals of overvoltage protection function diagram
Input:
BIBlk BI blocking
OV
Output:
Start IED startup
170
Operation IED trip
PhaseA Phase A trip
PhaseB Phase B trip
PhaseC Phase C trip
Input:
"HVSideOVConn": Ena_HVOV,the corresponding
ENA_Function hard connector is Ena_Ena_HVOV_5
Ena_ *OV
"MVSideOVConn": Ena_MVOV,the corresponding
hard connector is Ena_MVOV_5
Input:
"HVSideVoltConn": Ena_HVoltage,the hard
Ena_*Voltage connector is Ena_HVoltage_5
Ena_*Voltage
"MVSideVoltConn": Ena_MVoltage,the hard
When the voltage connector of local side is disabled, the overvoltage
protection of local side is also disabled.
Overvoltage protection selects the phase voltage or line voltage through
the on-off logic switch "OVChkPEVolt". Logic switch "OVChkPEVolt" set 1,
select the phase voltage UA-N, UB-N, UC-N; Logic switch "OVChkPEVolt"
set 0, select the line voltage UA-B, UB-C, UC-A. The overvoltage
protection of stage 1 will be taken as an example in below and the principle
will be introduced.
3.1.1 Definite time
When "OVStage1Curve"=0, overvoltage is the define time characteristic,
inverse time function is disabled.
U_∅> "OVStage1VoltSet", (∅=a, b, c)
When "OVChkPEVolt"=1, use the phase-to-earth voltage; when
"OVChkPEVolt"=0, use the phase-to-phase voltage. When the
phase-to-earth (phase-to-phase) voltage is greater than
"OVStage1VoltSet", timing component starts and until timing to the
"OVStage1Time", overvoltage protection trips, when the phase-to-earth
(phase-to-phase) voltage U_∅<overvoltage reset
coefficient×"OVStage1VoltSet", timing component returns, overvoltage
protection resets.
3.1.2 Inverse time
When "OVStage1Curve"=1-13, overvoltage is the inverse time
characteristic, define time function is disabled.
171
 
 
A
t  B  T
  U P 
  1 
  Uset  
Where:
A: "InvTimeOVStage1CoefA"
P: "InvTimeOVStage1IndexP"
B: "InvTimeOVStage1TimeB"
T: "InvTimeOVStage1ConstT"
U  : Phase-to-earth/phase-to-phase voltage
U set "OVStage1VoltSet"
When "OVChkPEVolt"=1, use the phase-to-earth voltage; when
"OVChkPEVolt"=0, use the phase-to-phase voltage. If the phase-to-earth
(phase-to-phase) voltage exceeds "OVStage1VoltSet", the timing
delay according to the setting of the A, P, B, T. When the calculated delay
time is less than "InvTimeOVMinTime", the component will trip in
accordance with the "InvTimeOVMinTime".
Inverse time
Curve A P B
characteristic
0. Definite time
1. IEC INV. 0.14 0.02 0
2. IEC VERY INV. 13.5 1.0 0
4. IEC SHORT INV 0.05 0.04 0
5. IEC LONG INV. 120.0 1.0 0
6. ANSI INV. 8.9341 2.0938 0.17966
7. ANSI SHORT INV. 0.2663 1.2969 0.03393
8. ANSI LONG INV. 5.6143 1 2.18592
10. ANSI VERY INV. 3.922 2.0 0.0982
172
Inverse time
Curve A P B
characteristic
13. User defined

When overvoltage protection is enabled and there is no binary input
blocking, if "OVStage1On"=1, then overvoltage protection of the
corresponding stage is enabled.
Negative sequence voltage protection is tripped, after the starting of
protection trip, if the action conditions are met, timing component starts,
take stage 1 for example, when time is over, "OVStage1Trip" is issued.
LED and protection trip can be configured by AESP.
The three-phase analog quantity U1, U2 and U3 of the trip time issued
when the overvoltage protection trips, the component is based on the
phase-to-earth voltage judgment, it issues three-phase phase-to-earth
voltage; when it is based on the phase-to-phase voltage judgment, it
issues three-phase phase-to-phase voltage.
3.1.4 Logic diagram
The logic diagram of overvoltage protection is shown in following figure.
max(Ua,Ub,Uc)>“OVStage1VoltSet” &
“OVChk1Ph”=1 ≥1
min(Ua,Ub,Uc)>“OVStage1VoltSet” &
“OVChk1Ph”=0
&
“OVChkPEVolt”=1
max(Uab,Ubc,Uca)>“OVStage1VoltSet” &
min(Uab,Ubc,Uca)>“OVStage1VoltSet” &
& &
T1 Overvoltage Stage 1
Protection Trip
“OVChkPEVolt”=0
Overvoltage Stage 1 Protection Function On
“OVStage1On”=1
the voltage connector of local side=1
T1：“OVStage1Time”
Figure 65 The logic diagram of overvoltage protection
3.2 Setting list

Table 98 Overvoltage protection setting of high voltage side
Default
value
0: definite time
1: IEC INV.
2: IEC VERY
1. HVSideOVStage1Curve 0~13 0
INV.
3: IEC
EXTERMELY
173
Default
value
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
2. HVSideOVStage1VoltSet 40.00~200.0 110 V
3. HVSideOVStage1Time 0.00~120.00 120 s
4. HVSideInvTimeOVStage1ConstT 0.025~1.5 0.025

Inverse time
5. HVSideInvTimeOVStage1CoefA 0.001~1000 10 s
characteristic
6. HVSideInvTimeOVStage1TimeB 0.000~100.00 100
7. HVSideInvTimeOVStage1IndexP 0.01~10.00 10
0: definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
8. HVSideOVStage2Curve 0~13 0 7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
174
Default
value
DEFINITE INV.
13: User
defined
9. HVSideOVStage2VoltSet 40.00~200.0 110 V
10. HVSideOVStage2Time 0.00~120.00 120 s
11. HVSideInvTimeOVStage2ConstT 0.025~1.5 0.025

Inverse time
12. HVSideInvTimeOVStage2CoefA 0.001~1000 10 s
characteristic
13. HVSideInvTimeOVStage2TimeB 0.000~100.00 100
14. HVSideInvTimeOVStage2IndexP 0.01~10.00 10
15. HVSideOVDropoffCoef 0.95~1 1
16. HVSideOVRstTime 0.00~100.00 0.04 s
17. HVInvTimeOVMinTripTime 0.10~100 0.10 s
Table 99 Overvoltage protection logic switch of high voltage side

Set Default
mode value
1. HVSideOVStage1On 1/0 0 /
2. HVSideOVStage2On 1/0 0 /
3. HVSideOVChkPEVolt 1/0 0 /
4. HVSideOVChk1Ph 1/0 0 /
Table 100 Overvoltage protection setting of medium voltage side
Default
value
0: definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
1. MVSideOVStage1Curve 0~13 0 7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
175
Default
value
DEFINITE INV.
13: User
defined
2. MVSideOVStage1VoltSet 40.00~200.0 110 V
3. MVSideOVStage1Time 0.00~120.00 120 s
4. MVSideInvTimeOVStage1ConstT 0.025~1.5 0.025

Inverse time
5. MVSideInvTimeOVStage1CoefA 0.001~1000 10 s
characteristic
6. MVSideInvTimeOVStage1TimeB 0.000~100.00 100
7. MVSideInvTimeOVStage1IndexP 0.01~10.00 10
0: definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8. MVSideOVStage2Curve 0~13 0
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
9. MVSideOVStage2VoltSet 40.00~200.0 110 V
10. MVSideOVStage2Time 0.00~120.00 120 s

11. MVSideInvTimeOVStage2ConstT 0.025~1.5 0.025
Inverse time
12. MVSideInvTimeOVStage2CoefA 0.001~1000 10 s
characteristic
13. MVSideInvTimeOVStage2TimeB 0.000~100.00 100
14. MVSideInvTimeOVStage2IndexP 0.01~10.00 10
15. MVSideOVDropoffCoef 0.95~1 1
16. MVSideOVRstTime 0.00~100.00 0.04 s
17. MVInvTimeOVMinTripTime 0.10~100 0.10 s
176
Table 101 Overvoltage protection logic switch of medium voltage side

Setting Default
Mode value
1. MVSideOVStage1On 1/0 0 /
2. MVSideOVStage2On 1/0 0 /
3. MVSideOVChkPEVolt 1/0 0 /
4. MVSideOVChk1Ph 1/0 0 /
3.3 Report list

Table 102 Report list(2 stage is the same as 1 stage)

Trip report:
1. HVSideOVStage1Trip /
2. HVSideOVStage2Trip /
3. MVSideOVStage1Trip /
4. MVSideOVStage2Trip /

Table 103 Overvoltage protection technical parameter
Voltage wiring type PPVolt or phase-to-earth ≤ ±2.5% setting or ±1V
voltage
Phase voltage setting value 40V～100V, step 0.01V ≤ ±2.5% setting or ±1V
Line voltage setting 80V～200V, step 0.01V ≤ ±2.5% setting or ±1V
DropoffCoef 0.95～1, step 0.01 ≤ ±3% setting
Time delay setting 0.00s～120.00s, step 0.01s ≤ ±1% setting or +60 ms,
At 1.2 times of trip voltage
Reset time <40ms
Phase voltage setting value 40V～100V, step 0.01V ≤ ±2.5% setting or ±1V
Line voltage setting 80V～200V, step 0.01V ≤ ±2.5% setting or ±1V
IEC standard curve Normal inverse time; U U
Very inverse time; In the case of 2<  / set
Extreme inverse time; <20, the allowable trip time
Long inverse time; error is: ± 5% or +60 ms;
ANSI standard curve Standard inverse time; U U
Short inverse time In the case of 2<  / set
Long inverse time; <20, the allowable trip time
Normal inverse time; error is: ± 5% or +60 ms;
Very inverse time;
User defined curve   U U
  In the case of 2<  / set
T= t   A 
 B T
<20, it meets the
 P IEC60255-151 standard
  I2  1 
  I 2set  
Time coefficient of inverse 0.001 to 10.0, step 0.001
177

time : A
Time delay of inverse time 0.000 to 100.00, step 0.01
B
Inverse time constant: T 0.025 to 1.5, step 0.01
178
Chapter 15 Zero sequence voltage protection(64)
Chapter 15 Zero sequence voltage

protection (64)
About this chapter

This chapter describes the zero sequence voltage principle,
the input and output signals, setting value parameters,
179
Chapter 15 Zero sequence voltage protection (64)
1 Overview
Zero sequence voltage protection is generally used in the power network
with small grounding fault current.
The main features of zero sequence voltage protection are as follows:
1) It provides 1 stages of definite time and reverse time selective
protection;
2) Zero sequence voltage 3U0 can be selected as self-produce zero
sequence voltage (the total of three phase measurement voltage), or
external zero sequence voltage (zero sequence residual voltage).
3) When zero sequence voltage is self-produced. if the voltage connector
of local side is disabled, zero sequence overvoltage protection is
disabled.
soft-hard parallel.

The input and output signals of zero sequence voltage protection function
diagram is shown below, left side is input and right side is output:
Voltage Displacement Protection
1 1
BIBlk Start
2 2
Ena_*ZSOV Operation
3
Ena_*Voltage
Figure 66 The input and output signals diagram of zero sequence voltage protection
function
Input:
BIBlk BI blocking
ZSOV Output:
Start IED startup
Operation IED trip

Input:
ENA_Function
Ena_*ZSOV HVSide3U0Conn:Hard connector is Ena_HVZSOV_5
180
MVSide3U0Conn:Hard connector is Ena_MVZSOV_5

"LVSide1 3U0Conn":The corresponding hard
connector is Ena_LV1ZSOV_5
"LVSide2 3I0Conn": The corresponding hard
connector is Ena_LV2ZSOV_5
Input:
"HVSideVoltConn":Ena_HVoltage,the corresponding
"MVSideVoltConn":Ena_MVoltage,the hard connector
Ena_*Voltage is Ena_MVoltage_5
Ena_*Voltage
"LVSide1VoltConn": Ena_L1Voltage,the hard
connector is Ena_L1Voltage_5
"LVSide2VoltConn": Ena_L2Voltage,the hard
connector is Ena_L2Voltage_5
When zero sequence voltage is self-produced, if the voltage connector of
local side is disabled, zero sequence overvoltage protection is disabled.
Zero sequence voltage protection is used for ground fault check. Zero
sequence voltage protection can be set as alarm or trip, reverse and
reverse time are selective.
Compare the external or self-produce zero sequence voltage and the
corresponding setting value, if it is greater than the setting, trip timer starts.
Timer starts timed to the user defined time delay. The time delay setting
can be adjusted independently by settings. When time delay defined by
the users is over, the protection device sends out a trip command. The
zero sequence voltage protection stage 1 will be taken as an example
below and the principle will be introduced.
3.1.1 Definite time
When "3U0Stage1CurveSel" =1~0, zero sequence voltage is definite time
characteristic.
3U0 > “3U0Stage1VoltSet”
If the zero sequence voltage exceeds the inverse time starting setting
"3U0Stage1VoltSet", the start signal is triggered and timing component
starts, time to "3U0Stage1Time", zero sequence voltage protection trips.
3.1.2 Inverse time
When "3U0Stage1CurveSel" =1~13, zero sequence voltage is the inverse
time characteristic.
 
 
 A 
t P
 B T
  3U 0   1 
  3U 0set  
Where:
181
A:”InvTime3U0Stage1CoefA”
P:”InvTime3U0Stage1IndexP”
B: "InvTime3U0Stage1TimeB"
T: "InvTime3U0Stage1ConstT"
3U 0 : 3U0
3U 0set : "3U0Stage1VoltSet"
If the zero sequence voltage exceeds "3U0Stage1VoltSet", Start signal is
triggered and the timing component starts, inverse time characteristic
curve is selected by curve, A, P, B are determined when the value is from
1 to 12, see the following table; when the value is 13, it is the user defined
characteristic, calculate the trip delay in accordance with the setting of the
A, P, B, T. When the timing is up, and zero sequence voltage protection
trips. When the calculated delay time is less than the
"InvTime3U0MinTime", the component will trip according to the
"InvTime3U0MinTime".
0. Definite time
1. IEC INV. 0.14 0.02 0
2. IEC VERY INV. 13.5 1.0 0
4. IEC SHORT INV 0.05 0.04 0
5. IEC LONG INV. 120.0 1.0 0
6. ANSI INV. 8.9341 2.0938 0.17966
7. ANSI SHORT INV. 0.2663 1.2969 0.03393
8. ANSI LONG INV. 5.6143 1 2.18592
10. ANSI VERY INV. 3.922 2.0 0.0982
13. User defined

When zero sequence voltage protection is enabled and no binary input
blocking, if "3U0Stage1On"=1, then zero sequence voltage protection is
enabled.
Zero sequence voltage protection is tripped, after the starting of protection
182
trip, if the action conditions are met, timing component starts, take stage 1
for example, when time is over, "3U0Stage1Trip" is issued. LED and
Zero sequence voltage protection simultaneously outputs the trip value at
the corresponding time during operation.
3.2 Setting list

Table 106 Zero sequence voltage protection setting of high voltage side
Default
value
0:Definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
1. HVSide3U0Stage1CurveSel 0~13 0
8: ANSI LONG
INV.
9: ANSI
MODERATEL
Y INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
2. HVSide3U0Stage1Set 2.00~100.0 100 V
3. HVSide3U0Stage1Time 0.00~120.00 120 s

HVSideInvTime3U0Stage1Cons
4. 0.025~1.5 0.025
tT
HVSideInvTime3U0Stage1Coef
5. 0.001~1000 10
A
HVSideInvTime3U0Stage1Time
6. 0.000~100.00 100
B
HVSideInvTime3U0Stage1Inde
7. 0.01~10.00 10
P
8. HVSide3U0RstTime 0.0~100 0.04 s
9. HVInvTime3U0MinTripTime 0.100~100.00 0.1 s
183
Table 107 Zero sequence voltage protection logic switch of high voltage side
Default
Number Logic switch name Range Remark
value
1. HVSide3U0Stage1On 1/0 0
1- Zero sequence external
connection
2. HVSideExtr3U0 1/0 0
0- Zero sequence voltage
calculated
Table 108 Zero sequence voltage protection setting of medium voltage side
Default
value
0:Definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
1. MVSide3U0Stage1CurveSel 0~13 0
8: ANSI LONG
INV.
9: ANSI
MODERATEL
Y INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
2. MVSide3U0Stage1Set 2.00~100.0 100 V
3. MVSide3U0Stage1Time 0.00~120.00 120 s

MVSideInvTime3U0Stage1Cons
4. 0.025~1.5 0.025
tT
MVSideInvTime3U0Stage1Coef
5. 0.001~1000 10
A
MVSideInvTime3U0Stage1Time
6. 0.000~100.00 100
B
MVSideInvTime3U0Stage1Inde
7. 0.01~10.00 10
P
8. MVSide3U0RstTime 0.0~100 0.04 s
9. MVInvTime3U0MinTripTime 0.100~100.00 0.1 s
Table 109 Zero sequence voltage protection logic switch of medium voltage side
184
Default
value
1. MVSide3U0Stage1On 1/0 0
connection
2. MVSideExtr3U0 1/0 0
calculated
Table 110 Zero sequence voltage protection setting of low voltage side1
Default
value
0:Definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
1. LVSide13U0Stage1CurveSel 0~13 0
8: ANSI LONG
INV.
9: ANSI
MODERATEL
Y INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
2. LVSide13U0Stage1Set 2.00~100.0 100 V
3. LVSide13U0Stage1Time 0.00~120.00 120 s

LVSide1InvTime3U0Stage1Con
4. 0.025~1.5 0.025
stT
LVSide1InvTime3U0Stage1Coef
5. 0.001~1000 10
A
LVSide1InvTime3U0Stage1Time
6. 0.000~100.00 100
B
LVSide1InvTime3U0Stage1Inde
7. 0.01~10.00 10
P
8. LVSide13U0RstTime 0.0~100 0.04 s
9. LV1InvTime3U0MinTripTime 0.100~100.00 0.1 s
185
Table 111 Zero sequence voltage protection logic switch of low voltage side1
Default
value
1. LVSide13U0Stage1On 1/0 0
connection
2. LVSide1Extr3U0 1/0 0
calculated
Table 112 Zero sequence voltage protection setting of low voltage side2
Default
value
0:Definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
1. LVSide2 3U0Stage1CurveSel 0~13 0
8: ANSI LONG
INV.
9: ANSI
MODERATEL
Y INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
2. LVSide2 3U0Stage1Set 2.00~100.0 100 V
3. LVSide2 3U0Stage1Time 0.00~120.00 120 s

LVSide2InvTime3U0Stage1Con
4. 0.025~1.5 0.025
stT
LVSide2InvTime3U0Stage1Coef
5. 0.001~1000 10
A
LVSide2InvTime3U0Stage1Time
6. 0.000~100.00 100
B
LVSide2InvTime3U0Stage1Inde
7. 0.01~10.00 10
P
8. LVSide2 3U0RstTime 0.0~100 0.04 s
9. LV2InvTime3U0MinTripTime 0.100~100.00 0.1 s
186
Table 113 Zero sequence voltage protection logic switch of low voltage side2
Default
value
1. LVSide2 3U0Stage1On 1/0 0
connection
2. LVSide2Extr3U0 1/0 0
calculated
3.3 Report list


Trip report:
1. HVSide3U0Trip /
2. MVSide3U0Trip
3. LVSide1 3U0Trip
4. LVSide2 3U0Trip

Table 115 Zero sequence voltage protection technical parameter
Operating voltage 3V0 2V to 100V, step 1V ≤ ±5% setting or ±1V
(self-produced)
Trip time 0.00 - 60.00s, step 0.01s ≤ ±1% setting or +50 ms,
when trip voltage is set as
120% of setting
DropoffCoef About 0.95
Operating voltage 3V0 2V～100V, step 0.01V, ≤ ±5% setting or ±1V
(self-produced)
IEC standard curve Normal inverse time; 3U 3U set
Very inverse time; In the case of 2< 0 / 0
ANSI standard curve Standard inverse time; 3U 3U set
Short inverse time In the case of 2< 0 / 0
Very inverse time;
User defined curve   3U 3U 0set
  In the case of 2< 0 /
T= t   A

 <20, it meets the
 P
B  T IEC60255-151 standard
  3U  
0
1
  3U 0set  
time : A
Time delay of inverse 0.000 to 100.00, step 0.01
time: B
187

188
Chapter 16 Negative sequence voltage protection (47)
Chapter 16 Negative sequence

voltage protection (47)
About this chapter

This chapter describes the negative sequence voltage
principles, the input and output signals, setting parameters,
189
1 Overview
In normal operating three-phase system, the negative sequence voltage is
almost 0, and the negative sequence voltage will occur when there is
asymmetrical situation in the system. Negative sequence voltage
protection is operated by checking negative sequence voltage.
The main features of negative sequence voltage protection are as follows:
1) High/medium voltage sides provide 2 stages of protection on each
side and definite or inverse time can be selected.
2) When the voltage connector of local side is disabled, the negative
sequence overvoltage protection is disabled.
soft-hard parallel.

The input and output signals of negative sequence voltage protection
function are shown below, left side is input and right side is output:
Negative Sequence Over Voltage
Protection
1 1
BIBlk Start
2 2
Ena_*NSOV Operation
3
Ena_*Voltage
Figure 67 The input and output signals diagram of negative sequence voltage
protection function
Input:
BIBlk BI blocking
NSOV Output:
Start IED startup
Operation IED trip
Input:
"HVSideU2Conn":Ena_HVNSOV,the
ENA_Function corresponding hard connector is
Ena_*NSOV Ena_HVNSOV_5
“MVSideU2Conn:Ena_MVNSOV,Hard
connector is Ena_MVNSOV_5
Ena_*Voltage Input:
190

"HVSideVoltConn":Ena_HVoltage,the
Ena_HVoltage_5
Ena_*Voltage
"MVSideVoltConn":Ena_MVoltage,the
Ena_MVoltage_5
When the voltage connector of local side is disabled, the negative
sequence overvoltage protection is disabled.
The negative sequence voltage protection stage 1 will be taken as an
example below and the principle will be introduced.
3.1.1 Definite time
When "3U2Stage1Curve"=0, negative sequence voltage is the inverse
The negative sequence voltage protection trip voltage is calculated by the
three-phase voltage as follow:
U̇2 = U̇A + a2 U̇B + aU̇C
U2 > “3U2Stage1VoltSet”
If the voltage is exceeds "3U2Stage1VoltSet", timing component starts and
until timing to "3U2Stage1Time", negative sequence voltage protection
trips.
Where:
U 2 :Negative sequence voltage
3.1.2 Inverse time

When "3U2Stage1Curve"=1~13, negative sequence voltage is the inverse
 
 
 A 
t P
 B T
  U2  1 
 U 2set  
If the voltage exceeds "3U2Stage1VoltSet", the timing component starts,

inverse time characteristic curve is selected by inverse time characteristic
curve, A, P, B are determined when the value is from 1 to 12, see Table 3;
when the value is 13, it is the user defined characteristics, calculate the trip
delay in accordance with the setting of the A, P, B, T. timing, negative
sequence voltage protection trips. When the calculated delay time is less
than the "InvTimeU2MinTime", the component will trip in accordance with
the "InvTimeU2MinTime".
Where:
A: "InvTime3U2Stage1CoefA"
191
P: "InvTime3U2Stage1IndexP"
B: "InvTime3U2Stage1TimeB"
T: "InvTime3U2Stage1ConstT"
U2
: Negative sequence voltage
U 2 set
: "3U2Stage1VoltSet"
0. Definite time
1. IEC INV. 0.14 0.02 0
2. IEC VERY INV. 13.5 1.0 0
6. ANSI INV. 8.9341 2.0938 0.17966
7. ANSI SHORT INV. 0.2663 1.2969 0.03393
8. ANSI LONG INV. 5.6143 1 2.18592
10. ANSI VERY INV. 3.922 2.0 0.0982
13. USER DEFINE

When negative sequence voltage protection function is enabled and there
is no binary input blocking, if "3U2Stage1On"=1, then the negative
sequence voltage protection is enabled.
After the protection trip starts, if the trip conditions are satisfied, timing
component starts, and works till the IED issues "U2Trip". LED and
3.2 Setting list

Table 118 Negative sequence voltage protection setting of high voltage side
Default
value
0:definite time
1. HVSideU2Stage1Curve 0~13 0 1: IEC INV.
2: IEC VERY
192
Default
value
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
2. HVSideU2Stage1VoltSet 40~100.00 100 V
3. HVSideU2Stage1Time 0.00~100.00 100 s
4. HVSideInvTimeU2Stage1ConstT 0.025~1.5 0.025
5. HVSideInvTimeU2Stage1CoefA 0.001~1000 10
6. HVSideInvTimeU2Stage1TimeB 0.000~100.00 100
7. HVSideInvTimeU2Stage1IndexP 0.01~10.00 10
0:definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
8. HVSideU2Stage2Curve 0~13 0
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
193
Default
value
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
9. HVSideU2Stage2VoltSet 40~100.00 100 V
10. HVSideU2Stage2Time 0.00~100.00 100 s
11. HVSideInvTimeU2Stage2ConstT 0.025~1.5 0.025
12. HVSideInvTimeU2Stage2CoefA 0.001~1000 10
13. HVSideInvTimeU2Stage2TimeB 0.000~100.00 100
14. HVSideInvTimeU2Stage2IndexP 0.01~10.00 10
15. HVSideU2RstTime 0.000~100.00 0.04 s
16. HVInvTimeU2MinTripTime 0.100~100.00 0.1 s
Table 119 Negative sequence voltage protection logic switch on high voltage side
Setting
Number Logic switch name Default value Remark
Mode
1. HVSideU2Stage1On 1/0 0
2. HVSideU2Stage2On 1/0 0
Table 120 voltage protection setting of medium voltage side

Default
value
0:definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
1. MVSideU2Stage1Curve 0~13 0 SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
194
Default
value
defined
2. MVSideU2Stage1VoltSet 40~100.00 100 V
3. MVSideU2Stage1Time 0.00~100.00 100 s
4. MVSideInvTimeU2Stage1ConstT 0.025~1.5 0.025
5. MVSideInvTimeU2Stage1CoefA 0.001~1000 10
6. MVSideInvTimeU2Stage1TimeB 0.000~100.00 100
7. MVSideInvTimeU2Stage1IndexP 0.01~10.00 10
0:definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8. MVSideU2Stage2Curve 0~13 0
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
9. MVSideU2Stage2VoltSet 40~100.00 100 V
10. MVSideU2Stage2Time 0.00~100.00 100 s
11. MVSideInvTimeU2Stage2ConstT 0.025~1.5 0.025
12. MVSideInvTimeU2Stage2CoefA 0.001~1000 10
13. MVSideInvTimeU2Stage2TimeB 0.000~100.00 100
14. MVSideInvTimeU2Stage2IndexP 0.01~10.00 10

15. MVSideU2RstTime 0.000~100.00 0.04 s
16. MVInvTimeU2MinTripTime 0.100~100.00 0.1 s
195
Table 121 Negative sequence voltage protection logic switch on medium voltage side
Setting
Mode
1. MVSideU2Stage1On 1/0 0
2. MVSideU2Stage2On 1/0 0
3.3 Report list


Trip report:
1. HVSideU2Stage1Trip /
2. HVSideU2Stage2Trip /
3. MVSideU2Stage1Trip /
4. MVSideU2Stage2Trip /

Table 123 Negative sequence voltage protection technical parameter
Trip voltage 3U2 (self-produce) 40.0V to 100V, step 0.01V ≤ ±5% setting or ±1V
Time setting 0.00 to 100.00s, step 0.01s ≤ ±1% setting or +60 ms,
when trip voltage is set as
120% of setting
Trip voltage 3U2 (self-produce) 40V～100V, step 0.01V, ≤ ±5% setting or ±1V
IEC standard curve Normal inverse time; U U set
Very inverse time; In the case of 2< 2 / 2
ANSI standard curve Standard inverse time; U U set
Short inverse time In the case of 2< 2 / 2
Very inverse time;
User defined curve   U U 2 set
  In the case of 2< 2 /
T= t   A 
 B T
<20, it meets the
 P IEC60255-151 standard
  U2  1 
 U 2set  
time : A
Time delay of inverse time B 0.000 to 100.00, step 0.01
196
Chapter 17 Undervoltage protection (27)
Chapter 17 Undervoltage protection

(27)
About this chapter

This chapter describes the principles of undervoltage
protection, the input and output signals, setting parameters,
197
1 Overview
Undervoltage protection can effectively protect the power equipment from
the impact of voltage drop.
The main features of undervoltage protection are as follows:
1) It provides 2 stages of protection, and definite and inverse time can be
selected.
2) Undervoltage protection voltage can be selected as phase-to-earth
voltage or phase-to-phase voltage.
3) Undervoltage blocking current check.
4) Detection of circuit breaker state
5) VT failure detection, VT failure blocking undervoltage protection.
6) Dropoff coefficient is adjustable.
7) When the voltage connector of local side is disabled, undervoltage
protection is disabled.
soft-hard parallel.

The input and output signals of undervoltage protection function diagram
are shown below, left side is input and right side is output:
Undervoltage Protection
1 1
2 BIBlk Start 2
3 Ena_*UV Operation
Ena_*Voltage
Figure 68 The input and output signal diagram of undervoltage protection function
Input:
BIBlk BI blocking
UV Output:
Start IED startup
Operation IED trip

Input:
"HVSideUVConn":Ena_HVUV,the
Ena_ *UV corresponding hard connector is
Ena_HVUV_5
198

MVSideUVConn":Ena_MVUV,the
Ena_MVUV_5
ENA_*Voltage Input:
"HVSideVoltConn": Ena_HVoltage,the hard
Ena_*Voltage
"MVSideVoltConn":Ena_MVoltage,the hard
When the voltage connector of local side is disabled, undervoltage
IED consists of four stages of undervoltage protection, phase-to-earth
voltage or phase-to-phase voltage, alarm or trip and definite time or
inverse time are selectable, please refer to setting list for details. The
undervoltage protection stage 1 will be taken as an example below and the
principle will be introduced.

Undervoltage protection can provide three stages protection, with the
changeable definite/inverse time. Take the undervoltage 1 stage as the
example, it can be enabled or disabled via the enabled/disabled platen
"UVStage1On". With the enabled logic switch "UVChkPEVolt", the
undervoltage protection operation voltage setting can choose
phase-to-earth voltage UA-N, UB-N, UC-N, otherwise, it chooses
phase-to-phase voltage UA-B, UB-C, UC-A.
With the limit of field condition, the voltage transformer of the circuit
breaker may be connected to the power supply side or the load side. The
installation position of VT is different, and the operation characteristics of
undervoltage protection are different. As the undervoltage protection starts
tripping and the breaker is off, the voltage beside power supply stays
unchangeable but the voltage beside load drops to zero, now undervoltage
protection resets. If the voltage transformer is installed on the power
supply side, and does not want to protect the undervoltage detection
current, the setting of "UVChkCurrOn" can be set to 0. In addition, the
undervoltage protection can also be controlled by the word
"UVChkCBState" to choose whether the action logic is to detect the circuit
breaker status. When the undervoltage protection is required to check the
circuit breaker state, the undervoltage protection sends out the trip
command only when the circuit breaker is closed. If the voltage
transformer is installed on the power supply side, and does not want the
undervoltage protection to check circuit breaker status, the logic switch
"UVChkCBState" is set to 0.
3.1.1 Blocking condition
When "UVChkCBState"=1, circuit breaker will be checked at blocking
protection during the trip, with non-blocking protection starting and
blocking protection delaying.
When the maximum value of the three-phase current is less than
"UVCurrSet", the blocking is protected, the non-blocking protection starts,
199
and the blocking is delayed.

As VT failure blocking is 1, the blocking is protected, the non-blocking
protection starts, and the blocking is delayed.
When "UVChkPEVolt"=1, and three-phase voltage is lower than
"3PhUVBlkSet", or when "UVChkPEVolt"=0 and three-phase voltage is
lower than the 1.732 times of "3PhUVBlkSet", the blocking is protected,
and the blocking protection starts.
3.1.2 Definite time
When "UVStage1CurveSel"=0, undervoltage is the definite time
characteristic, and inverse time function is disabled.
U < “UVStage1VoltSet”
When the voltage is lower than the setting "UVStage1VoltSet", the timing
component will start and work until the setting "UVStage1Time", and
undervoltage protection trips. When
current U < Dropout × ”UVStage1VoltSet” , timing component drops out,
undervoltage protection drops out.
3.1.3 Inverse time
When "UVStage1CurveSel"=1~4, undervoltage is the definite time
characteristic, and inverse time function is disabled.
 
 
A
t  B  T
  U P 
1    
 Uset  
If the voltage is lower than "UVStage1VoltSet", the timing component
starts, inverse time characteristic curve is selected by
"UVStage1CurveSelection", A, P, B are determined when the value is from
1 to 3, see Table 3; when the value is 4, it is the user defined
characteristics, calculate the trip delay in accordance with the setting of the
A, P, B, T. timing, undervoltage protection trips. When the calculated delay
time is less than the "InvTimeUVMinTime", the component will trip in
accordance with the "InvTimeUVMinTime".
Where:
A: "InvTimeUVStage1CoefA"
P: "InvTimeUVStage1IndexP"
B: "InvTimeUVStage1TimeB"
T: "InvTimeUVStage1ConstT"
U : Voltage
Uset :"UVStage1VoltSet"
0. Definite time
200
1. Curve1 1 1 0
2. Curve2 40 2 1
3. Curve3 5 2 2
4. User defined

When undervoltage protection is enabled and there is no binary input
blocking, if "UVStage1On"=1, then undervoltage protection of the
corresponding stage is enabled.
When "UVChkPEVolt"=1, check phase-to-earth voltage; when
"UVChkPEVolt"=0, check phase-to-phase voltage.
Three phases can be equipped with "OR" logic and the protection starts
while at least one voltage is lower than the setting; it can also be equipped
with "AND" logic, and the protection starts while three voltages are all
lower than the setting.
Undervoltage protection is tripped, after the starting of protection trip, if the
action conditions are met, timing component starts, take stage 1 for
example, when time is over, "UVStage1Trip" is issued. LED and protection
trip can be configured by AESP.
The three-phase analog quantity U1, U2 and U3 of the trip time issued
when the undervoltage protection trips, the component is based on the
phase-to-earth voltage judgment, it issues three-phase phase-to-earth
voltage; when it is based on the phase-to-phase voltage judgment, it
issues three-phase phase-to-phase voltage.
201
3.1.5 Logic diagram

Ua<“UVStage1VoltSet”
≥1
&
Ub<“UVStage1VoltSet”
Uc<“UVStage1VoltSet”
“UVChk1Ph”=1 ≥1
“UVChk1Ph”=0
Ua<“UVStage1VoltSet”
& &
&
Ub<“UVStage1VoltSet”
Uc<“UVStage1VoltSet”
≥1
“UVChkPEVolt”=1 Undervoltage Stage 1
Protection Startup
“UVChkPEVolt”=0
Uab<“UVStage1VoltSet”
≥1
Ubc<“UVStage1VoltSet” & &
Uca<“UVStage1VoltSet”
“UVChk1Ph”=1
≥1
“UVChk1Ph”=0
Uab<“UVStage1VoltSet”
&
&
Ubc<“UVStage1VoltSet”
Uca<“UVStage1VoltSet”
202
UVStage1FcnOn1
“UVStage1On”=1
UVStage1Startup
Binary Blocking
CB Trip Position &

≥1
“UVChkCBState”=1 &
T1
UVStage1Trip
“UVChkCBState”=0
max(Ia,Ib,Ic)>“UVCurrSet” &
≥1
≥1
&
“UVChkCurrOn”=1
“UVChkCurrOn”=0
VT Failure blocking
Ua<“3PhUVBlkSet”
Ub<“3PhUVBlkSet”
&
Uc<“3PhUVBlkSet”
“UVChkPEVolt”=1
≥1
“UVChkPEVolt”=0
Uab<“1.732×3PhUVBlkSet”
&
Ubc<“1.732×3PhUVBlkSet”
Uca<“1.732×3PhUVBlkSet”
T1：“UVStage1Time”
Figure 69 Low voltage protection logic diagram
3.2 Setting list

Table 126 Undervoltage protection setting on high voltage side
Default
value
0:reverse time
1: A-1;P-1;B-0
1. HVSideUVStage1CurveSel 0~4 0 2: A-40;P-2;B-1
3: A-5;P-2;B-2
4: User defined
2. HVSideUVStage1VoltSet 5.00~150 100 V
3. HVSideUVStage1Time 0.00~120.0 120 s
4. HVSideInvTimeUVStage1T 0.025~1.5 0.025
5. HVSideInvTimeUVStage1A 0.001~1000 10
6. HVSideInvTimeUVStage1B 0.000~100.00 100
7. HVSideInvTimeUVStage1P 0.01~10.00 10
0:reverse time
1: A-1;P-1;B-0
8. HVSideUVStage2CurveSel 0~4 0 2: A-40;P-2;B-1
3: A-5;P-2;B-2
4: User defined
9. HVSideUVStage2VoltSet 5.00~150 100 V
10. HVSideUVStage2Time 0.00~120.0 120 s
203
Default
value
11. HVSideInvTimeUVStage2T 0.025~1.5 0.025
12. HVSideInvTimeUVStage2A 0.001~1000 10
13. HVSideInvTimeUVStage2B 0.000~100.00 100
14. HVSideInvTimeUVStage2IndexP 0.01~10.00 10
15. HVSideUVChkCurrSet 0.0 5n ~ 40 In 10 A
16. HVSideUVMinVoltSet 0.000~40.00 2 V
17. HVSideUVDropoffCoef 1.00~2.00 1
18. HVSideUVRstTime 0.000~100.00 0.0 s
19. HVInvTimeUVMinTripTime 0.100~100.00 0.1 s
Table 127 Undervoltage protection logic switch of high voltage side
Setting Default
Mode value
1. HVSideUVStage1On 1/0 0
2. HVSideUVStage2On 1/0 0
1-check current;
3. HVSideUVChkCurrOn 1/0 0
0-check current
1-check CB state;
4. HVSideUVoltChkCBState 1/0 0
0-not check CB state
1-check phase 1 voltage;

5. HVsideUVChk1Ph 1/0 0
0-check phase 3 voltage
1-check phase-to-earth voltage;
6. HVSideChkPEVolt 1/0 0
0- check phase-to-phase voltage
Table 128 Undervoltage protection setting on medium voltage side

Default
value
0:reverse time
1: A-1;P-1;B-0
1. MVSideUVStage1CurveSel 0~4 0 2: A-40;P-2;B-1
3: A-5;P-2;B-2
4: User defined
2. MVSideUVStage1VoltSet 5.00~150 100 V
3. MVSideUVStage1Time 0.00~120.0 120 s
4. MVSideInvTimeUVStage1T 0.025~1.5 0.025
5. MVSideInvTimeUVStage1A 0.001~1000 10
6. MVSideInvTimeUVStage1B 0.000~100.00 100
7. MVSideInvTimeUVStage1P 0.01~10.00 10
0:reverse time
1: A-1;P-1;B-0
8. MVSideUVStage2CurveSel 0~4 0 2: A-40;P-2;B-1
3: A-5;P-2;B-2
4: User defined
9. MVSideUVStage2VoltSet 5.00~150 100 V
10. MVSideUVStage2Time 0.00~120.0 120 s
11. MVSideInvTimeUVStage2T 0.025~1.5 0.025
12. MVSideInvTimeUVStage2A 0.001~1000 10
13. MVSideInvTimeUVStage2B 0.000~100.00 100
204
Default
value
14. MVSideInvTimeUVStage2IndexP 0.01~10.00 10
15. MVSideUVChkCurrSet 0.05In ~ 40In 10 A
16. MVSideUVMinVoltSet 0.000~40.00 2 V
17. MVSideUVDropoffCoef 1.00~2.00 1
18. MVSideUVRstTime 0.000~100.00 0.0 s
19. MVInvTimeUVMinTripTime 0.100~100.00 0.1 s
Table 129 Undervoltage protection logic switch of medium voltage side
Setting Default
Mode value
1. MVSideUVStage1On 1/0 0
2. MVSideUVStage2On 1/0 0
1-check current;
3. MVSideUVChkCurrOn 1/0 0
0-check current
1-check CB state;
4. MVSideUVoltChkCBState 1/0 0
0-not check CB state
1-check phase 1 voltage;

5. MVSideUVChk1Ph 1/0 0
0-check phase 3 voltage
1-check phase-to-earth voltage;
6. MVSideChkPEVolt 1/0 0
0- check phase-to-phase voltage
3.3 Report list


Trip report:
1. HVSideUVStage1Trip /
2. HVSideUVStage2Trip /
3. MVSideUVStage1Trip /
4. MVSideUVStage2Trip /
205

Table 131 Undervoltage protection technical parameter
Accessed voltage PPVolt or phase-to-earth ≤ ±2.5% setting or ±1V
voltage
Phase voltage setting value 5V～75V, step 0.01V, ≤ ±2.5% setting or ±1V
Line voltage setting 10V～150V, step 0.01V, ≤ ±2.5% setting or ±1V
DropoffCoef 1.00～1.05, step 0.01 ≤±3% setting
Time setting 0.00s～120.00s, step 0.01s ≤ ± 1% times of setting or
+60ms, when trip value is set
at 80% of setting
Reset time ≤ 50ms
Phase voltage setting value 5V～75 V, step 0.01V, ≤ ±2.5% setting or ±1V
Line voltage setting 10V～150V, step 0.01V, ≤ ±2.5% setting or ±1V
IEC 60255-127
In the case of 0.05< U / Uset
<0.5, the allowable trip time
error is: ± 5% or +60 ms;
User defined curve   ≤ ±5% setting or +40ms,
  when 2< U / Uset <20, it
 A
t  B T meets IEC60255-151
  U P 
1     standard
 Uset  
time : A
Time delay of inverse time 0.000 to 100.00, step 0.01
B
206
Chapter 18 Thermal overload protection (49)
Chapter 18 Thermal overload

protection (49)
About this chapter

This chapter describes the principles of thermal overload
207
1 Overview
Thermal overload protection protects the device against overheating
caused by overload. Overheating can affect insulation characteristics of
insulation material between transformers, lines and other electrical
equipment. In fact, if the device temperature exceeds the allowable
operating temperature, the insulation material will accelerate aging.
Therefore, special protection should be provided to prevent the protected
equipment from excessive temperature. Since the temperature is
proportional to the square of the current, the thermal overload protection is
based on the square of the measured current flowing through the
protected device. In addition, due to the cumulative effect of over
temperature, the thermal overload protection needs to consider the
historical thermal effect of the device. The device realizes the above
functions by providing a thermal model of the simulated protected device.
In this way, the thermal overload protection of the device has the ability of
memory, which can consider the historical overload and heat loss.
parallel.

The input and output signals of thermal overload protection function are
Thermal Overload Protection
1 1
Ena_*ThermOL Start
2
ACT1
3
ACT2
4
ACT3
Figure 70 The input and output signals of thermal overload protection function diagram
Output:
Start IED startup
ThermOL ACT1 Stage 1 alarm of thermal overload
ACT2 Stage 2 alarm of thermal overload
ACT3 Protection trip of thermal overload

Input:
"HVSThermalOLConn":Ena_HVThermOL,the
ENA_Function corresponding hard connector is Ena_HVThermOL_5
Ena_*ThermOL
"MVSThermalOLConn":Ena_MVThermOL,the
corresponding hard connector is Ena_MVThermOL_5
208
The device provides 1 stage thermal overload trip stage and 2 stage
thermal overload alarm stage. The alarm stage needs to adjust the
"ThermalOLAlarmCoef", which means that the value of the alarm stage trip
setting is the product of the setting of the trip stage and the overload alarm
coefficient. The thermal overload protection function is realized by a
temperature model equivalent to the protected device. Temperature model
(low temperature curve or high temperature curve) is selected from
IEC60255-8 standard. Temperature model can be used to calculate the
temperature rise of each phase current. The maximum temperature rise
calculated from the three-phase current is the trip value of thermal
overload protection.

The temperature rise of each phase is calculated by the following formula:
d I
    ( )2
dt I
In which, τ is "ThermalTimeConst", and s is the unit; Iθ is

"ThermalOLCurrSet" that is the maximum permissible continuous thermal
overload current, Θ is the temperature rise of unit per unit time under
maximum allowable thermal overload current, I is the fundamental current
that is measured through the phases of the protected device.
Based on the difference model, the calculation formula of overload trip
time:
 I 2  I 2 
     P  
 I 
t   ln     2   
I
  I   1 
  I   
 
Where, IP is the steady current before the overload, the formula is the heat
curve in the IEC60255-8 specification, and the trip time is calculated in
accordance with the cold curve, which is shown as follows:
  I 2 
   
 I 
t   ln    2 
  I   1
  I   
 
Thermal overload protection can reflect the current fundamental frequency
component or RMS value trip, which are divided into stage 1 trip and stage
2 alarm, whenI > “ThermalOLCurrSet”, over heat protection starts, take
stage 1 alarm for example, when the thermal overload percentage reaches
"ThermalOLAlarmCoef1", the report "ThermalOLAlarmCoef1" is sent out;
when the thermal load percentage reaches 100%, the report
"ThermalOLTrip" is sent out. Light, protection trip and others can be
configured by AESP after the alarm or trip report is issued.
The calculation formula of thermal curve alarm time is as follows:
209
  I 2  I 2 
     P  
 I  I  
t   ln   2 
  I   RatioAct 
 I  
   
The calculation formula of cold curve alarm time is as follows:
 I  2
   
  I  
t   ln 2 
  I 
  RatioAct 
 I 
   
Where RatioActis“ThermalOLAlarmCoef”.
While alarming or tripping, three-phase current value Ia, Ib, Ic of trip
moment and each phase of trip moment are sent out.
When overheating protection is enabled, three-phase thermal
accumulative percentage is sent out timely by ThermalA, ThermalB, and
ThermalC.
The stop load current is 0, and the time coefficient of the equipment in the
process of heat dissipation is the product of "ThermalOLCoolingCoef" and
"ThermalTimeConst".
3.2 Setting list

Table 133 Thermal overload protection setting of high voltage side
Default
value
0.05In~40
1. HVSideThermalOLCurrSet 10 A
In
2. HVSideThermalTimeConst 6~9999 60 s
3. HVSideThermalOLCoolingCoef 0.1~10 10
4. HVSideThermalOLAlarmCoef1 0.5~1 1
5. HVSideThermalOLAlarmCoef2 0.5~1 1
Table 134 Thermal overload logic switch of high voltage side

Setting Default
Mode value
1. HVSideThermalOLOn 1/0 0
1: alarm enabling
2. HVSideThermalOLAlarm1On 1/0 0
o-1: alarm disabling
1- 2: alarm enabling
3. HVSideThermalOLAlarm2On 1/0 0
0- 2: alarm disabling
1: hot curve;
4. HVSideThermalCurve 1/0 0
0: cool curve
210
Table 135 Thermal overload protection setting of medium voltage side

Default
value
0.05In~40
1. MVSideThermalOLCurrSet 10 A
In
2. MVSideThermalTimeConst 6~9999 60 s
3. MVSideThermalOLCoolingCoef 0.1~10 10
4. MVSideThermalOLAlarmCoef1 0.5~1 1
5. MVSideThermalOLAlarmCoef2 0.5~1 1
Table 136 Thermal overload logic switch of medium voltage side

Setting Default
Mode value
1. MVSideThermalOLOn 1/0 0
1: alarm enabling
2. MVSideThermalOLAlarm1On 1/0 0
o-1: alarm disabling
1- 2: alarm enabling
3. MVSideThermalOLAlarm2On 1/0 0
0- 2: alarm disabling
1: hot curve;
4. MVSideThermalCurve 1/0 0
0: cool curve
3.3 Report list


Trip report:
Thermal overload protection of high voltage
1. HVSideThermalOLTrip
side sends off tripping order
Thermal overload protection of medium
2. MVSideThermalOLTrip
voltage side sends off tripping order
Alarm report:
1. HVSideThermalOLStage1Alarm
side sends off alarm 1 order
2. HVSideThermalOLStage2Alarm
side sends off alarm 2 order
3. MVSideThermalOLStage1Alarm
voltage side sends off alarm 1 order
4. MVSideThermalOLStage2Alarm
voltage side sends off alarm 2 order

Table 138 Thermal overload protection technical parameter
Current setting 0.05In～40.00In ≤ ±2.5% setting or ±0.02In
Thermal overload protection
6s～9999s
heating time constant
Cooling coefficient of thermal
0.1～10
overload
211
 I eq2  IEC 60255–8,

IEC low-temperature curve t   ln  2 2
≤ ±5% times of setting or
 I eq  I   +40ms.
 I eq2  I P2  IEC 60255–8,

IEC high-temperature curve t   ln  2 2
 I eq  I   +40ms.
212
Chapter 19 Circuit Breaker Failure protection (50BF)
Chapter 19 Circuit Breaker Failure

protection (50BF)
About this chapter

parameter for circuit breaker failure protection function.
213
1 Overview
CBF protection can detect whether CBF is operating or not during the fault
clearance. This protection can clear the fault by tripping the breaker of
corresponding busbars as fast backup protection. Once there is a breaker
failure on feeder or transformer, the connected busbar can be
disconnected from the power grid by CBF protection.
In order to improve the reliability of circuit breaker failure protection, the
current criterion is added. Three phase current, zero sequence current and
negative sequence current can be selected.
In order to avoid the other around circuit breaker trip caused by the error of
judgment, circuit breaker failure protection can be set to issue a trip
command to the local circuit breaker once again.
CBF protection has the characteristics as below:
1) 2 trip stages (local breaker retrip and trip the busbar)
2) Internal/ external initiation
3) Three-phase initiating failure
4) Breaker auxiliary contact check
5) Current criteria checking (including phase current, zero and negative
sequence currents)
soft-hard parallel.

The input and output signals of CBF protection function are shown below,
left side is input and right side is output:
Circuit-Breaker Failure Protection
1
CBOpenA
2 1
CBOpenB CBF_Init
3 2
CBOpenC BIAlarm
4 3
CBClose3P Trip1
5 4
BIInitCBF3P Trip2
6
BICBFail
7
BIBlk
8
TrInit3P
9
Ena_*CBF
Figure 71 CBF protection function input and output signal diagram

Input:
BIConfig CBOpenA Circuit breaker trip position A
CBOpenB Circuit breaker trip position B
214
CBOpenC Circuit breaker trip position C
CBClose Circuit breaker close position
BIInitCBF3P External BI Initiation CBF
BICBFFail CBF Spring discharge binary input
Input:
BIBlk BI blocking
TrInit3P Internal initiating failure signal
Output:
CBF
CBF_Init Circuit breaker failure startup signal
BIAlarm Circuit breaker failure binary input is abnormal
Trip1 Circuit breaker failure stage 1 trip
Trip2 Circuit breaker failure stage 2 trip
Input:
"HVSideCBFConn":Ena_HVCBF,the
corresponding hard connector is Ena_HVCBF_5
"MVSideCBFConn":Ena_MVCBF,the
ENA_Function corresponding hard connector is Ena_MVCBF_5
Ena_*CBF
"LVSide1CBFConn":Ena_LV1CBF,the
corresponding hard connector is Ena_LV1CBF_5
“LVSide2CBFConn":Ena_LV2CBF,the
corresponding hard connector is Ena_LV2CBF_5
3.1 Protection function
CBF protection can be enabled or disabled by setting the logic switch In
the case of the protection function is enabled, the protection function trips,
the relevant protection function start failure protection, and the timing of
the counter works until to setting time delay, and the time delay is set
to”CBFTime1". If the circuit breaker is still closed after the setting time,
circuit breaker failure protection will send trip command to trip the circuit
breaker (for example, through the secondary trip coil) If the breaker has no
response when the other time delay ”CBFTime2", then IED will send off trip
command to trip the corresponding breakers to isolate the fault (e.g. other
breakers on the same busbar connected with the failure circuit breaker).
After tripping, light, protection trip and others can be configured by AESP.
The internal and external protection function can both start circuit breaker
failure protection. If the external initiating function protection is failed, then
it needs to be equipped with "3PhaseCBFStartup".
CBF check includes two criteria. The first criterion is detecting the
disappeared current after issuing the trip command. The second criterion
is detecting the auxiliary contacts of breaker.
215
3.1.1 Current check

When the current is disappeared, the breaker is considered to be on the
open position. the first criterion (current criterion) is the most effective way
to detect the position of breaker. The current check, therefore, is used to
detect the breaker position in CBF protection. At this time, the current
measurement of each phase compares with the setting of
'CBFCurrentValue'. Besides, the zero sequence ( 3İ0 = İA + İB + İC ) or
negative sequence (3𝐼2̇ = 𝐼𝐴̇ + 𝛼 2 𝐼𝐵̇ + 𝛼𝐼𝐶̇ ) current can also be used as
current criteria by setting the logic switch. If the IED is set to detect zero
and negative sequence current, then the zero and negative currents
should be compared with the corresponding settings separately.
&
Ia >“CBFCurrSet”
Calculate3I0 >“CBF3I0Set” ≥1
&
≥1 &
3I2 > “CBFI2Set”
Ib >“CBFCurrSet”
Ic >“CBFCurrSet”
“CBFChk3I0/I2”=1
&
Calculate3I0 >“CBF3I0Set” ≥1 ≥1
& CB Failure Current
≥1 & judged
3I2 > “CBFI2Set” by 3 Phase Current
&
Calculate3I0 >“CBF3I0Set” ≥1
&
≥1 &
3I2 > “CBFI2Set”
Figure 72 Breaker current detection logic diagram
3.1.2 Breaker auxiliary contacts check

For tripping criterion which is not based on current protection function,
current monitoring criterion is not suitable for monitoring the state of circuit
breaker. In this case, it is necessary to set the control word "CBF check
position" to 1 to judge whether the circuit breaker is acting correctly by
using the auxiliary contacts of the circuit breaker.
It should be noted that the auxiliary contact monitoring criterion of failure
protection circuit breaker only works when the current monitoring is not
started. In the delay time of failure protection, once the current criterion is
activated and the discrimination current disappears, even if the auxiliary
contacts of the circuit breaker do not identify that the circuit breaker has
been disconnected, the protection also considers that the circuit breaker
216
has been disconnected. The more reliable current criterion has higher
priority and avoids the signal errors caused by the failure of auxiliary
contact mechanism or circuit.
CB Trip Position &
Breaker close
Internal/External 3 & position
Phase Initiating CBF
CBF Current Judged ≥1

By 3 Phase Current
Figure 73 Breaker auxiliary contact judgment logic diagram
3.1.3 CBF protection trip logic

&
CBF BIErr
T_alarm &
ExtrInitCBFSignal
≥1
IntrInitCBFSignal
&
3PhInitCBF
CBFProtFcnOn=1
Figure 74 The internal and external initiating CBF logic diagram

“HVSideCBFChkPosn” &
Breaker close
position
≥1
Failure current determine &

3 phase with current 3 phase
failure initiation
3 phase initiation failure
Figure 75 Initiating CBF logic diagram

3-phase T1 Failure stage 1 trip
failure initiation
T1：“CircuitBreakerFailureTime1”
Figure 76 CBF state 1 trip logic diagram

3 phase T2
failure initiation ≥1
Failure stage 2 trip
&
0
CBFail input
T2：“CircuitBreakerFailureTime2”
Figure 77 CBF state 2 trip logic diagram
3.2 Setting list

Table 140 The settings of circuit-breaker failure protection of high voltage side
Default
value
1. HVSideCBFCurrSet 0.05In~40 In 40 A
2. HVSideCBF3I0Set 0.05In~40 In 40 A
217
3. HVSideCBFI2Set 0.05In~40 In 40 A
4. HVSideCBFTime1 0.00~100.00 100 s
5. HVSideCBFTime2 0.00~100.00 100 s

HVSideCBF
6. 0.00~100.00 100 s
BIAlarmTime
Table 141 CBF protection logic switch of high voltage side
Setting Default
Mode value
1-CBFprotection enabling
1. HVSideCBFOn 1/0 1
0-CBF protection disabling
1-check zero/negative sequence current
2. HVSideCBFChk3I0/I2 1/0 1 0-not check zero/negative sequence
current
1-check circuit breaker position;
3. HVSideCBFChkPosn 1/0 1
0-non-check circuit breaker position;
Table 142 The settings of circuit-breaker failure protection of medium voltage side
Default
value
1. MVSideCBFCurrSet 0.05In~40 In 40 A
2. MVSideCBF3I0Set 0.05In~40 In 40 A
3. MVSideCBFI2Set 0.05In~40 In 40 A
4. MVSideCBFTime1 0.00~100.00 100 s

5. MVSideCBFTime2 0.00~100.00 100 s
MVSideCBF
6. 0.00~100.00 100 s
BIAlarmTime
Table 143 CBF protection logic switch of medium voltage side
Setting Default
Mode value
1. MVSideCBFOn 1/0 1
1-check zero/negative sequence current
2. MVSideCBFChk3I0/I2 1/0 1 0-not check zero/negative sequence
current
3. MVSideCBFChkPosn 1/0 1
Table 144 The settings of circuit-breaker failure protection of low voltage side1
Default
value
1. LVSide1CBFCurrSet 0.05In~40 In 40 A
2. LVSide1CBF3I0Set 0.05In~40 In 40 A
3. LVSide1CBFI2Set 0.05In~40 In 40 A
4. LVSide1CBFTime1 0.00~100.00 100 s
5. LVSide1CBFTime2 0.00~100.00 100 s

LVSide1CBF
6. 0.00~100.00 100 s
BIAlarmTime
218
Table 145 CBF protection logic switch of low voltage side1

Setting Default
Mode value
1. LVSide1CBFOn 1/0 1
1-check zero/negative sequence
current
2. LVSide1CBFChk3I0/I2 1/0 1
0-not check zero/negative sequence
current
3. LVSide1CBFChkPosn 1/0 1
Table 146 The settings of circuit-breaker failure protection of low voltage side2
Default
value
1. LVSide2CBFCurrSet 0.05In~40 In 40 A
2. LVSide2CBF3I0Set 0.05In~40 In 40 A
3. LVSide2CBFI2Set 0.05In~40 In 40 A
4. LVSide2CBFTime1 0.00~100.00 100 s
5. LVSide2CBFTime2 0.00~100.00 100 s

LVSide2CBF
6. 0.00~100.00 100 s
BIAlarmTime
Table 147 CBF protection logic switch of low voltage side2
Setting Default
Mode value
1. LVSide2CBFOn 1/0 1
1-check zero/negative sequence
current
2. LVSide2CBFChk3I0/I2 1/0 1
0-not check zero/negative sequence
current
3. LVSide2CBFChkPosn 1/0 1
3.3 Report list


Trip report:
1. HVSideCBFStarup /
2. HVSideCBFStage1Trip /
3. HVSideCBFStage2Trip /
4. MVSideCBFStartup /
5. MVSideCBFStage1Trip /
6. MVSideCBFStage2Trip /
7. LVSide1CBFStarup /
8. LVSide1CBFStage1Trip /
9. LVSide1CBFStage2Trip /
10. LVSide2CBFStarup
11. LVSide2CBFStage1Trip
12. LVSide2CBFStage2Trip
Alarm report:
219
1. HVSideCBF BIErr /
2. MVSideCBF BIErr /
3. LVSide1CBF BIErr /
4. LVSide2CBF BIErr
3.4 Parameters
Table 149 CBF protection technical parameter
Current setting 0.05In ~ 40.00In ≤ ±2.5% setting or ±0.02In
Negative sequence current
setting
Zero sequence current
setting
Time 1 of circuit breaker 0.00s~100.00s, step 0.01s ≤ ± 1% times of setting or
failure +40ms, when trip current is
Time 2 of circuit breaker 0.00s~100.00s, step 0.01s set as 200% setting
failure
Reset time Less than 20ms
220
Chapter 20 Dead zone protection (50DZ)
Chapter 20 Dead zone protection

(50DZ)
About this chapter

parameter for dead zone protection.
221
1 Overview
IED provides dead zone protection to detect dead zone fault, i.e. when
breaker is in open position, a fault occurs between CT and breaker. So,
when breaker auxiliary contact shows that the breaker is in open position,
IED can detect fault current of dead zone. The protective function can be
disabled through the function connector. The connector properties can be
configured as soft connector, hard connector, soft-hard series, soft-hard
parallel, and the default is soft-hard parallel.
For busbar side CT, when dead zone fault occurs, IED trips all breakers on
the busbar where the fault bay is located. Trip logic is shown as below:
TrIp
Busbar
IFAULT
Line 1 Line 2 Line N
Example:
CB open position
CB close position
Figure 78 Busbar side trip logic diagram

For CT at line side, when dead zone fault occurs, IED sends remote trip
command to the IED on the opposite side to isolate fault. Trip logic is
shown as below:
Interal trip
Busbar
IFAULT
Line
Line 2 Line N
1
Trip
装置
Example:
CB open position
CB close position
Figure 79 Line side trip logic diagram
222

The input and output signals of dead zone protection function diagram is
Dead Zone Protection
1 1
CBOpenA Start
2 2
CBOpenB Operation
3 3
CBOpenC Alarm
4
CBClose
5
BI_IntDZ
6
SigIntDZ
7
BIBlk
8
Ena_LVDZ
Figure 80 The input and output signals of dead zone protection function diagram
Input:
CBOpenA Circuit breaker trip position A

BIConfig
CBClose Circuit breaker close position
BIInitDZ External startup dead zone binary input
Input:
SinInitDZ Internal startup dead zone signal
BIBlk BI blocking
DZ Output:
Start IED startup
Operation IED trip

Alarm Abnormal alarm of external binary input
Input:
ENA_Function "LVSide1DZConn",the corresponding hard
Ena_LV1DZ
connector is Ena_LV1DZ_5
When dead zone protection function is enabled (En=1) and binary input
blocking is disabled, if "DZProtOn"=1, then the corresponding dead zone
protection is enabled.
223
The trip conditions are shown below:

1) Trip initiates dead zone flag SigIntDZ =1, or external IB initiates dead
zone 'BI_IntDZ =1' and no abnormal alarm of external BI;
2) There should be open position but no close position;
3) I∅ > “DZCurrSet”, (∅ = a, b, c);
4) Enabled or disabled the criterion of zero current and negative sequence current
by setting the logic switch " DZChk3I0/3I2 ". If the logic switch is set as 1, the
zero or negative sequence current is also necessary to be larger than the
corresponding setting.
If the trip conditions are met, time component starts, when time is over,
"DZTrip" is issued. LED and protection trip can be configured by AESP. At
the same time, the three-phase fundamental current values Ia, Ib, Ic, zero
and negative sequence current of trip time are displayed. When current or
breaker position is not satisfied, timing component returns, dead zone
protection resets. When the existing time of external BI initiating dead zone
is longer than the alarm time, "DZ BIErrAlarm” will be issued. LED and
224
&
“DZChk3I0/I2”=0
Ia>“DZCurrSet”
Ib>“DZCurrSet”
& ≥1
≥1 &
Ic>“DZCurrSet”
3I0>“DZ3I0Set”
3I2>“DZI2Set”
“DZChk3I0/I2”=1
“DZChk3I0/I2”=0
&
Ib>“DZCurrSet”
Ic>“DZCurrSet”
& ≥1 ≥1
≥1 & Dead zone current
Ia>“DZCurrSet” condition satisfied
3I0>“DZ3I0Set”
3I2>“DZI2Set”
“DZChk3I0/I2”=1
“DZChk3I0/I2”=0 &
Ic>“DZCurrSet”
Ib>“DZCurrSet”
& ≥1
≥1 &
Ia>“DZCurrSet”
3I0>“DZ3I0Set”
3I2>“DZI2Set”
“DZChk3I0/I2”=1
Dead zone protection on
BI blocking
Dead zone current condition satisfied

&
&
3 phase trip T
Dead zone protection trip
≥1
Protection trip initiate dead zone
&
Outside initiate T_BIErr

dead zone BI
Dead zone protection

BI abnormal alarm
“DZProtOn”=1
T：“DZTripTime”
T_BIErr：“BIErrTime”
Figure 81 Dead zone logic diagram
225
3.2 Setting list

Table 151 Dead zone protection setting of low voltage side
Default
value
1. LVSideDZ1CurrSet 0.05In~40 In 40 A
2. LVSideDZ1Prot3I0Set 0.05In~40 In 40 A
3. LVSideDZ1ProtI2Set 0.05In~40 In 40 A
4. LVSideDZ1Time 0~100 100 s
5. LVSideDZ1 BIErrTime 0.00~100 100 s
Table 152 Dead zone logic switch

Setting Default
Mode value
1. LVSide1DZ1On 1/0 0
2. LVSide1DZ1Chk3I0/I2 1/0 0
3.3 Report list


Trip report:
1. LVSide1DZTrip /
Alarm report:
1. LVSide1DZ BIErrAlarm /

Table 154 Dead zone protection technical parameter
Current setting 0.05In～40.00In ≤ ±2.5% setting or ±0.02In
Time setting 0.00s～100.00s, step 0.01s ≤ ±1% times of setting or
+40ms, when trip current is
set as 200% setting
226
Chapter 21 Stub protection (50STUB)
About this chapter

This chapter describes the protection principle, the input and
output signals, fixed value parameters, messages and
technical parameters for stub protection.
227
1 Overview
The stub protection protects the zone between the CTs and the
dis-connectors. The stub protection is enabled when the open position of
the dis-connector is informed to the IED through connected binary input.
The function has 2 stages of definite time at high voltage and medium
voltage side separately.
parallel.

The input and output signals of differential protection function diagram are
STUB-Bus Overcurrent Stage

1 1
STUB_Enable Start
2 2
BIBlk Operation
3 3
Ena_*STUB APhase
4
BPhase
5
CPhase
Figure 82 The input and output signals of stub protection function diagram
Input:
BIConfig
STUB_Enable Isolation position signal input
Input:
BIBlk BI blocking
Output:
Start IED startup

STUB
Operation IED trip
APhase Phase A trip
BPhase Phase B trip
CPhase Phase C trip
Input:
ENA_Function “HVSideStubConn” ： Ena_HVSTUB ， the
Ena_*STUB
corresponding hard connector is Ena_HVSTUB_5
228

“MVSideStubConn” ： Ena_MVSTUB ， the
corresponding hard connector is Ena_MVSTUB_5
The stub protection is an overcurrent protection which is only in service if
the status of the line disconnector indicates the open condition. Stub
protection is disabled while the disconnector is at the close position. The
stub protection stage provides one definite time stage with settable delay
time. This protection function can be enabled or disabled via the logic
switch. Corresponding current setting value can be inserted in setting.
When the current is greater than the setting value and the time delay is
over, the IED sends out "StubTrip". LED and protection trip can be
configured by AESP.
Ia>“StubCurrSet”
≥1
Ib>“StubCurrSet”
Ic>“StubCurrSet”
&
Isolator in the open position T
Stub protection trip
BI blocking
“StubOn”=1
StubProtFcnOn=1
T：“StubTime”
Figure 83 Stub protection function logic

Bus line A
CB1
STUB-Bus
CT1 Overcurrent fault
Line1
Switch1
CB3
CT3
Line2
Switch2
CT2
CB2
Bus line B
229
Figure 84 Logic diagram of application scenarios
3.2 Setting list

Table 156 Stub protection setting of high voltage side
Default
value
0.05In~40
1. HVSideStubStage1ProtSet 40 A
In
2. HVSideStubStage1ProtTime 0~100 100 s
0.05In~40
3. HVSideStubStage2ProtTime 40 A
In
4. HVSideStubStage1ProtTime 0~100 100 s
5. HVSideStubRstTime 0~100 40 s
Table 157 Stub protection logic switch of high voltage side

Setting Default
Mode value
1. HVSideStubStage1On 0/1 0
2. HVSideStubStage2On 0/1 0
Table 158 Stub protection setting of medium voltage side

Default
value
1. MVSideStubStage1ProtSet 0.05In~40 In 40 A
2. MVSideStubStage1ProtTime 0~100 100 s
3. MVSideStubStage2ProtTime 0.05In~40 In 40 A
4. MVSideStubStage1ProtTime 0~100 100 s
5. MVSideStubRstTime 0~100 40 s
Table 159 Stub protection logic switch of medium voltage side

Setting Default
Mode value
1. MVSideStubStage1On 0/1 0
2. MVSideStubStage2On 0/1 0
3.3 Report list

1. HVSideStubStage1Trip /
2. HVSideStubStage1PhATrip /
3. HVSideStubStage1PhBTrip /
4. HVSideStubStage1PhCTrip /
230
5. HVSideStubStage2Trip /
6. HVSideStubStage2PhATrip /
7. HVSideStubStage2PhBTrip /
8. HVSideStubStage2PhCTrip /
9. MVSideStubStage1Trip /
10. MVSideStubStage1PhATrip /
11. MVSideStubStage1PhBTrip /
12. MVSideStubStage1PhCTrip /
13. MVSideStubStage2Trip /
14. MVSideStubStage2PhATrip /
15. MVSideStubStage2PhBTrip /
16. MVSideStubStage2PhCTrip /

Table 161 Stub protection technical parameters
≤ ±2.5% times of setting or
Current setting 0.05 In～40.00In
±0.02In
Time setting 0.00s～100.00s, step 0.01s +40ms, when trip current is
set as 200% setting
231
Chapter 22 Pole discrepancy protection (62PD)
Chapter 22 Pole discrepancy

protection (62PD)
About this chapter

parameter for pole discrepancy protection.
233
1 Overview
Under normal operating condition, all three poles of the circuit breaker
must be closed or open at the same time. The split phase operating circuit
breakers can be in different positions (close-open) due to electrical or
mechanical failures. This can cause negative and zero sequence currents
which gives thermal stress on rotating machines and can cause unwanted
operation of zero sequence or negative sequence current functions.
Single pole opening of the circuit breaker is permitted only in the short
period related to single pole dead times, otherwise the breaker is tripped
three pole to resolve the problem. If the problem still remains, the remote
end can be intertripped via circuit breaker failure protection function to
clear the unsymmetrical load situation.
The pole discrepancy function operates based on information from
auxiliary contacts of the circuit breaker for the three phases with additional
criteria from unsymmetrical phase current.
parallel.

The pole discrepancy protection function diagram is shown below, left side
is input and right side is output:
Pole_Discrepancy Protection
1 1
CBOpenA Start
2 2
CBOpenB Operation
3
CBOpenC
4
BIBLK
5
Ena_LV1PD
Figure 85 Pole discrepancy protection function input and output signals diagram
Input:
CBOpenA Circuit breaker trip position A

BIConfig
Input:
PD BIBlk BI blocking
Output:
234
Start IED startup: timer starts
Operation IED trip
ENA_Function Input:
“LVSide1PDConn”,the corresponding hard
Ena_LV1PD
connector is Ena_LV1PD_5
The CB position signals are connected to IED via binary input in order to
monitor the CB status. Poles discordance condition is established when
logic switch of three-pole discrepancy is enabled, and at least one pole is
open and at the same time not all three poles are closed. The auxiliary
contact of the circuit breaker is inspected by the corresponding phase
current. When the auxiliary contact signal of the breaker is indicated as a
division, the current is in phase, and after the 5S, the device alarm is made
of "PDProtTripPosnErr". LED and protection trip can be configured by
AESP.
In addition, criterion for zero sequence current and negative sequence
current can be enabled or disabled through logic switch under this function.
Pole discrepancy can be detected when current is not flowing through all
three poles. When current is flowing through all three poles, all three poles
must be closed even if the breaker auxiliary contacts indicate a different
status.
3.2 Logic diagram

Pole discrepancy protection logic diagram is as below:
235
Circuit breaker trip positionA &
Ia > 0.06In
Circuit breaker trip positionB & ≥1
Ib > 0.06In
Circuit breaker trip positionC &
Ic > 0.06In
&
5s
PDProtFcnOn=1 3 phase PD trip abnormal
Circuit breaker trip positionA
&
Circuit breaker trip positionB
Circuit breaker trip positionC
Circuit breaker trip positionA &
&
Ia < 0.06In T_PD 3 phase PD
protection trip
Circuit breaker trip positionB & ≥1
Ib < 0.06In
Circuit breaker trip positionC &
Ic < 0.06In
3I2 > 3I2Set ≥1
3I0 > f3I0Set
&
≥1
“PDChk3I0/3I2”=1
PDProtFcnOn=1
3I2Set：“PD3I2Set”
3I0Set：“PD3I0Set”
T_PD：“PDTripTime”
Figure 86 Pole discrepancy protection logic diagram
3.3 Setting list

Table 163 Three-phase unbalanced protection setting of low voltage side 1
Default
Range
(In:5A/1A)
(In:5A/1A)
1. LVSide1PD3I0Set 0.05In~40In 40 A
2. LVSide1PDI2Set 0.05In~40In 40 A
3. LVSide1PDTripTime 0~60 10 s
236
Table 164 Three-phase unbalanced protection logic switch of low voltage side 1
Set Default
mode value
1. LVSide1PDOn 0/1 0
1-check zero or negative
0/1 0 sequence current
2. LVSide1PDChk3I0/I2
0-not check zero or negative
sequence current
3.4 Report list


Trip report:
1. LVSide1PDTrip /
Alarm report:
2. LVSide1PDProtTripPosnErr /

Table 166 Pole discrepancy protection technical parameter
Current 0.05In to 40.00In ≤ ±3% setting or ±0.02In
Time delay 0.00s to 100.00s, step 0.01s ≤ ±1% setting or +40ms,
when 200% setting
DropoffCoef >0.95
237
Chapter 23 Overexcitation protection（24）
Chapter 23 Overexcitation protection

(24)
About this chapter

This chapter describes the Overexcitation protection principle,
the input and output signals, fixed value parameters,
239
1 Overview
The overexcitation protection is used to detect impermissible
overexcitation conditions which can endanger power transformers. The
saturation of the iron core and large eddy current losses led by the
situation that the transformer flux exceeds the related values can cause
impermissible temperature rise in transformer core.
This protection function has the following characteristics:
1) The alarm or trip of the three stages of definite time can be selected
respectively, the alarm or trip of one stage of inverse time can be
selected respectively;
2) High/Medium/Low voltage channel can be selected;
3) Phase voltage and line voltage is available;
4) When the voltage connector of local side is disabled, the
overexcitation protection is disabled.
soft-hard parallel.

The input and output signals of overexcitation protection function diagram
Overexcitation Protection
1 1
BIBlk bDefStart
2 2
Ena_OFlux bDefAlarm
3 3
Ena_HVoltage bDefOp
4 4
Ena_MVoltage bInvStart
5 5
Ena_L1Voltage bInvAlarm
6
bInvOp
Figure 87 The input and output signals of overexcitation protection function diagram
Input:
BIBlk BI blocking
Output:
OFlux bDefStart Definite time start

bDefAlarm Definite time alarms
bDefOp Definite time trips

Inverse time startup (used only to configure the
bInvStart
number of inverse time stages)
240
Inverse time alarm (used only to configure the

bInvAlarm
number of inverse time stages)
Inverse time trip (used only to configure the number
bInvOp
of inverse time stages)
Input:
ENA_Function "OEConn",the corresponding hard connector is
Ena_OFlux
Ena_OFlux_5
Input:
ENA_HVoltag
e "HVSideVoltConn",the hard connector is
Ena_HVoltage
Ena_HVoltage_5
Input:
ENA_MVoltag
e "MVSideVoltConn",the hard connector is
Ena_MVoltage
Ena_MVoltage_5
Input:
ENA_L1Voltag
e LVSide1VoltConn",the hard connector is
Ena_L1Voltage
Ena_L1Voltage_5
When the voltage connector of local side is disabled, the overexcitation
Overexcitation will occur when the load uncouples from system and
voltage regulator can't control the increase of voltage promptly. Similarly,
the overexcitation condition may occur as result of a decrease in frequency,
e.g. isolated system. To protect the power transformer in such conditions,
the overexcitation protection function should start operating when the flux
exceeds the permissible limit value of transformer core. The ratio of
overexcitation protection function measures the voltage to frequency (U/f)
is proportional to the flux density B in transformer core, comparing to the
rated flux density BN. The decision is then made based on the calculated
ratio as is shown in below equation.
B U f
N 
BN U N f N
Where N is the ratio between the voltage and the frequency calculated by
the device.
U and f are the measured voltage and frequency
UN and fN are the rated voltage and frequency of the device.
While the rated frequency is fixed to 50Hz or 60Hz in software, device is
informed about rated voltage by setting “ReferenceVolt” which
corresponds to nominal phase-neutral voltage of the protected transformer
when is transferred to secondary value, using the turn ratio of voltage
transformer. Thus, the use of the overexcitation protection presumes that
measured voltage is connected to the device. Calculation of voltage/hertz
ratio above is performed based on the maximum voltage of the three
phase-neutral or phase-phase voltages. Logic switch “OEUsePEVolt”
determines that overexcitation protection should use phase-to-phase
voltage or phase-to-earth voltage.
241
The overexcitation protection includes two inverse characteristics (alarm

and trip are optional)) and one thermal characteristic. The latter
characteristic provides an approximate replica of the temperature rise
caused by overexcitation in the protected object. The inverse time alarm
stage can be enabled or disabled by using logic switch "InvTimeOExcitOn".
Thermal characteristic can be enabled or disabled by "InvTimeOExcitOn".
It should be mentioned that the overexcitation protection can be applied at
HV, MV or LV side of the protected transformer. However, it is not
recommended to apply the function on the transformer side with variable
winding turns such as the transformer side with an installed tap changer.
Overexcitation voltage can be set by setting "Overexcitation Voltage
Channel Selection". 0/1/2 represents high/medium/low voltage side
voltage respectively, default is 0 (high voltage side voltage).
The overexcitation protection uses phase-to-phase voltage or
phase-to-earth voltage of the corresponding side in their calculations,
based on the setting applied at logic switch “OEUsePEVolt”.
Take protection stage1 as an example, if the inverse time alarm is enabled,
and the calculated volt/hertz ration exceeds the setting value, then a report
“InvTimeOEAlarm” will be sent by the device after the time delay setting.
Similarly, if the trip inverse time is enabled, and the calculated volt/hertz
ration exceeds the setting value, a report “InvTimeOETrip” will be sent by
the device after the time delay expiration. Light of alarm and protection trip
can be configured by AESP.
If thermal characteristic is enabled in one of transformer sides, it uses the
measured voltage and frequency of the corresponding side, together with
the data from the manufacturer. The points correspond to the desired
tripping times for a given volt/hertz ratios. Intermediate values are
determined by performing linear interpolation by the device. The
overexcitation 1 stage factor can be set to 1.05, and the rest stages
increases by differential 0.05. Ratio range is
1.05~1.70(“InvTimeOEStage14Time”,1.70) The inverse times are set as
below: "InvTimeOEStage1Time", "InvTimeOEStage2Time",
"InvTimeOEStage3Time", "InvTimeOEStage4Time",
"InvTimeOEStage13Time", "InvTimeOEStage14Time", These points are
used to draw the inverse time characteristic curve, as shown in the
following figure:
242
u/f
V/F(T14)
V/F( T13)
V/F( T12)
V/F( T11)
V/F( T10)
V/F( T9)
V/F( T8)
V/F( T7)
V/F( T6)
V/F( T5)
V/F( T4)
V/F( T3)
V/F( T2)
V/F(T1)
T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 t(s)

Figure 88 Overexcitation characteristics
It can be observed from the above picture, N=1.05 is the starting threshold
of thermal characteristics stage; the calculated ratio of voltage/frequency is
greater than starting threshold and the thermal model increases from 0%
to 100% through the counter. If the counter reaches to 100%, then IED
trips. When the voltage / frequency ratio is lower than the start threshold,
the trip signal will be canceled. According to the transformer cooling time,
the counter will be reduced to zero (the value of thermal model counter is
from 100% to 0%). The cooling time is set as "OECoolingTime".
The inverse time characteristics shall take less than or equal to 14 points.
If the time delay setting of T1-T5 are set as 9999 seconds, then the inverse
time characteristic from the setting stage to stage T1 will be disabled.
243
3.2 Setting list

Table 168 Overexcitation protection setting
Setting Default
Number Range Unit Description
value
Voltage frequency
T1 time,
1. InvTimeOEStage1Time 0.1~9999 10 s
Set the value to
9999 and T1 exits.
Voltage frequency
T2 time,
2. InvTimeOEStage2Time 0.1~9999 10 s Set the value to
9999 and T1- T2
exits.
Voltage frequency
T3 time,
9999 and T1- T3
exits.
Voltage frequency
T4 time,
9999 and T1- T4
exits.
Voltage frequency
T5 time,
9999 and T1- T5
exits.
Voltage frequency
T6 time
Voltage frequency
T7 time
Voltage frequency
T8 time
Voltage frequency
T9 time
Voltage frequency
T10 time
Voltage frequency
T11 time
Voltage frequency
T12 time
Voltage frequency
T13 time
Voltage frequency
T14 time
15. InvTimeOERstTime 0.00~100.00 0.04 s
Cooling time of
16. OECoolingTime 0.1~9999 25 s
overexcitation
17. DefTimeOEStage1TripSet 1~1.5 1.1
18. DefTimeOEStage1Time 0.1~9999 100 s
244
Default
Number Setting Range Unit Description
value

0- Voltage of high
voltage side
1- Voltage of high
23. OEVoltChanSel 0~2 0 voltage side
2-Branch 1
voltage of low
voltage side
Rated value of PE
24. OEVoltRatedVal 10~120 57.74 V
or PP voltage
25. DefTimeRstTime 0.00~100.00 0.04 s
26. OEDropoffCoef 0.95~1.0 1.0
Table 169 Logic switch of overexcitation protection

Setting Default
Mode value
1. InvTimeOExcitOn 1/0 0 1-On, 0-Off
2. InvTimeOEAlarm 1/0 0 1-alarm, 0-trip
3. DefTimeOEStage1On 1/0 0 1-On, 0-Off
4. DefTimeOEStage1Alarm 1/0 0 1-alarm, 0-trip
1-phase-to-earth voltage;
9. OEUsePEVolt 1/0 0
0-phase-to-phase voltage
3.3 Report list


Trip report:
1. InvTimeOETrip /
2. DefTimeOEStage1Trip /
3. DefTimeOEStage2Trip /
4. DefTimeTimeOEStage3Trip /
Alarm report:
1. InvTimeOEAlarm /
2. DefTimeOEStage1Alarm /
245

Table 171 Overexcitation protection technical parameter
Reference voltageUN 10V～120V ≤ ±3% setting or ±1V
Time delay 0.1s～9999s ≤ ±5% setting or ±70ms
1.05 /1.10 /1.15 /1.20 /1.25
V/F characteristics /1.30 /1.35 /1.40 /1.45 /1.50 ≤ ±5% setting or ±70ms
/1.55 /1.60 /1.65 /1.7
Dropoff ratio ≥0.96
DefTime time characteristic
≤±5% setting or ±70ms, under
time delay T 0.1s～9999s
the circumstance of twice trip
Ratio: 1.00～1.50 ≤±2.5% setting or 0.01
Dropoff ratio ≥0.96
246
Chapter 24 Underfrequency protection (81UF)
Chapter 24 Underfrequency
Protection (81UF)
About this chapter

This chapter describes the principles of underfrequency
247
1 Overview
Underfrequency protection is used to monitor whether the network is
normal by detecting the frequency. When the frequency is lower than the
underfrequency protection setting value and meet other conditions, the
underfrequency protection trips to remove the specified load.
The main features of underfrequency protection are as follows:
1) Undervoltage blocking
2) Frequency changing rate(df/dt) blocking;
3) Circuit breaker position check and loaded current blocking;
4) VT secondary circuit failure blocking.
5) Underfrequency protection configuring 1 stage protection, can be
enabled or disabled respectively.
6) When the voltage connector of local side is disabled, the load
shedding protection is disabled.
soft-hard parallel.

The input and output signals of underfrequency protection function
diagram are shown below, left side is input and right side is output:
Under Frequency protection
1 1
CBOpen Start
2 2
BIBlk Operation
3
Ena_UF
4
Ena_HVoltage
Figure 89 The input and output signals of underfrequency protection function diagram
Input:
BinaryInput CBOpen Circuit breaker trip position
BIBlk BI blocking
Output:
UF Start IED startup
Operation IED trip
Input:
ENA_Function "GenlUFProtConn",the corresponding hard
Ena_UF
connector is Ena_UF_5
248
Input:
Ena_HVoltage "HVSideVoltConn",the hard connector is
Ena_HVoltage
Ena_HVoltage_5
3.1.1 Protection function introduction
When the voltage connector of local side is disabled, the load shedding
The principle of underfrequency and load shedding protection is "shed in
the line of interval". Specifically, the principle means that each interval will
be configured with underfrequency load shedding protection rather than
the incoming line interval will be configured with underfrequency load
shedding protection and send off tripping command through outlet line
interval. Then, every interval can be set with appropriate frequency
settings to start protection and with appropriate time settings to trip
protection. Trip frequency of underfrequency load shedding protection can
be tested by input three-phase voltage or single-phase voltage. Take
underfrequency load shedding stage 1 as example, as the measured
frequency is lower than settings "UFLSStage1FreqSet", the timing
component will start working; however, as it delays to the definite time
"UFLSStage1Time", the IED will send out a command "UFStage1Trip".
As the trip frequency of underfrequency load shedding protection is
calculated by measuring voltage, underfrequency load shedding protection
will be blocked with meeting the following requirement.
1) When three-phase voltage is connected, the lowest line voltage is
lower than settings, "LoadShedVoltBlkSet".
2) The device detects VT disconnection or the device will detect
high-level from VT disconnection;
3) When "UFLSChkCurrOn ", check current meets the blocking condition.
Loaded current is lower than settings, "LoadShedVoltBlkSet". As
voltage transformer is configured at the side of power supply, it is
useful to detect current setting. As the circuit is blocking,
"LoadShedVoltBlkSet" refers to as the smallest loaded current.
4) Circuit breaker is at open position. If it is in the same case, as voltage
transformer is configured at the side of power supply, it is useful to
detect current setting. Meanwhile, although the frequency is lower
than the underfrequency load shedding setting, the protection will not
send off trip command.
5) The frequency changing rate (Δf/Δt) succeeds setting value
"Df/dtBlkSet".
249
3.1.2 Logic diagram

UFProtFcnOn=1
&
“UFOn”=1
frequency<“UFFreqSet”
frequency<54Hz
&
or frequency>66Hz
System frequency=60Hz ≥1
frequency<45Hz
&
or frequency>55Hz
System frequency=50Hz
VT failure blocking
≥1
switch trip position
BI blocking
&
max(Ia,Ib,Ic)< ≥1 T1 Underfrequency
&
“LoadShedCurrBlkSet” protection trip
“UFLSChkCurrOn”=1
min(Uab,Ubc,Uca)<
&
“LoadShedVoltBlkSet”
“3PhVoltConnect”=1 ≥1
Frequency changing rate absolute value>

“Df/dtBlkSet” &
“UFLSChkDf/dt”=1
T1：“UFTime”
Figure 90 logic diagram of underfrequency protection
3.2 Setting list

Table 173 Underfrequency protection setting of high voltage side
Default
value
1. HVSideUFFreqSet 0.9Fn~1.0Fn 49.5 Hz
2. HVSideUFLoadShedTime 0.10~100.00 100 s
The frequency is
greater than the
3. HVSideDf/dtBlkFreqSet 0.9Fn~1.0Fn 49.5 Hz setting value, and
slippage locking
returns
4. HVSideFreqDf/dtBlkSet 0.30~20.00 20 Hz/s
250
Table 174 Underfrequency protection logic switch of high voltage side

Setting Default
Mode value
1. HVSideUFOn 1/0 0
1-Check current
2. HVSideUFLoadShedChkCurrOn 1/0 0
0-not check current
1- Check df/dt
3. HVSideUFChkDf/dt 1/0 0
0-not check df/dt;
Default
value
1. HVSideLoadShedVoltBlkSet 10.00~120.00 120 V
2. HVSideLoadShedCurrBlkSet 0.05In~10.0In 10 A
3.3 Report list


Trip report:
1. HVSideUFTrip /

Table 177 Underfrequency protection technical parameter
Underfrequency load shedding
Rated frequency fn=50Hz 45.00Hz～50.00Hz, step 0.01Hz ≤±20mHz
Rated frequency fn=60Hz 54.00Hz～60.00Hz，step 0.01Hz ≤±20mHz
≤ ± 1.5% times of setting
Time setting 0.1s～100.00s, step 0.01
or +60ms
Blocking condition
Frequency changing rate
0.3Hz/s～20Hz/s ≤±0.5Hz/s
Δf/Δt
Blocking voltage setting 1.0V～120V, step 1V ≤ ±2.5% setting or ±1V
Blocking current setting 0In～10In ≤ ±2.5% setting or ±0.01In
251
Chapter 25 Overfrequency protection (81OF)
Chapter 25 Overfrequency protection

(81OF)
About this chapter

This chapter describes the principles of overfrequency
253
1 Overview
Overfrequency protection is used to monitor whether the network is normal
by detecting the frequency. When the frequency is higher than the
overfrequency protection setting value and meet other conditions, the
overfrequency protection trips to remove the specified load.
Main characteristics of overfrequency protection are as follow:
1) Undervoltage blocking;
2) VT secondary circuit failure blocking;
3) Overfrequency protection configuring 1 stage protection.
4) When the voltage connector of local side is disabled, the
overfrequency protection is disabled.
soft-hard parallel.

The input and output signals of overfrequency protection function diagram
Over Frequency protection
1 1
BIBlk Start
2 2
Ena_OF Operation
3
Ena_HVoltage
Figure 91 The input and output signals of overfrequency protection function diagram
Input:
BIBlk BI blocking
OF Output:
Start IED startup
Operation IED trip
Input:
ENA_Function "HVSideOFConn",the corresponding
Ena_OF
hard connector is Ena_OF_5
Input:
Ena_HVoltage "HVSideVoltConn",the hard connector is
Ena_HVoltage
Ena_HVoltage_5
254
3.1.1 Protection function introduction
When the voltage connector of local side is disabled, the overfrequency
The device offers 1 stages of overfrequency protection. Function of each
stage will be enabled or disabled through corresponding logic switch with
logic switch of each stage. The overfrequency protection trip frequency
can be measured by the input three-phase voltage or single phase voltage.
Enable/Disable logic switch "3PhVoltAccess" to choose the input voltage
mode. Note that if the access voltage is a single-phase voltage, then the A
phase or B phase voltage is required to be accessed to measure the
system frequency. Similarly, if the access voltage is a single phase
phase-to-phase voltage, then it needs to access the phase-to-phase
voltage UAB. No matter what kind of voltage access, the measurement
frequency is obtained by the measurement of the voltage frequency. Take
overfrequency stage 1 as example, if the measured frequency is higher
than setting value "OFFreqSet", the timing component will start timing. As
time delay reaches "OFTime", trip command will be sent.
As the trip frequency of overfrequency protection is calculated by
measuring voltage, overfrequency protection will be blocked with meeting
the following requirement.
1) When three-phase voltage is connected, the lowest line voltage is
lower than settings, "LoadShedVoltBlkSet".
2) The device detects VT disconnection or the device will detect
high-level from VT disconnection.
255
3.1.2 Logic diagram

OFFcnOn=1
&
“OFOn”=1
frequency>“OFFreqSet”
frequency<54Hz
&
or frequency>66Hz
System frequency=60Hz ≥1
frequency<45Hz
&
or frequency>55Hz
System frequency=50Hz
VT failure blocking
&
≥1 ≥1 T1 Over frequency
Protection trip
3 phase trip
BI blocking
min(Uab,Ubc,Uca)<
“LoadShedVoltBlkSet” &
“3PhVoltConnect”=1
T1：“OFTime”
Figure 92 Logic diagram of overfrequency protection
3.2 Setting list

Table 179 Overfrequency protection setting of high voltage side
Default
value
1. HVSideOFSet 1.00Fn~1.10Fn 50.5 Hz
2. HVSideOFTime 0.10~100.00 100 s

Default
value
1. HVSideLoadShedVoltBlkSet 10.00~120.00 120 V
2. HVSideLoadShedCurrBlkSet 0.05In~10.0In 10 A
Table 181 Logic switch of overfrequency protection of high voltage side
Setting
Mode
1. HVSideOFOn 1/0 0
256
3.3 Report list


Trip report:
1. HVSideOFTrip /

Table 183 Overfrequency protection technical parameter
Overfrequency
Rated frequency fn=50Hz 50.00Hz～55.00Hz, step 0.01Hz ≤ ±20mHz
Rated frequency fn=60Hz 60.00Hz～66.00Hz, step 0.01Hz ≤ ±20mHz
≤ ±1.5% times of setting or
Time setting 0.1s～100.00s, step 0.01
+60ms
Blocking condition
Blocking voltage setting 10V～120V, step 1V ≤ ±2.5% setting or ±1V
257
Chapter 26 Non-electric protection
About this chapter

This chapter describes the principles of non-electric
259
1 Overview
Non-electric protection supports eight groups of consumer non-electric
tripping.

The input and output signals of non-electric protection function diagram
External trip initiation

1 1
BI Start
2
Operation
Figure 93 The input and output signals of non-electric protection function diagram
Input:
BI Non electric BI
ExtBI Output:
Start IED startup
Operation IED trip
External BI stay time reaches non-electric time setting, protection will trip.
“NonElectricGrp1On”=1 &
T1
Non-electric 1 protectin trip
Non-electric 1 BI
T1：“NonElectric1Time”
Figure 94 Non-electric protection 1 logic diagram
3.2 Setting list

Table 185 Non-electric protection setting
Default
value
1. NonElectric1Time 0~100 100 s
260
Default
value
9. NonElectricRstTime 0~100 0.04 s
Table 186 Non-electric protection logic switch

Logic switch Setting Default
Number Remark
name Mode value
1. NonElectric1On 1/0 0
3.3 Report list


Trip report:
1. NonElectric1Trip /
261
Chapter 27 Side differential protection
Chapter 27 Side differential

protection
About this chapter

This chapter describes the side differential protection
principle, input and output signals, parameter, IED report and
technical parameter for differential protection function.
263
1 Overview
The side differential protection took side winding and its lead wire of
transformer as the protection scope. Side differential can be applied to
autotransformer or ends of ordinary split phase transformer high voltage
side winding.
parallel.

The input and output signals of restricted side differential protection
function are shown as below, the left side is input signals and right side is
output signals:
DiffSideTripBO
1 1
Ena_DiffSide PerDiffSideATrip
2
PerDiffSideBTrip
3
PerDiffSideCTrip
4
ComWindingCT_Fail
5
DiffSide_Alarm
Figure 95 The input and output signals of side differential protection function diagram
Function Identification Description
Input：
ENA_Function "DiffSideConn",the corresponding hard connector is
Ena_DiffSide
Ena_DiffSide_5
Output：
PerDiffSideATrip Phase A trip of side differential
PerDiffSideBTrip Phase B trip of side differential

DiffSideTripBO
PerDiffSideCTrip Phase C trip of side differential
ComWindingCT_Fail Common Winding CT failure
DiffSide_Alarm Current overlimit alarm of side differential
The side differential protection is not affected by inrush current, over
excitation and transformer voltage adjustment. It can be applied to
autotransformer, the high voltage side, medium voltage side and common
widing current are connected to the IED to form the side differential
protection. It can also be used for high voltage side of ordinary split phase
transformer. The head end and tail end current of high side are connected
to the IED to form the side differential protection. When applied to the high
voltage side of ordinary split phase transformer, the tail end current should
264
be connected to the common winding current input(IComa/b/c).

The side differential protection applied to autotransformer is shown as
figure bellow:
IH HV
MV
IM
ComWinding
ICom
CSC-326
Figure 96 Application of side differential protection on an auto-transformer

When applied to the high voltage of the ordinary split phase transformer,
the head end currents should be connected to IED high voltage side
current channels, and the tail end currents should be connected to IED
common winding current channels.
The side differential protection applied to the ordinary split phase
transformer is shown as figure bellow:
IHa IComa
A
IHb IComb
B
IHc IComc
C
CSC-326
Figure 97 Application of side differential protection on the ordinary split phase

transformer high voltage side
265

The differential current Idiff and restricted current Irest are calculated as
the following equation:
𝑁
𝐼𝑑𝑖𝑓𝑓 = ∑ 𝐼𝑖̇
{
𝑖=1
𝐼𝑟𝑒𝑠 = max{|𝐼𝑖̇ |}
Where: ∑𝑁 ̇
𝑖=1 𝐼𝑖 is sum of all side pahse currents of high, medium and
common winding. max{|𝐼𝑖̇ |} is maxium phase current in all sides. Each
side currents are converted by correction coefficient. When applied to the
high voltage side of split phase transformer, the medium voltage side
currents are not included in the calculation of differential current idiff and
break current Ires.
Idiff and Ires are compared by the side differential protection with a
dual-slope operating characteristic defined by below equation and shown
in below figure.
I diff  S1I res  I D  I res  I R1 

I diff  S 2 ( I res  I R1 )  S1  I R1  I D  I R1  I res  I R 2 

I diff  S3 ( I res  I R 2 )  S 2 ( I R 2  I R1 )  S1  I R1  I D  I R 2  I res 
Where, S1 is the slope 1 (setting "SideDiffSlope1RatioRestrCoef").

ID> is the threshold value of the side differential protection sensitivity (the
setting is “SideDiffStartupSet”);
IR1 is the first break point setting of restricted current
“SideDiffBreakPoint1CurrSet”;
IR2 is the second break point setting of restricted current
“SideDiffBreakPoint2CurrSet”;
If the operating point calculated from the quantities of differential and
restraint current falls into the trip area, a trip signal is issued by the percent
differential protection. The issued signals are phase selective. They can be
found in event report as “SideDiffPhATrip”, “SideDiffPhBTrip” and
“SideDiffPhCTrip”.
This side differential characteristic can be enabled or disabled by using
logic switch “SideDiffOn”). If setting “1-on” is selected, a trip signal is
issued by side differential protection when the operating point lies into
tripping area (see below figure).
The trip logic for side differential protection is shown in below figure.
266
I
differ
ential
Differential
Slope3
Trip area
current
Slope2 restraint
Slope1
area I
Differential restra
int
startup setting
I restraint point1 I restraint point2 Restraint current
Figure 98 Characteristic of side differential protection
SideDiffProtFcnOn
&
“SideDiffOn”=1
Phase A
& Phase A trip of
I diff  A , I rest  A side differential
ID
>
Phase B
I diff  B , I rest  B
ID
>
Phase B trip of
&
side differential
Phase C
I diff C , I rest C
ID
>
Phase C trip of
&
side differential
“ CTFailBlkSideDiff”=1
&
CTFail
Figure 99 Tripping logic of the side differential protection

The high voltage side rated current is used as the reference current, and
the medium voltage side current and the common winding current are
automatically matched with the high voltage side rated current through
their respective calculated correction coefficients. The correction
coefficients are shown as formulas bellow:
𝑛𝐶𝑇−𝑀𝑉
𝐾𝐶𝑇−𝑀𝑉 =
𝑛𝐶𝑇−𝐻𝑉
267
𝑛𝐶𝑇−𝐶𝑜𝑚
𝐾𝐶𝑇−𝐶𝑜𝑚 =
𝑛𝐶𝑇−𝐻𝑉
Where: 𝐾𝐶𝑇−𝑀𝑉 is medium side correction coefficient, 𝐾𝐶𝑇−𝐶𝑜𝑚 is

common winding CT 𝑛𝐶𝑇−𝑀𝑉 is medium side CT ratio, 𝑛𝐶𝑇−𝐶𝑜𝑚 is
common winding CT ratio.
3.1.3 CT failure supervision
During steady-state operation, the CT failure supervision monitors the
transient behavior of the currents flowing through secondary circuit of each
phase and thus registers failures in the secondary circuit of the current
transformers for each side of the power transformer. The function can be
enabled or disabled by using setting “SideDiffCTFailDetectOn” (1-On,
0-Off). If setting “1-On” is applied whenever a CT failure is detected, IED
issues the alarm report. The differential protection can be configured as
whether the blocking is through CT failure by the logic switch
"SideDiffCTFailBlkDiff". By setting blocking through the logic switch, the
percent differential protection is blocked immediately in all phases when
CT failure occurs. Blocking condition is cancelled as soon as the device is
again supplied with a normal current in the relevant faulty phase(s).
The criteria for CT failure check are as follow:
The currents flowing through all three phases of CT secondary are normal
at each side of the protected object. As a result, the differential current is
near to zero. When one or two phase current of one side is decreased to
less than a threshold (half of the memory current), at the same time all
three phase currents in other side(s) are normal, and at least one phase
current is larger than a threshold (>0.3I_Percent Diff), the condition maybe
an indication of CT failure. CT failure check logic is illustrated in below
figure.
268
“SideDiffCTFailDetectOn”=1
Max {Idiff_A, Idiff_B, Idiff_C}>0.3*IDiffSet
{IHV_A, IHV_B, IHV_C}

only one phase or two phases
reduce.
&
{IMV_A, IMV_B, IMV_C} and {ICom_A,
ICom_B, ICom_C}
All current is unchanged.
{IMV_A, IMV_B, IMV_C} &

CT failure
reduce.
& ≥1
{IHV_A, IHV_B, IHV_C} and {ICom_A,
ICom_B, ICom_C}
{ICom_A, ICom_B, ICom_C}

reduce.
&
{IHV_A, IHV_B, IHV_C} and {IMV_A,
IMV_B, IMV_C}
IDiffSet“SideDiffStartupSet”
Figure 100 Logic diagram of side differential CT failure supervision
3.1.4 Side differential CT Saturation supervision

When Internal and external faults occurs, it is possible that transient and
steady fault currents induce the CT saturation. CT saturation may lead to
mal-operation of differential protection when an external fault occurs. In
order to avoid mal-operation of protection in such situations, CT saturation
supervision component is integrated in IED.
When transient saturation of CT occurs, the second harmonic content in
the corresponding phase current is dominant. Also whenever steady
saturation of CT occurs, the 3rd harmonic content in the corresponding
phase current is dominant. Both second and 3rd harmonic contents of all
phase currents of each side of the protected transformer are calculated to
judge whether CT saturation occurs or not. Comprehensive harmonic ratio
is calculated by below equation.
I 2 I 3
  K har
I I
Where:
Iφ2 is the secondary harmonic of current on each side;
Iφ3 is the third harmonic of current on each side;
Khar is the setting of comprehensive harmonic ratio, and the fixed setting
of software.
If the second and 3rd harmonic contents of any phase current are more
269
than Khar, then CT satisfies the above formulas and it is saturated. Usually
before the CT saturation status. there is a short time period in which CT
still works in its linear characteristic. By very fast CT saturation detection of
IED, it needs only 4ms before any CT saturation happening to detect the
fault which is internal or external fault. x In order to distinguish saturation
caused by internal faults and external faults effectively, percent differential
protection based on sample values is used. If CT saturation is induced by
external fault, differential protection will be blocked. However if CT
saturation is induced by internal fault, differential protection will send its trip
signal.
The typical saturation figure of phase A CT saturation is shown in below
figure.
Figure 101 Typical phase A current transformer Saturation waveform
3.1.5 Side differential current supervision

In normal operation condition, zero differential current is assumed in each
phase. The differential current supervision monitors the differential
currents and checks its value to be less than a threshold. An alarm report
is generated as “SideDiffCurrOverLmtAlarm” after 5s, if the differential
current exceeds the threshold value. The alarm is an indication of
miss-connection in CT secondary windings, and therefore is released to
remind user to detect the faulty connection in secondary circuit and
remove it. This function can be enabled or disabled by the logic switch
"SideDiffOn" (1-on, 0-off). The fixed threshold for releasing alarm is 0.3
times of “SideDiffStartupSet”. However, to avoid incorrect alarm, the
threshold value will increase to 0.05A (1A CT) and to 0.25A (5A CT) if 0.3
times of "DiffCurrSet" <0.05In.
Logic of side differential current supervision is shown in below figure.
SideDiffProtFcnOn=1
“SideDiffOn”=1
Idiff_A>ID.alarm
Current overlimit
Idiff_B>ID.alarm ≥1 & 5s alarm of side
differential
Idiff_C>ID.alarm
Figure 102 CT Fail detection logic
270
DANGER: Before side differential protection is put into operation on

site, polarity of current transformer must have been checked right by
an energizing test of every side of the transformer or a test of
simulating an external fault of the side in primary system. Otherwise
a mal-operation may occur during an external fault.
3.2 Setting list

Table 189 Side differential protection setting
Default
Range
(In:5A/1A)
(In:5A/1A)
Differential
1. SideDiffStartupSet 0.05In~4In 2 A Startup
Current Setting
The current
setting of first
2. SideDiffBreakPoint1CurrSet 0.1In~In 0.6 A
break point
(IR1)
The 2nd
breakpoint
3. SideDiffBreakPoint2CurrSet 0.1In~10In 2 A
restraint
current (IR2)
Ratio restraint
4. SideDiffSlope1RatioRestrCoef 0.00~0.2 0.2 coefficient of
the first slope
Ratio restraint
coefficient of
5. SideDiffSlope2RatioRestrCoef 0.2~0.7 0.5
the second
slope
Ratio restraint
6. SideDiffSlope3RatioRestrCoef 0.25~0.95 0.7 coefficient of
the third slope
Table 190 Side differential protection logic switch
Setting Default
Mode value
1. SideDiffOn 0/1 0 1-enabling, 0-disabling
2. SideDiffCTFailDetectOn 0/1 0 1- enabling, 0- disabling
3. SideDiffCTFailBlkDiff 0/1 0 1-blocking, 0-unblocking
3.3 Report list


Trip report:
1. SideDiffPhATrip
2. SideDiffPhBTrip Three-slope ratio differential phase A/B/C trip
3. SideDiffPhCTrip
Alarm report:
1. HVSide1CTFail
2. HVSide2CTFail
3. MVSide1CTFail
4. MVSide2CTFail
5. CommonWindCTFail
271
6. SideDiffCurrOverLmtAlarm Imbalance differential current alarm

Table 192 Technical parameter for side differential protection
Side ratio differential current 0.05In to 4.00In ≤ ±3% setting or ±0.02In,
Side differential restraint
0.1In to 1In ≤ ±3% setting or ±0.02In
current 1
Side differential restraint
0.1In to10In ≤ ±3% setting or ±0.02In
current 2
Side differential slope 1 0.0 to 0.2
Side differential Reset ratio of
About 0.7
restrained differential
it ≤ 30ms when the setting is
Side differential operating
in 200% times, and
time of restraint differential
IDifferential>2IRestraint
272
Chapter 28 Secondary circuit supervision
Chapter 28 Secondary circuit

supervision
About this chapter

This chapter describes VT failure secondary circuit
monitoring function.
273
1 Overview
When the secondary circuit of the voltage transformer is broken or short
circuit, the measured voltage is zero by the protections based on the
undervoltage criterion and this can cause the mis-operation of IED. VT
failure check provides voltage monitoring for such protections. VT
monitoring is used to monitor the voltage transformer circuit, single-phase
VT failure, two-phase VT failure and three-phase VT failure. Main
characteristics is as follows:
1) Symmetry/ asymmetry (asymmetric) VT failure;
2) Three-phase AC voltage miniature transformer failure monitoring;
3) It is used in grounding system, non-direct grounding system and
ungrounded system;
4) When the voltage connector of local side is disabled, the VT failure
function of local side is disabled.

The input and output signals of VT failure check function diagram is shown
below, left side is input and right side is output:
Symmetrical and asymmetrical
VT Fuse Fail Detection
1 1
V3P_BI VTFail
2 2
Ena_*Voltage VTFailRet
Figure 103 VT failure check function input and output signal diagram
Input:
BIConfig
V3P_BI Three-phase VT failure BI
Output:
VTFail VTFail VT failure alarm
VTFailRet VT failure reset
Input:
"HVSideVoltConn": Ena_HVoltage,the corresponding
"MVSideVoltConn": Ena_MVoltage,the corresponding
ENA_*Voltage hard connector is Ena_MVoltage_5
Ena_*Voltage
"LVSide1VoltConn",the corresponding hard connector is
Ena_L1Voltage_5
"LVSide2VoltConn": Ena_L2Voltage, the corresponding
hard connector is Ena_L2Voltage_5
274
3.1.1. Protection function introduction
When the voltage connector of local side is disabled, the VT failure
function of local side is disabled
VT failure function can be enabled or disable by setting the logic switch
“VTFailOn”, when the logic switch is set as 1, VT failure protection is
enabled, it can be used to detect single-phase, two-phase and
three-phase VT failure.
There are three main criteria for detecting VT failure, which are the check
of the three phase failure, the check of the asymmetric failure of the
grounding system, and the check of the asymmetry of the non-direct
grounding system. The prerequisite is that the protection device starting
component does not start and the zero sequence current and negative
sequence current are less than "VTFail3I03I2Set" Specifically as follows:
1) Three-phase (symmetry) VT failure: when the secondary side
three-phase of VT failure occurs, if the stating component does not
start, then the maximum of compounded zero sequence voltage
3U0 and three-phase phase-to-earth voltage are both less than
"VTFailPEVoltSet" and the maximum of three-phase current
exceeds "VTFailCurrSet".
2) Single-phase/ two-phase (asymmetric) VT failure
a) When the secondary side single-phase or two-phase of VT failure
occurs, if the system is directly grounded and the stating
component does not start, then the maximum of compounded
zero sequence voltage 3U0 exceeds "VTFailPEVoltSet".
b) When the secondary side single-phase or two-phase of VT failure
occurs, if the system is not directly grounded and the stating
component does not start, then then compounded zero sequence
voltage 3U0 exceeds "VTFailPEVoltSet" and the difference
between the maximum and minimum of voltage exceeds
"VTFailPPVoltSet".
In addition, when the device detects V3P_BI, then it is judged as
"3PhVTFail". If the device detects V3P_BI and the voltage exceeds
"VTFailPEVoltSet", it is judged as abnormal BI signal.
After "VTFailAlarm" or "VTFailBIErrAlarm" are issued, LED and protection
trip can be configured by AESP.
3.1.2. Logic diagram
If the secondary circuit failure of VT is detected, the protection based on
the standard of direction or undervoltage will be blocked and it will send off
the report "VTFailAlarm" through the delay of "VTFailDelayAlarm". When
one of the following conditions is met within the delay of
"VTFailAlarmTime" (that is, before sending off the report "VTFailAlarm"),
VT failure blocking opens.
1) While the protection does not start, the minimum phase-to-phase
voltage exceeds "VTFailNormalVolt" with 500ms delay.
275
2) While the protection does not start, the minimum phase-to-phase

voltage exceeds "VTFailNormalVolt" and the zero sequence current
and negative current exceed "VTFail3I03I2Set".
3) While the protection does not start after the "VTFailAlarm" is sent off ,
the minimum phase-to-phase voltage exceeds "VTFailNormalVolt", VT
failure blocking opens through “VTFailBlkTime” delay.
The report "VTFailRst" is issued when the third VT failure recovery is
checked.
max(Ia,Ib,Ic)>“VTFailCurrSet”
&
max(Ua,Ub,Uc)<“VTFailPEVoltSet”
Calculated3U0<
“VTFailPEVoltSet”
“NutrPointEarth”=1 & ≥1
Calculated3U0>=
“VTFailPEVoltSet”
“NutrPointEarth”=0 &
Max(PPVoltage)-Min(PPVoltage)>
“VTFailPPVoltSet”
&
Current type ≥1
protection start-up &
InstantVTFailure=1
3PhaseVTFailureBI
VTFailureFunctionOn
“VTFailOn”=1
“VTFailOn”=0
&
Calculated3I0>“VTFail3I0/3I2Set” ≥1 &
≥1
InstantVTFailure=0
3I2>“VTFail3I0/3I2Set”
min(Ua,Ub,Uc)>“VTFailNormalVolt”
&
VTFailureAlarm=1
&
&
T
T
InstantVTFailure=1 VTFailureAlarm=1
T1
VTFailBlk=1
T：“VTFailAlarmTime”
T1：“VTFailBlkTime”
Figure 104 VT failure protection logic diagram

Minimum value of PE voltage>
“VTFailPEVoltSet” &
T_Err
VT failure BI abnormal alarm
3 phase VT failure BI
T_Err：“VTFailBIErrTime”
Figure 105 Binary input VT failure protection logic diagram
276
3.2 Setting list

Table 194 VT failure check setting of high voltage side
Number Setting name Range Default value Unit Remark

1. HVSideVTFailCurrSet 0.05In~40.0In 0.25 A
2. HVSideVTFail3I03I2Set 0.05In~40.0In 0.25 A
3. HVSideVTFailPEVoltSet 5.00~20.00 8 V
4. HVSideVTFailPPVoltSet 10.00~30.00 16 V
5. HVSideVTFailNormalVolt 40.00~120.0 40 V
6. HVSideVTFailBlkTime 0.04~5.0 2 s
7. HVSideVTFailAlarmTime 0.04~100 10 s
8. HVSideVTFailBIErr 0~100 10 s
Table 195 VT failure check logic switch of high voltage side

Setting Default
Mode value
1. HVSideVTFailOn 1/0 0
2. HVSideNutrPointEarth 1/0 0
Table 196 VT failure check setting of medium voltage side

1. MVSideVTFailCurrSet 0.05In~40.0In 0.25 A
2. MVSideVTFail3I03I2Set 0.05In~40.0In 0.25 A
3. MVSideVTFailPEVoltSet 5.00~20.00 8 V
4. MVSideVTFailPPVoltSet 10.00~30.00 16 V
5. MVSideVTFailNormalVolt 40.00~120.0 40 V
6. MVSideVTFailBlkTime 0.04~5.0 2 s
7. MVSideVTFailAlarmTime 0.04~100 10 s
8. MVSideVTFailBIErr 0~100 10 s
Table 197 VT failure check logic switch of medium voltage side

Setting Default
Mode value
1. MVSideVTFailOn 1/0 0
2. MVSideNutrPointEarth 1/0 0
Table 198 VT failure check setting of low voltage side1

1. LVSide1VTFailCurrSet 0.05In~40.0In 0.25 A
2. LVSide1VTFail3I03I2Set 0.05In~40.0In 0.25 A
3. LVSide1VTFailPEVoltSet 5.00~20.00 8 V
4. LVSide1VTFailPPVoltSet 10.00~30.00 16 V
5. LVSide1VTFailNormalVolt 40.00~120.0 40 V
6. LVSide1VTFailBlkTime 0.04~5.0 2 s
277

7. LVSide1VTFailAlarmTime 0.04~100 10 s
8. LVSide1VTFailBIErr 0~100 10 s
Table 199 VT failure check logic switch of low voltage side1

Setting Default
Mode value
1. LVSide1VTFailOn 1/0 0
2. LVSide1NutrPointEarth 1/0 0
Table 200 VT failure check setting of low voltage side2

1. LVSide2VTFailCurrSet 0.05In~40.0In 0.25 A
2. LVSide2VTFail3I03I2Set 0.05In~40.0In 0.25 A
3. LVSide2VTFailPEVoltSet 5.00~20.00 8 V
4. LVSide2VTFailPPVoltSet 10.00~30.00 16 V
5. LVSide2VTFailNormalVolt 40.00~120.0 40 V
6. LVSide2VTFailBlkTime 0.04~5.0 2 s
7. LVSide2VTFailAlarmTime 0.04~100 10 s
8. LVSide2VTFailBIErr 0~100 10 s
Table 201 VT failure check logic switch of low voltage side2

Setting Default
Mode value
1. LVSide2VTFailOn 1/0 0
2. LVSide2NutrPointEarth 1/0 0
3.3 Report list


Alarm report:
1. HVSideVTFail /
2. HVSideVTFailBIErr /
3. MVSideVTFail /
4. MVSideVTFailBIErr /
5. LVSide1VTFail /
6. LVSide1VTFailBIErr /
7. LVSide2VTFail
8. LVSide2VTFailBIErr
278

Table 203 VT failure check technical parameter
VT Failure Current 0.05In～40In, step 0.01A ≤ ±3% setting or ±0.02In
Zero and negative sequence 0.05In～40In, step 0.01A ≤ ±5% setting or ±0.02In
currents of VT failure
VT failure phase-to-earth 5.0V～20.0V, step 0.01V ≤ ±3% setting or ±1V
voltage
VT failure phase-to-phase 10.0V～30.0V, step 0.01V ≤ ±3% setting or ±1V
voltage
return to VT normal voltage 40.0V～120.0V, step 0.01V ≤ ±3% setting or ±1V
279
Chapter 29 Gap protection
About this chapter

This chapter describes gap protection function.
281
1 Overview
Gap protection is a backup protection for single-phase grounding fault
when the neutral point of a non fully insulated transformer is grounded by
discharge gap.
parallel.

The input and output signals in this manual only show the visible part of
the project, and the input and output signals of user defined protection
diagram are shown as below, the left side is input signals.
Gap Function
1 1
BIBlk bStart
2 2
Ena_*Gap bOperationI1
3 3
Ena_*Voltage bOperationI2
4
bOperationU1
5
bOperationU2
Figure 106 The input and output signals of gap protection diagram
Table 204 Parameter description of input and output
Input:
BIBlk Binary input blocking
Output:
Start IED startup
Gap
bOperationI1 GapOCTime1Trip
bOperationI2 GapOCTime2Trip
bOperationU1 GapOVTime1Trip
bOperationU2 GapOVTime2Trip
Input:
"HVSideGapConn": Ena_HVGap, the corresponding
ENA_Function hard connector is Ena_HVGap_5
Ena_*Gap
"MVSideGapConn":Ena_MVGap, the corresponding
hard connector is Ena_MVGap_5
Input:
"HVSideVoltConn":Ena_HVoltage,the corresponding
ENA_*Voltage hard connector is Ena_HVoltage_5
Ena_*Voltage
"MVSideVoltConn":Ena_MVoltage,the corresponding
hard connector is Ena_MVoltage_5
282
Gap protection includes zero sequence voltage protection and gap
overcurrent protection.
Zero sequence voltage protection trip voltage can be selected as external
or calculated by logic switch. When it is calculated, it is blocked by VT
failure or disabling voltage connector.
The trip current of gap overcurrent protection is taken from the gap zero
sequence CT current of the transformer earthing circuit through the gap,
and forms “OrLogic” time trip together with the zero sequence voltage.
The logic diagram of gap protection trip is shown in.
GapProtFcnOn=1
Calculated3U0>“GapOVSet”
≥1 &
VT failure
&
the voltage connector of local side=0
≥1
3U0Component Trip
“GapCalc3U0”=1
&
Calculated3U0> “GapOVSet”
“GapOVOn”=1
&
T_JXU0 Gap overvoltage
protection trip
3U0Component Trip
≥1
&
T_JXI0 Gap overcurrent
protection trip
Gap current>ISet_Gap
“GapOCOn”=1
Iset_JX：“GapOCSet”
T_JXU0：“GapOVTime”
T_JXI0：“GapOCTime”
Figure 107 The logic diagram of gap protection
3.2 Setting list

Table 205 Gap protection setting of high voltage side

1. HVSideGapOCSet 0.05In~40In 40 A
2. HVSideGapOCTime1 0.1~100 100 s
3. HVSideGapOCTime2 0.1~100 100 s
4. HVSideGapOVSet 10~200 180 V
283

5. HVSideGapOVTime1 0.1~100 100 s
6. HVSideGapOVTime2 0.1~100 100 s
Table 206 Gap protection logic switch of high voltage side

Setting Default
Mode value
1. HVSideGapOCTime1On 1/0 1
2. HVSideGapOCTime2On 1/0 1
1-calculated zero pressure,
3. HVSideGapCalc3U0 1/0 1
0-external zero sequence voltage
4. HVSideGapOVTime1On 1/0 1
5. HVSideGapOVTime2On 1/0 1
Table 207 Gap protection setting of medium voltage side

1. MVSideGapOCSet 0.05In~40In 40 A
2. MVSideGapOCTime1 0.1~100 100 s
3. MVSideGapOCTime2 0.1~100 100 s
4. MVSideGapOVSet 10~200 180 V
5. MVSideGapOVTime1 0.1~100 100 s
6. MVSideGapOVTime2 0.1~100 100 s
Table 208 Gap protection logic switch of medium voltage side

Setting Default
Mode value
1. MVSideGapOCTime1On 1/0 1
2. MVSideGapOCTime2On 1/0 1
1-calculated zero pressure,
3. MVSideGapCalc3U0 1/0 1
0-external zero sequence voltage
4. MVSideGapOVTime1On 1/0 1
5. MVSideGapOVTime2On 1/0 1
3.3 Report list


Trip report:
1. HVSideGapOCTime1Trip /
2. HVSideGapOCTime2Trip /
3. HVSideGapOVTime1Trip /
4. HVSideGapOVTime2Trip /
5. MVSideGapOCTime1Trip
284
6. MVSideGapOCTime2Trip
7. MVSideGapOVTime1Trip
8. MVSideGapOVTime2Trip
285
Chapter 30 Overload protection
About this chapter

This chapter describes Overload, start fan and blocking
voltage adjustment protection function.
287
1 Overview
Overload protection, start fan protection and blocking voltage adjustment
protection. The protective function can be disabled through the function
connector. The connector properties can be configured as soft connector,
hard connector, soft-hard series, soft-hard parallel, and the default is
soft-hard parallel.

The input and output signals in this manual only show the visible part of
the project, and the input and output signals of Overload protection
diagram are shown as below, the left side is input signals.
Overload Function
1 1
BIBlk Alarm
2
Ena_HVStartFan
3
Ena_HVBlkVoltAdj
4
Ena_*OL
parallel.
Figure 108 The input and output signals of Overload protection diagram
Table 210 Parameter description of input and output
Input:
OL/StartFan/BlkV BIBlk BI blocking

oltAdj Output:
Alarm IED alarm
Input:
Ena_HVStartF "HVStartFanConn", the corresponding hard connector is
an Ena_HVStartFan_5
Ena_HVBlkVol "HVBlkVoltAdjConn", the corresponding hard connector is
tAdj Ena_HVBlkVoltAdj_5
"HVSideOLConn": Ena_HVOL, the corresponding hard
connector is Ena_HVOL_5
ENA_Function "MVSideOLConn": Ena_MVOL, the corresponding hard
connector is Ena_MVOL_5
"LVSide1OLConn": Ena_LV1OL, the corresponding hard
Ena_*OL
connector is Ena_LV1OL_5
288
The device is equipped with overload protection, delayed action on signal,
and overload protection to detect three-phase current.
In addition, user-defined protection is provided with overload start fan
protection and blocking voltage adjustment protection, and the
three-phase current of the high voltage side can be detected, and the
setting value can be set.
Overload alarm trip logic diagram is shown below:
Ia>“OLCurrSet”
≥1
&
Ib>“OLCurrSet” T
Overload
Ic>“OLCurrSet”
“OLOn”=1
OLProtFcnOn=1
T：“OLTime”
Figure 109 Overload logic diagram

Start fan trip logic diagram is shown below:
Ia>“StartFanCurrSet”
≥1
&
Ib>“StartFanCurrSet” T
StartFan
Ic>“StartFanCurrSet”
“StartFanOn”=1
StartFanProtFcnOn=1
T：“StartFanTime”
Figure 110 Start fan logic diagram

Blocking voltage adjustment trip logic diagram is shown below:
Ia>“BlkVoltAdjCurrSet”
≥1
&
Ib>“BlkVoltAdjCurrSet” T Blocking voltage
adjustment
Ic>“BlkVoltAdjCurrSet”
“BlkVoltAdjOn”=1
BlkVoltAdjProtFcnOn=1
T：“eBlkVoltAdjTime”
Figure 111 Blocking voltage adjustment logic diagram
3.2 Configuration specification of BO module

The starting ventilation and locking voltage regulating contacts may cause
the outgoing coil to be excited for a long time. Therefore, the starting
ventilation and locking voltage regulating outgoing contacts shall be
configured in the last several channels of the outgoing board, and other
contacts of the Board shall be configured to be started and locked.
For example, for BIO board, start ventilation and lock voltage regulating
289
output are configured in BO10-BO12, BO10-BO12 is configured not to be

started and locked, BO1-BO9 is configured to be started and locked, and
BO10-BO12 should not be configured with other output except start
ventilation and lock voltage regulating.
For BIO board, the start fan and blocking voltage adjustment contact is
configured in BO10-BO12, BO10-BO12 is configured as not subject to
start locking, and BO1-BO9 is configured as subject to start locking. BO10-
BO12 shall not be equipped with other outlets except for start fan and
blocking voltage adjustment.
For BO board, the start fan and blocking voltage adjustment contact is
configured in BO13-BO16, BO13-BO16 is configured as not subject to
start locking, and BO1-BO12 is configured as subject to start locking.
BO13- BO16 shall not be equipped with other outlets except for start fan
and blocking voltage adjustment.
3.3 Setting list

Table 211 Overload protection setting of high voltage side
Default
value
1. HVSideOLCurrSet 0.05In~40In 40 A
2. HVSideOLTime 0.1~100 100 s
Table 212 Overload protection logic switch of high voltage side

Number Remark
name Mode value
1. HVSideOLOn 1/0 1
Table 213 Overload protection setting of medium voltage side

Default
value
1. MVSideOLCurrSet 0.05In~40In 40 A
2. MVSideOLTime 0.1~100 100 s
Table 214 Overload protection logic switch of medium voltage side

Number Remark
name Mode value
1. MVSideOLOn 1/0 1
Table 215 Overload protection setting of low voltage side1

Default
value
1. LVSide1OLCurrSet 0.05In~40In 40 A
2. LVSide1OLTime 0.1~100 100 s
Table 216 Overload protection logic switch of low voltage side1

Number Remark
name Mode value
1. LVSide1OLOn 1/0 1
290

Default
value

Number Remark
name Mode value

Default
value

Number Remark
name Mode value
Table 221 Start fan protection setting of high voltage side

Default
value
1. HVSideStartFanStage1CurrSet 0.05In~40In 40 A
2. HVSideStartFanStage1Time 0.1~100 100 s
3. HVSideStartFanStage2CurrSet 0.05In~40In 40 A
4. HVSideStartFanStage2Time 0.1~100 100 s
Table 222 Start fan protection logic switch of high voltage side
Set Default
mode value
1. HVStartFanStage1On 1/0 1 1-On, 0-Off
2. HVStartFanStage2On 1/0 1 1-On, 0-Off
Table 223 Blocking voltage adjustment protection setting of high voltage side
Default
value
1. HVSideBlkVoltAdjCurrSet 0.05In~40In 40 A
2. HVSideBlkVoltAdjTime 0.1~100 100 s
Table 224 Blocking voltage adjustment logic switch of high voltage side
Setting
Mode
1. HVSideBlkVoltAdjOn 1/0 1
291
3.4 Report list

Alarm report:
1. HVSideOL /
2. MVSideOL /
3. LVSide1OL /
4. LVSide2OL
5. LVSide3OL
6. HVSideStartFan1 /
7. HVSideStartFan2 /
8. BlkVoltAdj /
292
Chapter 31 User-defined function
About this chapter

This chapter describes BI, BO, LED configuration and user
defined logic function.
293
1 Overview
The binary input and output, report, LED of device can be defined
secondly in accordance with demands. According to the actual situation of
the project, the user can user-definedize the logic. This chapter mainly
describes the function of the AESPStudio tool software which may be used
in engineering application to perform the user defined function and the
matters needing attention.
2 User-defined configuration
2.1 Open project
Click the file→open, in the open file dialog box, open the file named
aespro.
2.2 Binary input configuration

The title of BI can be modified by engineering example. The property of
each BI can be set in BI configuration according to demand.
Table 226 Binary input configuration
Binary input configuration
Configuration Description
item
Binary input Excitation changes from 0 to 1, and close position of binary input is defined
time 1 by time 1
Binary input Excitation changes from 1 to 0, and open position of binary input is defined
time 2 by time 2
Waveform Configure "DFR", "RisingEdgeTrigger", "FallingEdgeTrigger"

record set
Property 1: Configuration "SirenBit", "BellBit", "PulseQuantity", "SendSOE",

"DualPosnBI", "ACInput" and "BCUProtocol"
Property 2: Configure "NonSmartModule", "24V", "48V", "110V", "125V", "220V", "250V"
Property 3: Configure "OrdinaryBI", "MaintState", "Rmt/Local", "Invalid"
Bay control
unit and
Configure "Prot", "BCU"
protection
property
294
Note: when setting waveform record, if "DFR" is configured, then the BI will
be in the waveform recording; if "RisingEdgeTrigger" is configured, when
the BI changes from 0 into 1, the waveform record will be generated; if
"FallingEdgeTrigger" is configured, when the BI changes from 1 into 0, the
waveform record will be generated. The generated waveform record file
will be saved into the list of startup waveform records.
The work voltage can only be configured within ranges defined by this
module unit. Hardware board contains high power voltage level and low
power voltage level, respectively marked with the work voltage of DC
"110V", "125V", "220V", "250V" and "24V", "48V".
The time sequence explanation of "BITime1" and "BITime2" is shown as
below.
Excitation
Binary input time delay 1
Binary input
Binary input time delay 2
Figure 112 Binary input time delay sequence

Configuration way of double position binary input:
Two single-position binary inputs can be used to describe the
double-position binary input, and the close position of single input
accesses to the n hardware binary input, and then the open position of
single input accesses to the n+1 hardware binary input. "DualPosnBI" can
be selected for the property 1 of binary input n; but it cannot be selected for
the property 1 of binary input n+1; and "Invalid “can be selected for the
property 3.
The logic state of a pair of binary inputs (binary input n and n+1)
configured with double-0position will no longer be that of the hardware
binary input. Only when (hardware binary input n, n+1) = (1, 0), the logic
binary input n refers to the close position state; only when (hardware
binary input n, n+1) = (0, 0) or (1, 1), the property of double-position of
binary input is 1, which means the invalid state.
Both the BI state and BI state in IO Matrix of double-position hardware BI
and logic BI are shown below
Table 227 State list for hardware binary input of double position and logic binary input
Binary input of hardware (binary
0, 0 0, 1 1, 0 1, 1
input, binary inputn+1)
Logic binary input(binary input,
0, 1 0, 0 1, 0 0, 1
binary inputn+1)
2.3 Binary output configuration

The title of BI can be modified by engineering example. The property of
each BI can be set in BI configuration according to demand,\/.
295
Table 228 Binary output configuration
Binary output configuration
Configuration Description
item
Holding time Excitation returns and BO also returns experiencing retention time.
Waveform Configure "DFR", "RisingEdgeTrigger", "FallingEdgeTrigger"

record set
Binary output Configure "ElectricLatched", "TripRedundancy", "ReclaimRedundancy",

property "BlkedByStartup", "NCContact"
To configure "ElectricLatched" property, the electric relay will return only

after the signals recovering. The movement sequence is shown as below.
When the device is powered down and then power up, the electric relay
can recover the state before power down.
Excitation
Reset
Relay
Figure 113 Electric latched relay trip sequence

Configuration is the node of electric retention, which can't
"BlkedByStartup"; otherwise startup relay will return and so does BI.
Non "ElectricLatched" BI can configure "LatchedTime", excitation will
return, after the set time, the relay returns.
Excitation
Relay
Figure 114 Non-electric latched relay trip sequence

Please configure in line with the hardware jumper of BO, and determine
whether BO is "BlkedByStartup" or not, and whether "NCContact" or not.
As CPU and other redundant CPU will send off command; the
configuration as "Trip Redundancy" of node relay trips; as CPU and other
redundant CPU retreat all the command, the configuration as
"ReclaimRedundancy" of node relay will trip. If the protection configuration
doesn't configure redundancy, "ReclaimRedundancy" and “Trip
296
Redundancy" can't be set.

This device is equipped with redundant CPU, therefore, for the BO used
for tripping, it must be configured with "TripRedundancy", and it is
suggested not be configured with "RedundancyRecovery" according to the
principle “BO contacts are driven by both of the two CPU and command is
withdrew by one of the CPUs". For the BO used for alarm, it is suggested
not be configured with "TripRedundancy" but with "RedundancyRecovery"
according to the principle “BO contacts are driven by one of the two CPUs
and commands are withdrew by both of the two CPUs".
It should be noted that the redundant attributes of “BOCfg” and “LEDCfg”
should be consistent.
It is suggested that the BO used for tripping on tripping module should be
set as “BlkedByStartup”, and the BO used for sending trip or alarm signal
on tripping module needn't to be set as "BlkedByStartup". The
configuration of hardware jumper and the BO should be consistent.
Please set the attributes of "NCContact" according to the needs of project.
The configuration of hardware jumper and the BO should be consistent.
See figure bellow, one of configuration properties of BO "BlkedByStartup"
must be linked with the contact of hardware, and every three BOs shall
form a group to be configured similarly. Which means BO1, BO2 and BO3
shall form a group; BO4, BO5 and BO6 form a group and so on.
Figure 115 Diagram of binary output configuration
2.4 LED configuration

The title of LED can be modified by engineering example. On control plate,
the calibrated LED indicator tag can be embedded into the corresponding
position of the indicator light. The property of each LED can be set in LED
configuration according to demand.
Table 229 Light configuration.
Light configuration.
Configuration item Description
297
Light configuration.
Holding property Configuration "Latched", "NonLatched", and configuration is

"Latched", recovery action should be enacted to eliminate light state.
Light color The color of LED is "yellow", "green" and "red"
Flashing The LED is flashing or constant on, n represents the flash frequency
is n*50ms; when it is 0 or 1, the LED is always on.
Redundancy As the configuration is "Redundancy" property, multiple CPU will

trigger light at the same time and the LED will be enlightened
As CPU and other redundant CPU all send out lighting commands, the
LED configured with "Redundancy" can be enlightened. If LED doesn't
have redundancy property, "Redundancy" property cannot be set.
2.5 IO Matrix configuration

The IO Matrix configuration achieves a fast correlation between virtual and
real points in the software. Virtual point comes from the application
software, corresponding to the functional software to modify the data
points, the real point from the limited resources provided by the device.
2.5.1 IO Matrix channel configuration
The IO Matrix channel configuration is used to specify the source of the
required input information for the application, the AC or DC excitation of
the device is configured as AC sampling or SV data.
“X” means the valid selection.
Figure 116 Diagram of channel configuration
2.5.2 IO Matrix function configuration

The IO Matrix function configuration is used to specify the protection action
of the device. External input signal is dependent on each function of the
298
device and external manifestations of action include the opening and the
lights, etc., through the configuration to achieve the definition.
“H” refers to the valid high power level ,”L” is valid low power level.
Figure 117 Diagram of function configuration
2.6 Binary input switch setting group

2.6.1 Function description
IED can switch the setting zone in two ways. When the setting
"BISwitchSetGrp" is set as 0, IED will response to the panel or SCADA to
switch the setting group; when the setting "BISwitchSetGrp" is set as 1,
IED will not response to the panel or SCADA to switch the setting group, it
will switch the setting group automatically according to the status of binary
input.
The device provides four default configurable BI to switch setting group, in
BIToSetGrp, BI1, BI2, BI3, BI4 can be set by users in the engineering
research and development version.
Table 230 Four binary input switch setting group configuration examples
Number BIToSetGrp4/2/1 Setting group

1. 0000 1
2. 0001 2
3. 0010 3
4. 0011 4
5. 0100 5
6. 0101 6
7. 0110 7
8. 0111 8
9. 1000 9
10. 1001 10
11. 1010 11
12. 1011 12
13. 1100 13
14. 1101 14
15. 1110 15
16. 1111 16
If the various BI groups designate target setting group randomly, and the
user-defined logic of engineering research and development is realized,
299
then write the target setting group to **::ChangeSetGrp.InSettingZone. IED

provides up to 32 setting groups.
Figure 118 Diagram of binary input switch setting group configuration
2.6.2 Setting list

Table 231 Logic switch of binary input switching setting group diagram
Logic switch Set Default
mark mode value
1 BISetGrp BISwitchSetGrp 1/0 0
2.7 Configuration startup

The function configuration of IO Matrix offers a settable startup trip to
decide whether the protection trip of IED should be blocked by starting.
Taking the overcurrent stage 1 as an example, the diagram is shown
below:
Figure 119 Diagram of initiated blocking configuration

Protection trip of overcurrent stage 1 is configured via startup relay
blocking:
The corresponding Start of OC1 is the startup trip of overcurrent stage 1,

which is connected with the node PickupContact of startup relay, and the
output of BIO module is set as initiation by jumper.
300
Figure 120 Diagram of non-initiating blocking configuration

Protection trip of overcurrent stage 1 is configured without startup relay
blocking:
The corresponding Start of OC1 is not connected with the node
PickupContact of startup relay, and the output of BIO module is set as
non-initiation by jumper.
If the protection trip of overcurrent stage 1 doesn't connect with the node
PickupContact of startup relay, but the output of BIO module is set as
initiated by jumper, then the output of overcurrent stage 1 will be blocked.
2.8 Other configuration

The name of the device can be changed according to the requirements of
the project, and it can be named in accordance with the project schedule,
so as to facilitate the maintenance of the project.
The default length of waveform recording file generated by IED is 2.5
cycles before fault and 20 cycles before and after the fault together. It
supports to instantiate RS_WAVEPARAM by AESP tool and the users can
define the length of waveform records according to their needs. The length
of single waveform record cannot be longer than 200ms before fault, the
total length of waveform records cannot be longer than 20s. Single
waveform record cannot be greater than 512k.
301
Figure 121 DFR parameter configuration figure
2.9 Defined logic

The AESP tool provides the basic components of the module to support
user-defined simple engineering logic. The intermediate data and the
intermediate nodes in the application software which is open to the user
can be used conveniently in the configuration interface, and the logical
application of the project is realized.
Figure 122 AESPStudio working interface
2.10 Connector attribute change

The connector attribute is soft-hard parallel by default. The user can
change the connector attributes as soft connector, hard connector,
soft-hard connector series connection and soft-hard connector parallel
connection in the classified configuration / protection connector state as
required.
302
Figure 123 Example of connector attribute change
303
Chapter 32 Control function
About this chapter

This chapter describes the control functions, including the
isolator telecontrol, direct control and tap control functions.
The required control functions can be configured according to
the requirements of the project.
305
1 CB/Isolator control
1.1 Introduction
The CB/Isolator control function is used to control the opening and closing
operation of the circuit breaker or the isolator or the earthswitch, and the
control objects can be added according to the different bay requirement.
1.2 Function module description

Input and output signals of isolator telecontrol function are shown as
follow:
CB/Isolator Control
1 1
OpenPermit OpenBO
2 2
ClosePermit CloseBO
3
BIState
Figure 124 The diagram of input and output signals of CB/Isolator control function
right.
Input:
OpenPermit Open permission of object
ClosePermit Close permission of object
CB/Isolator Control BIState Binary input state of double position
Output:
OpenBO Open command
CloseBO Close command
1.3 Detailed description

Object pre-selection operation is required before executing the SBO
(Select before operation) command.
The Object is blocked by the remote/local state. When the device is in the
remote state, it is only remotely controllable; when the device is in the local
state, it is only locally controllable.
The opening of object permission and closing of object permission can be
connected to the interlock signal or the permission logic of user-defined
opening/closing object.
The object can be configured for position check. When using the check
function, the input state of dual position needs to be connected to the
function block. If the check is not selected, it can provide open and close
command without the position check.
When using position check, if the input position state match with control
command being sended, IED will return success, if not return fail after 30s.
306
2 Direct control
2.1 Introduction
Direct control can be used for directly controlled objects, such as
intermediate relay reset or any free output command without pre-selection.
2.2 Function module description

Input and output signals of direct control function are shown as follows:
Direct Control
1
OpenBO
2
CloseBO
Figure 125 The diagram of input and output signals of direct control function
right.
Output:
Direct Control OpenBO Open command
CloseBO Close command

The direct control does not require a pre-selection and is directly execute
operation.
The direct control is blocked by the remote/local state. When the device is
in the remote state, it is only remotely controllable; when the device is in
the local state, it is only locally controllable.
3 Tap control
3.1 Overview
The tap control is used to control the tap position of the transformer to
perform the operation of rise, low and stop.
3.2 Description of function module

Input and output signals of direct control function are shown as follows:
307
Tap Control
1 1
Permit TapUpBO
2 2
ATap TapDnBO
3 3
BTap TapStopBO
4
CTap
Figure 126 Input and output signal diagram of tap control

right.

Input:
Permit Allowable voltage adjustment
ATap Phase A gear
BTap Phase B gear
Tap Control CTap Phase C gear
Output:
TapUpBO Tap rise

TapDnBO Tap low
TapStopBO Tap stop

The direct control is blocked by the remote/local state. When the device is
in the remote state, it is only remotely controllable; when the device is in
the local state, it is only locally controllable.
4 Report list
Operation report:
1. TelectrlObject /
2. TelectrlCmdSrc /
3. TelectrlResult /
4. TelectrlCmd /
5. TelectrlType /
6. FailReason /
308
Chapter 33 Substation communication
Chapter 33 Substation
communication
About this chapter

This chapter describes functions such as substation
communication and protocol, clock synchronization and so
on.
309
1 Overview
Each IED provides communication port to communicate with one or more
substation system. IED supports following communication protocols:
1) IEC 61850-8-1 communication protocol
2) IEC 60870-5-103 communication protocol
3) DNP 3.0
4) MODBUS
2 Communication protocol
2.1 IEC 61850-8-1 communication protocol
Protocol IEC61850-8 allows two or more IED in one or more factories to
communicate and cooperate on the basis of their functions.
Standard IEC 61850-8-1 rules GOOSE (generic object of substation event).
By publishing and subscribing mechanism, GOOSE standardizes
communication state and control information between IEDs. That is to say,
if event is tested to happen, IED shall send information to devices which
have subscribed the event by multi cast.
2.2 IEC 60870-5-103 communication protocol

IEC 60870-5-103 is master-slave type protocol and communicate with
control system through serial port. According to IEC rules, main station is
the master and substation is the slave. Communication is carried out on
the basis of point-to-point principle. Main station should be equipped with
the software that is able to receive IEC 60870-5-103 communication report.
For a more comprehensive understanding of the IEC60870-5-103 protocol,
you can refer to the fifth part of "IEC60870 standard": 103 section of
"communication protocol": "the standard of information communication
interface for IED protection"
3 Communication port
3.1 Front plate communication port
Front plates of all IEDs have a RJ45 communication port respectively. By
this port, users can use PC to operate Sifang debug software to connect
IED for setting, testing, configuring and so on.
3.2 RS485 communication port

IED provides an independent electric RS485 communication port
connecting to automatic system for substation. The port supports protocol
IEC60870-5-103 and other ports could be used for clock synchronization.
3.3 Ethernet communication port

IED provides three electric or two optical Ethernet ports to connect to
substation's automatic system, in which two of them can support the same
protocol at the same time, IEC61850 or IEC60870-5-103.
310
4 Technical parameter
Table 236 Front plate communication port
Items Data
No. 1
Connection mode Debugging RJ45 port for software
Communication rate 100Mbit/s
Table 237 RS485 communication port

Items Data
No. 1
By two conductors
Connection mode
Communication port of rear plate
Maximum communication distance 1.0 km
Test voltage 500V AC earthing
Support protocol IEC 60870-5-103
Parameter is set as 9600 baud,
Communication rate Minimum 1200 baud rate, maximum 19200
baud rate
Table 238 Ethernet communication port
Items Data
Ethernet communication port
No. Three RJ45 or two optical ports
Cable or optical fibers/backboard
Connection mode
communication port
Maximum communication distance 100m
Support IEC 61850 protocol
Support protocol IEC 60870-5-103
Table 239 Time synchronization port
Items Data
Time synchronization mode Pulse or optical signal time synchronization
IRIG-B signal format IRIG-B000
Connected by two conductors or optical fibers
Connection mode
Communication port of rear plate
Volt level Differential signal
311
5 Typical substation communication

mode
Through communication protocols supported by communication port, IED
is able to communicate with one or more substation system or device.
Server or Server or
Work Station 1 Work Station 2
Switch
Work Station 3
Net 1: IEC61850/IEC103,Ethernet Port A
Switch Net 2: IEC61850/IEC103,Ethernet Port B Switch

Switch
Gateway Switch
or
converter
Net 3: IEC103, RS485 Port A
Figure 127 Multiple network substation automatic system connection case
6 Typical clock synchronization mode

All IEDs provide a clock synchronization port ( as fiure bellow shows), it is
able to choose IRIG-B code or pulse time synchronization. For pulse time
synchronization, IED can automatically adapt to second or minute pulse
time synchronization mode. Meanwhile IED could adopt SNTP mode to
synchronize.
SNTP IRIG-B Pulse
Ethernet port IRIG-B port Binary input
Figure 128 Clock synchronization mode
312
Chapter 34 Man-machine interface (MMI) and operation
Chapter 34 Man-machine interface

(MMI) and operation
About this chapter

This chapter describes the relative display of man-machine
interface and its operation.
313
1 Overview
The MMI is composed of liquid crystal display (LCD), LED, panel buttons
and panel Ethernet port. Users can view information, set parameters and
debug through MMI.
2 Function description
2.1 Liquid crystal display(LCD)
The LCD back light of HMI is blue, 9 lines can be displayed. When
operating Sifang key or IED issuing alarm or trip report, background blue
light automatically lights up. Soon after the latest trip or alarm, background
blue light dies out after 5 minutes of time setting.
2.2 Man-machine interface (MMI)

MMI is man-machine interface. LCD screen displays the device running
information, such as measured value for current and voltage, connector
state and BI, BO and bay signal line diagram.
If there is no key operation, the MMI main cycle interface shows part of
device information. User could press “ESC” to lock current display, and
press “ESC” again to restore circulation display.
Take the multifunction device of half length as an example. The description
of faceplate area is as follows: zone one is for the user-defined indicator
area; zone two is for the key area of the control function; zone three is for
the debugging of net port; zone four is for the key district of the basic key.
CSC-326
Figure 129 CSC-326-EB MMI schematic diagram
314
Figure 130 CSC-326-EBL MMI schematic diagram

The user-defined indicator area consists of 24 lights, where the position of
running lights and alarm light are fixed, and the functions of other 22 lamps
can carry out the configuration of light color, light property according to the
needs of the user ; in key areas, there is indicator indicating device state
on each of the remote, local and blocking key respectively.
RUN: When running lights, the green light is lightened during the normal
operation, while the running light is off if there is an alarm of class 1.
ALARM: alarm indicator, the device alarm lightens the red light.
The faceplate uses the Ethernet port to connect PC and device, which
supports setting device parameter, measuring function, downloading
programs and analyzing data. The debugging IP address of Ethernet port
is 192.178.111.31 for CSC-326-EB and 192.178.111.221 for
CSC-326-EBL, which is unchangeable.
The key includes basic key and control functional key. Basic key is on the
right of the screen and control functional key is below the screen to realize
human-computer interaction. Keys for IED of CSC series contain the same
appearance and operation mode, for details in below table.
Table 240 IED MMI Key
Key Function
Move to the next line in menu
Move to the next line in menu
Move left in the menu
315
Key Function
Move right in the menu
 Reseting LED light

 Directly back to normal circulation display interface
 Entering main menu or sub-menu

 Affirming revised setting
 Back to previous menu

 Exit revising setting
 Back to circulation display interface
 Blocking or unlocking circulation display interface (when
blocking, top right corner of LCD displays an icon of a
small key)
 Value adds 1
+ 

Page down
Logic switch shift from the present value to the opposite
value; namely "1" to "0", or "0" to "1"
 Value minus 1
- 

Page up
Logic switch shift from the present value to the opposite
value; namely "1" to "0", or "0" to "1"
F1
F2  User-defined function key

 The shortcuts for menu options are able to set to relate
with menu items to execute functions of this menu.
F3  as the input signal to participate in logic
F4
 Switching to remote operation mode, and earthing control
F2
shall be blocked.
 Switching to earthing control mode, remote operation shall
be blocked.
 It is used for locking and unlocking control key and
user-defined key so as to prevent mistakenly touching.
 Breaker closes
 Breaker opens
2.3 Menu structure

Click the key MMI to enter the IED menu, and view information or take
some related operations. Due to the differences in the function of various
316
type of IED,language settings, the following lists show the maximum menu
configuration; the value and language of related setting information and
various type of IED is on the basis of actual display.
Table 241 IED menu
L1 menu L2 menu L3 menu L4 menu Description

Read the measure
PriVal input primary-value
of the IED
Calc
Read the measure
SecVal input second-value
of the IED
Read the measure
PriVal input primary-value
of the IED
Measure
Read the measure
SecVal input second-value
of the IED
Read the analog
Analog
input of the IED
Read the power
PowerMetr
metering of the IED
Read the binary
ConventionalBI
IEDState input of the IED
Read the original
BIO GOOriginBI binary input state of
GOOSE
Read the binary
ConventionalBO
output of the IED
Read state
information of
GOOSESubState
GOOSE
ViewInfo
GOState subscription
Read state
GOOSEPubState information of
GOOSE publishing
Read state
StateMon information of the
IED
Read the current
AlarmInfo
alarm information
Read the IED
ProtSet
setting
Read the calculation
CalcSet
setting
ViewSet Read the equipment
EquipParm
parameters
Read the
BCUParm measurement and
control parameters
Read the function
FunctionCon connector
information
Read connector
ConState
GOOSEPubCon state information of
GOOSE publishing
Read connector
GOOSESubSoftCon
state information of
317

GOOSE
subscription
Read the unique
IED IDCode
code of IED
Read the version
VerInfo IEDVer
information of IED
Read the VT check
VrtlTrmlChkCode
code
Read the
SyncMode synchronization
IEDSet mode of IED
Read the Ethernet
CommParm EthernetSet
information of IED
Set function
FunctionCon
connector state
Set state
GOOSEPubCon information of
ConOn/Off GOOSE publishing
Set state
information of
GOOSESubSoftCon
GOOSE
Operate subscription
Switch current
SwitchSetGrp operation setting
area
Switch remote/local
LocalCtrl
control mode
Bay single line
Bay0
SLDCtrl diagram control
…
Read the general
GenlRpt
repotr
Read the startup
StartupRpt
report
TripRpt Read the trip Report
Read the alarm
AlarmRpt
report
ViewRpt Read the operation
OperationRpt
report
Read the BI change
BIChangeRpt
report
Startup waveform
StartupDFRList
record shown in list
Trip waveform
TripDFRList
record shown in list
ProtSet ProtSet Setting the ProtSet
Copy setting of
GrpCopy
setting zone
Set substation
name, adopt
WriteSet SubstationName Unicode with a
maximum input of
EquipParm
24 characters
Set the protected
ProtEquipName equipment name,
adopt Unicode with
318

a maximum input of
24 characters
Set equipment
EquipParm
parameters
Set measurement
BCUParm and control
parameters
Test the BO
ConventionalBO
BOTest contacts
GOOSE BO TestGOOSEsignal
FnAlarmChk
TripRepChk
GOAlarmChk
BIChk Test communication
CommChk
MSTAlarmChk signal
ConChk
AnalogChk
MeasureChk
TestMenu
LEDTest TestLEDlight
Manual triggering to
MC DFR generate fault and
disturbance record
ViewZeroDrift
ViewScale
AdjZeroDrift
FactoryTest AdjScale
AngleCorrection
SystemSet
IntrSet
ProtSet
SoftConn
Analog
SampleVal
IEDState BIO
ConnState
Print VerInfo
StartupRpt
TripRpt
AlarmRpt
IEDSet Rpt
OperRpt
BIChgRpt
SetClock Set time

Choose
SyncMode synchronization
mode
TimeSet NetTimeSyncIPSet Set SNTP
address
Set the local time
TimeZone
zone
DST Mode1 Set daylight saving
319

Mode2 time
Set the Ethernet
EthernetSet
information of IED
IEDAddr Set IED address
Serial1Set
Set serial port
SerialSet Serial2Set
parameters
Serial3Set
CommParm Set the protocol
ProtocolSet
information
PRPSet Set PRP information
IEDName Set IED Name,

adopt Unicode with
a maximum input of
24 characters
Password Set IED password
Contrast Set the contrast
Set the mode that
OtherSet sending
DisplayMode
primary-secondary
value to SCADA
Set the power
PowerMetrZeroing
metering as 0
CHN Confirm
Language ENG Confirm Switch language
RUS Confirm
Fre Confirm
Click the key in the recycle main interface, the menu tree will be shown
in the MMI interface; click the key or to select menu items, when the
cursor stays in the corresponding menu item, if there is a symbol ""
behind this menu item, it can click the key or to enter the next menu; if
there is no signal "", it can click the key to enter the menu items.
SIFANG 2017-10-01 21:30:15
IEDState  Calc  ConventionalBI

GOOriginBI
ViewSet  Measure 
ConventionalBO
ConState  Analog
VerInfo  PowerMetr

GOOSEState
BIO
ViewInfo  IEDSet 
StateMon
Operate  ChanInfo
ViewRpt  AlarmInfo
WriteSet 
TestMenu
IEDSet 
Language 
PresentSetGrpNo.:
Figure 131 Menu tree diagram

The following diagram is an example of "ConventionalBO" menu.
320
BO 1/2
IEDFaultAlarm 0
RunningErrorAlarm 0
X9_BO3 0
X9_BO4 0
X8_BO1 0
X8_BO2 0
X8_BO3 0
X8_BO4 0
X8_BO5 0
Figure 132 Menu diagram
321
Chapter 35 IED hardware
About this chapter

This chapter describes hardware for device.
323
1 Overview
1.1 IED structure
1.1.1 4U, 19 inch device
2
Height for IED crate is 4U and width is 19 2 inches. The whole is for
embedded installation with back-wiring mode.
Figure 133 CSC-326-EB Installation size diagram (unit mm)

1) The front panel of IED is aluminum alloy by founding in integer and
overturn downwards. LCD, LED and setting keys are mounted on the
plate. There is a RJ45 interface on faceplate supporting PC
connection.
2) Back plug mode, module is fixed by screw spike.
3) Module is connected through bus of rear plate.
324
1.1.2 4U, 19inch device

Height for IED crate is 4U and width is 19 inches. The whole is for
embedded installation with back-wiring mode.
482.6 465.1±0.2
465.1 +0.3
450 0
4-?
6.5
+0.3
101.6
101.6
178 0
177
447.1
426.7
263
281.4
236.5
Figure 134 CSC-326-EBL Installation size diagram (unit mm)

1) The front panel of IED is aluminum alloy by founding in integer and
overturn downwards. LCD, LED and setting keys are mounted on the
plate. There is a RJ45 interface on faceplate supporting PC
connection.
2) Back plug mode, module is fixed by screw spike.
3) Module is connected through bus of rear plate.
325
1.2 Module arrangement diagram

1.2.1 4U, 19 inch device
2
Figure 135 CSC-326-EB IED rear plate module layout diagram
1.2.2 4U, 19inch device
Figure 136 CSC-326-EBL IED rear plate module layout diagram
2 Analog input module

2.1 Overview
AC module contains voltage and current transformers. The module
converts two-side current and voltage to processable signal for IED data
collecting system and serves as electrical isolation. IED in different type
shall be with different current and voltage transformers. The module is
optional according to different project requirements.
326
2.2 Analog input module introduction

The following figure shows an AC module terminal diagram, the module
supports the access of 6 channels of protective current and 3 channels of
voltage.
The 6 channels of protection current channelsI1a、I1b、I1c、I2a、I2b
and I2c support 1A or rated 5A current access, and each current channel
provides 3 wiring terminals. The terminal identification without ' suffix is
shared inlet positive terminal, while that with' suffix is the outlet negative
terminal. For example, the use of rated 1A of I1a should access the current
from the Ia terminal to the I1a_1’ terminal and Ia_5 ' terminal is suspended;
the use of rated 5A should access the current from the Ia terminal to Ia_5'
and Ia_1' terminal is suspended; the wiring principle of other protection
type of current channels is same.
Ua, Ub, Uc in the following figure are voltage channels, and the terminal
identification without ' suffix is shared inlet positive terminal, while that with'
suffix is the outlet negative terminal.
AC
b a
1 I1a_1' I1a
2 I1b_5' I1a_5'
3 I1b_1' I1b
4 I1c_1' I1c
5 I2a_5' I1c_5'
6 I2a_1' I2a
7 I2b_1' I2b
8 I2c_5' I2b_5'
9 I2c_1' I2c
10 Ua' Ua
11 Ub' Ub
12 Uc' Uc
Figure 137 AC module terminal diagram

Table 242 Current transformer parameters
Items Executive standard Data
Rated current IEC 60255-1 1A or 5A
Protection CT is 0.05 In to
Sampling range for nominal current
40 In, while measurement
transformer
CT is 0.05 In to 1.2 In.
327

Sampling range for high sensitive
0.005 to 1.2A
current transformer
When In=1A,≤0.2VA;
Power consumption (per phase)
When In=5A,≤0.5VA
Thermal overload capacity of nominal IEC 60255-1 100In overload 1s
current transformer IEC 60255-27 Continuous 4 In
Thermal overload capacity for high IEC 60255-27 100A overload 1s
sensitive current transformer DL/T 478-2013 3A continuous
Table 243 Voltage transformer parameter

Rated voltage Vr (line voltage) IEC 60255-1 100V/110V
Sampling range (phase-to-earth voltage) 0.4V~180V
IEC 60255-27
Power consumption (Vr = 110V) ≤ 0.1VA each phase
DL/T 478-2013
Thermal overload capacity (phase-to-earth IEC 60255-27 400V, overload 60s

voltage) DL/T 478-2013 200V, continuous
3 BI modules
3.1 Introduction
The binary input hardware of BI module includes two types of soldering: 1)
Strong power level, self-adapting 110V, 220V, 125V, 250V and 2) low
power voltage level, adaptive 24V and 48V. Work rated power source of
device BI is modified by configuration file before applying.
3.2 BI Module description

There are three indicator lights on the BI faceplate to show the status of
the board, the indicator light definition is shown in the following table.
Table 244 Definition of BI module indicator light
The serial number Introduction of indicator light
Indicator light function
of indicator light state
Light is on when device is
1 Power supply light
energized
2 Running light Flash when work properly
3 Spare Off
Due to the different location of the slot, the BI module can be set at different
address of module, and the address is set through the jumper J2. Take the
side away from single board as L side, the side near single board as H side,
from bottom to top are AD0, AD1, AD2 and AD3.
328
Table 245 BI module address definition

Slot
Jumper Control content Jumper settings
location
AD3~AD0 are short connected
BI1 J2 BI1 address
to the L side
28 binary inputs are divided into 4 groups, common terminal of all groups
are independent from each other.
BI
1 2 3 LED
c a
2 BI14 BI1
4 BI15 BI2
6 BI16 BI3
8 BI17 BI4
10 BI18 BI5
BINARY INPUT
12 BI19 BI6
14 BI20 BI7
16 BI21 BI8
18 BI22 BI9
20 BI23 BI10
22 BI24 BI11
24 BI25 BI12
26 BI26 BI13
28 COM2 COM1
30 BI28 BI27
32 COM4 COM3
Figure 138 BI module terminal diagram

Table 246 BI parameter
Implementation
Items Data
standards
110V/125V/220V/250V DC
Rated voltage IEC 60255-1
24V/48V DC
Startup voltage IEC 60255-1 70%Ur, rated DC 24V/48V, 110V/125V/220V/250V;
Return voltage IEC 60255-1 55%Ur, rated DC 24V/48V, 110V/125V/220V/250V;
The maximum 286V, rated DC voltage 110V/125V/220V/250V;
IEC 60255-1
BI voltage 62V, rated DC voltage 24V/48V;
Power Maximum 0.5W/input, 110V DC
IEC 60255-1
consumption Maximum 1W/input, 220V DC
329
4 BO modules
4.1 Introduction
Module provides certain of protection tripping and closing circuit breaker
control and realizes telecontrol opening or closing of isolator. Some
channels could be switched to normally open or closed contact.
4.2 BO Module description

There are three indicator lights on the BO faceplate to show the status of the
board, the indicator light definition is shown in the following table.
Table 247 Definition of BO module indicator light
The serial
Introduction of
number of Indicator light function
indicator light state
indicator light
Light is on when device
1 Power supply light
is energized
Flash when work
2 Running light
properly
3 Spare Off
Due to the different location of the slot, the BO module can be set at different
address of module, and the address is set through the jumper J2. Take the
side away from single board as L side, the side near single board as H side,
from bottom to top are AD0, AD1, AD2 and AD3.
Table 248 BO module address definition
Slot
location
J7 BO1 Address AD3~AD1 are short connected to the L side, AD0
BO1
is short connected to the H side
BO2 BO2 Address AD3, AD2, AD0 are short connected to the L side,
J7
AD1 is short connected to the H side
BO3 BO3 Address AD3 and AD2 are short circuited to L side, AD1
J7
and AD0 are short circuited to H side
Each binary input and output board has 16 binary outputs. 16 binary
outputs are divided into 5 groups, each group can be set as startup
blocking or not startup blocking by changing the jumper position, there are
total four groups of jumpers J1~J5. The jumper inserting into 1, 2 pin
represents that binary output is blocked by startup relay, inserting into 2, 3
pin represents that binary output is unblocked by startup relay.
Table 249 BO module address definition
The definition of
address jumper of
Binary output 1 and 2 pin 2 and 3 pin
binary input and
output module
J1 BO1~ BO3 Startup blocking Not startup blocking
BO16 can switch to normally open or normally closed contacts. J30 is normally open
when trip to A, and normally closed when trip to B.
330
BO
1 2 3 LED
c a
2 BO1
4 BO2
6 BO3
8 BO4
10 BO5
BINARY OUTPUT
12 BO6
14 BO7
16 BO8
18 BO9
20 BO10
22 BO11
24 BO12
26 BO13
28 BO14
30 BO15
32 BO16
Figure 139 BO module terminal diagram

Table 250 BO parameter
Items Implementation Data
standards
Maximum work voltage IEC60255-1 250V AC
Impact overcurrent capacity IEC60255-1 5A continuous,
30A, 200ms ON, 15s OFF
Closing capacity IEC60255-1 1100 W( ) inductive load L/R >40ms
1000VA (AC)
Arc breaking capacity IEC60255-1 220V , 0.15A, L/R ≤40ms
110V , 0.30A, L/R ≤40ms
Electrical life IEC60255-1 50,000,000 times (switching frequency is
3HZ)
Opening times IEC60255-1 ≥1000
Closing times IEC60255-1 ≥1000

Authentication IEC60255-1 UL/CSA, TŰV
IEC60255-23
IEC61810-1
Contact circuit resistance IEC60255-1 30mΩ
IEC60255-23
IEC61810-1
Contact insulation test (AC IEC60255-1 AC1000V 1min
dielectric strength ) IEC60255-27
Maximum temperature
IEC60255-1 55℃
operation allows
331
5 BIO module
5.1 Overview
BIO module provides a certain of protection tripping and closing control so
as to realize telecontrol switching of the switch and isolator.
The BIO hardware of BI module includes two types of welding : 1) high
power voltage level, adaptive 110V, 220V, 125V, 250V and 2) low power
voltage level, adaptive 24V and 48V. Work rated power source of device
BI is modified by configuration file before applying.
5.2 BIO module introduction

There are three indication lights on the BIO panel to show the status of the
board, the indication light definition is shown in the following.
Table 251 Definition of BIO module indicator
Serial
number of
Indicator function Indicator state introduction
indicator
light
1 Power supply light Light is on when power on
2 Running light Flash when operating properly
3 Spare Off
Due to the different location of the slot, the BIO module can be set at
different address of board cards, and the address is set through the jumper
J6. Take the side away from single board as L side, the side near single
board as H side, from bottom to top is AD0, AD1, AD2, AD3.
Table 252 Definition of BIO module address
Slot
location
BIO1 J6 BIO1 address AD3~AD0 are short connected to the L side
AD3 and AD1 are short connected to the L
BIO2 J6 BIO2 address
side, AD0 is short connected to the H side
AD3, AD2, AD0 are short connected to the L
BIO3 J6 BIO3 address
side, AD1 is short connected to the H side
AD3, AD2 are short connected to the L side,
BIO4 J6 BIO4 address AD1 and AD0 are short connected to the H
side
Each BIO board has 6 BI and 12 BO. 6 BI are divided into 2 groups, and
each of 3 BI shares a common terminal.
12 BO are divided into 4 groups, and each group can be set as whether
through the starting through jumper, with total four groups of jumpers
J11~J14. The jumper inserting into 1, 2 pin represents through starting
relay outlet, inserting into 2, 3 pin represents not through starting relay
outlet.
Table 253 Description 1 for jumper of BIO module
BIO module address definition jumper Binary output 1 and 2 pin 2 and 3 pin
J11 BO1~ BO3 Start Without start
332
BO12 can switch normally open or normally closed node by JP1 jumper ,
that is, jumper jumping to the NC side is the normally closed node, while
jumper jumping to the NO side is the normally open node.
Table 254 Description 2 for jumper of BIO module
Jumper Binary output NC NO
JP1 BO12 Normally closed node Normally open node
BIO
1 2 3
c a
2 BO1
4 BO2
6 BO3
BINARY OUTPUT
8 BO4
10 BO5
12 BO6
14 BO7
16 BO8
18 BO9
20 BO10
22 BO11
24 BO12
26 BI4 BI1
BINARY INPUT
28 BI5 BI2
30 BI6 BI3
32 COM2 COM1
Figure 140 BIO module terminal diagram

Table 255 BI parameter
Executi
Items Data
ve standard
110V/125V/220V/250V DC
Rated voltage IEC 60255-1
24V/48V DC
70%Ur, rated DC 24V/48V,
Startup voltage IEC 60255-1
110V/125V/220V/250V
55%Ur, rated DC 24V/48V,
Return voltage IEC 60255-1
110V/125V/220V/250V
286V, rated DC voltage 110V/125V/220V
The maximum BI voltage IEC 60255-1 /250V;
62V, rated DC voltage 24V/48V;
Maximum 0.5W/ input, 110V DC
Power consumption IEC 60255-1
Maximum 1W/ input, 220V DC
333
Maximum work voltage IEC 60255-1 250V current
5A continuous,
Current carrying capacity IEC 60255-1
30A, 200ms On, 15s Off
1100W(DC) at inductive load L/R>40ms

Closing capacity IEC 60255-1
1000VA(AC)
220V(DC), 0.15A, L/R≤40ms

Arc breaking capacity IEC 60255-1
110V(AC),0.30A, L/R≤40ms
50,000,000 times (switching frequency is

Mechanical endurance IEC 60255-1
3HZ)
Opening times IEC 60255-1 ≥1000
Closing times IEC 60255-1 ≥1000
IEC 60255-1
Authentication IEC 60255-23 UL/CSA, TŰV
IEC 61810-1
IEC 60255-1
Contact circuit resistance IEC 60255-23 30mΩ
IEC 61810-1
Contact insulation test IEC 60255-1
AC1000V 1min
(AC dielectric strength ) IEC 60255-27
Maximum temperature
IEC 60255-1 55℃
that operation allows
6 CPU module
6.1 Overview
CPU module is the core of the IED and responsible for running all
protection logic to carry out the hardware self-check and communication
with external devices such as MMI, PC, measurement, substation
automatic system, working station, RTU, printers and so on. Besides, CPU
module sends telemetry, telesignalisation, SOE, event report and recorded
wave to backstage, it provides time synchronization and communication
port.
CPU module provides multiple configuration for user's need. Differences
lie in quantities for Ethernet port, optical/electric port, time synchronization
mode, storage capacity and so on.
6.2 CPU module terminal diagram

The CPU module panel has six indicators to indicate the operation status
334
of the board and the definition of indicator is shown as below table.

Table 257 Definition of indicator of CPU module
No. of indicator
light
Indicator 1 of Ethernet Flash when communicating normally while
1
Plate close when communicating abnormally
2
3
Flash when operating normally while close
4 Running light of core 1
when operating abnormally
CPU
1 2 3
4 5 6
ETH1
ETH2
ETH3
1
RS485-1A/PULSE-
2
RS485-1B/PULSE+
RS485-1GND 3
4
RS485-2A 5
RS485-2B 6
RS485-2GND 7
8
RS232-TXD 9
RS232-RXD 10
RS232-GND 11
Figure 141 CSC-326-EB CPU module terminal diagram

CSC-326-EB CPU supports serial port 1 and time synchronization
multiplex hardware ports. The functions are switched by software. When
used as time synchronization port, the protocol of serial port 1 needs to be
set to none.
Table 258 Definition of CSC-326-EB CPU module in serial communication terminal
Terminal Definition Remark
01 485-1A Serial port 1
02 485-1B
03 485-1GND
04
335
Terminal Definition Remark

05 485-2A Serial port 2
06 485-2B
07 485-2GND
08
09 RS232-TXD Serial port 3
10 RS232-RXD
11 RS232-GND
Table 259 CSC-326-EB ethernet port configuration
Number Configuration
1 RJ45 electrical port+RJ45 electrical port+RJ45

electrical port
2 Light port+light port+RJ45 electrical port
X0 CPU X2 CPU
1 2 3
1 2 3 4 5 6 LED
4 5 6 LED
ETH1
ETH2
ETH3
1 1 RS485-1A
RS485-1A/PULSE-
RS485-1B/PULSE+ 2 RS485-1B
2
RS485-1GND 3 RS485-1GND
3
4 4
5 5 RS485-2A
6 6 RS485-2B
7 7 RS485-2GND
8 8
9 9 RS232-TXD
10 10 RS232-RXD
11 11 RS232-GND
Figure 142 CSC-326-EBL CPU module terminal diagram

The first three serial ports of CPU1 module in CSC-326-EBL device is the
time synchronization port.
Table 260 Definition of CPU1 of CSC-326-EBL module in serial communication terminal
Module Definition
01 RS485-1A/PULSE-
02 RS485-1B/PULSE+
03 RS485-1GND
04 \
336
Module Definition
05 \
06 \
07 \
08 \
09 \
10 \
11 \
Table 261 Definition of CPU2 of CSC-326-EBL module in serial communication terminal
Module Definition Remark
01 485-1A Serial port1
02 485-1B
03 485-1GND
04
05 485-2A Serial port2
06 485-2B
07 485-2GND
08
09 RS232-TXD Serial port 3
10 RS232-RXD
11 RS232-GND
Table 262 CSC-326-EBL Ethernet port
Number Configuration
1 RJ45 electrical port+RJ45 electrical port+RJ45
electrical port
2 Optical port+Optical port+RJ45 electrical port

Table 263 RS485 communication port
Items Data
Number 2
Lead by double wires, on the CPU module
Port type
bottom plate
Maximum transmission distance 1.0km
Test voltage 500V earthing AC voltage
Used for IEC 60870-5-103 protocol
Default setting 9600bps
Transmission rate
Minimum: 1200bps; maximum: 19200bps
Table 264 Ethernet communication port
Items Data
Ethernet port
Number 3
RJ45 or optical Ethernet port, on the CPU
Port type
module bottom plate
337
Items Data
Maximum transmission distance 100m
Used for IEC 61850 protocol
Transmission rate 100Mbit/s
Support TCP103 Protocol
Transmission rate 100Mbit/s
Table 265 Time synchronization
Items Data
Synchronization mode IRIG-B time synchronization
IRIG-B signal format IRIG-B000
Double wire conductor or optical fibers
Port type
connector, on the CPU module bottom plate
Voltage level Differential signal input
7 Power supply module

7.1 Overview
The input of the power supply module is the working voltage of the device,
and the output is the working voltage of the other boards of the device. The
input and output circuits of the power supply module are not common,
which plays the electric isolation role. In order to improve anti-interference
ability for power supply module circuit, the power supply module is
equipped with anti-interference filter inside the device. What's more, the
module is equipped with sophisticated power protection function
(undervoltage, overvoltage, overcurrent, overpower, etc.) to prevent IED
breakdown from power supply module failure. Power supply module
provides 11 channels BI and 4 channels relay BO, and provides reliable
electric isolation.
7.2 Power supply module terminals diagram

There is a power indicator on the power supply module panel to indicate
the status of the board, which is light during normal operation.
BI 10 on the power supply module is defined fixedly as “IEDRst”, BI 1 is
defined fixedly as "IEDFaultAlarm", and BO 2 is defined fixedly as
"RunErrAlarm". Other BI and BO can be user-defined according to
different functional requirements by the user. Each channel has two sets of
nodes, respectively, corresponding to BO common terminal 1 and BI
common terminal 2, and BO relays are all unlatched type.
Note: BO 3 and BO 4 are fixed without starting relay exit.
338
POWER
PWR
c a
2 BI7 BI1
4 BI8 BI2
BINARY INPUT
6 BI9 BI3
8 RELAY RESET BI4
10 BI11 BI5
12 BICOM BI6
14 COM2 COM1
SIGNAL CONTACT
16 FAIL 1 FAIL 2
18 ALARM 1 ALARM 2
20 BO3-1 BO3-2
22 BO4-1 BO4-2
24 IN+
POWER INPUT
26
28 IN-
30
32
Figure 143 Power module terminal diagram

Table 266 The definition of power supply module terminals
Number c a
2 Binary input 7 BI1
4 Binary input 8 Binary input 2
8 Device reset Binary input 4
12 BI common terminal Binary input 6
14 BO common port 1 BO common port 2
16 IED fault alarm 1 IED fault alarm2
18 Abnormal operation alarm 1 Abnormal operation alarm 2
20 BO3-1 BO3-2
22 BO4-1 BO4-2
24 Power supply positive Power supply positive
26 Undefined Undefined
28 Negative power supply Negative power supply
30 Undefined Undefined
32 Grounding Grounding

Table 267 Technical parameter
Item number Executive standard Data
Rated voltage Uaux IEC 60255-1 110 to 250V
Input voltage error range IEC 60255-1 ±20%Uaux
Static power consumption IEC 60255-1 ≤ 50W for each power module
Maximum load power
IEC 60255-1 ≤ 60W for each power module
consumption
339
8 TCS Module
8.1 Overview
It shall be noticed that the facia shall be assembled and welded according
to the different rated working power, please make sure before use.
The built-in TCS function is applicable to the occasion when the trip
contacts in device are used for trip directly; generally, it is applied to the
occasion when installing protection device with medium voltage in switch
cabinet. In 80% occasions, only the trip circuit is monitored, the closing
circuit doesn't get monitored. Therefore, the device provides a module with
TCS circuit and trip relay cooperating with each other.
8.2 TCS Module instructions

TCS plate provides one tripping monitoring circuit, two large capacity BI
circuits and two pairs of relays and four outlet contacts.
Figure 144 TCS module terminal diagram

There are three indication lights on the TCS panel to show the status of the
board, the indication light definition is shown in the following.
340
Table 268 Definition of indicators of TCS module

Serial
number of
indicator
light
1 Power supply light Light is on when power on
2 Running light Flash when operating properly
3 Spare Off
1) TCS trip monitoring circuit
TCS module can monitor the open circuit of breaker the whole time,
including various operating conditions.
Figure 145 TCS circuit schematic diagram

Terminal a2, c4, a4 are connected with tripping circuit via auxiliary contact,
when failure occurs in circuit, K1 and K2 open simultaneously, and send
alarm signal; block can be realized through external circuit connection.
Figure 146 TCS circuit wiring diagram

2) Binary output circuit with large capacity
Taking the binary output circuit with large capacity PO1 as an example, the
341
schematic diagram and wiring instruction are as follows, open PO1 to drive
trip coil or closing coil.
Figure 147 Binary output circuit with large capacity schematic diagram
When the binary output current is larger than 6A, then the terminals of list
and list c need to be connected in parallel.
3) Ordinary BO circuit
Figure 148 Ordinary BO circuit schematic diagram

Table 269 Binary output instruction
Relay BO name Terminal BO type
c26～a26 Normally open

RELAY3A BO1

RELAY4A BO2
c32～a32 Always close
342

Table 270 Binary output circuit with large capacity parameters
Items Executive Data
standard
Maximum work voltage IEC 60255-1 250V AC
8A continuous,
Current carrying capacity IEC 60255-1
30A, 200ms On, 15s Off
240W (DC)
2000VA(AC)
220V(DC), 0.15A, L/R≤40ms
110V(DC), 0.30A, L/R≤40ms
Mechanical endurance IEC 60255-1 10100,000 times (resistive load)

Opening times IEC 60255-1 ≥1000
Closing times IEC 60255-1 ≥1000
IEC 60255-1
Authentication IEC 60255-23 UL/CSA, TŰV
IEC 61810-1
IEC 60255-1
IEC 61810-1
Contact insulation test (AC IEC 60255-1
AC1000V 1min
dielectric strength ) IEC 60255-27
Maximum temperature that

IEC 60255-1 55℃
operation allows
Table 271 TCS circuit (binary input) parameter

Executive
Items Data
Standards
Rated voltage IEC 60255-1 110V/220V DC
Startup voltage IEC 60255-1 70%Ur
Return voltage IEC 60255-1 55%Ur
The maximum BI 143V. rated DC voltage110V
IEC 60255-1
voltage 286V, rated DC voltage 220V
Maximum 0.5W/input, 110V DC
Power consumption IEC 60255-1
Maximum 0.5W/input, 220V DC
Standards
Maximum work voltage IEC 60255-1 250V AC
8A continuous,
Impact overcurrent capacity IEC 60255-1
30A，200ms ON，15s OFF
240W(DC) inductive load L/R>40 ms
2000 VA(AC)
220V(DC)，0.15A，L/R≤40 ms
110V(DC)，0.30A，L/R≤40 ms
Electrical life IEC 60255-1 100,000 times (resistive load)
343

Standards
Opening times IEC 60255-1 ≥1000 times
Closing times IEC 60255-1 ≥1000 times
IEC 60255-1
Authentication IEC 60255-23 UL/CSA、TŰV
IEC 61810-1
IEC 60255-1
IEC 61810-1
Contact insulation test (AC IEC 60255-1
AC1000V 1min
dielectric strength ) IEC 60255-27
Maximum temperature
IEC 60255-1 55℃
operation allows
9 Test
Table 273 Insulation test
Items Executive Standards Test method
Faceplate: IP54
IEC 60255-27
Protection level (IP) Side plate: IP52
IEC 60529
Backplate: IP 30
2KV, 50Hz (rated voltage >
63V) is tested between the
following circuits:
 Power supply
 CT / VT input
IEC 60255-5  Binary input
EN 60255-5  Binary output
Insulation withstanding ANSI C37.90 Enclosure ground 500V，50Hz
GB/T 15145-2008 (rated voltage ≤63V)
DL/T 478-2013 tested between the following
circuits:
 Communication port
 Time synchronization
port
 Case earthing
5kV (rated voltage>60V)
1kV (rated voltage≤60V)
1.2/50μs，0.5J
IEC 60255-5 tested between the following
IEC 60255-27 circuits:
EN 60255-5  Power supply
Impulse voltage
ANSI C37.90  CT / VT input
GB/T 15145-2008  Binary input
DL/T 478-2013  Binary output
 Communication port
 Time synchronization
port
 Case earthing
344

IEC 60255-5
IEC 60255-27
EN 60255-5
Insulation resistance ≥ 100MΩ，500V DC
ANSI C37.90
GB/T 15145-2008
DL/T 478-2013
Earthing resistance IEC 60255-27 ≤0.1Ω
Flame rating IEC 60255-27 Class V2
Table 274 EMC test
1MHz pulse group IEC 60255-22-1
interference test IEC 60255-26 Class III
IEC 61000-4-18 2.5kV CM；
EN 60255-22-1 1kV DM
ANSI/IEEE C37.90.1
Immunity degree of IEC 60255-22-2 Class IV
electrostatic discharge IEC 61000-4-2 ±8kV electro-contact discharge;
EN 60255-22-2 ±15kV air discharge;
Radiated electromagnetic Class IV；
field immunity IEC 60255-22-3
10V/m 、 80MHz~1GHz 、
EN 60255-22-3
1.4GHz~2.7GHz
Immunity degree of IEC 60255-22-4,
Class IV
electrical fast transient pulse IEC 61000-4-4
Communication port: 4KV；
group EN 60255-22-4
Other ports: 2KV
ANSI/IEEE C37.90.1
Surge (impact) immunity Class IV
IEC 60255-22-5
4.0kV CM；
IEC 61000-4-5
2.0kV DM
Radio frequency Frequency scanning: 150kHz–80MHz
interference test Calibration frequency: 27MHz and
IEC 60255-22-6
68MHz
IEC 61000-4-6
10V
AM，80%，1kHz
Power frequency immunity Class A
test IEC 60255-22-7 300V CM
150V DM
Power frequency magnetic Class V
field immunity test IEC 61000-4-8 100 A/m > 30s
1000 A/m，1s-3s
100KHz pulse-group noise Class III
immunity IEC 61000-4-18 Communication port: 2KV；
Other ports: 4KV
Damped oscillation Class V
IEC 61000-4-10
magnetic field immunity 100A/m
Pulse magnetic field Class V
IEC 61000-4-9
immunity test 1000A/m
Conducted emission IEC 60255-25 0.15MHz~30MHz，class A
Radiated emission IEC 60255-25 30MHz~1000MHz，class A
Table 275 Mechanical experiment
345

Sinusoidal vibration IEC 60255-21-1 Class 1
response test EN 60255-21-1
Sinusoidal vibration and IEC 60255-21-1 Class 1
endurance test EN 60255-21-1
Impact response test IEC 60255-21-2 Class 1
EN 60255-21-2
Impact and endurance test IEC 60255-21-2 Class 1
EN 60255-21-2
Collision test Class 1
IEC 60255-21-2
Seismic test IEC 60255-21-3 Class 1
Table 276 Environmental test
Items Data
High and low temperature test -40°C to +70°C
Temperature storage test -40°C to +70°C
Maximum relative humidity 95%, no
Humidity test
condensation
10 Structural design
Table 277 1Structural design
Items Data
Dimension 4U×1/2 19 inches
Weight ≤ 9kg
11 CE Certification
Table 278 CE Certification
Items Data
EN 61000-6-2 and EN 61000-6-4(EMC guide
EMC
committee 2004/108/EC)
LVD EN 60255-27(LVD 2006/95 EC)
346
Chapter 36 Appendix
Chapter 36 Appendix
347
Chapter 36 Appendix
1 IED parameter
Table 279 Logic switch pf device parameters
Number Name Range Default Unit Remark

1. BISwitchSetGrp 0/1 0
Table 280 IED parameter Setting

1. HVSideRatedCapacity 1~3000 120 MVA

2. MVSideRatedCapacity 1~3000 120 MVA
3. LVSideRatedCapacity 1~3000 120 MVA
4. HVSideConnectMode 0~1 0
5. MVSideVectorGrp 1~12 12
6. LVSideVectorGrp 1~12 11
7. HVSideRatedVolt 1~1000 150 kV
8. MVSideRatedVolt 1~1000 75 kV
9. LVSideRatedVolt 4~1000 75 kV
10. HVSideVTRatio 1~9999 150
11. MVSideVTRatio 1~9999 75
12. LVSideVTRatio 1~9999 75
13. HVSideCTPriVal 1~9999 1000 A
14. HVSideCTSecVal 1~5 1 A
15. MVSideCTPriVal 1~9999 1000 A
16. MVSideCTSecVal 1~5 1 A
17. LVSide1CTPriVal 1~9999 1000 A
18. LVSide1CTSecVal 1~5 1 A
23. HVSideExtrCT(REF)PriVal 1~9999 1000 A
24. HVSideExtrCT(REF)SecVal 1~5 1 A
25. HVSideExtrCT(Spare)PriVal 1~9999 1000 A
26. HVSideExtrCT(Spare)SecVal 1~5 1 A
27. MVSideExtrCT(REF)PriVal 1~9999 1000 A
28. MVSideExtrCT(REF)SecVal 1~5 1 A
29. MVSideExtrCT(Spare)PriVal 1~9999 1000 A
30. MVSideExtrCT(Spare)SecVal 1~5 1 A
31. LVSideExtrCT(REF)PriVal 1~9999 1000 A
32. LVSideExtrCT(REF)SecVal 1~5 1 A
348
Chapter 36 Appendix
33. LVSideExtrCT(Spare)PriVal 1~9999 1000 A

34. LVSideExtrCT(Spare)SecVal 1~5 1 A
35. HVSideGapCTPriVal 1~9999 1000 A

36. HVSideGapCTSecVal 1~5 1 A
37. MVSideGapCTPriVal 1~9999 1000 A
38. MVSideGapCTSecVal 1~5 1 A
39. CommonWindCTPriVal 1~9999 1000 A
40. CommonWindCTSecVal 1~5 1 A
41. MeasureCTPriVal 1~9999 1000 A
42. MeasureCTSecVal 1~5 1 A
Note：Different protection devices present different device parameters.
2 Common setting
Table 281 Commin logic switch
earth fault
protection,
1. VTFailProtOff 0/1 0 negative
sequence voltage
protection
high voltage side
1. HVSideHarmUnblkPhCurr 0.05In~40 In 40 A Overcurrent, earth
fault protection
high voltage side
2. HVSideOC2ndHI2/I1Ratio 0.07~0.50 0.07 Overcurrent, earth
fault protection
medium voltage side
3. MVSideHarmUnblkPhCurr 0.05In~40 In 40 A overcurrent, earth
fault protection
medium voltage side
4. MVSideOC2ndHI2/I1Ratio 0.07~0.50 0.07 overcurrent, earth
fault protection
low voltage side
5. LVSideHarmUnblkPhCurr 0.05In~40 In 40 A overcurrent, earth
fault protection
low voltage side
6. LVSideOC2ndHI2/I1Ratio 0.07~0.50 0.07 overcurrent, earth
fault protection
Earth fault protection
8. HVSide3I02ndHI02/I01 0.07~0.50 0.07
9. MVSide3I0HarmUnblkCurr 0.05In~40 In 40 A of medium voltage
side
10. MVSide3I02ndHI02/I01 0.07~0.50 0.07
of medium voltage
349
Chapter 36 Appendix

side
11. LVSide3I0HarmUnblkCurr 0.05In~40 In 40 A
of low voltage side
12. LVSide3I02ndHI02/I01 0.07~0.50 0.07
of low voltage side
Underfrequency and
13. HVSideLoadShedVoltBlkSet 10~120 30 V overfrequency
protections
Underfrequency and
14. LVSideLoadShedVoltBlkSet 0.05In~10 In 1 A overfrequency
protections
3 Report list
About operation report and protection alarm report, please see the report
list in the protection chapter.
3.1 Alarm report

IED contains three kinds of alarm reports, showing as follows:
1) Alarm I belongs to IED alarm. When alarm I happens, the alarm LED
on the faceplate of the IED will be on, the Run LED will be off, all of
protection function will be out of service and the trip power of protection
will be blocked by the IED.
2) Alarm II belongs to other alarm. When class II alarms triggered, IED's
LED alarm light shall be lightened (except configurating setting group).
Alarm II won't block the trip power of protection. About alarm II
protection functions report list, please see alarm report lists in the
protection chapter.
Table 283 Alarm report list of class I
Number Report name Alarm code Description
1 SampleValErr 32769
2 IEDParmErr 32770
3 ROMSumChkErr 32771
4 SetErr 32772 Need to rewrite setting
5 UnconfirmConnMode 32773
6 SoftConnErr 32774
7 SystemCfgErr 32775
8 IED CPUModuleErr 32778
9 SetGrpPointerErr 32780
10 LogicFileErr 32798 Need to reload sf, esdc file
11 CfgFileErr 35769
12 CfgFileInconsist 35770
13 IOMatrixErr 35771 Need to reload sf, esdc file

The setting of binary output module jumper
14 BOChkNoResponse 33769
is not consistent with the software
350
Chapter 36 Appendix
Number Report name Alarm code Description

configuration, and the jumper should be
reset.
15 BOBreakdown 33770
16 BIBreakdown 33784
17 BIO CPUErr 33789
18 BIO ROMSumErr 33790

The module of BI and BO is unmarked,
19 BIO EEPROMErr 32779
please remark it.
20 BIOCfgErr 32777
21 BISelfChkCircuitErr 33787
BOLatchedPropertyC
22 33793
fgErr
You need to confirm the module address

23 BICommInterrupt 33781 jumper, module should be plugged tightly,
and confirm that the program of BI is correct.
You need to confirm the module address
24 BOCommInterrupt 33782 jumper, module should be plugged tightly,
and confirm that the program of BI is correct.
Table 284 Alarm report list of class II
Number Alarm report Alarm code Description

1 SRAMSelfChkErr 33771
2 TestStateNotRst 33772
3 OperFail 33773
4 CanCommInterrupt 33775
5 FLASHSelfChkErr 33776
6 WorkInTestSetGrp 33783
7 BIInputErr 33785
8 DualPosnInputIncosist 33786
9 BIOInputPowerErr 33788
3.2 Operation Report

Table 285 operation report list
Number Report Alarm code
1 SwitchSetGrpSuccess 32769
2 CopySetGrpSuccess 32789
3 WriteIEDSetSuccess 32770
4 WriteParmSuccess 32771
5 WriteCfgSuccess 32772
351
Chapter 36 Appendix
Number Report Alarm code
6 AdjScaleSuccess 32773
7 AdjAngleSuccess 32788
8 HardConnOn/OffSuccess 32774
9 SoftConnOn/OffSuccess 32775
10 ClearCfg 32776
11 IEDRst(CPUReboot) 32778
12 FactoryRst 32779
13 BOTestSuccess 32780
14 ZeroDriftAdjSuccess 32782
15 ClearAllRptSuccess 32783
16 MaintModeOn 32785
17 MaintModeOff 32786
18 AutoRebootAfterCfg 32868
4 Analog list
Table 286 Analog list
Number LCD display Description Remark
1 UHa Phase A voltage of high voltage side
2 UHb Phase B voltage of high voltage side
3 UHc Phase C voltage of high voltage side
4 UH0 Zero sequence voltage of high voltage side
5 UMa Phase A voltage of medium voltage side
6 UMb Phase B voltage of medium voltage side
7 UMc Phase C voltage of medium voltage side
8 UM0 Zero sequence voltage of medium voltage side
9 UL1a Phase A Protection current of low voltage branch1
10 UL1b Phase B voltage of low voltage branch1
11 UL1c Phase C voltage of low voltage branch1
12 UL2a Phase A voltage of low voltage branch2
13 UL2b Phase B voltage of low voltage branch2
14 UL2c Phase C voltage of low voltage branch2
352
Chapter 36 Appendix
External Zero sequence voltage of low voltage side

15 UL10
branch1
External Zero sequence voltage of low voltage side

16 UL20
branch2
17 IH1a Phase A Protection current of high voltage branch1
18 IH1b Phase B Protection current of high voltage branch1
19 IH1c Phase C Protection current of high voltage branch1
20 IH2a Phase A Protection current of high voltage branch2
21 IH2b Phase B Protection current of high voltage branch2
22 IH2c Phase C Protection current of high voltage branch2
The currents
of each
branch of
the high
voltage side
should be
converted to
the currents
of first
Calculated Zero sequence current of high voltage branch of
23 IH_3I0Cal
side high voltage
side, and
then
calculate the
zero
sequence
current by
using the
sum
currents.
External Zero sequence current of high voltage side

24 IH0REF
(Restricted earth fault)

25 IH0BU
(Backup)

26 IH0Gap
(Gap)
Phase A Protection current of medium voltage

27 IM1a
branch1
Phase B Protection current of medium voltage

28 IM1b
branch1
Phase C Protection current of medium voltage

29 IM1c
branch1
353
Chapter 36 Appendix
Phase A Protection current of medium voltage

30 IM2a
branch2
Phase B Protection current of medium voltage

31 IM2b
branch2
Phase C Protection current of medium voltage

32 IM2c
branch2
The currents
of each
branch of
the medium
voltage side
should be
converted to
the currents
of first
Calculated Zero sequence current of medium voltage branch of
33 IM_3I0Cal
side medium
voltage side,
and then
calculate the
zero
sequence
current by
using the
sum
currents.
External Zero sequence current of medium voltage

34 IM0REF
side (Restricted earth fault)

35 IM0BU
side (Backup)

36 IM0Gap
side (Gap)
37 IL1a Phase A Protection current of low voltage branch1
38 IL1b Phase B Protection current of low voltage branch1
39 IL1c Phase C Protection current of low voltage branch1
Calculated Zero sequence current of low voltage

40 IL1_3I0Cal
branch1

44 IL2_3I0Cal
branch2
354
Chapter 36 Appendix

48 IL3_3I0Cal
branch3
External Zero sequence current of low voltage side

49 IL0REF
(Restricted earth fault)
External Zero sequence current of low voltage side

50 IL0BU
(Backup)
51 IComa Phase A current of the common winding
52 IComb Phase B current of the common winding
53 IComc Phase C current of the common winding
54 IDA Differential current of differential phase A
55 IDB Differential current of differential phase B
56 IDC Differential current of differential phase C
57 IResA Restraint current of longitudinal differential phase A
58 IResB Restraint current of longitudinal differential phase B
59 IResC Restraint current of longitudinal differential Phase C
Secondary harmonic of differential phase A

60 ID2A
Secondary harmonic of differential phase B

61 ID2B
Secondary harmonic of differential phase C

62 ID2C
Third harmonic of differential phase A differential

63 ID3A
current
Third harmonic of differential phase B differential

64 ID3B
current
Third harmonic of differential phase C differential

65 ID3C
current
Fifth harmonic of differential phase A differential

66 ID5A
current
Fifth harmonic of differential phase B differential

67 ID5B
current
355
Chapter 36 Appendix
Fifth harmonic of differential phase C differential

68 ID5C
current
69 IDSideA Side differential phase A differential current
70 IDSideB Side differential phase B differential current
71 IDSideC Side differential phase C differential current
72 IResSideA Restraint current of side differential phase A
73 IResSideB Restraint current of side differential phase B
74 IResSideC Restraint current of side differential phase C
Restricted earth fault differential current of the high

75 ID0H
voltage side
Restricted earth fault differential current of the

76 ID0M
medium voltage side
Restricted earth fault differential current of the low

77 ID0L
voltage side
78 VFA Phase A over excitation multiple
79 VFB Phase B over excitation multiple
80 VFC Phase C over excitation multiple
Phase A thermal accumulated percentage of the high

81 HThermalA
voltage side
Phase B thermal accumulated percentage of the high

82 HThermalB
voltage side
Phase C thermal accumulated percentage of the high

83 HThermalC
voltage side
Phase A thermal accumulated percentage of the

84 MThermalA
medium voltage side
Phase B thermal accumulated percentage of the

85 MThermalB
medium voltage side
Phase C thermal accumulated percentage of the

86 MThermalC
medium voltage side
87 F Frequency
Note: different protection devices present different analogs.
5 Connector list
connector, soft-hard series, soft-hard parallel, and soft-hard parallel by
356
Chapter 36 Appendix
default.
Table 287 Connector list
No. Connector name Description Remark
1 MaintState 1-On, 0-Off
2 HVSideVoltConn 1-On, 0-Off
3 MVSideVoltConn 1-On, 0-Off
4 LVSide1VoltConn 1-On, 0-Off
5 LVSide2VoltConn 1-On, 0-Off
6 DiffConn 1-On, 0-Off
7 DiffSideConn 1-On, 0-Off
8 HVSideREFConn 1-On, 0-Off
9 HVSideREFConn 1-On, 0-Off
10 HVSideImpedConn 1-On, 0-Off
11 HVSideOCConn 1-On, 0-Off
12 HVSide3I0Conn 1-On, 0-Off
13 HVSideI2Conn 1-On, 0-Off
14 HVSideStubConn 1-On, 0-Off
15 HVSThermalOLConn 1-On, 0-Off
16 HVSideCBFConn 1-On, 0-Off
17 HVSideGapConn 1-On, 0-Off
18 OEConn 1-On, 0-Off
19 HVSideUFConn 1-On, 0-Off
20 HVSideOFConn 1-On, 0-Off
21 HVSideUVConn 1-On, 0-Off
22 HVSideOVConn 1-On, 0-Off
23 HVSide3U0Conn 1-On, 0-Off
24 HVSideU2Conn 1-On, 0-Off
25 HVSStartFanConn 1-On, 0-Off
26 HVSBlkVoltAdjConn 1-On, 0-Off
27 HVSideOLConn 1-On, 0-Off
28 MVSideImpedConn 1-On, 0-Off
29 MVSideOCConn 1-On, 0-Off
30 MVSide3I0Conn 1-On, 0-Off
31 MVSideI2Conn 1-On, 0-Off
32 MVSideStubConn 1-On, 0-Off
33 MVSThermalOLConn 1-On, 0-Off
34 MVSideCBFConn 1-On, 0-Off
35 MVSideGapConn 1-On, 0-Off
36 MVSideUVConn 1-On, 0-Off
37 MVSideOVConn 1-On, 0-Off
38 MVSide3U0Conn 1-On, 0-Off
39 MVSideU2Conn 1-On, 0-Off
40 MVSideOLConn 1-On, 0-Off
41 LVSide1OCConn 1-On, 0-Off
42 LVSide1 3I0Conn 1-On, 0-Off
43 LVSide1I2Conn 1-On, 0-Off
44 LVSide1CBFConn 1-On, 0-Off
45 LVSide1DZConn 1-On, 0-Off
46 LVSide1PDConn 1-On, 0-Off
47 LVSide1 3U0Conn 1-On, 0-Off
48 LVSide1OLConn 1-On, 0-Off
51 LVSide2CBFConn 1-On, 0-Off
52 LVSide2 3U0Conn 1-On, 0-Off
357
Chapter 36 Appendix
No. Connector name Description Remark

57 InterturnConn 1-On, 0-Off
Note: Different protection devices have different display connectors.
6 Typical wiring
As for transformer backup protection IED, the typical wiring is shown as
below:
A
B
C
AIM2
I01
I02 IA
I03
I04 IB
* * * I05
I06 IC
I07
I08 IN
AIM1
* I01
I02
I1
Figure 149 Apply to transformer backup protection measurement three phase current,
zero sequence current and neutral point earth current
358
Chapter 36 Appendix
A
B
C
AIM2
U01
UA
U02
UB
U03
UC
U04
UN
AIM2
I01
I02 IA
I03
I04 IB
* * * I05
I06 IC
I07
I08 IN
AIM1
* I01
I02 I1
Figure 150 Apply to transformer backup protection measurement three-phase current,

zero sequence current and neutral point earth current and three-phase voltage beside
busbar
A
B
C
AIM2
I01
I02 IA
I03
I04 IB
* * * I05
I06 IC
I07
I08 IN
AIM2
U01
UA
U02
UB
U03
UC
U04
UN
AIM1
* I01
I02 I1
Figure 151 Apply to transformer backup protection measurement three-phase current,

zero sequence current and neutral point earth current and three-phase voltage beside line
359
Chapter 36 Appendix
A
B
C
AIM2
U01
UA
U02
UB
U03
UC
U04
UN
AIM2
I01
I02 IA
I03
I04 IB
* * * I05
I06 IC
I07
I08 IN
AIM1
* I01
I02 I1
zero sequence current and neutral point earth current and single line voltage beside
busbar
A
B
C
AIM2
U01
UA
U02
UB
U03
UC
U04
UN
AIM2
I01
I02 IA
I03
I04 IB
* * * I05
I06 IC
I07
I08 IN
AIM1
* I01
I02 I1
zero sequence current and neutral point earth current and single-phase voltage beside
busbar
360
Chapter 36 Appendix
7 Inverse time characteristic

7.1 Twelve types of IEC and ANSI time inverse
property curve
In setting, if time inverse property curve is set, the corresponding curve will
be related. Curve which can support IEC and ANSI standard.
Table 288 Twelve types of inverse time property of IEC and inverse time characteristics of
ANSI
Serial
number Inverse time curve Parameter A Parameter P Parameter B
of curve
1 IEC inverse time 0.14 0.02 0
2 IEC abnormal inverse time 13.5 1.0 0
3 IEC extreme inverse time 80.0 2.0 0
4 IEC short inverse time 0.05 0.04 0
5 IEC long inverse time 120.0 1.0 0
6 ANSI inverse time 8.9341 2.0938 0.17966
7 ANSI short inverse time 0.2663 1.2969 0.03393
8 ANSI long inverse time 5.6143 1 2.18592

ANSI moderate inverse
9 0.0103 0.02 0.0228
time
10 ANSI very inverse time 3.922 2.0 0.0982
11 ANSI extreme inverse time 5.64 2.0 0.02434
12 ANSI definite inverse time 0.4797 1.5625 0.21359
7.2 Definable properties by the user

For inverse time characteristic, when the curve No. is set 13, it is
user-defined characteristic.
A
t= ( i p
+ B)T
( ) −1
I
Where:
A: time coefficient of inverse time
B: time delay of inverse time
P: inverse time index
T: inverse time constant
361
Chapter 36 Appendix
8 CT requirements
8.1 Overview
In fact, due to the limitation of manufacturing cost and installation location,
the traditional core current transformer (hereinafter referred to as CT) can
not accurately transmit all fault current signals in the whole fault process.
The current distortion caused by CT saturation may cause abnormal
operation of the device or malfunction of some functions. Although most of
the protection devices can operate correctly when CT is saturated, the
performance of protection function still depends on CT.
8.2 Current transformer classification

Traditional CT manufacturing is based on IEC 60044, ANSI / IEEE C57.13,
ANSI / IEEE C37.110 or other similar standards, in which CT used for
different protection categories are described.
At present, CT used for protection is classified as follows according to
functional characteristics:
 Class P CT
The accuracy limit is determined by the composite error when the primary
current is a steady symmetrical current. Infinite residual flux.
 Class PR CT
CT is limited by remanence coefficient. In some cases, it is necessary to
explain the time constant value of secondary circuit or winding resistance
value.
 Class PX CT
The values of secondary excitation characteristic, low leakage reactance,
secondary winding resistance, secondary load resistance and turn ratio
can be used to evaluate the performance of related protective devices.
 Class TPS CT
The limitation of low leakage current transient transformer is determined by
the secondary excitation characteristics and the turns ratio error. Infinite
residual flux.
 Class TPX CT
The accuracy limit is determined by the instantaneous peak error of the
specified transient duty cycle. Infinite residual flux.
 Class TPY CT
The accuracy limit is determined by the instantaneous peak error of the
specified transient duty cycle. Infinite residual flux.
 Class TPZ CT
The accuracy limit is determined by the peak value error of the
instantaneous AC component at the maximum DC offset under the specific
secondary circuit time constant. There is no requirement for DC element
error limit. The residual flux is negligible.
 TPE CT (TPE means electronic type of transient protection)
362
Chapter 36 Appendix
8.3 Abbreviations (based on IEC 60044-1, IEC

60044-6 standard)
Table 289 Abbreviation comparison table
Abbreviation Description
Esl Rated secondary limiting electromotive force
Eal Rated equivalent secondary limit electromotive
force
Ek Rated inflexion electromotive force
Uk Inflection point voltage (effective value)
Kalf Accurate limit coefficient
Kssc Rated symmetrical short circuit current multiple
K’ssc Effective symmetrical short-circuit current
K”ssc multiple based on different Ipcf
Kpcf Protection calibration coefficient
Ks Given transient coefficient
Kx Calculating coefficient
Ktd Transient calculation coefficient
Ipn Rated primary current
Isn Rated secondary current
Ipsc Rated primary short circuit current
Ipcf Protection check primary fault current
Isscmax Maximum symmetrical short circuit current
Rct Secondary winding resistance at 75 °C / 167 °F
(or other specified temperature)
Rb Secondary load resistance
R’b =Conductor resistance+Relay
resistance=Actual load resistance
Rs Total secondary circuit resistance, including
secondary winding resistance corrected at
75 ℃ , including all connected external
loads unless otherwise specified
Rlead Conductor resistance
Zbn Rated secondary load impedance
Zb Secondary load impedance
Tp Specified primary time constant
Ts Quadratic time constant
8.4 Basic current transformer requirements

8.4.1 Protection check current
Under certain current conditions, CT current error should be within the
accuracy limit.
In order to verify the accuracy of CT, it is necessary to select appropriate
protection to verify the primary current,Ipcf.
For different protections, Ipcf is the fault current of the corresponding fault at
the appropriate fault location, which flows through the calibrated CT.
In order to ensure the reliability of the protection device, the Ipcf shall be
the maximum fault current of the fault in the area, such as the maximum
primary three-phase short-circuit fault current at different positions or the
single-phase fault current based on the system sequence impedance.
363
Chapter 36 Appendix
Moreover, in order to ensure the safety of the protection device, Ipcf shall
be the maximum fault current of out of area fault.
Last but not least, the calculation of Ipcf should be based on the possible
system capacity.
Kpcfis the protection verification coefficient, which is used to verify CT

performance.
𝐼𝑝𝑐𝑓
𝐾𝑝𝑐𝑓 =
𝐼𝑝𝑛
In order to reduce the impact of transient, Kalf is the accurate limit
coefficient of CT, which shall meet the requirements of the following
formula.
Ks is the given transient coefficient, which is used for setting based on

actual operation state and operation experience.
𝐾𝑎𝑙𝑓
𝐾𝑠 =
𝐾𝑝𝑐𝑓
8.4.2 CT classification
The selected CT shall ensure that the error symmetrical short-circuit
current is within the accuracy limit error. The influence of DC component
and remanence of short-circuit current shall be considered, based on the
influence of system transient, protection function characteristics, transient
saturation and time operation experience. In order to meet the
requirements of saturation time, the rated equivalent secondary
electromotive force of CT must be greater than the maximum equivalent
secondary electromotive force calculated based on practical application.
For line protection and transformer differential protection applied to 330kV
and above voltage level, and CT applied to differential protection of
300MW and above generator transformer unit, the time constant of power
system is very large, because of the transient process of the system, CT is
easy to be seriously saturated. In order to prevent CT from saturation in
the actual work cycle, TP CT is more suitable.
For TPS type CT, Eal is determined by the following formula
Where:
Ks: Given transient coefficient;
Kssc: Rated symmetrical short circuit current multiple.
For TPX, TPY and TPZ category CT, Eal (rated equivalent two-limit EMF)
is determined by the following formula:
Where:
364
Chapter 36 Appendix
Ktd: Transient calculation coefficient.

Consider 100% offset of short circuit current.
For C-t-o duty cycle,
t: Working cycle duration;
For C-t '- O-tfr-C-t "- O duty cycle,
t ': working cycle duration;

t ": duration of the second working cycle;
tfr: Duration between two duty cycles.
For line protection and transformer differential protection applied to

110-220kV voltage level, as well as CT applied to 100-200mw generator
transformer differential protection and large capacity motor differential
protection, the impact of system transient process on CT is very small, CT
selection can be based on the main system transient fault state, and there
is enough margin to bear the negative impact of transient state. Therefore,
CT of P, PR and PX can be selected.
For class P and PR CTS, Esl is determined by the following formula:
Kalf: Accurate limit factor.
For PX type CT, Ek (rated inflection point EMF) is determined by the

following formula:
Kx: Calculate the coefficient.
For CT applied to 110kV and below voltage level protection, CT selection

shall be based on the steady-state fault state of the system, and class P
CT can be selected.
8.4.3 Precision level

CT accuracy level shall ensure that the applied protection device can
operate correctly under very sensitive setting conditions, such as sensitive
neutral overcurrent protection. Generally speaking, the accuracy level of
current transformer refers to that the current error is less than ± 1% at
rated primary current (e.g. 5P level).
If a current transformer of very low accuracy level is applied, the actual
zero sequence current shall be checked during equipment commissioning.
365
Chapter 36 Appendix
8.4.4 CT ratio
The selection of CT transformation ratio is based on power system data,
such as maximum load. The CT transformation ratio selected when the
current detected by the protection is greater than the minimum action
value of all faults shall be verified. For different protection functions, the
minimum action value is different and can be adjusted. Therefore, each
function shall be verified separately.
8.4.5 Rated secondary current

Two rated secondary currents, 1A or 5A. Generally, 1A is preferred,
especially for HV and UHV stations, to reduce the load of CT secondary
circuit. Because for CT with rated current 5A, I2R is 25x while CT with
rated current 1A is 1x. For reducing the opening voltage of secondary
circuit, CT of 5A can be selected.
8.4.6 Secondary load

Too much flux will cause CT saturation. The secondary electromotive force
is proportional to the corresponding magnetic flux. In order to generate the
rated secondary current, CT needs to generate enough secondary
electromotive force to feed to the secondary load. Therefore, the larger the
secondary load, the greater the need for the secondary electromotive force,
and the closer to saturation. Therefore, the actual secondary load R'b of
CT must be less than the rated secondary load RB.
Rb > R’b
Rated secondary load impedance, Zbn, is calculated as follows:
𝑆𝑟
𝑍𝑏𝑛 =
𝐼𝑠𝑛2
Where:
Sr: load of each phase current input channel of the protection device, unit:
VA.
For earth faults, conductors consist of phase and neutral conductors and
are usually twice the resistance of a single secondary circuit. For
three-phase fault, the zero sequence current is zero, and the resistance
from single-phase conductor to common neutral point conductor shall be
considered. The most common practice is to use four wire secondary
cables, so it is OK to consider only single-phase secondary conductors for
three-phase conditions.
For isolated or high resistance grounding systems, the calculation of

ground fault is not considered, so the single-phase secondary conductor
resistance can be used in the calculation.
8.4.7 Rated equivalent secondary electromotive force

requirements
In order to ensure correct operation, CT must be able to generate current
in the minimum time before CT starts to saturate.
366
Chapter 36 Appendix
For the transformer differential protection, it is recommended that the CT

types and characteristics of each side of the transformer are the same to
ensure the sensitivity of the protection.
For CT used in 330kV and above voltage level step-down transformer,
TPY type CT is recommended for each side.
For the CT used in the high voltage side and medium voltage side, Eal
shall be verified by the out of area fault C-O-C-O working cycle.
For CT used in low-voltage side angle connection mode, Eal shall be
verified by three-phase short-circuit fault C-O working cycle outside the
area.
Eal must meet the following formula requirements:
𝐸𝑎𝑙 > 𝐾′𝑡𝑑 × 𝐾𝑠𝑠𝑐 × 𝐼𝑠𝑛 × (𝑅𝑐𝑡 + 𝑅′𝑏)
Where:
K'td: recommended to verify the transient calculation coefficient,
recommended 3.
For 220kV and below voltage level transformer differential protection, CT
of class P, PR and PX can be selected. Because the time constant of the
system is relatively small and the DC component is relatively small, the
possibility of saturation caused by the through fault current generated by
the out of area fault is relatively small.
For class P and PR CT, Esl can be verified by the following formula:
Where:
Ks: given the transient coefficient, 2 is recommended.
For PX CT, Ek can be verified by the following formula:
Where:
Ks: given the transient coefficient, 2 is recommended.
367
Chapter 36 Appendix
9 Abbreviation comparison table

Table 290 Abbreviation comparison table
SetName Description
InstantDiffCurrSet Instantaneous differential current setting
DiffStartupSet Differential startup setting
BreakPoint1CurrSet Current setting of knee point 1
BreakPoint2CurrSet Current setting of knee point 2
Slope1RatioRestrCoef Restricted coefficient of slope 1
2ndHRestrCoef Restraint coefficient of the second harmonic
3rd/5thHRestrCoef Restraint coefficient of the third/fifth harmonic
2ndHCrossBlkTime Blocking time of the second harmonic
3rd/5thHBlkTime Blocking time of 3rd/5th harmonic
DiffOn Enable differential protection
InstantaneousDiffOn Enable instantaneous differential
CTFailDetectOn Enable CT failure detection
CTFailBlkDiff CT failure block differential
ExcitInrushBlkDiff Excitation inrush current blocking differential
2ndHRestr Second harmonic restraint
OEBlkDiff Overexcitation block differential
OE5thHOn Enable fifth harmonic of overexcitation
Delta connection minus zero sequence current of high

HVSideDeltaMinus3I0
voltage side
Delta minus zero sequence current of medium voltage
MVSideDeltaMinus3I0
side
LVSideDeltaMinus3I0 Delta minus zero sequence current of low voltage side
VarDiffOn Enable differential protection of variables
368
Chapter 36 Appendix
DiffPhATrip Trip of differential phase A
DiffPhBTrip Trip of differential phase B
DiffPhCTrip Trip of differential phase C
InstantDiffPhATrip Trip of instantaneous differential phase A
InstantDiffPhBTrip Trip of instantaneous differential phase B
InstantDiffPhCTrip Trip of instantaneous differential phase C
VarDiffPhATrip The trip of variable differential phrase A
VarDiffPhBTrip The trip of variable differential phrase B
VarDiffPhCTrip The trip of variable differential phrase C
HVSide1CTFail CT failure of high voltage side 1
MVSide1CTFail CT failure of middle voltage side 1
LVSide1CTFail CT failure of low voltage side 1
DiffCurrOverLmtAlarm Differential current overlimit alarm
2ndHBlkDiff Blocking differential of the second harmonic
3rd/5thHBlkDiff Blocking differential of third or fifth harmonic
Restricted earth fault startup current of high voltage

HVSideREFStartupCurr
side
Restricted earth fault alarm current of high voltage
HVSideREFAlarmCurr
side
Restricted earth fault restraint coefficient of high
HVsideREFRestrCoef
voltage side
HVsideREFTripTime Restricted earth fault trip time of high voltage side
HVsideREFAlarmTime Restricted earth fault alarm time of high voltage side
Restricted earth fault startup current of middle voltage

MVSideREFStartupCurr
side
Restricted earth fault alarm current of middle voltage
MVSideREFAlarmCurr
side
369
Chapter 36 Appendix
Restricted earth fault restraint coefficient of middle

MVSideREFRestrCoef
voltage side
MVSideREFTripTime Restricted earth fault trip time of middle voltage side
MVSideREFAlarmTime Restricted earth fault alarm time of middle voltage side
Current of restricted earth fault startup of low voltage

LVSideREFStartupCurr
side
Current of restricted earth fault alarm of low voltage
LVSideREFAlarmCurr
side
Restraint coefficient of restricted earth fault of low
LVSideREFRestrCoef
voltage side
LVSideREFTripTime Restricted earth fault trip time of low voltage side
LVSideREFAlarmTime Restricted earth fault alarm time of low voltage side
Restricted earth fault protection trip of high voltage

HVSideREFProtTrip
side
HVSideREFAlarm Restricted earth fault alarm of high voltage side
CT failure blocking restricted earth fault of high

CTFailBlkHVSideREF
voltage side
Restricted earth fault protection trip of middle voltage
MVSideREFProtTrip
side
MVSideREFAlarm Restricted earth fault alarm of middle voltage side
CT failure blocking restricted earth fault of middle

CTFailBlkMVSideREF
voltage side
LVSideREFTrip Restricted earth fault trip of low voltage side
LVSideREFAlarm Restricted earth fault alarm of low voltage side
CT failure blocking restricted earth fault of low voltage

CTFailBlkLVSideREF
side
HVSideREFTrip Restrict earth fault trip of high voltage side
MVSideREFTrip Restrict earth fault trip of medium voltage side
LVSideREFTrip Restrict earth fault trip of low voltage side r
HVSideREFCurrOverLmt Restrict earth fault overlimit of high voltage side
MVSideREFCurrOverLmt MVSideREFCurrOverLmt
LVSideREFCurrOverLmt Restrict earth fault overlimit of low voltage side
Phase-to-phase impedance sensitive angle of high

PPZSensitiveAngle
voltage side
Phase-to-earth impedance sensitive angle of high
HVSidePEZSensitiveAngle
voltage side
Phase-to-phase zone 1 point to transformer of high
HVSidePPZ1PointToTransf
voltage side
370
Chapter 36 Appendix

voltage side
voltage side
voltage side
Phase-to-phase zone 1 point to system of high voltage
HVSidePPZ1PointToSystem
side
side
side
side
Time 1 of phase-to-phase impedance zone 1 of high
HVSidePPZ1Time1
voltage side
HVSidePPZ1Time2
voltage side
HVSidePPZ1Time3
voltage side
HVSidePPZ2Time1
voltage side
HVSidePPZ2Time2
voltage side
HVSidePPZ2Time3
voltage side
HVSidePPZ3Time1
voltage side
HVSidePPZ3Time2
voltage side
HVSidePPZ3Time3
voltage side
Phase-to-phase impedance zone 4 time of high
HVSidePPZ4Time
voltage side
HVSideImpedRstTime Impedance reset time of high voltage side
Phase-to-earth zone 1 point to transformer of high

HVSidePEZ1PointToTransf
voltage side
voltage side
voltage side
voltage side
Phase-to-earth zone 1 point to system of high voltage
HVSidePEZ1PointToSystem
side
side
side
side
371
Chapter 36 Appendix
Phase-to-earth zone 1 impedance K0 of high voltage

HVSidePEZ1K0
side
HVSidePEZ2K0
side
HVSidePEZ3K0
side
HVSidePEZ4K0
side
Time 1 of phase-to-earth impedance zone 1 of high
HVSidePEZ1Time1
voltage side
HVSidePEZ1Time2
voltage side
HVSidePEZ1Time3
voltage side
HVSidePEZ2Time1
voltage side
HVSidePEZ2Time2
voltage side
HVSidePEZ2Time3
voltage side
HVSidePEZ3Time1
voltage side
HVSidePEZ3Time2
voltage side
HVSidePEZ3Time3
voltage side
Time of phase-to-earth impedance zone 4 of high
HVSidePEZ4Time
voltage side
Enable time 1 of phase-to-phase impedance zone 1 of
HVSidePPZ1Time1On
high voltage side
HVSidePPZ1Time2On
high voltage side
HVSidePPZ1Time3On
high voltage side
Phase-to-phase impedance zone 1 is blocked by
HVSidePPZ1BlkByPowerSwing
power swing of high voltage side
HVSidePPZ2Time1On
high voltage side
HVSidePPZ2Time2On
high voltage side
HVSidePPZ2Time3On
high voltage side
HVSidePPZ3Time1On
high voltage side
HVSidePPZ3Time2On
high voltage side
HVSidePPZ3Time3On
high voltage side
372
Chapter 36 Appendix
Enable phase-to-phase impedance zone 4 of high

HVSidePPZ4On
voltage side
Enable phase-to-earth impedance zone 1 time 1 of
HVSidePEZ1Time1On
high voltage side
HVSidePEZ1Time2On
high voltage side
HVSidePEZ1Time3On
high voltage side
Phase-to-earth impedance zone 1 is blocked by
HVSidePEZ1BlkByPowerSwing
HVSidePEZ2Time1On
high voltage side
HVSidePEZ2Time2On
high voltage side
HVSidePEZ2Time3On
high voltage side
HVSidePEZ3Time1On
high voltage side
HVSidePEZ3Time2On
high voltage side
HVSidePEZ3Time3On
high voltage side
Enable phase-to-earth impedance zone 4 of high
HVSidePEZ4On
voltage side
Phase-to-phase distance sensitive angle of middle
PPZSensitiveAngle
voltage side
Phase-to-earth impedance sensitive angle of middle
MVSidePEZSensitiveAngle
voltage side
Phase-to-phase zone 1 pointing to transformer of
MVSidePPZ1PointToTransf
middle voltage side
middle voltage side
middle voltage side
middle voltage side
Phase-to-phase zone 1 pointing to system of middle
MVSidePPZ1PointToSystem
voltage side
voltage side
voltage side
voltage side
373
Chapter 36 Appendix
Phase-to-phase distance zone 1 time 1 of middle

MVSidePPZ1Time1
voltage side
MVSidePPZ1Time2
voltage side
MVSidePPZ1Time3
voltage side
MVSidePPZ2Time1
voltage side
MVSidePPZ2Time2
voltage side
MVSidePPZ2Time3
voltage side
MVSidePPZ3Time1
voltage side
MVSidePPZ3Time2
voltage side
MVSidePPZ3Time3
voltage side
Phase-to-phase impedance stage 4 time delay of
MVSidePPZ4Time
middle voltage side
MVSideImpedRstTime Impedance reset time of middle voltage side
Phase-to-earth zone 1 pointing to transformer of

MVSidePEZ1PointToTransf
middle voltage side
middle voltage side
middle voltage side
middle voltage side
Phase-to-earth zone 1 point to system of middle
MVSidePEZ1PointToSystem
voltage side
voltage side
voltage side
voltage side
Phase-to-earth zone 1 impedance K0 of middle
MVSidePEZ1K0
voltage side
MVSidePEZ2K0
voltage side
MVSidePEZ3K0
voltage side
MVSidePEZ4K0
voltage side
MVSidePEZ1Time1 Phase-to-earth zone 1 time 1 of middle voltage side
374
Chapter 36 Appendix
Phase-to-earth impedance stage 4 time of middle

MVSidePEZ4Time
voltage side
Enable phase-to-phase distance zone 1 time 1 of
MVSidePPZ1Time1On
middle voltage side
MVSidePPZ1Time2On
middle voltage side
MVSidePPZ1Time3On
middle voltage side
Phase-to-phase distance zone 1 is blocked by power
MVSidePPZ1BlkByPowerSwing
swing of middle voltage side
MVSidePPZ2Time1On
middle voltage side
MVSidePPZ2Time2On
middle voltage side
MVSidePPZ2Time3On
middle voltage side
MVSidePPZ3Time1On
middle voltage side
MVSidePPZ3Time2On
middle voltage side
MVSidePPZ3Time3On
middle voltage side
Enable phase-to-phase impedance stage 4 of middle
MVSidePPZ4On
voltage side
Enable phase-to-earth zone 1 time 1 of middle voltage
MVSidePEZ1Time1On
side
MVSidePEZ1Time2On
side
MVSidePEZ1Time3On
side
Phase-to-earth impedance stage 1 is blocked by
MVSidePEZ1BlkByPowerSwing
power swing of middle voltage side
MVSidePEZ2Time1On
side
375
Chapter 36 Appendix

MVSidePEZ2Time2On
side
MVSidePEZ2Time3On
side
MVSidePEZ3Time1On
side
MVSidePEZ3Time2On
side
MVSidePEZ3Time3On
side
Enable phase-to-earth impedance stage 4 of middle
MVSidePEZ4On
voltage side
Time 1 trip of phase-to-phase impedance zone 1 of
HVSidePPZ1Time1Trip
high voltage side
HVSidePPZ1Time2Trip
high voltage side
HVSidePPZ1Time3Trip
high voltage side
HVSidePPZ2Time1Trip
high voltage side
HVSidePPZ2Time2Trip
high voltage side
HVSidePPZ2Time3Trip
high voltage side
HVSidePPZ3Time1Trip
high voltage side
HVSidePPZ3Time2Trip
high voltage side
HVSidePPZ3Time3Trip
high voltage side
Trip of Phase-to-phase impedance zone 4 of high
HVSidePPZ4Trip
voltage side
Time 1 trip of phase-to-earth impedance protection
HVSidePEZ1Time1Trip
zone 1 of high voltage side
HVSidePEZ1Time2Trip
HVSidePEZ1Time3Trip
HVSidePEZ2Time1Trip
HVSidePEZ2Time2Trip
HVSidePEZ2Time3Trip
HVSidePEZ3Time1Trip
376
Chapter 36 Appendix

HVSidePEZ3Time2Trip
HVSidePEZ3Time3Trip
Trip of phase-to-earth impedance protection zone 4 of
HVSidePEZ4Trip
high voltage side
Time 1 trip of phase-to-phase distance zone 1 of
MVSidePPZ1Time1Trip
middle voltage side
MVSidePPZ1Time2Trip
middle voltage side
MVSidePPZ1Time3Trip
middle voltage side
MVSidePPZ2Time1Trip
middle voltage side
MVSidePPZ2Time2Trip
middle voltage side
MVSidePPZ2Time3Trip
middle voltage side
MVSidePPZ3Time1Trip
middle voltage side
MVSidePPZ3Time2Trip
middle voltage side
MVSidePPZ3Time3Trip
middle voltage side
Trip of phase-to-phase distance zone 4 of middle
MVSidePPZ4Trip
voltage side
Time 1 trip of phase-to-earth zone 1 of middle voltage
MVSidePEZ1Time1Trip
side
MVSidePEZ1Time2Trip
side
MVSidePEZ1Time3Trip
side
MVSidePEZ2Time1Trip
side
MVSidePEZ2Time2Trip
side
MVSidePEZ2Time3Trip
side
MVSidePEZ3Time1Trip
side
MVSidePEZ3Time2Trip
side
MVSidePEZ3Time3Trip
side
Trip of phase-to-earth impedance protection stage 4
MVSidePEZ4Trip
of middle voltage side
Interturn3I0StartupSet Interturn zero sequence startup current setting
InterturnProtIsOn Enable interturn protection
InterturnTrip Interturn protection trip
377
Chapter 36 Appendix
HVSideOCStage1Curve Overcurrent stage 1 curve of high voltage side
Current setting of overcurrent stage 1 of high voltage

HVSideOCStage1CurrSet
side
HVSideOCSatge1Time1 Time 1 of overcurrent stage 1 of high voltage side
Constant T of inverse time overcurrent stage 1 of high

HVSideInvTimeOCStage1ConstT
voltage side
Coefficient A of inverse time overcurrent stage 1 of
HVSideInvTimeOCStage1CoefA
high voltage side
Time B of inverse time overcurrent stage 1 of high
HVSideInvTimeOCStage1TimeB
voltage side
Index P of inverse time overcurrent stage 1 of high
HVSideInvTimeOC1IndexP
voltage side

side

voltage side
high voltage side
voltage side
voltage side

side
HVSideOCStage3Time1 Time of overcurrent stage 3 of high voltage side

voltage side
high voltage side
voltage side
voltage side
Sensitive angle of directional overcurrent of high
HVSideDirOCSensitiveAngle
voltage side
Phase-to-phase voltage blocking current setting of
HVSidePPVoltBlkOCSet
high voltage side
Overcurrent negative sequence voltage blocking
HVSideOCU2BlkOCSet
setting of high voltage side
Overcurrent harmonic crossing Overcurrent harmonic crossing blocking time of high
blocking time of high voltage side voltage side
HVSideOCRstTime Overcurrent reset time of high voltage side
378
Chapter 36 Appendix
Minimum trip time of inverse time overcurrent of high

HVInvTimeOCMinTripTime
voltage side
Enable time 1 of overcurrent stage 1 of high voltage

HVSideOCSatge1Time1On
side
Overcurrent stage 1 is blocked by voltage of high
HVSideOCStage1BlkByVolt
voltage side
HVSideDirOCStage1 Directional overcurrent stage 1 of high voltage side
Forward direction of overcurrent stage 1 of high

HVSideOCStage1Fwd
voltage side
Overcurrent stage 1 of high voltage side is blocked by
HVSideOCStage1BlkBy2ndH
second harmonic
side
voltage side

HVSideOCStage2Fwd
voltage side
second harmonic
side
voltage side

HVSideOCStage3Fwd
voltage side
second harmonic
Overcurrent of high voltage side VT failure protection
HVSideOCVTFailProtOff
off
HVSideCVCBlkUseHVS High voltage side CVC blocking use high voltage side
HVSideCVCBlkUseMVS HVSideCVCBlkUseMVS
HVSideCVCBlkUseLVS1 HVSideCVCBlkUseLVS1
379
Chapter 36 Appendix
HVSideCVCBlkUseLVS2 HVSideCVCBlkUseLVS2

side
side
side
side
side
side
MVSideOCStage1Curve Overcurrent stage 1 curve of middle voltage side
Overcurrent stage 1 current setting of middle voltage

MVSideOCStage1CurrSet
side
MVSideOCSatge1Time1 Overcurrent stage 1 time 1 of middle voltage side
Constant T of inverse time overcurrent stage 1 of

MVSideInvTimeOCStage1ConstT
middle voltage side
MVSideInvTimeOCStage1CoefA
middle voltage side
Time B of inverse time overcurrent stage 1 of middle
MVSideInvTimeOCStage1TimeB
voltage side
Index P of inverse time overcurrent stage 1 of middle
MVSideInvTimeOC1IndexP
voltage side

side

middle voltage side
middle voltage side
voltage side
voltage side

side
MVSideOCStage3Time1 Overcurrent stage 3 time 1 of middle voltage side

middle voltage side
middle voltage side
380
Chapter 36 Appendix

voltage side
voltage side
Overcurrent direction sensitive angle of middle voltage
MVSideDirOCSensitiveAngle
side
Phase-to-phase voltage blocking overcurrent setting
MVSidePPVoltBlkOCSet
MVSideOCU2BlkOCSet MVSideOC U2BlkSet
MVSideHarmCrossBlkOCTime MVSideHarmCrossBlkOCTime
MVSideOCRstTime Overcurrent reset time of middle voltage side
Minimum trip time of inverse time overcurrent of

MVInvTimeOCMinTripTime
middle voltage side
Enable overcurrent stage 1 time 1 of middle voltage

MVSideOCSatge1Time1On
side
Middle voltage side overcurrent stage 1 is blocked by
MVSideOCStage1BlkByVolt
voltage
MVSideDirOCStage1 Directional overcurrent stage 1 of middle voltage side
Forward direction of middle voltage side overcurrent

MVSideOCStage1Fwd
stage 1
MVSideOCStage1BlkBy2ndH
2nd harmonic
side
voltage

MVSideOCStage2Fwd
stage 2
2nd harmonic
side
voltage
381
Chapter 36 Appendix

MVSideOCStage3Fwd
stage 3
2nd harmonic
MVSideOCVTFailProtOff MVSideOC VTFailProtOff
MVSideCVCBlkUseHVS MVSideCVCBlkUseHVS
MVSideCVCBlkUseMVS MVSideCVCBlkUseMVS
MVSideCVCBlkUseLVS1 MVSideCVCBlkUseLVS1
MVSideCVCBlkUseLVS2 MVSideCVCBlkUseLVS2

side
side
side
side
side
side
LVSide1OCStage1Curve Overcurrent stage 1 curve of low voltage side 1
Overcurrent stage 1 current setting of low voltage side

LVSide1OCStage1CurrSet
1
LVSide1OCSatge1Time1 Overcurrent stage 1 time 1 of low voltage side 1

LVSide1InvTimeOCStage1ConstT
low voltage side 1
LVSide1InvTimeOCStage1CoefA
low voltage side 1
Time B of inverse time overcurrent stage 1 of low
LVSide1InvTimeOCStage1TimeB
voltage side 1
Index P of inverse time overcurrent stage 1 of low
LVSide1InvTimeOC1IndexP
voltage side 1

1

low voltage side 1
low voltage side 1
382
Chapter 36 Appendix

voltage side 1
voltage side 1

1
LVSide1OCStage3Time Overcurrent stage 1 time setting of low voltage side 3

low voltage side 1
low voltage side 1
voltage side 1
voltage side 1
Overcurrent direction sensitive angle of low voltage
LVSide1DirOCSensitiveAngle
side 1
Overcurrent phase-to-phase voltage blocking set of
LVSide1PPVoltBlkOCSet
low voltage side 1
LVSide1OCU2BlkOCSet LVside1OC U2BlkSet
LVSide1HarmCrossBlkOCTime LVSide1HarmCrossBlkOCTime
LVSide1OCRstTime Overcurrent reset time of low voltage side 1
LVS1OCInvTimeMinTripTime LV1OC Inverse time minimum trip time
Enable overcurrent stage 1 time 1 of low voltage side

LVSide1OCSatge1Time1On
1
Overcurrent stage 1 of low voltage side 1 is blocked
LVSide1OCStage1BlkByVolt
by voltage
LVSide1DirOCStage1 Directional overcurrent stage 1 of low voltage side 1
Forward direction of overcurrent stage 1 of low voltage

LVSide1OCStage1Fwd
side 1
LVSide1OCStage1BlkBy2ndH
by second harmonic
383
Chapter 36 Appendix

1
by voltage

LVSide1OCStage2Fwd
side 1
by second harmonic
1
by voltage

LVSide1OCStage3Fwd
side 1
by second harmonic
LVSide1OCVTFailProtOff LVSide1OC VTFailProtOff
LVSide1CVCBlkUseHVS LVSide1CVCBlkUseHVS
LVSide1CVCBlkUseMVS LVSide1CVCBlkUseMVS
LVSide1CVCBlkUseLVS1 LVSide1CVCBlkUseLVS1

1
1
1
1
1
1

2

low voltage side 2
low voltage side 2
384
Chapter 36 Appendix

voltage side 2
voltage side 2

2

low voltage side 2
low voltage side 2
voltage side 2
voltage side 2

2

low voltage side 2
low voltage side 2
voltage side 2
voltage side 2
side 2
low voltage side 2
385
Chapter 36 Appendix

2
by voltage

LVSide2OCStage1Fwd
side 2
by second harmonic
2
by voltage

LVSide2OCStage2Fwd
side 2
by second harmonic
2
by voltage

LVSide2OCStage3Fwd
side 2
by second harmonic

2
2
2
2
386
Chapter 36 Appendix

2
2

3

low voltage side 3
low voltage side 3
voltage side 3
voltage side 3

3

low voltage side 3
low voltage side 3
voltage side 3
voltage side 3

3

low voltage side 3
low voltage side 3
voltage side 3
voltage side 3
side 3
low voltage side 3
387
Chapter 36 Appendix

3
by voltage

LVSide3OCStage1Fwd
side 3
by second harmonic
3
by voltage

LVSide3OCStage2Fwd
side 3
by second harmonic
3
by voltage

LVSide3OCStage3Fwd
side 3
by second harmonic
388
Chapter 36 Appendix

3
3
3
3
3
3
Harmonic unblocking phase current of high voltage
HVSideHarmUnblkPhCurr
side
Overcurrent second harmonic I2/I1 ratio of high
HVSideOC2ndHI2/I1Ratio
voltage side
Harmonic unblocking phase current of overcurrent of
MVSideHarmUnblkPhCurr
middle voltage side
I2/I1 ratio of overcurrent 2nd harmonic of middle
MVSideOC2ndHI2/I1Ratio
voltage side
LVSideHarmUnblkPhCurr
low voltage side
Overcurrent I2/I1 ratio of second harmonic of low
LVSideOC2ndHI2/I1Ratio
voltage side
HVSideOCSatge1Time1Trip Overcurrent stage 1 time 1 trip of high voltage side
HVSideOCStage1PhATrip Overcurrent stage 1 phase A trip of high voltage side
HVSideOCStage1PhBTrip Overcurrent stage 1 phase B trip of high voltage side
HVSideOCStage1PhCTrip Overcurrent stage 1 phase C trip of high voltage side
389
Chapter 36 Appendix
MVSideOCSatge1Time1Trip Overcurrent stage 1 time 1 trip of medium voltage side
MVSideOCStage1PhATrip Medium voltage side overcurrent stage 1 phase A trip
MVSideOCStage1PhBTrip Medium voltage side overcurrent stage 1 phase B trip
Overcurrent stage 1 phase C trip of medium voltage

MVSideOCStage1PhCTrip
side

side

side
LVSide1OCSatge1Time1Trip Overcurrent stage 1 time 1 trip of low voltage side 1
390
Chapter 36 Appendix
LVSide1OCStage1PhATrip Overcurrent stage 1 phase A trip of low voltage side 1
LVSide1OCStage1PhBTrip Overcurrent stage 1 phase B trip of low voltage side 1
LVSide1OCStage1PhCTrip Overcurrent stage 1 phase C trip of low voltage side 1
391
Chapter 36 Appendix
392
Chapter 36 Appendix
HVSideOCInrushBlk Overcurrent inrush blocking of high voltage side
MVSideOCInrushBlk Medium voltage side overcurrent inrush blocking
LVSide1OCInrushBlk Overcurrent inrush blocking of low voltage side 1
Curve of emergency overcurrent stage 1 of high

HVSideEmOCStage1Curve
voltage side
Current setting of emergency overcurrent stage 1 of
HVSideEmOCStage1CurrSet
high voltage side
Time 1 of emergency overcurrent stage 1 of high
HVSideEmOCS1Time1Set
voltage side
Constant T of inverse time emergency overcurrent
HVSInvTime3U0Stage2ConstT
Coefficient A of inverse time emergency overcurrent
HVSideEmOCStage1CoefA
Time B of inverse time emergency overcurrent stage 1
HVSideEmOCStage1TimeB
Index P of inverse time emergency overcurrent stage
HVSideEmOCStage1IndexP
1 of high voltage side
Curve of emergency overcurrent stage 1 of high
HVSideEmOCStage2Curve
voltage side
HVSideEmOCStage2CurrSet
high voltage side
HVSideEmOCStage2TimeSet
voltage side
HVSInvTime3U0Stage2ConstT
HVSideEmOCStage2CoefA
HVSideEmOCStage2TimeB
HVSideEmOCStage2IndexP
2 of high voltage side
Overcurrent harmonic crossing blocking time of high
HVSideHarmCrossBlkOCTime
voltage side
HVSideOCRstTime Overcurrent reset time of high voltage side
Minimum trip time of inverse time overcurrent of high

HVInvTimeOCMinTripTime
voltage side
HVSideEmOCStage1Time2
voltage side
voltage side
voltage side
393
Chapter 36 Appendix

voltage side
Enable time 1 of emergency overcurrent stage 1 of
HVSideEmOCStage1Time1On
high voltage side
Emergency overcurrent stage 1 of high voltage side is
HVSideEmOC1BlkBy2nd
blocked by second harmonic
high voltage side
Emergency overcurrent stage 2 of high voltage side is
HVSideEmOC4BlkBy2nd
high voltage side
high voltage side
high voltage side
high voltage side
Curve of emergency overcurrent stage 1 of medium
MVSideEmOCStage1Curve
voltage side
MVSideEmOCStage1CurrSet
medium voltage side
Time 1 of emergency overcurrent stage 1 of medium
MVSideEmOCS1Time1Set
voltage side
MVSInvTime3U0Stage2ConstT
stage 1 of medium voltage side
MVSideEmOCStage1CoefA
MVSideEmOCStage1TimeB
of medium voltage side
MVSideEmOCStage1IndexP
1 of medium voltage side
MVSideEmOCStage2Curve
voltage side
MVSideEmOCStage2CurrSet
medium voltage side
MVSideEmOCStage2TimeSet
voltage side
MVSInvTime3U0Stage2ConstT
MVSideEmOCStage2CoefA
MVSideEmOCStage2TimeB
of medium voltage side
MVSideEmOCStage2IndexP
2 of medium voltage side
MVSideHarmCrossBlkOCTime MVSideHarmCrossBlkOCTime
MVSideOCRstTime Overcurrent reset time of middle voltage side
Minimum trip time of inverse time overcurrent of

MVInvTimeOCMinTripTime
middle voltage side
394
Chapter 36 Appendix

MVSideEmOCStage1Time2
voltage side
voltage side
voltage side
voltage side
MVSideEmOCStage1Time1On
medium voltage side
Emergency overcurrent stage 1 of medium voltage
MVSideEmOC1BlkBy2nd
side is blocked by second harmonic
medium voltage side
Emergency overcurrent stage 2 of medium voltage
MVSideEmOC4BlkBy2nd
side is blocked by second harmonic
medium voltage side
medium voltage side
medium voltage side
medium voltage side
side
voltage side
middle voltage side
voltage side
Emergency overcurrent stage 1 time 1 trip of high
HVSideEmOCS1Time1Trip
voltage side
Emergency overcurrent stage 1 phase A trip of high
HVSideEmOCS1PhATrip
voltage side
Emergency overcurrent stage 1 phase B trip of high
HVSideEmOCS1PhBTrip
voltage side
Emergency overcurrent stage 1 phase C trip of high
HVSideEmOCS1PhCTrip
voltage side
voltage side
voltage side
voltage side
HVSideEmOCS2PhATrip
voltage side
HVSideEmOCS2PhBTrip
voltage side
HVSideEmOCS2PhCTrip
voltage side
395
Chapter 36 Appendix

voltage side
voltage side
MVSideEmOCS1Time1Trip
voltage side
MVSideEmOCS1PhATrip
voltage side
MVSideEmOCS1PhBTrip
voltage side
MVSideEmOCS1PhCTrip
voltage side
voltage side
voltage side
voltage side
MVSideEmOCS2PhATrip
voltage side
MVSideEmOCS2PhBTrip
voltage side
MVSideEmOCS2PhCTrip
voltage side
voltage side
voltage side
HVSideOCInrushBlk Overcurrent inrush blocking of high voltage side
MVSideOCInrushBlk Medium voltage side overcurrent inrush blocking
Zero sequence current stage 1 curve of high voltage

HVSide3I0Stage1Curve
side
Zero sequence current stage 1 current setting of high
HVSide3I0Stage1CurrSet
voltage side
Time 1 of zero sequence current stage 1 of high
HVSide3I0Satge1Time1
voltage side
Constant T of inverse time zero sequence current
HVSideInvTime3I0Stage1ConstT
Coefficient A of inverse time zero sequence current
HVSideInvTime3I0Stage1CoefA
Time B of inverse time zero sequence current stage 1
HVSideInvTime3I0Stage1TimeB
Index P of inverse time zero sequence current stage 1
HVSideInvTime3I0Stage1IndexP
side
HVSide3I0Stage2CurrSet
voltage side
voltage side
396
Chapter 36 Appendix

HVSideInvTime3I0 Stage 2TimeB
side
HVS3I0Stage3CurrSet
voltage side
HVSideI3I0Stage3Time1
voltage side
HVSideInvTime3I0 Stage 3TimeB
Zero sequence current negative direction sensitive
HVSideDir3I0SensitiveAngle
angle of high voltage side
Negative sequence direction sensitive angle of zero
HVSide3I0NSDSensitiveAngle
sequence current of high voltage side
HVSide3I0RstTime Zero sequence current reset time of high voltage side
Minimum trip time of inverse time earth fault of high

HVInvTime3I0MinTripTime
voltage side
voltage side
voltage side
voltage side
voltage side
voltage side
voltage side
Enable time 1 of zero sequence current stage 1 of
HVSide3I0Stage1Time1On
high voltage side
External zero sequence current stage 1 of high
HVSide3I0Stage1Extr
voltage side
HVSideDir3I0Stage1 Directional earth fault stage 1 of high voltage side
Forward direction of zero sequence current stage 1 of

HVSide3I0Stage1FowardDir
high voltage side
Zero sequence current stage 1 of high voltage side is
HVSide3I0Stage1BlkBy2ndH
397
Chapter 36 Appendix

high voltage side
HVSide3I0Stage2Extr
voltage side
HVSideDir3I0Satge Directional earth fault stage 2 of high voltage side

high voltage side
high voltage side
HVSide3I0Stage3Extr
voltage side
HVSideDir3I0Satge3 Directional earth fault stage 3 of high voltage side

high voltage side
HVSideExtr3IO3U0 HVSideExtr3IO3U0
Enable zero sequence check U2/I2 direction of high

HVSideZeroSeqChkU2/I2DirOn
voltage side
Zero sequence current harmonics check external
HVSide3I0HarmonChkExtrI02/I01
connection I02I01 of high voltage side
HVSide3I0Satge1Time2On
high voltage side
high voltage side
high voltage side
high voltage side
high voltage side
high voltage side
Zero sequence current stage 1 curve of middle
MVSide3I0Stage1Curve
voltage side
Current setting of zero sequence current stage 1 of
MVSide3I0Stage1CurrSet
middle voltage side
Zero sequence current stage 1 time 1 of middle
MVSide3I0Satge1Time1
voltage side
MVSideInvTime3I0Stage1ConstT
stage 1 of middle voltage side
MVSideInvTime3I0Stage1CoefA
MVSideInvTime3I0Stage1TimeB
MVSideInvTime3I0Stage1IndexP
398
Chapter 36 Appendix

voltage side
MVSide3I0Stage2CurrSet
middle voltage side
voltage side
voltage side
MVS3I0Stage3CurrSet
middle voltage side
MVSideI3I0Stage3Time1
voltage side
Zero sequence current direction sensitive angel of
MVSideDir3I0SensitiveAngle
middle voltage side
Zero sequence current negative sequence direction
MVSide3I0NSDSensitiveAngle
sensitive angel of middle voltage side
Zero sequence current reset time of middle voltage
MVSide3I0RstTime
side
Minimum trip time of inverse time earth fault of middle
MVInvTime3I0MinTripTime
voltage side
voltage side
voltage side
voltage side
voltage side
voltage side
voltage side
Enable zero sequence current stage 1 time 1 of
MVSide3I0Stage1Time1On
middle voltage side
External connection zero sequence current stage 1 of
MVSide3I0Stage1Extr
middle voltage side
399
Chapter 36 Appendix
MVSideDir3I0Stage1 Directional earth fault stage 1 of middle voltage side
Forward direction of middle voltage side zero

MVSide3I0Stage1FowardDir
Zero sequence current stage 1 is blocked by second
MVSide3I0Stage1BlkBy2ndH
harmonic of middle voltage side
middle voltage side
MVSide3I0Stage2Extr
middle voltage side
MVSideDir3I0Satge Directional earth fault stage 2 of middle voltage side

middle voltage side
MVSide3I0Stage3Extr
middle voltage side
MVSideDir3I0Satge3 Directional earth fault stage 3 of middle voltage side

MVSideExtr3IO3U0 MVSideExtr3IO3U0
Enable zero sequence check U2/I2 direction of low

MVSideZeroSeqChkU2/I2DirOn
voltage side
MVSide3I0HarmonChkExtrI02/I01
connection I02/I01 of low voltage side
MVSide3I0Satge1Time2On
middle voltage side
middle voltage side
middle voltage side
middle voltage side
middle voltage side
middle voltage side
Zero sequence current stage 1 curve of low voltage
LVSide1 3I0Stage1Curve
side 1
Zero sequence current stage 1 current setting of low
LVSide1 3I0Stage1CurrSet
voltage side 1
LVSide1 3I0Satge1Time1 LVSide1 3I0Stage1Time1

LVSide1InvTime3I0Stage1ConstT
stage 1 of low voltage side 1
400
Chapter 36 Appendix

LVSide1InvTime3I0Stage1CoefA
LVSide1InvTime3I0Stage1TimeB
of low voltage side 1
LVSide1InvTime3I0Stage1IndexP
side 2
voltage side 2

LVSide1InvTime3I0Stage 2TimeB
side 3
LVS1 3I0Stage3CurrSet
voltage side 3
LVSide1 3I0Stage3Time1 LVSide1 3I0Stage3Time1

Zero sequence direction current sensitive angel of low
LVSide1Dir3I0SensitiveAngle
voltage side 1
LVSide1 3I0NSDSensitiveAngle
sensitive angle of low voltage side 1
Reset time of the low voltage side1 zero sequence
LVSide1 3I0RstTime
current
LVS1InvTime3I0MinTripTime LV1EF Inverse time minimum trip time
Zero sequence current stage 1 time 2 of low voltage

LVSide1 3I0Satge1Time2
side 1
side 1
side 1
side 1
side 1
401
Chapter 36 Appendix

side 1
Enable zero sequence current stage 1 time 1 of low
LVSide1 3I0Stage1Time1On
voltage side 1
External zero sequence current stage 1 of low voltage
LVSide1 3I0Stage1Extr
side 1
Directional earth fault stage stage 1 of low voltage
LVSide1Dir3I0Stage1
side 1
Forward zero sequence current stage 1 of low voltage
LVSide1 3I0Stage1FowardDir
side 1
Zero sequence current stage 1 of low voltage side 1 is
LVSide1 3I0Stage1BlkBy2ndH
voltage side 1
side 2
LVSide1Dir3I0Satge
side 2
side 2
voltage side 1
side 3
LVSide1Dir3I0Satge3
side 3
side 3
LVSide1Extr3IO3U0 LVSide1Extr3IO3U0

LVSide1ZeroSeqChkU2/I2DirOn
voltage side
LVSide1 Zero sequence current harmonics check external
3I0HarmonChkExtrI02/I01 connection I02/I01 of low voltage side
LVSide1 3I0Satge1Time2On
voltage side 1
voltage side 1
voltage side 1
voltage side 1
voltage side 1
voltage side 1
side 1
402
Chapter 36 Appendix

voltage side 1

side 2
voltage side 2

side 3
LVS13I0Stage3CurrSet
voltage side 3

voltage side 2
LVSide2 3I0RstTime
current

side 2
side 2
403
Chapter 36 Appendix

side 2
side 2
side 2
side 2
voltage side 2
side 1
LVSide2Dir3I0Stage1
side 1
side 1
voltage side 2
side 2
LVSide2Dir3I0Satge
side 2
side 2
voltage side 2
side 3
LVSide2Dir3I0Satge3
side 3
side 3

voltage side
voltage side 2
voltage side 2
voltage side 2
voltage side 2
404
Chapter 36 Appendix

voltage side 2
voltage side 2
side 1
voltage side 1

side 2
voltage side 2

side 3
LVS13I0Stage3CurrSet
voltage side 3

voltage side 3
LVSide3 3I0RstTime
current
405
Chapter 36 Appendix

side 3
side 3
side 3
side 3
side 3
side 3
voltage side 3
side 1
LVSide3Dir3I0Stage1
side 1
side 1
voltage side 3
side 2
LVSide3Dir3I0Satge
side 2
side 2
voltage side 3
side 3
LVSide3Dir3I0Satge3
side 3
side 3

voltage side
voltage side 3
406
Chapter 36 Appendix

voltage side 3
voltage side 3
voltage side 3
voltage side 3
voltage side 3
side
voltage side
middle voltage side
voltage side
LVSideHarmUnblkPhCurr
low voltage side
Overcurrent I2/I1 ratio of second harmonic of low
LVSideOC2ndHI2/I1Ratio
voltage side
Harmonic unblocking zero sequence current of high
HVSide3I0HarmUnblkCurr
voltage side
Zero sequence current second harmonic I02/I01 ratio
HVSide3I02ndHI02/I01
Harmonic unblocking zero sequence current of
MVSide3I0HarmUnblkCurr
medium voltage side
MVSide3I02ndHI02/I01
Harmonic unblocking zero sequence current of low
LVSide3I0HarmUnblkCurr
voltage side
LVSide3I02ndHI02/I01
of low voltage side
VTFailProtOff Disable VT failure protection
Zero sequence current stage 1 time 1 trip of high

HVSide3I0Stage1Time1Trip
voltage side
HVSide3I0Satge1Time2Trip
voltage side
voltage side
voltage side
voltage side
voltage side
voltage side
voltage side
407
Chapter 36 Appendix

voltage side
Zero sequence current stage 1 time 1 trip of medium
MVSide3I0Stage1Time1Trip
voltage side
MVSide3I0Satge1Time2Trip
voltage side
voltage side
voltage side
voltage side
voltage side
voltage side
voltage side
voltage side
LVSide1 3I0Stage1Time1Trip Earth fault stage 1 time limit 1 trip of low voltage side 1
LVSide1 3I0Satge1Time2Trip Earth fault stage 1 time limit 1 trip of low voltage side 2
408
Chapter 36 Appendix
Zero sequence current inrush blocking of high voltage

HVSide 3I0InrushBlk
side
Medium voltage side zero sequence current inrush
MVSide 3I0InrushBlk
blocking
Zero sequence current inrush blocking of low voltage
LVSide1 3I0InrushBlk
side 1
side 2
side 3
Curve of emergency earth fault protection stage 1 of
HVSideEm3I0Stage1Curve
high voltage side
Current setting of emergency earth faultstage 1 of
HVSideEm3I0Stage1CurrSet
high voltage side
Time 1 of emergency earth fault stage 1 of high
HVSideEm3I0S1Time1Set
voltage side
Constant T of inverse time emergency earth fault
HVSInvTimeEm3I0S1ConstT
Coefficient A of inverse time emergency earth fault
HVSInvTimeEm3I0S1CoefA
Time B of inverse time emergency earth fault stage 1
HVSInvTimeEm3I0S1TimeB
Index P of inverse time emergency earth fault stage 1
HVSInvTimeEm3I0S1IndexP
Curve of emergency earth fault protection stage 2 of
HVSideEm3I0Stage2Curve
high voltage side
Current setting of emergency earth faultstage 2 of
HVSideEm3I0Stage2CurrSet
high voltage side
HVSideEm3I0Stage2Time1
voltage side
409
Chapter 36 Appendix
Constant T of inverse time emergency earth fault

HVSide3I0RstTime Zero sequence current reset time of high voltage side
Minimum trip time of inverse time earth fault of high

HVInvTime3I0MinTripTime
voltage side
voltage side
voltage side
voltage side
voltage side
HVSideEm3I0S1Time1On
high voltage side
Zero sequence current external connection of
HVSideEm3I0Stage1Extr emergency earth fault protection stage 1 of high
voltage side
Emergency emergency earth fault protection stage 1
HVSEm3I0Stage1BlkBy2ndH
of high voltage side is blocked by second harmonic
high voltage side
HVSideEm3I0Stage2Extr emergency earth fault protection stage 2 of high
voltage side
HVSEm3I0Stage2BlkBy2ndH
of high voltage side is blocked by second harmonic
HVSide3I0HarmChkExtrI02/I01
connection I02I01 of high voltage side
high voltage side
high voltage side
high voltage side
high voltage side
MVSideEm3I0Stage1Curve
voltage side
MVSideEm3I0Stage1CurrSet
medium voltage side
MVSideEm3I0S1Time1Set
voltage side
410
Chapter 36 Appendix

MVSideEm3I0Stage2Curve
voltage side
MVSideEm3I0Stage2CurrSet
medium voltage side
MVSideEm3I0Stage2Time1
voltage side
MVSInvTimeEm3I0S2ConstT
MVSInvTimeEm3I0S2CoefA
MVSInvTimeEm3I0S2TimeB
MVSInvTimeEm3I0S1IndexP
Zero sequence current reset time of middle voltage
MVSide3I0RstTime
side
Minimum trip time of inverse time earth fault of middle
MVInvTime3I0MinTripTime
voltage side
voltage side
voltage side
voltage side
voltage side
MVSideEm3I0S1Time1On
medium voltage side
MVSideEm3I0Stage1Extr emergency earth fault protection stage 1 of medium
voltage side
MVSEm3I0Stage1BlkBy2ndH of medium voltage side is blocked by second
harmonic
Enable time 1 of emergency earth fault protection
MVSideEm3I0Stage2Extr emergency earth fault protection stage 2 of medium
voltage side
MVSEm3I0Stage2BlkBy2ndH of medium voltage side is blocked by second
harmonic
MVSide3I0HarmChkExtrI02/I01
connection I02/I01 of low voltage side
411
Chapter 36 Appendix

side
voltage side
middle voltage side
voltage side
Harmonic unblocking zero sequence current of high
HVSide3I0HarmUnblkCurr
voltage side
HVSide3I02ndHI02/I01
Harmonic unblocking zero sequence current of
MVSide3I0HarmUnblkCurr
medium voltage side
MVSide3I02ndHI02/I01
Emergency earth fault stage 1 time 1 trip of high
HVSideEm3I0S1Time1Trip
voltage side
voltage side
voltage side
voltage side
voltage side
voltage side
MVSideEm3I0S1Time1Trip
voltage side
voltage side
voltage side
voltage side
voltage side
voltage side
Zero sequence current inrush blocking of high voltage
HVSide3I0InrushBlk
side
Medium voltage side zero sequence current inrush
MVSide3I0InrushBlk
blocking
Negative sequence current stage 1 curve of high
HVSideI2Stage1Curve
voltage side
412
Chapter 36 Appendix
Current setting of negative sequence current stage 1

HVSideI2Stage1CurrSet
Time 1 of negative sequence current stage 1 of high
HVSideI2Stage1Time
voltage side
Constant T of inverse time negative sequence current
HVSideInvTimeI2Stage1CoefT
Constant A of inverse time negative sequence current
HVSideInvTimeI2Stage1CoefA
Constant B of inverse time negative sequence current
HVSideInvTimeI2Stage1CoefB
Constant P of inverse time negative sequence current
HVSideInvTimeI2Stage1IndexP
HVSideI2Stage2Curve
voltage side
HVSideI2Stage2Time
voltage side
HVSideI2Stage3Curve
voltage side
HVSideI2Stage3Time
voltage side
Negative sequence current reset time of high voltage
HVSideI2RstTime
side
Minimum trip time of inverse time negative sequence
HVInvTimeI2MinTripTime
current of high voltage side
HVSideI2Satge1Time2
voltage side
HVSideI2Satge1Time3
voltage side
HVSideI2Satge2Time2
voltage side
HVSideI2Satge2Time3
voltage side
413
Chapter 36 Appendix

HVSideI2Satge3Time2
voltage side
HVSideI2Satge3Time3
voltage side
Enable time 1 of negative sequence current stage 1 of
HVSideI2Stage1Time1On
high voltage side
high voltage side
high voltage side
high voltage side
high voltage side
high voltage side
high voltage side
high voltage side
high voltage side
Negative sequence current stage 1 curve of middle
MVSideI2Stage1Curve
voltage side
MVSideI2Stage1CurrSet
Negative sequence current stage 1 time 1 of middle
MVSideI2Stage1Time
voltage side
MVSideInvTimeI2Stage1CoefT
Coefficient A of inverse time negative sequence
MVSideInvTimeI2Stage1CoefA
current stage 1 of middle voltage side
Time B of inverse time negative sequence over
MVSideInvTimeI2Stage1CoefB
MVSideInvTimeI2Stage1IndexP
MVSideI2Stage2Curve
voltage side
MVSideI2Stage2Time
voltage side
MVSideI2Stage3Curve
voltage side
414
Chapter 36 Appendix

MVSideI2Stage3Time
voltage side
Negative sequence current reset time of middle
MVSideI2RstTime
voltage side
MVInvTimeI2MinTripTime
current of middle voltage side
MVSideI2Satge1Time2
voltage side
MVSideI2Satge1Time3
voltage side
MVSideI2Satge2Time2
voltage side
MVSideI2Satge2Time3
voltage side
MVSideI2Satge3Time2
voltage side
MVSideI2Satge3Time3
voltage side
Enable negative sequence current stage 1 time 1 of
MVSideI2Stage1Time1On
middle voltage side
middle voltage side
middle voltage side
middle voltage side
middle voltage side
middle voltage side
middle voltage side
middle voltage side
middle voltage side
LVSide1I2Stage1Curve LVSide1I2Stage1Curve
LVSide1I2Stage1CurrSet LVSide1I2Stage1Set
Negative sequence current stage 1 time 1 of low

LVSide1I2Stage1Time
voltage side
415
Chapter 36 Appendix
LVSide1InvTimeI2Stage1CoefT LVSide1InvTimeI2Stage1T
LVSide1InvTimeI2Stage1CoefA LVSide1InvTimeI2Stage1A
LVSide1InvTimeI2Stage1CoefB LVSide1InvTimeI2Stage1B
LVSide1InvTimeI2Stage1IndexP LVSide1InvTimeI2Stage1P

LVSide1I2Stage2Time
voltage side

LVSide1I2Stage3Time
voltage side
LVSide1I2RstTime LVSide1I2RstTime
LVS1InvTimeI2MinTripTime LV1NS Inverse time minimum trip time
LVSide1I2Satge1Time2 LVSide1I2Stage1Time2
416
Chapter 36 Appendix
Enable time of negative sequence current stage 1

LVSide1I2Stage1Time1On
time 1 of low voltage side
LVSide1I2Stage1Time2On LVSide1I2Stage1Time2On
Negative sequence current stage 1 time 1 trip of high

HVSideI2Satge1Time1Trip
voltage side
voltage side
voltage side
Negative sequence current stage 1 time 1 trip of
MVSideI2Satge1Time1Trip
medium voltage side
medium voltage side
medium voltage side
LVSide1I2Satge1Time1Trip LVSide1I2Stage1Time1Trip
HVSideOVStage1Curve Overvoltage stage 1 curve of high voltage side
Voltage setting of overvoltage stage 1 of high voltage

HVSideOVStage1VoltSet
side
HVSideOVStage1Time Time of overvoltage stage 1 of high voltage side
Constant T of inverse time overvoltage stage 1 of high

HVSideInvTimeOVStage1ConstT
voltage side
Coefficient A of inverse time overvoltage stage 1 of
HVSideInvTimeOVStage1CoefA
high voltage side
Time B of inverse time overvoltage stage 1 of high
HVSideInvTimeOVStage1TimeB
voltage side
Index P of inverse time overvoltage stage 1 of high
HVSideInvTimeOVStage1IndexP
voltage side
HVSideOVStage2Curve Overvoltage stage 2 curve of high voltage side
417
Chapter 36 Appendix
Voltage setting of overvoltage stage 2 of high voltage

HVSideOVStage2VoltSet
side
HVSideOVStage2Time Time of overvoltage stage 2 of high voltage side
Constant T of inverse time overvoltage stage 2 of high

HVSideInvTimeOVStage2ConstT
voltage side
HVSideInvTimeOVStage2CoefA
high voltage side
Time B of inverse time overvoltage stage 2 of high
HVSideInvTimeOVStage2TimeB
voltage side
Index P of inverse time overvoltage stage 2 of high
HVSideInvTimeOVStage2IndexP
voltage side
HVSideOVDropoffCoef Overvoltage dropoff coefficient of high voltage side
HVSideOVRstTime Overvoltage reset time of high voltage side
Minimum trip time of inverse time overvoltage of high

HVInvTimeOVMinTripTime
voltage side
HVSideOVStage1On Enable stage 1 of overvoltage of high voltage side
HVSideOVStage2On Enable stage 2 of overvoltage of high voltage side
Overvoltage checks phase-to-earth voltage of high

HVSideOVChkPEVolt
voltage side
HVSideOVChk1Ph Overvoltage checks phase 1 of high voltage side
MVSideOVStage1Curve Overvoltage stage 1 curve of middle voltage side
Overvoltage stage 1 voltage setting of middle voltage

MVSideOVStage1VoltSet
side
MVSideOVStage1Time Overvoltage stage 1 time of middle voltage side
Constant T of inverse time overvoltage stage 1 of

MVSideInvTimeOVStage1ConstT
middle voltage side
MVSideInvTimeOVStage1CoefA
middle voltage side
Time B of inverse time overvoltage stage 1 of middle
MVSideInvTimeOVStage1TimeB
voltage side
Index P of inverse time overvoltage stage 1 of middle
MVSideInvTimeOVStage1IndexP
voltage side
MVSideOVStage2Curve Overvoltage stage 2 curve of middle voltage side
Overvoltage stage 2 voltage setting of middle voltage

MVSideOVStage2VoltSet
side
MVSideOVStage2Time Overvoltage stage 2 time of middle voltage side
Constant T of inverse time overvoltage stage 2 of

MVSideInvTimeOVStage2ConstT
middle voltage side
MVSideInvTimeOVStage2CoefA
middle voltage side
Time B of inverse time overvoltage stage 2 of middle
MVSideInvTimeOVStage2TimeB
voltage side
418
Chapter 36 Appendix
Index P of inverse time overvoltage stage 2 of middle

MVSideInvTimeOVStage2IndexP
voltage side
MVSideOVDropoffCoef MVSideOVDropoffCoef
MVSideOVRstTime Middle voltage side overvoltage reset time
Minimum trip time of inverse time overvoltage of

MVInvTimeOVMinTripTime
middle voltage side
MVSideOVStage1On Enable overvoltage stage 1 of middle voltage side
MVSideOVStage2On Enable overvoltage stage 2 of middle voltage side
Overvoltage check phase-to-earth voltage of middle

MVSideOVChkPEVolt
voltage side
MVSideOVChk1Ph Middle voltage side overvoltage check phase 1
HVSideOVStage1Trip Trip of overvoltage stage 1 of high voltage side
HVSideOVStage2Trip Trip of overvoltage stage 2 of high voltage side
MVSideOVStage1Trip Trip of overvoltage stage 1 of medium voltage side
MVSideOVStage2Trip Trip of overvoltage stage 2 of medium voltage side
HVSide3U0Stage1CurveSel HVSide3U0Stage1CurveSel
HVSide3U0Stage1Set HVSide3U0Stage1VoltSet
HVSide3U0Stage1Time HVSide3U0Stage1Time
Constant T of inverse time zero sequence voltage

HVSideInvTime3U0Stage1ConstT
Coefficient A of inverse time zero sequence voltage
HVSideInvTime3U0Stage1CoefA
Time B of inverse time zero sequence voltage stage 1
HVSideInvTime3U0Stage1TimeB
Index P of inverse time zero sequence voltage stage 1
HVSideInvTime3U0Stage1IndeP
HVSide3U0RstTime HVSide3U0RstTime
HVInvTime3U0MinTripTime HVInvTime3U0MinTripTime
HVSide3U0Stage1On HVSide3U0Stage1On
HVSideExtr3U0 HVSideExtr3U0
MVSide3U0Stage1CurveSel MVSide3U0Stage1CurveSel
MVSide3U0Stage1Set MVSide3U0Stage1VoltSet
MVSide3U0Stage1Time MVSide3U0Stage1Time
419
Chapter 36 Appendix
MVSideInvTime3U0Stage1ConstT MVSInvTime3U0Stage1ConstT
MVSideInvTime3U0Stage1CoefA MVSInvTime3U0Stage1CoefA
MVSideInvTime3U0Stage1TimeB MVSInvTime3U0Stage1TimeB

MVSideInvTime3U0Stage1IndeP
MVSide3U0RstTime MVSide3U0RstTime
MVInvTime3U0MinTripTime MVInvTime3U0MinTripTime
MVSide3U0Stage1On MVSide3U0Stage1On
MVSideExtr3U0 MVSideExtr3U0
Curve selection of zero sequence voltage stage 1 of

LVSide13U0Stage1CurveSel
low voltage side 1
Setting of zero sequence voltage stage 1 of low
LVSide13U0Stage1Set
voltage side 1
Time of zero sequence voltage stage 1 of low voltage
LVSide13U0Stage1Time
side 1
LVSide1InvTime3U0Stage1ConstT
LVSide1InvTime3U0Stage1CoefA
Time B of inverse time over zero sequence voltage
LVSide1InvTime3U0Stage1TimeB
LVSide1InvTime3U0Stage1IndeP
Zero sequence voltage reset time of low voltage side
LVSide13U0RstTime
1
LV1InvTime3U0MinTripTime LV1 inverse time ZSOV Tmin
Enable stage 1 of zero sequence voltage of low

LVSide13U0Stage1On
voltage side 1
LVSide1Extr3U0 LVSide1 Extr3U0
Curve selection of zero sequence voltage stage 2 of

LVSide2 3U0Stage1CurveSel
low voltage side 1
Setting of zero sequence voltage stage 2 of low
LVSide2 3U0Stage1Set
voltage side 1
Time of zero sequence voltage stage 2 of low voltage
LVSide2 3U0Stage1Time
side 1
LVSide2InvTime3U0Stage1ConstT
LVSide2InvTime3U0Stage1CoefA
Time B of inverse time over zero sequence voltage
LVSide2InvTime3U0Stage1TimeB
LVSide2InvTime3U0Stage1IndeP
420
Chapter 36 Appendix
Zero sequence voltage reset time of low voltage side

LVSide2 3U0RstTime
2
LV2InvTime3U0MinTripTime LV2 inverse time ZSOV Tmin
Enable stage 2 of zero sequence voltage of low

LVSide2 3U0Stage1On
voltage side 1
LVSide2Extr3U0 LVSide1 Extr3U0
HVSide3U0Trip HVSide3U0Trip
MVSide3U0Trip MVSide3U0Trip
LVSide1 3U0Trip Zero sequence voltage trip of low voltage side 1
LVSide2 3U0Trip Zero sequence voltage trip of low voltage side 2
Negative sequence voltage stage 1 curve of high

HVSideU2Stage1Curve
voltage side
Voltage setting of negative sequence voltage stage 1
HVSideU2Stage1VoltSet
Time of negative sequence voltage stage 1 of high
HVSideU2Stage1Time
voltage side
Constant T of inverse time negative sequence voltage
HVSideInvTimeU2Stage1ConstT
HVSideInvTimeU2Stage1CoefA
voltage stage 1 of high voltage side
Time B of inverse time negative sequence voltage
HVSideInvTimeU2Stage1TimeB
Index P of inverse time negative sequence voltage
HVSideInvTimeU2Stage1IndexP
Negative sequence voltage stage 2 curve of high
HVSideU2Stage2Curve
voltage side
Voltage setting of negative sequence voltage stage 2
HVSideU2Stage2VoltSet
Time of negative sequence voltage stage 2 of high
HVSideU2Stage2Time
voltage side
HVSideInvTimeU2Stage2ConstT
HVSideInvTimeU2Stage2CoefA
voltage stage 2 of high voltage side
HVSideInvTimeU2Stage2TimeB
Index P of inverse time negative sequence voltage
HVSideInvTimeU2Stage2IndexP
Negative sequence voltage reset time of high voltage
HVSideU2RstTime
side
HVInvTimeU2MinTripTime
voltage of high voltage side
Enable stage 1 of negative sequence voltage of high
HVSideU2Stage1On
voltage side
Enable stage 2 of negative sequence voltage of high
HVSideU2Stage2On
voltage side
421
Chapter 36 Appendix
Curve of negative sequence voltage stage 1 of middle

MVSideU2Stage1Curve
voltage side
Negative sequence voltage stage 1 voltage setting of
MVSideU2Stage1VoltSet
middle voltage side
Time setting of negative sequence voltage stage 1 of
MVSideU2Stage1Time
middle voltage side
MVSideInvTimeU2Stage1ConstT
MVSideInvTimeU2Stage1CoefA
voltage stage 1 of middle voltage side
MVSideInvTimeU2Stage1TimeB
Constant P of inverse time negative sequence voltage
MVSideInvTimeU2Stage1IndexP
Curve of negative sequence voltage stage 2 of middle
MVSideU2Stage2Curve
voltage side
Negative sequence voltage stage 2 voltage setting of
MVSideU2Stage2VoltSet
middle voltage side
Time setting of negative sequence voltage stage 2 of
MVSideU2Stage2Time
middle voltage side
MVSideInvTimeU2Stage2ConstT
MVSideInvTimeU2Stage2CoefA
voltage stage 2 of middle voltage side
MVSideInvTimeU2Stage2TimeB
Constant P of inverse time negative sequence voltage
MVSideInvTimeU2Stage2IndexP
Negative sequence voltage reset time of middle
MVSideU2RstTime
voltage side
MVInvTimeU2MinTripTime
voltage of middle voltage side
Enable stage 1 of negative sequence voltage of
MVSideU2Stage1On
middle voltage side
Enable stage 2 of negative sequence voltage of
MVSideU2Stage2On
middle voltage side
Trip of negative sequence voltage stage 1 of high
HVSideU2Stage1Trip
voltage side
Trip of negative sequence voltage stage 2 of high
HVSideU2Stage2Trip
voltage side
Trip of negative sequence current stage 1 of medium
MVSideU2Stage1Trip
voltage side
Trip of negative sequence current stage 2 of medium
MVSideU2Stage2Trip
voltage side
Curve selection of undervoltage stage 1 of high
HVSideUVStage1CurveSel
voltage side
Voltage setting of undervoltage stage 1 of high voltage
HVSideUVStage1VoltSet
side
HVSideUVStage1Time Time of undervoltage stage 1 of high voltage side
Index T of inverse time undervoltage stage 1 of high

HVSideInvTimeUVStage1T
voltage side
422
Chapter 36 Appendix
Coefficient A of inverse time undervoltage stage 1 of

HVSideInvTimeUVStage1A
high voltage side
Time B of inverse time undervoltage stage 1 of high
HVSideInvTimeUVStage1B
voltage side
Index P of inverse time undervoltage stage 1 of high
HVSideInvTimeUVStage1P
voltage side
Curve selection of undervoltage stage 2 of high
HVSideUVStage2CurveSel
voltage side
Voltage setting of undervoltage stage 2 of high voltage
HVSideUVStage2VoltSet
side
HVSideUVStage2Time Time of undervoltage stage 2 of high voltage side
Index T of inverse time undervoltage stage 2 of high

HVSideInvTimeUVStage2T
voltage side
Coefficient A of inverse time undervoltage stage 2 of
HVSideInvTimeUVStage2A
high voltage side
Time B of inverse time undervoltage stage 2 of high
HVSideInvTimeUVStage2B
voltage side
Index P of inverse time undervoltage stage 2 of high
HVSideInvTimeUVStage2IndexP
voltage side
Undervoltage check current setting of high voltage
HVSideUVChkCurrSet
side
Undervoltage minimum voltage setting of high voltage
HVSideUVMinVoltSet
side
HVSideUVDropoffCoef Undervoltage dropoff coefficient of high voltage side
HVSideUVRstTime Undervoltage reset time of high voltage side
Minimum trip time of inverse time undervoltage of high

HVInvTimeUVMinTripTime
voltage side
HVSideUVStage1On Enable stage 1 of undervoltage of high voltage side
HVSideUVStage2On Enable stage 2 of undervoltage of high voltage side
Enable undervoltage checking current of high voltage

HVSideUVChkCurrOn
side
Undervoltage checks circuit breaker state of high
HVSideUVoltChkCBState
voltage side
HVsideUVChk1Ph Undervoltage checks 1 phase 1 of high voltage side
Undervoltage checks phase-to-earth voltage of high

HVSideChkPEVolt
voltage side
Curve selection of undervoltage stage 1 of middle
MVSideUVStage1CurveSel
voltage side
Undervoltage stage 1 voltage setting of middle voltage
MVSideUVStage1VoltSet
side
MVSideUVStage1Time Time of undervoltage stage 1 of middle voltage side
Inverse time T of undervoltage stage 1 of middle

MVSideInvTimeUVStage1T
voltage side
Coefficient A of inverse undervoltage stage 1 of
MVSideInvTimeUVStage1A
middle voltage side
423
Chapter 36 Appendix
Time B of inverse time undervoltage stage 1 of middle

MVSideInvTimeUVStage1B
voltage side
Inverse time P of undervoltage stage 1 of middle
MVSideInvTimeUVStage1P
voltage side
Curve selection of undervoltage stage 2 of middle
MVSideUVStage2CurveSel
voltage side
Undervoltage stage 2 voltage setting of middle voltage
MVSideUVStage2VoltSet
side
MVSideUVStage2Time Time of undervoltage stage 2 of middle voltage side
Inverse time T of undervoltage stage 2 of middle

MVSideInvTimeUVStage2T
voltage side
Coefficient A of inverse undervoltage stage 2 of
MVSideInvTimeUVStage2A
middle voltage side
Time B of inverse time undervoltage stage 2 of middle
MVSideInvTimeUVStage2B
voltage side
Inverse time P of undervoltage stage 2 of middle
MVSideInvTimeUVStage2IndexP
voltage side
Undervoltage check current setting of middle voltage
MVSideUVChkCurrSet
side
Undervoltage minimum voltage setting of middle
MVSideUVMinVoltSet
voltage side
MVSideUVDropoffCoef Undervoltage dropoff coefficient of middle voltage side
MVSideUVRstTime Undervoltage reset time of middle voltage side
Minimum trip time of inverse time undervoltage of

MVInvTimeUVMinTripTime
middle voltage side
MVSideUVStage1On Enable stage 1 of undervoltage of middle voltage side
MVSideUVStage2On Enable stage 2 of undervoltage of middle voltage side
Enable undervoltage check current of middle voltage

MVSideUVChkCurrOn
side
Undervoltage check circuit breaker state of middle
MVSideUVoltChkCBState
voltage side
MVSideUVChk1Ph Undervoltage check 1 phase of middle voltage side
Undervoltage check phase-to-earth voltage of middle

MVSideChkPEVolt
voltage side
HVSideUVStage1Trip Trip of undervoltage stage 1 of high voltage side
HVSideUVStage2Trip Trip of undervoltage stage 2 of high voltage side
MVSideUVStage1Trip Trip of undervoltage stage 1 of medium voltage side
MVSideUVStage2Trip Trip of undervoltage stage 2 of medium voltage side
HVSideThermalOLCurrSet Thermal overload current setting of high voltage side
HVSideThermalTimeConst Thermal time constant of high voltage side
424
Chapter 36 Appendix
Thermal overload cooling coefficient of high voltage

HVSideThermalOLCoolingCoef
side
Thermal overload alarm coefficient 1 of high voltage
HVSideThermalOLAlarmCoef1
side
Thermal overload alarm coefficient 2 of high voltage
HVSideThermalOLAlarmCoef2
side
HVSideThermalOLOn Enabled thermal overload of high voltage side
Enable thermal overload stage 1 alarm of high voltage

HVSideThermalOLAlarm1On
side
Enable thermal overload stage 2 alarm of high voltage
HVSideThermalOLAlarm2On
side
HVSideThermalCurve Hot curve of high voltage side
Thermal overload current setting of middle voltage

MVSideThermalOLCurrSet
side
MVSideThermalTimeConst Thermal time constant of middle voltage side
Thermal overload cooling coefficient of middle voltage

MVSideThermalOLCoolingCoef
side
Thermal overload alarm coefficient 1 of middle voltage
MVSideThermalOLAlarmCoef1
side
Thermal overload alarm coefficient 2 of middle voltage
MVSideThermalOLAlarmCoef2
side
MVSideThermalOLOn Enabled thermal overload of middle voltage side
Enable thermal overload stage 1 alarm of middle

MVSideThermalOLAlarm1On
voltage side
Enable thermal overload stage 2 alarm of middle
MVSideThermalOLAlarm2On
voltage side
MVSideThermalCurve Thermal curve of middle voltage side
HVSideThermalOLTrip Trip of thermal overload of high voltage side
MVSideThermalOLTrip Thermal overload trip of medium voltage side
HVSideThermalOLStage1Alarm Alarm of thermal overload stage 1 of high voltage side
HVSideThermalOLStage2Alarm Alarm of thermal overload stage 2 of high voltage side
Alarm of thermal overload stage 1 of medium voltage

MVSideThermalOLStage1Alarm
side
Alarm of thermal overload stage 2 of medium voltage
MVSideThermalOLStage2Alarm
side
Circuit breaker failure current setting of high voltage
HVSideCBFCurrSet
side
Zero sequence current setting of circuit breaker failure
HVSideCBF3I0Set
Negative sequence current setting of circuit breaker
HVSideCBFI2Set
failure of high voltage side
HVSideCBFTime1 Time of circuit breaker failure 1 of high voltage side
425
Chapter 36 Appendix
HVSideCBFTime2 Time of circuit breaker failure 2 of high voltage side
Circuit breaker failure binary input alarm time of high

HVSideCBF BIAlarmTime
voltage side
HVSideCBFOn Enable circuit breaker failure of high voltage side
Circuit breaker failure check negative zero sequence

HVSideCBFChk3I0/I2
current of high voltage side
Circuit breaker failure check position of high voltage
HVSideCBFChkPosn
side
Circuit breaker failure current setting of middle voltage
MVSideCBFCurrSet
side
Circuit breaker failure zero sequence current setting of
MVSideCBF3I0Set
middle voltage side
Circuit breaker failure negative sequence current
MVSideCBFI2Set
setting of middle voltage side
Time of circuit breaker failure 1 of medium voltage
MVSideCBFTime1
side
MVSideCBFTime2
side
Circuit breaker failure binary input alarm time of
MVSideCBF BIAlarmTime
middle voltage side
MVSideCBFOn Enable circuit breaker failure of middle voltage side
Circuit breaker failure check zero negative sequence

MVSideCBFChk3I0/I2
current of middle voltage side
Circuit breaker failure check position of middle voltage
MVSideCBFChkPosn
side
LVSide1CBFCurrSet Undercurrent setting of low voltage side 1
LVSide1CBF3I0Set 1CBF: Zero sequence current setting
LVSide1CBFI2Set 1CBF: Negative sequence current setting

LVSide1CBFTime1
side 1
LVSide1CBFTime2
side 1
Circuit breaker failure binary input alarm time of low
LVSide1CBF BIAlarmTime
voltage side 1
LVSide1CBFOn Enable circuit breaker failure of low voltage side 1
Pole discrepancy check zero sequence current of

LVSide1CBFChk3I0/I2
circuit breaker failure of low voltage side 1
Circuit breaker failure check position of low voltage
LVSide1CBFChkPosn
side 1
LVSide2CBFCurrSet Undercurrent setting of low voltage side 2
LVSide2CBF3I0Set 2CBF: Zero sequence current setting
LVSide2CBFI2Set 2CBF: Negative sequence current setting
426
Chapter 36 Appendix

LVSide2CBFTime1
side 2
LVSide2CBFTime2
side 2
Circuit breaker failure binary input alarm time of low
LVSide2CBF BIAlarmTime
voltage side 2
LVSide2CBFOn Enable circuit breaker failure of low voltage side 2
Pole discrepancy check zero sequence current of

LVSide2CBFChk3I0/I2
circuit breaker failure of low voltage side 2
Circuit breaker failure check position of low voltage
LVSide2CBFChkPosn
side 2
HVSideCBFStarup Circuit breaker failure startup of high voltage side
Trip of circuit breaker failure stage 1 of high voltage

HVSideCBFStage1Trip
side
Trip of circuit breaker failure stage 2 of high voltage
HVSideCBFStage2Trip
side
MVSideCBFStartup Circuit breaker failure startup of medium voltage side
Trip of circuit breaker failure stage 1 of medium

MVSideCBFStage1Trip
voltage side failure
Trip of circuit breaker failure stage 2 of medium
MVSideCBFStage2Trip
voltage side failure
LVSide1CBFStarup Circuit breaker failure startup of low voltage side 1
LVSide1CBFStage1Trip Circuit breaker failure stage 1 trip of low voltage side 1
LVSide2CBFStarup Circuit breaker failure startup of low voltage side 2
Binary input error of circuit breaker failure of high

HVSideCBF BIErr
voltage side
Binary input error of circuit breaker failure of medium
MVSideCBF BIErr
voltage side
Circuit breaker failure binary input abnormal of low
LVSide1CBF BIErr
voltage side 1
Circuit breaker failure binary input abnormal of low
LVSide2CBF BIErr
voltage side 2
LVSideDZ1CurrSet LVSide1DZCurrSet
LVSideDZ1Prot3I0Set LVSide1DZ3I0Set
LVSideDZ1ProtI2Set LVSide1I2Set
LVSideDZ1Time LVSide1DZTripTime
427
Chapter 36 Appendix
LVSideDZ1 BIErrTime LVSide1DZ BIErrTime
LVSide1DZ1On LVSide1DZOn
LVSide1DZ1Chk3I0/I2 LVSide1DZChk3I0/3I2
LVSide1DZTrip LVSide1DZTrip
LVSide1DZ BIErrAlarm LVSide1DZ BIErrAlarm
HVSideStubStage1ProtSet Current setting of stub stage 1 of high voltage side
HVSideStubStage1ProtTime Time of stub stage 1 of high voltage side
HVSideStubStage2ProtTime Current setting of stub stage 2 of high voltage side
HVSideStubStage1ProtTime Time of stub stage 2 of high voltage side
HVSideStubRstTime Stub protection reset time of high voltage side
HVSideStubStage1On Enable stub stage 1 of high voltage side
HVSideStubStage2On Enable stub stage 2 of high voltage side
MVSideStubStage1ProtSet Stub stage 1 current setting of middle voltage side
MVSideStubStage1ProtTime Stub stage 1 time of middle voltage side
MVSideStubStage2ProtTime Stub stage 2 current setting of middle voltage side
MVSideStubStage1ProtTime Stub stage 2 time of middle voltage side
MVSideStubRstTime Stub protection reset time of middle voltage side
MVSideStubStage1On Enable stub protection stage 1 of middle voltage side
MVSideStubStage2On Enable stub protection stage 2 of middle voltage side
HVSideStubStage1Trip Trip of stub stage 1 of high voltage side
HVSideStubStage1PhATrip Trip of stub stage 1 phase A of high voltage side
HVSideStubStage1PhBTrip Trip of stub stage 1 phase B of high voltage side
HVSideStubStage1PhCTrip Trip of stub stage 1 phase C of high voltage side
HVSideStubStage2Trip Trip of stub stage 2 of high voltage side
HVSideStubStage2PhATrip Trip of stub stage 2 phase A of high voltage side
HVSideStubStage2PhBTrip Trip of stub stage 2 phase B of high voltage side
428
Chapter 36 Appendix
HVSideStubStage2PhCTrip Trip of stub stage 2 phase C of high voltage side
MVSideStubStage1Trip Trip of stub stage 1 of medium voltage side
MVSideStubStage1PhATrip Trip of stub stage 1 phase A of medium voltage side
MVSideStubStage1PhBTrip Trip of stub stage 1 phase B of medium voltage side
MVSideStubStage1PhCTrip Trip of stub stage 1 phase C of medium voltage side
MVSideStubStage2Trip Trip of stub stage 2 of medium voltage side
MVSideStubStage2PhATrip Trip of stub stage 2 phase A of medium voltage side
MVSideStubStage2PhBTrip Trip of stub stage 2 phase B of medium voltage side
MVSideStubStage2PhCTrip Trip of stub stage 2 phase C of medium voltage side
Zero sequence current setting of pole discrepancy of

LVSide1PD3I0Set
low voltage side 1
Negative sequence current setting of pole discrepancy
LVSide1PDI2Set
LVSide1PDTripTime Pole discrepancy trip time of low voltage side 1
LVSide1PDOn LVSide1PDOn
Pole discrepancy of low voltage side 1 checks zero or

LVSide1PDChk3I0/I2
negative sequence current
LVSide1PDTrip LVSide1PDTrip
LVSide1PDProtTripPosnErr LVSide1PDProtTripPosnErr
InvTimeOEStage1Time Inverse time overexcitation stage 1 time
429
Chapter 36 Appendix
InvTimeOERstTime Reset time of inverse time overexcitation
OECoolingTime Cooling time of overexcitation
DefTimeOEStage1TripSet Trip setting of overexcitation definite time stage 1
DefTimeOEStage1Time Setting of overexcitation definite time stage 1
OEVoltChanSel Overexcitation protection voltage channel selection
OEVoltRatedVal Rated voltage of overexcitation
DefTimeRstTime Reset time of definite time
OEDropoffCoef Dropoff coefficient of overexcitation
InvTimeOExcitOn Enable inverse time overexcitation
InvTimeOEAlarm Inverse time overexcitation alarm
DefTimeOEStage1On Enable stage 1 of definite time overexcitation
DefTimeOEStage1Alarm Alarm of finite time overexcitation stage 1
OEUsePEVolt Overexcitation uses phase-to-earth voltage
InvTimeOETrip Trip of overexcitation inverse time
430
Chapter 36 Appendix
DefTimeOEStage1Trip Trip of overexcitation definite time stage 1
DefTimeOEStage2Trip Trip of overexcitation definite time stage 2
DefTimeTimeOEStage3Trip Trip of overexcitation definite time stage 3
InvTimeOEAlarm Inverse time overexcitation alarm
HVSideUFFreqSet Underfrequency setting of high voltage side
HVSideUFLoadShedTime Underfrequency time of high voltage side
HVSideDf/dtBlkFreqSet Df/dt blocking frequency setting of high voltage side
Frequency change rate blocking setting of high

HVSideFreqDf/dtBlkSet
voltage side
HVSideUFOn Enable underfrequency of high voltage side
Underfrequency load shedding checking current of

HVSideUFLoadShedChkCurrOn
high voltage side
HVSideUFChkDf/dt Underfrequency check df/dt of high voltage side
Load shedding voltage blocking setting of high voltage

HVSideLoadShedVoltBlkSet
side
Load shedding current blocking setting of high voltage
HVSideLoadShedCurrBlkSet
side
HVSideUFTrip Underfrequency trip of high voltage side
HVSideOFSet Overfrequency setting of high voltage side
HVSideOFTime Overfrequency time of high voltage side
Load shedding voltage blocking setting of high voltage

HVSideLoadShedVoltBlkSet
side
Load shedding current blocking setting of high voltage
HVSideLoadShedCurrBlkSet
side
HVSideOFOn Enable overfrequency of high voltage side
HVSideOFTrip Overfrequency trip of high voltage side
NonElectric1Time Non-electric 1 time
431
Chapter 36 Appendix
NonElectricRstTime Non-electric reset time
NonElectric1On Enable non-electric 1
NonElectric1Trip Non-electric 1 trip
SideDiffStartupSet Startup setting of side differential
SideDiffBreakPoint1CurrSet Knee point 1 current setting of side differential
SideDiffBreakPoint2CurrSet Knee point 2 current setting of side differential
SideDiffSlope1RatioRestrCoef Slope 1 restricted coefficient of side differential
432
Chapter 36 Appendix
SideDiffSlope2RatioRestrCoef Slope 2 ratio restricted coefficient of side differential
SideDiffSlope3RatioRestrCoef Slope 3 ratio restricted coefficient of side differential
SideDiffOn Enable side differential protection
SideDiffCTFailDetectOn Enable CT failure detection of side differential
SideDiffCTFailBlkDiff CT failure blocking differential of side differential
SideDiffPhATrip Phase A trip of side differential
SideDiffPhBTrip Phase B trip of side differential
SideDiffPhCTrip Phase C trip of side differential
CommonWindCTFail CT failure of common winding
SideDiffCurrOverLmtAlarm Current overlimit alarm of side differential
HVSideVTFailCurrSet VT failure current setting of high voltage side
HVSideVTFail3I03I2Set VT failure 3I03I2 setting of high voltage side
VT failure phase-to-earth voltage setting of high

HVSideVTFailPEVoltSet
voltage side
VT failure phase-to-phase voltage setting of high
HVSideVTFailPPVoltSet
voltage side
HVSideVTFailNormalVolt VT failure normal voltage setting of high voltage side
HVSideVTFailBlkTime Unblocking time of VT failure of high voltage side
HVSideVTFailAlarmTime VT failure alarm time of high voltage side
HVSideVTFailBIErr VT failure binary input error time of high voltage side
HVSideVTFailOn Enable VT failure of high voltage side
HVSideNutrPointEarth Neutral point earthing of high voltage side
MVSideVTFailCurrSet VT failure current setting of middle voltage side
MVSideVTFail3I03I2Set VT failure 3I03I2 setting of medium voltage side
433
Chapter 36 Appendix
VT failure phase-to-earth voltage setting of middle

MVSideVTFailPEVoltSet
voltage side
VT failure phase-to-phase voltage setting of middle
MVSideVTFailPPVoltSet
voltage side
VT failure normal voltage setting of middle voltage
MVSideVTFailNormalVolt
side
MVSideVTFailBlkTime Unblocking time of VT failure of medium voltage side
MVSideVTFailAlarmTime VT failure alarm time of middle voltage side
VT failure binary input error time of middle voltage

MVSideVTFailBIErr
side
MVSideVTFailOn Enable VT failure of middle voltage side
MVSideNutrPointEarth Neutral point earthing of middle voltage side
LVSide1VTFailCurrSet VT failure current setting of low voltage side 1
LVSide1VTFail3I03I2Set VT failure 3I03I2 setting of low voltage side
VT failure phase-to-earth voltage setting of low

LVSide1VTFailPEVoltSet
voltage side 1
VT failure phase-to-phase voltage setting of low
LVSide1VTFailPPVoltSet
voltage side 1
LVSide1VTFailNormalVolt VT failure normal voltage setting of low voltage side 1
LVSide1VTFailBlkTime Unblocking time of VT failure of low voltage side
LVSide1VTFailAlarmTime VT failure alarm time of low voltage side 1
VT failure binary input abnormal time of low voltage

LVSide1VTFailBIErr
side 1
LVSide1VTFailOn Enable VT failure of low voltage side 1
LVSide1NutrPointEarth Neutral point earthing of low voltage side 1
LVSide2VTFailCurrSet VT failure current setting of low voltage side 2
LVSide2VTFail3I03I2Set VT failure 3I03I2 setting of low voltage side 2
VT failure phase-to-earth voltage setting of low

LVSide2VTFailPEVoltSet
voltage side 2
VT failure phase-to-phase voltage setting of low
LVSide2VTFailPPVoltSet
voltage side 2
LVSide2VTFailNormalVolt VT failure normal voltage setting of low voltage side 2
LVSide2VTFailBlkTime Unblocking time of VT failure of low voltage side 2
LVSide2VTFailAlarmTime VT failure alarm time of low voltage side 2
VT failure binary input abnormal time of low voltage

LVSide2VTFailBIErr
side 2
434
Chapter 36 Appendix
LVSide2VTFailOn Enable VT failure of low voltage side 2
LVSide2NutrPointEarth Neutral point earthing of low voltage side 2
HVSideVTFail VT failure of high voltage side
HVSideVTFailBIErr Binary input error of VT failure of high voltage side
MVSideVTFail VT failure of medium voltage side
MVSideVTFailBIErr Binary input error of VT failure of medium voltage side
LVSide1VTFail VT failure of low voltage side 1
LVSide1VTFailBIErr VT failure abnormal binary input of low voltage side 1
LVSide2VTFail VT failure of low voltage side 2
LVSide2VTFailBIErr VT failure abnormal binary input of low voltage side 2
HVSideGapOCSet Gap overcurrent setting of high voltage side
HVSideGapOCTime1 Gap overcurrent time 1 of high voltage side
HVSideGapOCTime2 Gap overcurrent time 2 of high voltage side
HVSideGapOVSet Gap overvoltage setting of high voltage side
HVSideGapOVTime1 Gap overvoltage time 1 of high voltage side
HVSideGapOVTime2 Gap overvoltage time 2 of high voltage side
HVSideGapOCTime1On Enable gap overcurrent time 1 of high voltage side
HVSideGapOCTime2On Enable gap overcurrent time 2 of high voltage side
Calculated gap zero sequence voltage of high voltage

HVSideGapCalc3U0
side
HVSideGapOVTime1On Enable gap overvoltage time 1 of high voltage side
HVSideGapOVTime2On Enable gap overvoltage time 2 of high voltage side
MVSideGapOCSet Gap overcurrent setting of middle voltage side
MVSideGapOCTime1 Gap overcurrent time 1 of middle voltage side
MVSideGapOCTime2 Gap overcurrent time 2 of middle voltage side
MVSideGapOVSet Gap overvoltage setting of middle voltage side
MVSideGapOVTime1 Gap overvoltage time 1 of middle voltage side
435
Chapter 36 Appendix
MVSideGapOVTime2 Gap overvoltage time 2 of middle voltage side
MVSideGapOCTime1On Enable gap overcurrent time 1 of middle voltage side
MVSideGapOCTime2On Enable gap overcurrent time 2 of middle voltage side
Calculated gap zero sequence voltage of middle

MVSideGapCalc3U0
voltage side
MVSideGapOVTime1On Enable gap overvoltage time 1 of middle voltage side
MVSideGapOVTime2On Enable gap overvoltage time 2 of middle voltage side
HVSideGapOCTime1Trip Time 1 trip of gap overcurrent of high voltage side
HVSideGapOCTime2Trip Time 2 trip of gap overcurrent of high voltage side
HVSideGapOVTime1Trip Time 1 trip of gap overvoltage of high voltage side
HVSideGapOVTime2Trip Time 2 trip of gap overvoltage of high voltage side
MVSideGapOCTime1Trip Gap overcurrent time 1 trip of middle voltage side
MVSideGapOCTime2Trip Gap overcurrent time 2 trip of middle voltage side
MVSideGapOVTime1Trip Gap overvoltage time 1 trip of middle voltage side
MVSideGapOVTime2Trip Gap overvoltage time 2 trip of middle voltage side
HVSideOLCurrSet Overload current setting of high voltage side
HVSideOLTime Overload time of high voltage side
HVSideOLOn Enabled overload of high voltage side
MVSideOLCurrSet Current setting of middle voltage side overload
MVSideOLTime Time of middle voltage side overload
MVSideOLOn Enabled middle voltage side overload
LVSide1OLCurrSet Overload current setting of low voltage side 1
LVSide1OLTime LVSide1OLTime
LVSide1OLOn Enabled overload of low voltage side 1
436
Chapter 36 Appendix
Current setting of startup airing stage 1 of high voltage

HVSideStartFanStage1CurrSet
side
HVSideStartFanStage1Time Time of startup airing stage 1 of high voltage side
Current setting of startup airing stage 2 of high voltage

HVSideStartFanStage2CurrSet
side
HVSideStartFanStage2Time Time of startup airing stage 2 of high voltage side
HVStartFanStage1On Enable stage 1 of startup airing of high voltage side
HVStartFanStage2On Enable stage 2 of startup airing of high voltage side
Blocking voltage adjustment current setting of high

HVSideBlkVoltAdjCurrSet
voltage
HVSideBlkVoltAdjTime Blocking voltage adjustment time of high voltage side
Enable blocking voltage adjustment of high voltage

HVSideBlkVoltAdjOn
side
HVSideOL Overload of high voltage side
MVSideOL Overload of middle voltage side
LVSide1OL Overload of low voltage side 1
HVSideStartFan1 Startup airing stage 1 of high voltage side
HVSideStartFan2 Startup airing stage 2 of high voltage side
BlkVoltAdj Blocking voltage adjustment
TelectrlObject Telecontrol object
TelectrlCmdSrc Telecontrol command source
TelectrlResult Telecontrol result
TelectrlCmd Telecontrol command
TelectrlType Telecontrol type
FailReason Failure reason
437
Chapter 36 Appendix
SampleValErr Error of sampling value
IEDParmErr Error of IED parameter
ROMSumChkErr Error of ROM sum check
SetErr Error of setting
UnconfirmConnMode Connector mode is not confirmed
SoftConnErr Error of soft connector
SystemCfgErr Error of system configuration
IED CPUModuleErr Error of IED CPU module
SetGrpPointerErr Error of setting group pointer
LogicFileErr Error of logic file
CfgFileErr Error of configuration file
CfgFileInconsist Configured files are inconsistent
IOMatrixErr Error of IOMatrix
BOChkNoResponse Binary output checking has no response
BOBreakdown Binary output breakdown
BIBreakdown Binary input breakdown
BIO CPUErr The CPU of binary input and output works is error
BIO ROMSumErr ROM summing error of binary input and output
BIO EEPROMErr EEPROM error of binary input and output
BIOCfgErr Configuration error of binary input and output
BISelfChkCircuitErr Self-check circuit of binary input is error
BOLatchedPropertyCfgErr Configuration error of binary output latched property
BICommInterrupt Binary input communication is interrupted
BOCommInterrupt Binary output communication is interrupted
SRAMSelfChkErr Self-check error of SRAM
TestStateNotRst Test state is not reset
438
Chapter 36 Appendix
OperFail Operation is unsuccessful
CanCommInterrupt Can communication is interrupted
FLASHSelfChkErr Self-check error of FLASH
WorkInTestSetGrp Work in test setting group
BIInputErr Input of binary input is abnormal
DualPosnInputIncosist Double position inputs are not consistent
BIOInputPowerErr Input power of binary input and output is abnormal
SwitchSetGrpSuccess Switch setting group successfully
CopySetGrpSuccess Copy setting group successfully
WriteIEDSetSuccess Write IED setting successfully
WriteParmSuccess Write equipment parameter successfully
WriteCfgSuccess Write configuration successfully
AdjScaleSuccess Adjust scale successfully
AdjAngleSuccess Adjust angle successfully
HardConnOn/OffSuccess Enable/disable hard connector successfully
SoftConnOn/OffSuccess Enable/disable soft connector successfully
ClearCfg Clear configuration
IEDRst(CPUReboot) IED reset (CPU reboot)
FactoryRst Factory reset
BOTestSuccess Test binary output successfully
ZeroDriftAdjSuccess Adjustment zero drift successfully
ClearAllRptSuccess Clear all report successfully
MaintModeOn Enable maintenance mode
MaintModeOff Disable maintenance mode
AutoRebootAfterCfg Automatic reboot after configuration
MaintState Maintenance state
439
Chapter 36 Appendix
HVSideVoltConn Voltage connector of high voltage side
MVSideVoltConn Voltage connector of medium voltage side
LVSide1VoltConn LVSide1VoltConn
LVSide2VoltConn LVSide2VoltConn
DiffConn Differential protection connector
DiffSideConn Protection connector of side differential
Restricted earth fault protection of high voltage side

HVSideREFConn
connector
Restricted earth fault protection of middle voltage side
HVSideREFConn
connector
HVSideImpedConn High impedance protection connector
HVSideOCConn Overcurrent protection of high voltage side connector
HVSide3I0Conn Earth fault protection of high voltage side connector
Negative sequence current protection of high voltage

HVSideI2Conn
side connector
HVSideStubConn Stub protection of high voltage side connector
Thermal overload protection of high voltage side

HVSThermalOLConn
connector
HVSideCBFConn Connector of high voltage side CBF
HVSideGapConn Gap protection of high voltage side connector
OEConn Overexcitation protection connector
HVSideUFConn Undre frequency connector
HVSideOFConn Overfrequency protection connector
Undervoltage protection of high voltage side

HVSideUVConn
connector
HVSideOVConn Overvoltage protection of high voltage side connector
Zero sequence voltage protection of high voltage side

HVSide3U0Conn
connector
Negative sequence voltage protection of high voltage
HVSideU2Conn
side connector
HVSStartFanConn Startup airing connector of high voltage side
Blocking voltage adjustment protection connector of

HVSBlkVoltAdjConn
high voltage side
HVSideOLConn Overload protection connector of high voltage side
440
Chapter 36 Appendix
MVSideImpedConn Middle impedance protection connector
Overcurrent protection connector of Medium voltage

MVSideOCConn
side
Connector of zero sequence current of middle voltage
MVSide3I0Conn
side
MVSideI2Conn Negative sequence current protection connector
MVSideStubConn Stub protection connector
Thermal overload protection connector of medium

MVSThermalOLConn
voltage side
MVSideCBFConn Connector of middle voltage side CBF
MVSideGapConn Gap protection of medium voltage side connector
Undervoltage protection connector of medium voltage

MVSideUVConn
side
Overvoltage protection of medium voltage side
MVSideOVConn
connector
Zero sequence voltage protection connector of
MVSide3U0Conn
medium voltage side
Negative sequence voltage protection connector of
MVSideU2Conn
medium voltage side
MVSideOLConn Overload protection connector of Medium voltage side
LVSide1OCConn Overcurrent protection connector of low voltage side 1
Connector of the low voltage side 1 zero sequence

LVSide1 3I0Conn
current
Negative sequence current protection connector of the
LVSide1I2Conn
low voltage side 1
LVSide1CBFConn CBF connector of low voltage side 1
Dead zone protection connector of the low voltage

LVSide1DZConn
side 1
pole discrepancy protection connector of the low
LVSide1PDConn
voltage side 1
Connector of the low voltage side1 zero sequence
LVSide1 3U0Conn
voltage
LVSide1OLConn Overload protection connector of low voltage side 1

LVSide2 3I0Conn
current
LVSide2CBFConn CBF connector of low voltage side 2

LVSide2 3U0Conn
voltage
441
Chapter 36 Appendix

LVSide3 3I0Conn
current
InterturnConn Interturn protection connector
442

SIFANG CSC-326EB V2.00 Transformer Protection IED Manual 2020-09

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SIFANG CSC-326EB V2.00 Transformer Protection IED Manual 2020-09

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CSC-326

Transformer Protection IED

Manufacturer: Beijing Sifang Automation Co., Ltd.

Applicability of this manual

Strictly follow the company and international safety regulations.

Do not touch any circuitry during operation. Potentially lethal

Never connect or disconnect wire and/or linker to or from IED

Always connect the IED to protective earth regardless of the

Do not disconnect the secondary connection of current

Do not remove the screw from a powered IED or from an IED

Using the certified conductive bags to transport PCBs (modules).

Do not connect live wires to the IED, internal circuitry may be

When replacing modules using a conductive wrist strap

When installing and commissioning, take care to avoid electrical

About this chapter

CSC-326-EB 4U, 19 2 inches, two-windings, three-winding protection

CSC-326 and BCU scheme

5) The device is equipped with module self-diagnosis function;

Gap protection HV/MV

VT failure 97FF HV/MV/LV1/LV2

Application 1 is shown as below:

Application 2 is shown as below:

Application 3 is shown as below:

3.2 Control function

3.3 Measurement function

3.4 Monitoring function

Position of circuit breaker, disconnector and other switching devices monitoring

Position of circuit breaker monitoring

Auxiliary contacts of circuit breaker monitoring

Disturbance and fault record

3.5 Communication mode

Communication port on the front plate

RJ45 Ethernet communication port

Communication port on the rear plate

Isolated electrical RS485 communication port

Ethernet electrical/optical communication port

Time synchronization port

Chapter 2 Common functions

About this chapter

1 Event record and analysis

1.2 Fault record

1.3 Waveform record

1.4 Sequence of event (SOE)

1.5 Operation record

2.2 Diagnostic principle

3 Time synchronization function

3.2 Synchronization principle

Synchronization from a higher level

Optional synchronization of modules at

Figure 4 Synchronization principle diagram

3.3 IRIG-B code synchronization mode

3.4 PPS synchronization mode

3.5 SNTP synchronization mode

3.6 1588 synchronization mode

Chapter 3 Fault phase selection

About this chapter

2 Function module description

Faulty Phase Selection

Function Key Description

CTFailBlk CT failure blocking sign