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Somu Dailycommands Icc2andprimetime

ICC2 & Synopsis _Primetime commands Daily

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149 views24 pages

Somu Dailycommands Icc2andprimetime

ICC2 & Synopsis _Primetime commands Daily

Uploaded by

Agnathavasi
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1, set_colors -hierarchy_types all -cycle_color ~ it will highlight the ENDCAP cells 12. change_selection [all_macro_cells ] --Select all macros 13, change_selection [all_registers] 14, change_selection [get_cells -hierarchical filter "ref_name-~*FSDP* highlight the flops. 15. change_selection [g ct the Tie off cells 16. change_selection [ get_cells -hierarchical filter "design_type it will select all macros in the design 17. get_attribute [get_design] height —--showing height of the design 18, get_attribute [get_design] width 19. get_attribute [get_core_area] area 20. get_attribute [get_selection] height---- showing selection object height 21. get_attribute [get_selection] width [i [i li > it will cells -hierarchical -filter "ref_name=~*TIE*"]------> it will macro") ==> 22. get_attribute [get_selection] bbox 23. get_attribute [get_selection ] origin ----> it will give origin of selected cell. 24. get_attribute [get_shapes -of objects [get_pins ]] mask_constraint it will show the mask_name of the macro internal pin. 25. get_attribute [get_pins -of_objects [get_selection ]] name-—-> it will show the pin names of particular cells. 26. compute_area [get_attribute [get_selection] bbox] 27. lindex [get_attribute [get_port d&_clk] location] 28. report_design — it will give design info. 29, all_macro_cell-----it will give all macro names 30. get_cells -hierarchical -filter "is_hard_macro" names...it is accurate, use this command) 31. get_cells -hierarchical -quiet -filter "is_hard_macro —= true || is_io — true” will also gives macro names. 32. get_attribute -name boundary -objects [eurrent_block] boundaries(Itx lly, lrx Iry, urx ury, ulx uly) of the block 33. compute_area [get_attribute -name boundary -objects [current_block]] - will give the total area of the block. 34. get_attribute [current_design] name------> it will give tile name. 35. save_block -as / ~----> it will save the design. 36, save_interactive_design -design —-—--> it will save the design... > it will also gives macro > it will give all 37. get_lib_cells -of_objects [get_cells ] | —> find out the library cell used by particular cell 38. get_attribute [get_ports -filter "direction == in" ] name ~ will give the ). set_fixed_objects [get_selection] -unfix. 40. report_placement -hard_macro_overlap macros, lL get_attribute [get_selection] layer pitch — selected net. 42. get_attribute [get_layers M2/M3] -name pitch/min_width/min_spacing - give the values 43. set_attribute [get_cell ] origin {Ix lly} - the respected location. 44, get_attribute [get_cells ] ref_name 45, set_annotated_dclay -net -from 10 specify the delay to the particular net, 46. get_lib_cells -of_objects [get_cells -hierarchical filter "@ref_name =~ *BUF* ‘&& is_physical_only == FALSE"] > it will print all library buf cells 4747. > unfix the selected object. > it will check the overlapping of > it will give the pitch value of the -> it will >it will place the macro to >it will Macro name list foreach_in_collection cell [get_cells -hier -filter "@is_hard_macro—truc" J { set name [get_attribute Seell full_name] echo $name >> inst_list.xt } Particular cell identify purpose. ‘get_flat_cells -hierarchical filter [get_cell "ref_name == *HDPLVT08_FILL_Y2_3*"] Checking feedthroughs check_feedthroughs -unused_feedthroughs net_constraints - topo_constraints 1. eused_feedthroughs - change_selection [ get_timimg_paths - from -to ] Pin violations check_pin_placement -shorts true -missing true -pin_spacing true -wide_track true - wire_track true -self Creating blockages create_placement_blockage -name -boundary { {IIx lly} {urx ury} } - type {hard/partial/soft} -blocked_percentage - > it will add the placement blockage. create_placement_blockage -name bl -type partial -boundary { {160.6260 -381.1200} {193.8000 -283.6800} } -blocked_percentage 30 cteate_placement_blockage -type soft -boundary { {-326.3820 -494.4010} {-208.6755 - 443.6420} } create_channel_partial_blockages -percent_util 50 -buffer_only -channel_width 20 -verbose Creating bounds create_bound -name bpm -type soft -boundary { {-53.5800 75.3600} {-12.4830 115,4400}} [get_flat_cells bpm/*] Report_bounds -—>it gives the bounds reports Creating routing guide create_routing_guide name rguide4 -boundary {{-192.4045 254.0480} {-119.2040 100.4710}} -horizontal_track_utilization 75 -vertical_track_utilization 75 -layers {M1 M2 M3 M4 MS M6 M7 M8 M9 M10} Pin-constraints check_pin_placement -missing true -pin_spacing true -shorts true -wide_track true - wire_track true -self filename ../././eheck_pinplacement.rpt write_pin_constraints -file_name ././..write_pin_constraints.rpt -from_existing_pins - self - physical_pin_constraint {layer |sides joffset) read_pin_constraints -file_name J.4.dvrite_pin_constraints.xpt place_pins -self Removing overlays change_selection [get_cells -filter "name=~ *ovly*" - hier] set_attribute [get_selection ] status placed remove_physical_objects -remove_disconnected Save def write_def -objects [get_selection ] ~/move_port.def read_def ~/move_port.def 7. Moving cells, pushdowns as per offset values set_fixed_objects [get_ports Groopdetected] — -unfix _set_fixed_objects {[get_ports dfs_clk] -unfix s t_fixed_objects [get_cells droopdetect3_ROOT_BUF PUSHDOWN ] -unfix move_objects -delta {-209.88 279} -simple -force write_def -objects [get_selection ]~/move_port.def read_def, move_port.def Macro orientation should only be: MX MY RO R180. get_attribute [get_cells -quict -hicrarchical -filter "design_type — io_pad || design_type —= io || design_type == macro" orientation 10 buffers ar serted on all input signals Visual cheek: change_selection [get_ports * -flter "direction: ‘&& full_name!~VSS && full_name!~*FEED*"] n&Sefull_name!~VDD* AILIO pins in tile are placed and on track. get_ports * -filter "physical_status = unplaced” Retum value should ONLY have Power/Gound net names, no signal pins Keep-Out Margin it will add the halo create_keepout_margin -type hard -outer {left bottom right top} ~ cereate_keepout_mangin -type soft outer {0.5 0.5 0.5 0.5} [all_macro_cells] —> it will add halo. ereate_keepout_margin -type hard -outer {left bottom right top} [get_cells -within {{Ilx lly} {urx uty}} -filter "is_physical_only — false"]------> it will use for cell padding, report_keepout_margin --—-> it will shows the kepout margin info, sizeof_collection [get_keepout_margins ] —> it will give the count of halos. get_keepout_margins -of [get_cells -hierarchical] -type hard---> it retums keepout margins of type ‘hard! from all the cells in the design remove_keepout_margins [get_keepout_margins }-———-> removes all the halos in curren block... GroupPath group_path -from [] -to [] -name -weight - > it will create the path groups according to the paths which we give...... group_path -name SOCCLK -weight 4 ‘group_path name reg_to_macro -from [all_registers ] -to [get_cells -hierarchical - filter "is_hard_macro "] -weight 8 -priority 4 group_path -name macro_to_reg -from [get_cells -hierarchical -filter "is_hard_macro " ]- to [all_registers ] -weight 7 -priority 3 group_path -name grp2 -from { sdmai_body/dma_register/dma_reg_pub/dma_active_fen_id_reg_2_} -weight 6 Locked cells set_placement_status locked [get_cells ] > it will lock the particular cells (Note: we can use unplaced/placed/legalize_onlyifixed/application_fixed options instead of locked...) get_cells get_cells -quiet -filter "is_physical_only — true’ ~ > it will give physical cells. get_cells -quiet * -hier -flter "is_integrated_clock_gating_cell —=true"~—----> it will show the integreted_clock_gating cells get_attribute [get_via_defs -tech [get_techs] -filter "name =~ *_DFM_P*_VIA*"] name ——- > it will show the DFM VIA names get_pins -of_objects [get_nets -of_objects [get_pins [pin_name]]} drver and sinks of the nets, > it will give sizeof_collection (get_cells -of_objects [get_nets ] —~ count of the fanouts of that particular net. -> it will give Connect and Disconnect add_tie_cells -objects -tie_high_lib_cell ts07nxpllogl08hd1057f/HDBLVT08_TIE1_1 -tie_low_lib_cell ts07nxpllogl08hd10S7/HDBLV T08_TIE0_1 ~ > it will connect the tile cells. connect_net ----> it will connect the net to particular pin, Disconnect_net -----> It will discoonect the net to particular pin connect_pins -incremental -driver -———----> it will connect the output pin to other cell input pin if two cells are in diiferent hierarchy Find route length get_attribute [get_nets ] route_length —> it will give which layer layer routed which distance(ex: M4{20},MS {30} .. If lower layer routed most distance we can change to upper layer so, net delay will reduce. Records the fixes (like DRC ).. it won't record cell movement- Record_layout_editing -start .tel To Get Feed through info emnds: change_selection [get_ports FE*] > it will highlight the feedthroughs sizeof_collection [get_ports FE*] —> it will give count of feedthroughs sizeof_collection [get_ports FE* -filter "physical_status — fixed"] of placed feedthroughs -> it will give count sizeof_collection [get_ports FE* -filter "physical_status — unplaced” count of unplaced feedthroughs. > it will give ECO COMMANDS: add_buffer_on_route - repeater_distance 75 ~cell_prefix -net_prefix -punch_port-----> It will add the buffers every 7Smicrons 1 split_fanout -max_fanout 8 -net -on_route -net_prefix - cell_prefix -lib_cell > it will split the net according to the sinks (its usefull) 2. add_buffer_on_route -repeater_distance -cell_prefix - net_prefix —punch_po tt add_buffer_on_route -repeater_distance_length_ratio <0,5> -cell_prefix -net_prefix -punch_port Options: -repeater_distance -we need to specify a distance for this in microns. Tool will lay down buffers at that ratio -repeater_distance _length_ratio need to give a ratio (Example 0.1,0.2). If its 0.1 tool will lay buffers for every 10% of route length -punch_port - This will be useful to connect easily between hierarchies add_buffer_on_route -cell_prefix tran_fix_sept25 -detect_layer -lib_cell */ecObfn000abIn1 6x5 -location {144,001 1.036} [get_nets gti_eucp_dft_ugt] —> add buffer on routing net at particular location. add_buffer_on_route gti_eucp_dft_ugt -lib_cell ecObfn000ab1n16x5 -location {144.001 1.036} -detect_layer -punch_port > same above add buffer on routing net at particular location, add_buffer_on_route -repeater_distance 60 gtipdssmparS_wrap|/msarb_fork_sbus_data_d63788d678d88775d8b5 187dff83d59b_STAR T sbus_int.eu_sbus_data[178] -lib_cell ecObfn000ab1n28x5 -----using repeater distance add_buffer_on_route -repeater_distance_length_ratio 0.5 gtipdssmpar5_wrap]/msarb_fork_sbus_data_d63788d678d88775d8b5187df83d59b_STAR Es sbus_int.eu_sbus_data[178] -lib_cell ecObfn000ab1n28x5----—-using route repeater distance length distance length ratio. add_buffer_on_route [get_net sef_scf_smn_ScfSmnRouterR2_VSOC_ScfSmnTniuSYSTEMHUBO0_flit_RegFlitData[30] |] -first_distance 2 -lib_cell HDBLVT08_BUF_8 -repeater_distance 80 -punch_port - cell_prefix cksong_div_1004 —> it placed the first cell after 2 microns after that every 80 microns it will place the cell. ‘get_attribute [get_nets ] route_length or change_selection [get_nets ] get_attribute [get_selection] route_length----- This will give route length in each metal size_cell insert_buffer size_cell atipdssmparS_wrap|/sc_fl_avs_fork_top1/sc_fl_avs_forkO/target_demux2/demux2/route_o pt _Topt_mt_inst_2680867 ecObfn000ac1n20x5 insert_buffer ¢gtipdssmparS_wrapl /scunit/sc_mainO/scunitx/sc_cachel/sc_cache_controll se_cache_eb b _mask_fifool/gt_fifo_flopped_out_strg/wrdata_f_re ec0bfn000ac1n02x3 ) b12_b13_b14_b15_qreg/d1 insert_buffer [get_pins {n46_oss_sdma_t_G0_SOC_xtrigger_refelk_node/fixhold_18082017_fullchip_11_0/A}] HDBSVTI1_BUF_1 -new_net_names {fet0924_PTECO_HOLD_NET42} - new_cell_names {fet0924_PTECO_HOLD_BUF42} -location {281.9220 -381.1200} ~ buffer in particular location. > inserting the fanout 16 -net [get_nets gtIpdssmparS_wrap1/scandfxgtipdssmparSunit/Scandfxgenunit |_overpv_class40/scandfx_e dt_interp1/scandfx.edt_400ch.inst/scandfx_80r3_400ch_edt_controller_ Veonfig0_decoder3 / ropt_net_2143431] -cell_prefix eco_data_tran_fix_ww38p2_cell -net_prefix eco_data_tran_fix_ww38p2_net —> split the load set_cell_location -coordinates {259.0200 303.1440} gtipdssmparS_wrap]/Ibdmunit I/dm_sc_inf0/eco_tran_ww39p3_fix --> set the particular location of the cell. disconnect_net -net eco_net_0_gti_euep_dfi_ugt diode_on_partition_ports_gti_eucp_dft_ugvdpd1 —> for net to pin connection problem , disconnecting the particular net connection emd. connect_net -net gti_euep_dft_ugt diode_on_partition_ports_gti_euep_d --> for net to pin connection problem, connecting the particular net is connect the particular pin, report_global_timing -d. timing violations /_type max -separate_all_groups —> it showing setup overall report_global_timing -delay_type min -separate_all_groups —> it showing hold overall timing violations write_changes -format ice? -output ~/example.tel — for saving .tcl file whatever u changes Convert buffer to inverter: set_reference -block [get_lib_cells ecOpp60_bn/ecOinv000r1n32x5] -pin_map {a ao ol} [get_cells gtipdssmpar2_wrap]/sbe_ssbuf1/port[1].sbe_sslat/place_opt_BUFT_RR_829347] -> convert buffer to inverter pair Generating netlist write_verilog -compress gzip -exclude { physical_only cells scalar_wire_declarations eaf_module_declarations filler_cells pg_objects } .v.gz PT-Shell report_global_t timing violations ming -delay_type max -separate_all_groups —> it showing setup overall report_global_timing -delay type min -separate_all_groups —> it showing hold overall timing violations estimate_eco -type size_cell -lib_cell ecOpp60gtalpha_bn_p1274d7_ttit_v085_1100_max_cest_IvflecOfuy003ab2n08x5 gtIpdssmpar2_wrapl/sbe_ssbufl/sbe_ssfrag/ssbe_sbe_req_sender/gt_credit_inf_put_sende ‘it ar{0].countericredits_gte_f_reg{1][0] —> before applying eco it showing after applying eco how-much we have to get benefit (means estimation of eco), report_timing -capacitance -nets -input_pins -transition_time -nosplit general timing command in pba mode. get_attribute [get_nets -of_objects [gct_pins agtipdssmparS_wrap l/scunit /sc_main|/st_sc_infififo/gt_fifo.t_fifo_opt.fifo_inst/gt_fifo_ str gilatched_data_reg_2_b108_b109_b110_b111_qreg/o*]] total_coupling_capacitance — ~> it showing coupling capacitance of pin. report_analysis_coverage -status_details untested > my_file.txt —> analysis coverage of comer check_timing -verbose -override_defaults clock_crossing —> Information: Checking ‘clock_crossing’. Insert_butfer pin_name buffer_name —> insert_buffering Ex: insert_buffer sstIpdssmparS_wrap1/scunit l/sc_main0/scunitx1/se_cache1/sc_cache_controll /se_cache_eb b _mask_fifol/gt_fifo_flopped_out_strg/wrdata_f_reg_0_b12_b13_b14_b15_qreg/d1 ecObfn000acI n02x3 Size_cell cell_name sizeing_cell —> up/down sizing Ex: size_cell atlpdssmparS_wrap|/sc_fl_avs_fork_top]/sc_fl_avs_forkOstarget_demux2/demux2/route_o pt _Topt_mt_inst_2680867 ecObfn000ac1n20x5 report_timing -from ‘stIpdssmpar4_wrap] /maunit2/ma_outarb1/m: sveuX_obus_queuelfifout_pre_reg(8] -to gtIpdssmpard_wrap|/maunit2/ma_clkgatefubl/ma_clock_gate_b_rtl_clk_gate_ieg 0 - transition_time -capacitance -nets -delay_type max -input_pins -pa_mode exhaustive - path_type full_clock_expanded lable_outarb_insEU_REQ(2].ma_rgb_in all_fanin -to gtlpdssmparS_wrap]/scunitl/sc_common|/sc_cache_datal/sc_cache_bOUSt BB O/get_cbb.cbb_inst/prim_row0]-prim_colfO] last gfxwrapram_cbbinst /ary_6851212112.i p7 4d6npOvrfip2rlw68x512_instOsirenO -flat -startpoints_only -only_cells, all_fanout -from gtIpdssmparS_wrap|/gctunit_dop_Ixclk_gtdssmIxspine_} 5_elxclk/elk -flat -endpoints_only -only_cells |_tib7_1292_c307d_gtIpdssmpar report_timing [get_pins -of_objects [all_fanout -from gtlpdssmparS_wrap|/gctunit_dop_Ixclk_gtdssmlxspine_h_rib7_1292_c307d_gtlpdssmpar 5_clxclkielk -flat -endpoints_only -only_cells) -filter “direction=—iné&écis_clock_pin!=true"] history ././././fix_eco > pt_commands.rpt —> saving file report_timing -path_type full -delay_type max -max_paths 1 --> report worst timing path report_timing -path_type full -delay_type max -max_paths 1 -group e1xclk_gtdssmlxspine > reports worst timing path at particular group report_timing ~delay_type min -group clxclk_gtdssmIxspine —> reports hold timing at particular clock group report_timing ~delay_type max -group c1xclk_gtdssm1xspine ~ particular clock group reports setup timing at report_timing -group [get_path_groups *] --> reports timing all groups report_net -connections -verbose ‘gtIpmsampparl_wrap l/ereunit /crer! /ereretrll /erectr] k ed_strg/rpdpriv_rdsel_int[42] —> report net connections ;e_ram[1].ctrl_ste_ram/gt_ram_pac report_timing delay type max_rise -transition_time -capacitance -nets -input_pins -from gtIpmsampparl_wrap1 ereunit /erer! /creretrll crectrl_sre_ramf1 ].ctrl_sre_ram/gt_ram_pac k ed_strgtpd_genram_rdsel_drvr_s1p0_10/o1 —> reports timing for max rise write_changes -format ice2 output ~/example.tel — for saving .tcl file whatever u changes eco_netlist eco_netlist -by_verilog_file eco.v \ -compare_physical_only_cells - write_changes eco_changes.tel place_eco_cells place_eco_cells -legalize_mode minimum_physical_impact \ - eco_changed_cells - legalize_only -displacement_threshold 10 _ IEEE EEE EEE pre_floonplan_checks ##H#HHHHHHHAHAHA HEH check_design -checks {dp_pre_floorplan} dp_pre_create_placement_abstract, dp_pre_block_shaping dp_pre_macro_placement dp_pre_power_insertion dp_pre_pin_placement dp_pre_create_timing_abstract dp_pre_timing_estimation dp_pre_budgeting dp_floorplan_rules _HaraHteeEHEEH Setting Macro Constraints ####Htiiiitiiinniitie set macro_cells [get_cells -physical_context -filter "is_hard_macto && tis_physical_only" - quiet] set_macro_constraints -allowed_orientations {RO R180} $macro_cells report_macro_constraints _ Haste floorplan initialization at #initialize_floorplan -core_utilization 0.60 -core_offset 15 —-—-—> Sqaure shape Hinitialize_floorplan -core_utilization 0.6 -shape U -orientation N -side_ratio {211 1 Lay core_offset 15 -coincident_boundary true —> U shape ‘initialize floorplan -core_utilization 0.6 -shape L -orientation N -core_offset 15 - coincident_boundaty true -side_ratio {1111} > L shape #initialize floorplan -core_utilization 0.6 -shape T orientation N -core_offset 15 - coincident_boundary true -side_ratio {1 12121} —-> Tshape #initialize floorplan -core_utilization 0.6 -shape R -orientation N -core_offset 15 - coincident_boundary true -side_ratio (10 3} -boundary {{0 0} {150 300}} -——>R shape #initialize_floorplan -control_type die -boundary { {0.0} {0 3000} { 1000 3000} {1000 2000} {2000 2000} { 2000 3000} {3000 3000} { 3000 0} {2000 0} { 2000 1000} { 1000 1000} {1000 0}} -core_offset 100 —> H shape open_block Jevprj059/projects/raAwork/pdteanvevil Stusr7/thz/testI/latest/reflector_array_netlist.d lib:reflectoraray_aug02_Spm.design _ HAE EEE tap cll insertion Has AIEEE get_lib_cells *TAP* create_tap_cells -lib_cell saed 14rvt_frame_timing_ccs‘SAEDRVTI4_TAPDS - pattem stagger ~distance 15 ‘aaa get_lib_cells *TAP* create_tap_cells -lib_cell tebn28hpeplusbwp30p140ssg0p81v125e_ces/TAP ~distance 10 create_tap_cells -lib_cell EXPLORE_physical_only/TAPCELLBWP30P 140/frame - pattem stagger ~tistance 10 LBWP30P140 -pattem stagger “AEREEEAEHE EE EAE HE boundary cells insertions: iahi atta get_lib_cells *BOUND* tebn28hpeplusbwp30p140ssg0p81v125e_ces/BOUNDARY _LEFTBWP30P140 create_boundary_cells -tap_distance 10 -left_boundary_cell tcbn28hpeplusbwp30p140ssg0p8 lv125¢_ccs/BOUNDARY_LEFTBWP30P 140 - right_boundary_cell tcbn28hpeplusbwp30p140ssg0p8 1 v125e_ccs/BOUNDARY _LEFTBWP30P140 -top_boundary_cell tcbn28hpeplusbwp30p 140ssg0p81v12Se_ces/BOUNDARY_LEFTBWP30P 140 - bottom_boundary_cell tcbn28hpeplusbwp30p140ssg0p81v125e_ccs/BOUNDARY_LEFTBWP30P 140 create_boundary_cells -tight_boundary_cell tebn28hpeplusbwp30p140ssg0p81v125¢_ccyBOUNDARY_RIGHTBWP30P 140 - left_boundary_cell tcbn28hpeplusbwp30p140ssg0p81v125¢_ces/BOUNDARY_LEFTBWP30P140 create_boundary_cells -tap_distance 10 -top_boundary_cell tcbn28hpeplusbwp30p140ssg0p8 1v125e_ccs/BOUNDARY_RIGHTBWP30P 140 - bottom_boundary_cell tcbn28hpeplusbwp30p 140ssg0p81v125¢_ccs/BOUNDARY_LEFTBWP30P 140 create_boundary_cells -tap_distance 20 -left_boundary_cell - right_boundary_cell to fix the status _ YE EEE LO Giller cells FEE create_io_filler_cells -prefix filler_reference_cells {{ FILLER20A FILLERIOA FILLERSA FILLERIA FILLEROSA FILLEROOOSA }} > for inputs in }] (or) place_pins -ports > for outputs out}] (or) place_pins -ports ‘HHH atest terahertz filler cells before GDS extraction Hii ( avoid density errors) set pnr_std_fillers "*FILL*" set std_fillers "” foreach filler $pnr_std_fillers { lappend std_fillers "*/S{filler}" } create_stdcell_filler -lib_cell $std_fillers connect_pg_net -net VDD [get_pins -hierarchical "*/VDD"] connect_pg_net -net VSS [get_pins -hierarchical "*/VSS"] ‘EERE powerplan|L AHHHAE HEE ‘HH create ports vdd vss sit create_port -port_type ground -direction in VSS create_port -port_type power-direction in VDD. ‘iti create nets vdd vss Httt create_net -power VDD create_net -ground VSS +##H#4 connect ports to nets HHH connect_pg_net -net VDD [get_port VDD] connect_pg_net -net VSS [get_port VSS] connect_pg_net -net VDD [get_pins -hierarchical */VDD] connect_pg_net -net VSS [get_pins -hierarchical */VSS] ‘##4## to dissable via connection during compile pg set_app_options -name plan.pgroute.disable_via_creation -value true ‘HAM to create rail Hitt create_pg_std_cell_conn_pattem rail_pattem -layers MI -rail_width 0.15 set_pg_strategy MI_rails -core -pattem { {name: rail_pattem} nets: VDD VSS} compile_pg -strategies M1_rails ‘ttt define pg mesh for m2 t0 m7 layers (only core region) tit create_pg_mesh_pattern M4toM7 -layers { {{vertical_layer: M4} {spacing minimum} {pitch: 2.2} {width: 0.22} (offset: 0.6}} {{vertical_layer: M6} {spacing: minimum} {pitch: 24} {width:0.24} {offset: 0.6}} {{horizontal_layer: MS} {spacing: minimum) {pitch; 2.6} {width:0.26} {offset: 0.6}} { {horizontal layer: M7} {spacing: minimum} {piteh: 3} {width:0.5} {offset: 0.6}}} set_pg_strategy pg_mesh -core -pattem { {name: M4toM7 } {nets: VDD VSS }} - extension {{stop: 0.2) flayers: M4} } compile_pg -strategies pg_mesh ‘Hite AHHREPH define pg for M9 M8 s#ifiitideRittH create_pg_mesh_pattern M9 -layers { {orizontal_layer: M9} {width: 1.0} {pitch: 3} {spacing: minimum} {offset: 0.9}} set_pg_strategy ring_pg_M9 -design_boundary -pattem {{name: M9 } {nets: VDD VSS }} - extension { {stop: design_boundary_and_generate_pin}} compile_pg -strategies ring_pg_M9 create_pg_mesh_pattern M8 -layers { {vertical _layer: M8 } {width: 1.0} {piteh: 6) {spacing: minimum} {offset: 1.4}} set_pg_strategy ring_pg_M8 -design_boundary -pattem { {name: M8 } {nets: VDD VSS }} - extension {{stop: 1} {layers: M9}} compile_pg -strategies ring_pe_M8 ‘itt checks after pg mesh HH check_pg_dre HH create via creation HHIHHIHHIH Ht md tom HHH set_pg_via_master_rule M4_MI -contact_code {VIA12_LONG_H VIA23_lcut_V VIA34_LONG_HH} create_pg_vias -nets {VDD VSS} -from_layers M4 -to_layers M1 -via_masters M4_MI - allow_parallel_obj check_pg_dre check_pg_missing_vias #M5_M4333 set_pg_via_master_nule M5_M4 -contact_code {VIA45_LONG_V} create_pg_via! {VDD VSS} -from_layers M5 -to_layers M4 -via_masters MS_M4- allow_parallel_objects -within_bbox [get_attribute [current_block] bbox] check_pg_dre check_pg_missing_vias # M6_MS set_pg_via_master_tule M6_MS -contact_code {VIAS6_leut_V} create_pg_vias -nets {VDD VSS} -from_layers M6 -to_layers MS -via_masters M6_MS - allow_parallel_objects -within_bbox [get_attribute [current_block] bbox] check_pg_dre check_pg_missing_vias #M7_M6 set_pg_via_master_rule M7_M6 -contact_code {VIA67_lcut} create_pg_vias -nets {VDD VSS} -from_layers M7 -to_layers M6 -via_masters M7_MG6 - allow_parallel_objects -within_bbox [get_attribute [current_block] bbox] check_pg_dre check_pg_missing_vias #M8_M7 set_pg_via_master_tule M8_M7 -contact_code {VIA78_leut} create_pg_vias -nets {VDD VSS} -from_layers M8 -to_layers M7 -via_masters M8_M7- allow_parallel_objects -within_bbox [get_attribute [current_block] bbox] check_pg_dre check_pg_missing_vias #M9_M8 set_pg_via_master_rule M9_MB -contact_code {VIA89_lcut} create_pg_vias -nets {VDD VSS} -from_layers M9 -to_layers M8 -via_masters M9_M8 allow_parallel_objects -within_bbox [get_attribute [current_block] bbox] check_pg_dre check_pg_missing_vias ts -within_bbox [get_attribute [current_block] bbox] _ I EEE EEE EEE powerplan 2 HEHEHE remove_pg_via_master_rules -all remove_pg_pattems -all remove_pg_strategies -all remove_pg_strategy_via_rules -all create_net -power VDD create_net -ground VSS create_pg_ring_pattern ring_pattem -horizontal_layer M9 -horizontal_width {3} - horizontal_spacing {1} -vertical_layer M9 -vertical_width {3} -vertical_spacing {1} set_pg_strategy core_ring -pattemn {{name: ring_pattem} {nets: {VDD VSS }} {offset: {1 1}}} - core -extension { {stop: design_boundary_and_generate_pin}} compile_pg -strategies core_ring ditt 1st level grid tint create_pg_mesh_pattern mesh_pattem -layers { {{vertical_layer: M6} {width: 1.5} {pitch: 5} {offset: 5} { trime: true }} { {horizontal_ layer: MS} {width: 1.2} {pitch: 5} offset: 5} {trim : true} }} set_pg_strategy MSM6_mesh -pattem { {name: mesh_pattern} {nets: VDD VSS }} - core - extension { {stop: design boundary} } compile_pg -strategies MSM6_mesh ‘Hiei Ind level grid sata create_pg_mesh_pattern mesh_pattem -layers { {{vertical_layer: M5} {width: 1} {piteh: 3) {offset: 1.7} { trime: true }} {{horizontal_layer: M4} {width: 0.89} {piteh: 1.7} {offset: 1.5) {trim true}}} set_pg_strategy M4MS_mesh -pattem { {name: mesh_pattern} {nets: VDD VSS }} - core - extension { {stop: core_ring}} compile_pg -strategies M4MS_mesh ‘HORI alls aaa create_pg_std_cell_conn_patter rail_pattemn -layers MI -rail_width 0.9 set_pg_strategy MI_rails -core -pattem { {name: rail_patten} nets: VDD VSS} compile_pg strategies M1_rails ‘#unsueaieaaHH#E checks after powerplan ##HHHAHAHHHH check_pg_dre -nets {VDD VSS} analyze_power_plan -teport_track_utilization_only check_pg_missing_vias ‘before placement we should do ‘Hitt buffer adding at each portstiHisHiihiitiitiithit iri remove_from_collection [get_port *] {clk I1 12 VDD VSS} report_utilization, check_design -checks pre_placement_stage add_buffer -lib_cell [remove_from_collection [all_inputs] {clk 11 12 VDD VSS}] legalize_placement add_buffer -lib_cell [all_outputs] legalize_placement set_placement_status fixed [get_cell eco_cell*] #avoid overlapps legalize_placement ito set dont touch on net & cell get_cells eco_cell* set_dont_touch [get_cell eco_cell*] get_nets eco_net* set_dont_touch [get_nets eco_net*] check_pg_dre sizeof_collection [get_cells eco*] # connect_pg_net -net VDD [get_pins -hierarchical */VDD] connect_pg_net -net VSS [get_pins -hierarchical */VSS] check_pg_dre ‘Hi prefixing the newly added cells during place_opt st set_app_options -name opt.common.user_instance_name_prefix -value "newly_added” #opt.common.user_instance_name_prefix newly_added 4H do not use CK buff during placements ### set_lib_cell_purpose ~include none [get_lib_cells */CK*] ‘#iFHiH#iF# do not use high drive strength cell for better, tilizations Hesse set_lib_cell_purpose -include none [get_lib_cells {*/*D12* */*D16*#/*D20* *D24*}) Add checks before place cells itil tat aHHAHEBHERH report_gor -summary report_design report_utilization -verbose check_pg_dre check_pg_missing_vias check legality check_boundary_cells report_scenarios report_parasitic_parameters report_utilization _ YEE EE EEE placement create_placement -timing_driven -effort medium -congestion -congestion_effort, medium or create_placement -incremental -timing_driven -congestion set_app_options -name place.coarse.continue_on_missing_scandef -value 1 Ligalize_placement place_opt Ligalize_placement set_app_options -name time.disable_recovery_removal_checks -value false set_app_options -name time.disable_case_analysis value false set_app_options -name place.coarse.continue_on_missing_scandef -value true set_app_options -name plan.place.auto_create_blockages -value auto set_app_options -name opt.common.user_instance_name_prefix -value place set_app_options -name place.coarse.auto_density_control -value true ‘Hitt magnetic placement #i#ititit magnet_placement [get_cells "INST_1"] —> performs magnet placement on the INST_I cell ‘magnet_placement -mark_fixed [get_cells "INST_2"] --—+ performs magnet placement and marks the moved cells as fixed afterwards magnet_placement -logical_ levels 2 [get_cells "INST_2"] --— pulls two levels of cells to INST_2 ditdsdl bounds creation #iitititittit create_bound -effort high -name bound1 {celll cell2 cell3 ... celln} —-—+ Create a group bound for the collection of island of cells/macros create_bound -name "movebound1" -boundary { {50 60} { 40 80}} -type hard - exclusive {invA1 reset} -— creates a hard exclusive move bound named "move bound1" with square bound shape. The bound contains the invA cell and reset port. ‘Hitutttttt# keepout margin / cell padding Hist create_keepout_margin type soft -outer {10 10 10 10} [get_cells MY_LEAF_CELL] ‘itt to reduce congestion biw hard macros & perform coarse placement ##### set_app_options -name plan.place.congestion_driven_mode -value macro create_placement -floorplan -congestion -congestion_effort high +##H## timing-driven placement only to standard cells ######## set_app_options -name plan.place.timing_driven_mode -value std_cell create_placement -floorplan ~ Cel_2 Cel_3} sit Combined Congestion-Driven and Timing-Driven Placement tae set_app_options -name plan.place.congestion_driven_mode -value both set_app_options -name plan.place.timing_driven_mode -value both create_placement -timing_driven -buffering_aware_timing_driven -congestion effort high - congestion_effort high -incremental ‘Hit#iHtHHHHH individual stages placement ##H#tH#tH#tH# place_opt -from initial_place -to initial_place report_utilization place_opt -from initial_dre -to initia report_utilization place_opt -from initial_opto -to initial_opto report_utilization place_opt -from final_place -to final_place report_utilization place_opt -from final_opto -to final_opto report_utilization legalize_placement incremental check_legality -verbos report_congestion report_utilization iming_drivenmagnet_placement INST_3 -cells {Cel_1 dre tata ite eg OE create_placement_blockage -boundary {} # Simulated list of antenna numbers set antenna_numbers [list 1 2.3 45] # Adjust this list according to your needs # Iterate through the list of antenna numbers and rename instances foreach num $antenna_numbers { set old_instance_name "PR_num” sel new_instance_name "antennaSnum" # Logic to replace old_instance_name with new_instance_name in your design # Replace the following line with your design manipulation logic # Example: replace_in_design Sold_instance_name $new_instance_name puts "Renamed instance Sold_instance_name to $new_instance_name" } In this example, we assume you have a list of antenna numbers (antenna_numbers) that correspond to the instance names you want to replace. The script iterates through this list and renames instances of "PR_num" to "antennal," "antenna2," and so on, Please note that the script above is a simplified representation. You'll need to replace the comments with actual code that interacts with your design. The exact code will depend on the tools or environment you're using for your design. Make sure to adjust, the script to match your design manipulation logic and toolset. eteeaaHBREeeeeclock treetitenttee Jevprj059/projects/ra/work/pdteam/evl I Stusr6/terahertz/floorp lan/scripts ‘te tac OE EE check_routability set_app_options -name route.detail.timing_driven -value true set_app_options -name route.track.timing_driven -value tue set_app_options -name route.track.crosstalk_driven -value true set_app_options -name route.global.timing_driven -value true remove_ignored_layers -all set_ignored_layers “min_routing_layer M1 \_ #$Min-Routing-Layer -max_routing_ layer M9 # SMax-Routing-Layer route_auto -max_detail_route_iterations 5 -reuse_cxisting_global_route true - stop_after_track_assignment true -save_after_global_route true - save_after_track_assignment true route_global -congestion_map_only true -routing_utilization_only true - reuse_existing_global_route true route_track route_detail -max_number_iterations 3 incremental true -initial_dre_from_input true route_eco -open_net_driven true -max_detail_route_iterations 2 -reroute modified_nets_first_then_others route_opt _EEREEEAE HEE AE ERE EERE EERE EEE cts AFA EEEEEE ‘HEHEHE specify clock cells to build clock tree #it#itsisiitittat set_lib_cell_purpose -include cts [get_lib_cells *CK*] set_lib_cell_purpose -include optimization [get_lib_cells *CK*] ‘itt specifying don’t use cells Hitintiattitit ‘#set_lib_cell_purpose -include none [get_lib_cells BU*] +#set_lib_cell_purpose -include none [get_lib_cells DC*] ‘set_lib_cell_purpose -include none {get_lib_cells IN*] tiset_lib_cell_purpose -include none [get_lib_cells MU*] set_lib_cell_purpose -include none [get_lib_cells AOT*] ‘HIHHIERIEHHEHHE specify app options ##sHaHanitit set_app_options -name cts.common.max_fanout -value 10 tiset_app_options -name cts.compile.primary_comer -value slow_reworst set_app_options -name cts.compile.temove_existing_clock_trees -value true ‘#set_app_options -name cts.compile.global_route_aware_buffering -value true set_app_options -name clock_opt.place.congestion_effort -value high set_app_options -name time.remove_clock_reconvergence_pessimism -value true ‘Hittin setting clock skew & latency requirements #iHititit set_clock_tree_options -target_skew 0.1 -comers [all_comers ] set_clock_tree_options -target_latency 0.1 -comers [all_comers ] satel tate egttteitt setting DRV requirements #iftitttiiittaiittt set_max_transition 10 -clock_path [all_clocks ] -scenatios [all_scenarios] set_max_capacitance 10 -clock_path all_clocks ] -scenarios [all_scenarios] ‘HAHA MIM. HEE #source fevprj059/projects/ra/work/pdteam/evll Stusr6/terahertz/floorplan/scripts/ple_memm.t cl aba NID source Jevprj059/projects/ra/work/pdteam/evlI Stusr6/terahertz/floorplan/scripts/NDR_rules report_routing_rules ditt clock spacing rule titi set_clock_cell_spacing -x_spacing 2 -y_spacing 2 ‘odbaeueee TITRE Hide set_app_options -name cts.multisource.flexible_htree_synthesis -value true synthesize_clock_trees clock_opt -from build_clock -to route_clock set_freeze_ports -clock spi_clk_in ‘Hi LE LEE RCOUting. With less no of itterations#f##itiitiyt route_auto -max_detail_route_iterations 5 -save_after_global_route true - save_after_track_assignment true -save_after_detail_route true - reuse_existing_global_route true route_auto -max_detail_route_iterations 5 -save_after_global_route true - save_after_track_assignment true -save_after_detail_route true - reuse_existing_global_route true Use this command to control number of routing iterations ‘EAE A bata Eg write_verilog -top_module_first netlist.v write_sde -output routed.sde set a [get_object_name [all_comers]] foreach comer Sa { #ourrent_comer $comer write_parasitics -format spef -comer Scomer output ${DESIGN_NAME}_${comer} t To generate spef for all comers write_saif design_name.saif move routed Select one net to tel file : write_routes -objects [get_selection] -output mystripes.tel To write any all routes into on file: write_routes -output all_routes.tel remove routes -stripe : to remove all stripes or routes

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