SINCLAIR

ZX Spectrum 128

Service Manual
Edited by Brendan Alford

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CONTENTS
1 System Description .................................................................................................................................... 4
1.1 Introduction ........................................................................................................................................ 4
1.2 Architecture ........................................................................................................................................ 5
1.3 Z80A CPU............................................................................................................................................. 5
1.4 Memory Organisation ......................................................................................................................... 7
1.4.1 Read/Write Operations and Bus Arbitration ............................................................................... 8
1.5 Input/Output ..................................................................................................................................... 11
1.5.1 TV Picture Generation and Sound Output ................................................................................. 11
1.5.2 Keyboard Scanning ..................................................................................................................... 12
1.6 Tape Interface ................................................................................................................................... 15
1.6.1 ULA Sound Output ..................................................................................................................... 15
1.7 Programmable Sound Generator ...................................................................................................... 16
1.8 RS232/Midi Interface ........................................................................................................................ 17
1.9 Keypad Scanning ............................................................................................................................... 17
1.9.1 Reset Protocol ............................................................................................................................ 18
1.9.2 Bit Transfer Protocol .................................................................................................................. 19
1.10 Power Supplies ................................................................................................................................ 20
2 Disassembly/Assembly ............................................................................................................................. 22
2.1 Disassembly....................................................................................................................................... 22
2.2 Assembly ........................................................................................................................................... 22
3 Setting Up and System Test ..................................................................................................................... 24
3.1 Setting Up Instructions ..................................................................................................................... 24
3.2 System Test ....................................................................................................................................... 24
4 Fault Finding and Repair .......................................................................................................................... 25
4.1 Introduction ...................................................................................................................................... 25
4.1.1 Test Equipment .......................................................................................................................... 25
4.2 Fault Diagnosis .................................................................................................................................. 27
4.2.1 Techniques ................................................................................................................................. 27
4.2.2 Power Supply Unit...................................................................................................................... 27
4.2.3 Initialisation................................................................................................................................ 27
4.2.4 Symptomatic Faults.................................................................................................................... 29

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4.3 Repair ................................................................................................................................................ 29

5 Parts List ................................................................................................................................................... 33
5.1 Introduction ...................................................................................................................................... 33
5.2 Notes to Table 5.4 ............................................................................................................................. 33
5.3 Case Assembly Components ............................................................................................................. 34
5.4 Main PCB Components ..................................................................................................................... 35
5.5 Keypad PCB Components .................................................................................................................. 40
5.6 Part Number References................................................................................................................... 41
6 Appendices ............................................................................................................................................... 43
6.1 Spectrum 128 PCB Rear Foil Layout .................................................................................................. 43
6.2 Spectrum 128 Digital Schematics...................................................................................................... 44
6.3 Spectrum 128 Analogue Schematics................................................................................................. 45
6.4 Spectrum 128 Block Diagram ............................................................................................................ 46

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1 SYSTEM DESCRIPTION

Introduction

Architecture

Z80A CPU

Memory Organisation

Read/Write Operations and Bus Arbitration

Input/Output

TV Picture Generation and Sound Output

Keyboard Scanning

Tape Interface

Programmable Sound Generator

RS232C/MIDI Interface

Keypad Scanning

Power Supplies

1.1 INTRODUCTION
The Spectrum 128 is a derivative of the 48K Spectrum Plus offering 128K of RAM, music quality sound,
greatly improved video quality and higher hardware reliability.

The firmware is capable of running in Spectrum 48K mode or alternative in 128K mode, which will
support paged memory in the form of a RAM disk. Extended BASIC to handle the sound facility is
provided, and a full screen editor is incorporated in the firmware.

A list of the principal features appears below:

a) 128K dynamic RAM

b) 32K ROM
c) Numeric keypad
d) TV sound with composite video
e) Elimination of dot crawl (single crystal operation)
f) RGB output
g) RS232 serial port
h) Musical instrument digital interface (MIDI)
i) Software compatible with all previous Spectrums
j) Edge connector compatible with Spectrum.

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1.2 ARCHITECTURE
The architecture of the Spectrum 128 shown in Figure 1.1 is typical of many microcomputer systems in
that it comprises of a single microprocessor chip (in this case a Z80A or u780), a read only memory
(ROM), a paged random-access memory (RAM) and an input-output section. The latter handles the
keyboard input, tape and TV display functions using the logic gate array (ULA IC1), and the keypad input,
sound and RS232/MIDI interfaces using the sound generator circuit IC32.

The analogue circuits (not shown) generate the 17.7 MHz master clock, and process the RGB colour
monitor and sound signals. The resultant outputs are suitable for use with colour (RGB) or black and
white monitors, and domestic UHF colour television receivers. A modulated sound carrier is output with
the composite video.

The computer is built on a single printed circuit board which also includes a regulated power supply fed
from and external 9V power pack. The keyboard matrix is part of the upper case assembly and is
connected to the board via two ribbon cables KB1 and KB2. A digital keypad is also provided, connected
via a flexible cable. It can be used as a games controller or calculator pad and has special function keys
for use with the full screen editor. An in-built peripheral interface controller (PIC) performs the keypad
scanning routines and delivers an output to the Z80 on demand.

1.3 Z80A CPU

The Z80A is an 8-bit single chip central processing unit (CPU). It is clocked at 3.5 MHz from a divide of an
external source controlled by the logic gate array (ULA) and has a standard three bus input/output
arrangement. These buses are the Data Bus, Address Bus and Control Bus respectively.

Data Bus: D7-D0 constitutes an 8-bit bi-directional data bus with active high, tri-state input/outputs. It is
used for data exchanges with the memory, sound chip and the ULA.

Address Bus: A15-A0 constitutes a 16-bit address bus with active high, tri-state outputs. The address bus
provides the address for memory data exchanges and for data exchanges with the ULA. It is also used
during the interrupt routine (see below) when scanning the keyboard matrix.

Control Bus: The control bus is a collection of individual signals which generally organise the flow of data
on the address and data buses. The block diagram only shows five of these signals although others of
minor importance are made available at the expansion port (see Figure 1.5 for details).

Starting with memory request (/MREQ), this signal is active low indicating when the address bus holds a
valid address for a memory read or memory write operation. Input/output request (/IORQ) is also active
low but indicates when the address bus holds a valid I/O address for I/O read/write operations.

The read and write signals (/RD and /WR) are active low, and one or other is active indicating that the
CPU wants to read or write to a memory location or I/O device. All the control signals discussed so far
are active low, tri-state outputs.

The last control signal described here is the maskable interrupt (/INT). This input is active low and is
generated by the ULA once every 20ms. Each time it is received the CPU ‘calls’ the ‘maskable interrupt’
routine during which the real-time clock is incremented and the keyboard and keypad scanned.

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CPU Clock: Returning to the CPU clock mentioned earlier in this section, the ULA is able to inhibit this
input bringing the CPU to a temporary halt. This mechanism gives the ULA absolute priority allowing it to
access the contended RAM without interference from the CPU (see RAM description). Switching
transistor TR3 ensures that the clock amplitude is +5v rather than some arbitrary TTL level. This is
essential if the CPU is to operate effectively while executing fast machine code programs of the ‘space
invader’ type.

Dynamic Memory Refresh: The CPU incorporates built-in dynamic RAM refresh circuitry. As part of the
instruction opcode fetch cycle, the CPU performs a memory request after first placing the refresh
address on the lower eight bits of the address bus. At the end of the cycle the address is incremented so
that over 255 fetch cycles, each row of the dynamic RAM is refreshed.

The Z80 address space is allocated according to the two most significant bits of the address bus
(ZA14.15) and the contents of the bank register IC31 which is at address 7FFDH in the Z8O's I/O space.
The significance of the register bits is summarised below:

Bits Function
B2-B0 Selects the page occupying the top 16K of the Z80 address space. Any RAM page can
occupy the space.
B3 Instructs the ULA to access the display mapped in page 5 or 7.
Bit set: screen in page 7
Bit clear: screen in page 5
B4 Determines whether instruction fetches are from ROM 0 or ROM 1*
Bit set: fetches from the 48K Spectrum ROM (ROM 1)
Bit clear: fetches from the 128K Spectrum ROM (ROM 0)
B5 Set to prevent further accesses to the bank register (protection against SPECTRUM
programs crashing if the bank register is written to in error)

* see para. 4.12.2

Clearly, dependent on register bits B2-B0, the Z80 can access page 2 at address 8000H or C000H and the
screen in page 5 at address 4000H or C000H. The screen in page 7 can only be accessed at address C000H.
On power up, or after reset the bank register is cleared and loads page 0 at address C000H, selects the
128K Spectrum ROM at address 0000H and informs the ULA that screen accesses are from page 5.

This mechanism only applies to the non-contended RAM area. An alternative refresh method is adopted
for the contended RAM.

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1.4 MEMORY ORGANISATION

The Spectrum 128 has 160K bytes of addressable memory - a 32K byte ROM (IC5) and 128K bytes of
dynamic RAM (IC6-IC22). The latter is organised as eight 16K byte pages as indicated below.

Page 7 screen 2
Page 6
Contended video RAM (ICs 6-13)
Page 5 screen 1
Page 4
Page 3
Page 2
Uncontended ‘upper’ RAM (ICs 15-22)
Page 1
Page 0

Pages 0-3 are uncontended and are accessed solely by the Z80. Pages 4-7 are contended in that the Z80
and ULA IC1 both require access to pages 5 and 7 in order to generate the memory mapped displays.
(Editor’s note – this is inaccurate. Pages 1,3,5 and 7 are contended and pages 0,2,4 and 6 are uncontended. This is due to an
error in the PAL (IC29) equations. This was not corrected until the arrival of the +2A and +3 models.)

The address of any page of RAM depends on where it appears in the address space of the Z80 which is
structured as follows:

C000H page 0-7

8000H page 2
4000H page 5 Screen 1
0000H ROM 0 or 1

All memory accesses are controlled by the programmable logic array (PAL) IC29. It does this by decoding
the two most significant Z80 address bits Z15, Z14 with bits B2-B0 from the bank register to produce
three pairs of supplementary address lines. They are:

a) UA15, 14 specifying the page number in the uncontended RAM space

b) VA15, 14 specifying the page number in the contended RAM space
c) ULA15, 14 controlling bus arbitration and Z80 access to the ROM and contended RAM space.

The decodes are summarised below and described in the following paragraphs.
Z80 Operation ZA15 ZA14 B2 B1 B0 ULA15 ULA14 VA15 VA14 UA15 UA14
ROM access 0 0 X X X 0 0 X X X X
4000H-7FFFH 0 1 X X X 0 1 0 1 X X
8000H-BFFFH 1 0 X X X 1 0 X X 1 0
Page 0 access 1 1 0 0 0 1 X X X 0 0
Page 1 access 1 1 0 0 1 1 X X X 0 1
Page 2 access 1 1 0 1 0 1 X X X 1 0
Page 3 access 1 1 0 1 1 1 X X X 1 1
Page 4 access 1 1 1 0 0 0 1 0 0 X X
Page 5 access 1 1 1 0 1 0 1 0 1 X X
Page 6 access 1 1 1 1 0 0 1 1 0 X X
Page 7 access 1 1 1 1 1 0 1 1 1 X X

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ZA15 = ZA14 = 0: These bits select the first 16K of Z80 address space beginning at 0000H, and result in
the PAL generating ULA15 = ULA14 = 0. These are decoded by the ULA (IC1) to produce a signal /ROMCS
enabling the ROM IC5. A13-A0 on the Z80 address bus provide the instruction address, bank register bit
4 determines whether the upper or lower 16K of ROM is accessed.

ZA15 = 0, ZA14 = 1: These bits select the RAM page located in the second 16K of the Z80 address space
beginning at 4000H and result in the PAL generating ULA15 = VA15 = 0 and ULA14 = VA14 = 1. The ULA
lines signal an access of the contended RAM area and prompt IC1 to assert the /DRAS, /CAS and
/DRAMWE lines controlling the read/write operation. At the same time, ULA15 inhibits the /CAS output
from IC27 preventing any access to the uncontended RAM area.

The 2:1 data selector IC30 supplies the most significant row and column address bits to the contended
RAM as DMA7, first selecting the row address VA14 = 1 while /DRAS is low and the column address bit
VA15 = 0 when it returns high. This combination selects the second 16K bank of RAM in the contended
area, allowing DMA6 – DMA0 to access locations in page 5 used for the standard screen display.

ZA15 = 1, ZA14 = 0: These bits select the RAM page appearing in the third 16K of the Z80 address space
beginning at C000H, and result in the PAL generating ULA15 = UA15 = 1 and ULA14 = UA15 = 0. The ULA
lines signal an access to the uncontended RAM area and enable IC27 to assert the /CAS line which
together with /RAS (/MREQ) and /WR control the read/write operation. (Access control lines for the
contended RAM area generated by IC1 i.e. /CAS, /DRAS and /DRAMWE, are not asserted at this time).
VA15 and VA14 respectively supply the most significant row and column address bits for the
uncontended RAM area as MA7 and select the second 16K bank of RAM allowing MA6-MA0 to access
locations in page 2.

ZA15 = ZA14 = 1: These bits select the RAM page appearing in the top 16K of the Z80 address space
beginning at C000H. The bits together with B2-B0 from the bank register IC31 are decoded by the PAL to
select any page from the RAM according to the setting of the supplementary address line pairs. For the
uncontended RAM space ULA15 is always high allowing IC27 to control read/write operations. UA15,14
assume one of four possible states reflecting the state of B1, B0 and select a page in the range 0-3. For
contended RAM accesses ULA15 is always low allowing IC1 to control the read/write operations, and the
data selector IC30 to deliver the most significant row and column address bits VA14.15. The latter also
assume one of four states and since B2 is set, selects a page in the range 4-7.

1.4.1 Read/Write Operations and Bus Arbitration

The following description should be read in conjunction with the circuit diagram given in Figure 1.5.

Read Only Memory (IC5): The physical ROM is a 32K byte device, but appears in the Z80 address space
as two separate 16K ROM's. ROM 1 is the old 48K Spectrum ROM (slightly modified) and is selected
when bank register bit 4 sets address A14. ROM 0 is the new Spectrum 128 ROM and is selected when
bit 4 is clear. CPU accesses occur during memory read cycles when the Z80 asserts /MREQ and loads the
address bus A13-A0. /MREQ enables the ROM outputs onto the data bus D7-D0, /ROMCS decoded from
ZA14.15 (see para. 4.7) selects the chip.

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An external ROM chip select input, supplied via the expansion port on pin 25A, selectively disables the
on-board ROM by pulling the select input high. By virtue of R33 placed on the ULA side of the ROM the
ULA /ROMCS output is effectively inhibited. Interface 1 uses this mechanism, allowing the CPU to read
the extension ROM in the interface for microdrive and RS232 applications.

Uncontended RAM (IC15-22): The uncontended RAM comprises eight 64K dynamic RAM chips
organised as a 64K byte memory with a 256 x 256 row/column matrix. When ULA15 is high (see para.
4.11) separate 8-bit row/column addresses are supplied by IC27 as MA7-MA0. These are derived from
the Z80 address bus A13-A0 with UA14 and UA15 from IC29. The low order address bits A6-A0 with
UA14 provide the row address and are selected at the beginning of the memory access cycle when
initially the /RAS (/MREQ) output from the Z80 is low. Later, as the row address is latched, IC27 asserts
/CAS selecting the high order address bits A13-A7 with UA15.

Row/column address selection and RAS/CAS timing for the RAM is decoded in IC27 in conjunction with
IC28 and the associated discrete components. A theoretical timing diagram illustrating the RAS/CAS
waveforms is given in Figure 1.2 (A read operation is shown when the WRL line from the Z80 is high).

Contended RAM (IC6-13): The organisation of the contended and uncontended RAM described above is
identical. However, because ULA15 is low during accesses to the contended area, IC27 only sources a 7-
bit row/column address DMA6-DMA7. The most significant address bit is sourced by the 2:1 data
selector IC30. At the start of the memory access cycle IC1 asserts /DRAS and selects the row address as
A13-A7 off the Z80 address bus with VA14 via the selector. Later as the row address is latched IC1 sets
/DRAS and selects the column address as A6-A0 with VA15.

RAS/CAS timing for the contended RAM area is decoded by the ULA IC1 from /MREQ and A15. /DCAS is
asserted a short time after /DRAS returns high, and latches the column address. ULA15 prevents IC27
generating an identical signal for the uncontended RAM. The /DRAMWE signal, also generated by the
ULA, is a decode of the RD/WR waveforms and selects a RAM read or RAM write cycle.

It will be apparent from the circuit diagram that the ULA can access the contended RAM by generating a
set of addresses independent of those generated by the CPU. The address port for the RAM is therefore
dualled by the insertion of small value series resistors on the address lines between IC27 and the RAM.
This ensures that where there is likely to be conflict between the ULA and CPU, the ULA address has
priority. Priority is assigned on the basis that the ULA must access screen pages 5 and 7 at set intervals in
order to build up the video for the TV display. If the ULA is about to access the RAM and it detects either
A14 or A15 (i.e. the CPU is also about to access the RAM) the ULA inhibits the CPU clock temporarily
halting the CPU memory transaction until its own transaction is completed.

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Figure 1.2. Uncontended RAM RAS/CAS timing (read cycle shown)

Resistors R1 to R8, in series with the data bus lines, perform a similar function to the address port
resistors described above. They ensure that the ULA does not 'see' CPU write data while the ULA is
accessing the contended RAM.

Refresh for the contended RAM is accomplished during normal read cycles, i.e. most rows are refreshed
each time the ULA accesses screen pages during picture compilation; the remaining rows are refreshed
as a result of other read cycles also known to occur at regular intervals within the refresh period.

Bank Register (IC31): The bank register is at address 7FFDH in the Z80 address space. The register is
positive edge triggered and latches D5-D0 off the data bus on the negative (trailing) edge of the BANK
output from the PAL IC29. BANK is decoded (set high) from /IORQ and RD/WR active low (I/O read or
write cycle) and ZA1 and ZA15 low (address 7FFDH).

On selecting the 48K Spectrum mode, the Z80 writes a ‘1’ into bit 5 of the register, thus preventing any
further access. This action preserves the Z80 address space, preventing erroneous calls to address 7FFDH
crashing the SPECTRUM program. The bit can only be cleared by using the RESET pushbutton or by
interrupting the power supply input.

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1.5 INPUT/OUTPUT
The input/output functions are controlled by the Z80 in conjunction with the ULA (IC1) and the sound
generator circuit IC32. Like its counterpart in the 48K Spectrum, the ULA handles the tape recorder
read/write functions, and generates an interrupt during which it scans the main keyboard. It also
accesses the contended RAM area while generating the drive waveforms for the TV display and
produces a simple tone output while obeying the BEEP instruction.

The sound generator produces high quality music sound by mixing the outputs from up to three
programmable tone generators and a noise generator. It also handles the RS232/MIDI interface and
reads the keypad status. Each of these functions and the supporting circuits is described below.

1.5.1 TV Picture Generation and Sound Output

The video compilation section of the ULA operates in conjunction with the memory mapped picture
display area in the contended RAM, together with the colour encoder IC36 and UHF modulator. This
combination produces a high resolution 24 line x 32 character, eight colour display suitable for use with
RGB colour or black and white monitors or a domestic TV receiver. The sound output from the ULA or
the programmable sound generator is FM modulated and added to the composite video signal for
playback through the TV loudspeaker. If a monitor is used the sound is available through the MIC socket.

From the 17.73 MHz external clock (X1/IC37) the ULA derives line and field timing for the composite
sync signal on pin 23, and a pixel clock for timing accesses to the RAM. The ULA also generates two 8.8
MHz clocks on pins 46, 47 from which the encoder derives the 4.43 MHz reference and quadrature
chroma sub-carriers. The fact that the pixel and chroma carriers are derived from the same external
clock source means that dot crawl is eliminated. The dot pattern itself is minimised by adjusting the
display line length.

The digital RGB and bright-up signals available from the ULA on pins 19-22 are derived by accessing the
picture information located in page 5 or 7 of the contended RAM area at the pixel rate (para. 4.12.8).
The addresses are necessarily independent of the CPU and appear on the ULA address lines DMA6 to
DMA0 and DMA7 as two separate bytes, timed by the RAS/CAS row/column address select lines. DMA7
is a decode of bit 3 (VB) loaded in the bank register IC31 and sets the most significant row/column
address bits as follows:

VB (IC31) DMA7 (ULA) RAM page

Row Column
0 1 0 5
1 1 1 7

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The RGB colour, bright-up and composite sync signals (Figure 1.6) are coupled to the RGB output socket
via 68-ohm resistors and are suitable for direct input to a wide range of colour monitors. The same
signals are also applied to the encoder IC36 to produce a composite video output at pin 6. The video
circuit comprises of the following components:

a) Line/frame sync with colour burst, derived from the composite sync input CS and a burst
oscillator sustained by tank circuit L3. The position of the burst relative to the line sync pulse is
determined by a threshold level set-up on the RAMP input of IC36 by R113/C115.
b) Colour chrominance is derived by modulating the chroma sub-carriers with the colour difference
signals decoded from the RGB and bright-up signals. The latter are first combined using a diode
matrix D20-D25 to produce six colour inputs for IC36 - two for each colour, designated ‘0’ and
‘1’. Without bright-up the presence of any digital colour input at logic ‘1’ drives the ‘1’ input
only, producing a pixel display with the colour intensity set for normal viewing. With bright-up
activated the ‘0’ and ‘1’ inputs are driven, increasing the intensity so as to highlight the pixel
display.
c) Luminance (grey scale) derived by mixing the RGB inputs in a fixed proportion. The signal is used
to produce the colour difference signals in (b) and in its own right to drive the black and white
monitor. The luminance is brought out at IC36 pin 7 and is applied to the RGB output socket via
a complimentary transistor pair TR13,14.

The luminance is returned to IC36 mixed with the FM modulated sound carrier from IC38. The
sound modulator operates at 6 MHz in the UK (5.5 MHz in most other European countries) and
is tuned by L4. The modulating signal is derived either by the ULA sourced via R112/C123 or the
sound generator circuit IC32 via R132/C127.

The composite video signal at IC36 pin 6 is finally applied to an encapsulated UHF modulator operating
on European standard channel 36. The device is current driven via TR10,11,12 to give improved linearity
thus reducing the effect of sound on vision and vice-versa. The effect is further reduced by outputting
the sound carrier 20dB down with respect to the picture carrier.

1.5.2 Keyboard Scanning

Every 20ms (i.e. once per maskable interrupt), the CPU systematically scans the keyboard recording
which keys (if any) have been depressed. The scanning method is described below with the aid of
Figures 1.3 and 1.4, As the figures clearly illustrate the main keyboard consists of an upper and lower
membrane. The upper membrane is organised as an 8 x 5 matrix, the intersection of each row and
column bridged by a normally open switch contact. The lower membrane is organised in a similar
manner except that only 16 of the intersections are populated by switch contacts. The row 'outputs' and
column 'inputs' are shown connected in both cases to separate ribbon cables KB1 and KB2, one to the
ULA and the other to the high order address lines A15-A8. Pull-up resistors R65 through R69 ensure that
when the address bus is in the high Z state, or none of the switch contacts is closed, row outputs KB1-
KB4 remain high.

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When the keyboard scanning routines are entered, the CPU performs successive I/O read cycles setting
the /IORQ and /RD lines to the ULA low. At the same time, the I/O port addresses placed on the upper
half of the address bus are modified with each cycle such that each of the address lines A15 through A8
is set low in turn, the other lines remaining high.

The sequence starts with I/O port address FE driving address line A8 low. The keyboard matrix also sees
this potential on column 6, applied via D6 and the ribbon cable KB2. Thus, when any of the switches on
the intersection with the column is pressed, the corresponding row output supplying the ULA via the
second ribbon cable (KB1), is pulled low.

Figure 1.3. Keyboard Upper Membrane

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Figure 1.4. Keyboard Lower Membrane

The row signal(s) is subsequently buffered by the ULA and placed on one of the five low order data bus
lines. For example, if the CAPS SHIFT key is pressed, row one output drives data bus D0 high, and so on.
The sequence ends with I/O address 7F when column 8 is addressed. In this instance, operation of the
SPACE key drives D0 high. Clearly, the keyboard scanning routines make the distinction between the
CAPS SHIFT and SPACE key by knowing which address line is being driven.

If one of the following keys is pressed the corresponding switch contact on the lower membrane is
closed. Additionally, the CAPS SHIFT switch contact on the upper membrane closes.

TRUE VIDEO EXTEND MODE CURSOR RIGHT

INV VIDEO EDIT CURSOR LEFT

BREAK CAPS LOCK CURSOR UP

DELETE CURSOR DOWN

GRAPH

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For example, pressing TRUE VIDEO closes the switch contact at row 1, column 6 on the upper membrane
(CAPS SHIFT) and row 3, column 1 on the lower membrane (TRUE VIDEO).

Similarly, pressing any of the following keys results in the corresponding switch contact on the lower
membrane closing as well as the SYMBOL SHIFT switch on the upper membrane:

, (comma)
. (full-stop)
; (semi-colon)
" (quotes)

For example, pressing full stop closes the switch contact at row 2, column 8 on the upper membrane
(SYMBOL SHIFT) and row 3, column 8 on the lower membrane (full stop).

1.6 TAPE INTERFACE

When LOADing or SAVEing programs using a cassette recorder, the ULA transfers information between
the MIC and EAR sockets and the data bus, performing A/D and D/A conversions as required. During the
LOAD operation the CPU executes successive I/O read cycles to I/O port address 254, reading the EAR
input off bus line D6. When performing a SAVE operation, the CPU executes successive I/O write cycles
to I/O port address 254, this time writing data to the MIC output via bus line D3.

To ensure that I/O cycles are correctly implemented, the IORQ line supplying the ULA is gated with
address line AO via TR6. Thus, if any memory transactions occur when AO is high (i.e. not port address
254) then the IORQ input is forced high inhibiting any attempt to perform the I/O cycle.

1.6.1 ULA Sound Output

It should be noted that while SAVEing, the level of the MIC output is barely sufficient to modulate the
sound carrier to IC38. However, during the execution of a BEEP instruction the CPU writes instead to
port 254 on bus line D4. This effectively boosts the MIC output, modulating the sound carrier so that the
BEEP tone can be easily heard.

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1.7 PROGRAMMABLE SOUND GENERATOR

The audio from the sound generator IC32 is derived from a master clock input supplied by the ULA,
controlled and shaped in accordance with instruction codes loaded by the Z80 into 14 internal byte wide
registers (see below).

Bit B7 B6 B5 B4 B3 B2 B1 B0
Register
R0 Channel A Tone Period 8-bit Fine Tune A
R1 4-bit Coarse Tune A
R2 Channel B Tone Period 8-bit Fine Tune B
R3 4-bit Coarse Tune B
R4 Channel C Tone Period 8-bit Fine Tune C
R5 4-bit Coarse Tune C
R6 Noise Period 5-bit Period Control
R7 /Enable /IN OUT* /Noise /Tone
IOB IOA C B A C B A
R10 Channel A Amplitude M L3 L2 L1 L0
R11 Channel B Amplitude M L3 L2 L1 L0
R12 Channel C Amplitude M L3 L2 L1 L0
R13 Envelope Period 8-bit Fine Tune Envelope Period
R14 8-bit Coarse Tune Envelope Period
R15 Envelope Shape/Cycle CONT ATT ALT HOLD
R16 I/O Port A Data Store 8-bit Parallel I/O on Port A*
R17 I/O Port B Data Store 8-bit Parallel I/O on Port B*

* RS232/MIDI interface (see below)

The Z80 specifies a register by loading the data bus while writing to address FFFDH in the I/O space. DA3-
DA0 supply the octal address between 0 and 15, DA7-DA4 should be all zero. (In the address mode, DA7-
DA4 with IC32 pin 17 strapped high externally, are decoded in IC32 to provide a ‘chip select’ signal). The
instruction code is then written to the register by writing to address BFFDH.

BC1 and BDIR, decoded in D26,27 from PSG, A14 and RDL, define the type of write operation for the
sound generator as follows:

PSG A14 /RD BDIR BC1 I/O Address Operation

0 X X 0 0 - Inactive
1 1 1 1 1 FFFDH Write Address
1 0 1 1 0 BFFDH Write Data
1 1 0 0 1 FFFDH Read Data

* RS232C/MIDI interface (see below)

PSG is decoded in IC29 from /IORQ with /RD or /WR (I/O read/write cycle) and ZA1 = 0 and ZA15 = 1
(address FFFDH with A14 high; address BFFDH with A14 low).

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1.8 RS232/MIDI INTERFACE

The RS232C/MIDI interface is implemented using the Port A Data Store in the sound generator chip IC32.
The data store is a special register at octal address 16 which accesses an 8-bit bi-directional port A7-A0.
The port occupies the same I/O space as the sound generator registers and is accessed in much the
same way. The addition of a read cycle at I/O address FFFDH allows the Z80 to input data.

The port direction is determined by a control bit written to register R7 on bus line D6. When D6 is low
the port is configured as an input and when high as an output. In this application A3-AO are only used as
outputs and A7-A4 as inputs. A3/A2 supply an RS232C driver IC33 which converts the TTL outputs to
RS232C levels (+12V); A2 and A3 drive the CTS and RXD interface lines respectively. A4-A7 are supplied
from an RS232C receiver IC34 which converts the RS232C inputs to TTL levels; A6 and A7 are driven by
the DTR and TXD interface lines respectively. The data register contents are summarised as follows:

_________R7 (D6) = 0_________ _________R7 (D6) = 1_________

A7 A6 A5* A4 A3 A2 A1 A0*
TXD DTR CTS X RXD CTS X TXD Register R16
RS232 I/P RS232 O/P * see para. 5.8.4

It is evident from the signal directions that the Spectrum 128 adopts the role of a data communications
equipment (DCE). However, DTR and CTS do not perform a handshake but are the same signal
transmitted in opposite directions. The transmission format is asynchronous, full duplex with 11-bit data
frames comprising 1 start bit, eight data bits and two stop bits. Two stop bits are always sent, but the
interface can receive satisfactorily with one.

1.9 KEYPAD SCANNING

The keypad (Figure 1.7) comprises a 5 x 4 switch matrix and a peripheral interface controller (PIC) with
on-chip program and scratchpad memories. The PIC operates from a +5V rail derived by a simple
stabiliser from the + 12V Spectrum supply, and is clocked from an external LC network. The nominal
clock frequency is 2.556 MHz but may vary between 1.278 MHz and 3.835 MHz dependent on
component tolerances. The master clear input (MCLR) is active for a period after power-up or if the
+12V supply is temporarily disconnected.

A two-part protocol first synchronises the PIC with the Z80 after power up (or if the flex cable
connection is temporarily broken) and then supports the transfer of keystroke data. Assuming
synchronisation has been achieved (see below) the keypad scans the keypad once every other interrupt
on demand from the Z80.

The keypad scanning routine is much the same as the routine adopted by the Z80 and ULA when
scanning the main keyboard. The PIC addresses each column in turn and scans the rows to determine
whether a key is pressed. The results of the scan are logged and passed to the Z80 on a
demand/response basis (see para. 5.8.9). Each demand prompts the PIC to scan a row and report any
change in the status since the previous scan. If there is no change, the PIC responds negatively, sending

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a space in response to the START signal from the Z80. In this case the PIC and Z80 determine that the
next START signal is a call for the result of the row scan at the next column address. If the scan indicates
that there has been a change in status since the previous scan, the PIC responds positively by sending a
mark in response to the START signal. The Z80 responds by sending a further four START signals,
prompting the PIC to transmit a 4-bit serial code with a ‘1’ set in the bit position corresponding with the
particular row. Since the Z80 keeps a log of the column address by counting the number of START signals
it sends and registering the PIC responses since the start of the interrupt, it can readily identify the key
code from a look-up table.

On a physical level, data exchanges between the PIC and the Z80 are conducted at RS232 signal levels
over a single line pair - a transmit line (TXD/RXS) from the Z80 to the PIC and a receive line (CTS/TXS)
from the PIC to the Z80. The transmit signal, originated by the Z80, is output as bit AO from the Port A
Data Store in the sound generator IC32 during a write to I/O address BFFDH. From IC32 the data is
converted from logic to RS232 levels in IC33 and routed from there to the PIC. A 4.3V Zener diode on the
keypad receive line, limits the positive signal excursion (space) to +4.3V and the negative signal
excursion (mark) to 0V.

The transmit signal, originated by the PIC, follows a reciprocal path and is input to the Z80 from the
sound generator as bit A5 in the Port A Data Store during a read from I/O address FFFDH (NOTE: The
RS232C receiver IC34 recognises a mark as 0V and a space as any level exceeding +3V).

Accesses to the Port A Data Store are identical to those described under the heading ‘RS232/MIDI
Interface’.

1.9.1 Reset Protocol

The synchronising sequence which runs after power up or reconnection (as seen at the RS232
connector) is shown below:

The significant time delays are as follows:

a) The initial 3 second delay which ensures that the PIC is up and running. During this time the
keypad is inoperative.
b) The 1ms delay between the Z80 setting TXD high (MARKS) and the PIC responding by setting TXS
high (PRESENT). If the delay is exceeded, the Z80 assumes that some other device is connected,
and abandons the reset sequence.

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c) The 0.6ms delay between the PIC returning to the idle state (CORRECT) and the Z80 setting TXD
high (GO). If the delay is exceeded the keypad assumes that the Z80 has been reset and resets
itself (i.e. returns to the start of the sequence).
d) The 1ms delay between the Z80 setting TXD high (SET) and the PIC responding by putting TXS
low (CORRECT). If the delay is exceeded, the Z80 assumes that some other device is connected,
and abandons the reset sequence.

1.9.2 Bit Transfer Protocol

The protocol for transferring a single bit from the PIC to the Z80 (as seen at the RS232 connector) is
shown below:

The significant levels and time delays are as follows:

a) At the start of the transfer the Z80 polls TXS which should be idling low. If not the Z80 assumes
that some other device is connected and abandons the transfer.
b) Having detected that TXS is low the Z80 sets TXD low (ATTENTION) and waits for the PIC to
respond with READY. If READY is not received within 15ms, the Z80 assumes that the keypad has
been disconnected and abandons the transfer.
c) After setting READY high the PIC polls RXS waiting for START. If not received within 0.2ms the
PIC assumes that the Z80 has been reset, and resets itself.
d) On receiving START the PIC leaves TXS high if it wants to send a ‘0’ data bit, or puts it low to
send a ‘1’ (STARTED).
e) Having received the data bit, the Z80 sets TXD low (STOP); the PIC responds with TXS high, if not
already so (STOPPED).
f) Having responded with STOP, the PIC waits for the Z80 to set TXD high (STAND EASY); the PIC
responds by setting TXS low ready to transfer the next data bit. If the Z80 does not respond with
STAND EASY within 1.3ms the PIC assumes that the Z80 has been reset, and resets itself.

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1.10 POWER SUPPLIES

The on-board power supply unit receives a 9V unregulated supply from the external Sinclair ZX power
pack and derives the following internal supply rails:

a) Regulated +5V for the IC logic circuits, the ULA and the sound/UHF modulators
b) -5V for the expansion port
c) +12V for the RS232 driver IC33 and the keypad
d) -12V for the RS232 driver IC33 (unregulated -5V to -12V).

The external power pack incorporates a mains transformer, full wave rectifier and capacitive smoothing.
A thermal fuse is fitted at the transformer input.

The on-board power supply unit (Figure 1.5) incorporates a 7805 regulator, deriving the +5V power rail,
and an input supply for the inverter stage TR4/TR5. The latter raises the level of the +9V unregulated
supply above +12V. The resultant square wave at the junction of TR4 collector and the inverter coil is
subsequently rectified and smoothed by D15/C44 producing the +12V output. The square wave at TR4
collector also supplies a charge pump C111/112 and D28/29 which derives the -12V rail. The -5V supply
is taken from this rail via a Zener D19.

The following supplies are available on the expansion connector:

a) +5V (pin 3A)

b) Pulsed +12V (pin 23B)
c) +12V (pin 23A)
d) -5V (pin 20B)
e) +9V unregulated (pin 4A)
f) Ground (pins 6A, 7A, 14A)

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Figure 1.7. Keypad Circuit

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2 DISASSEMBLY/ASSEMBLY

Disassembly

Assembly

2.1 DISASSEMBLY
Unplug all input/output connectors and turn the computer upside down to reveal eight fixing screws.
Release the screws (noting the position of two countersunk screws for re-assembly), turn the computer
right side up and separate the case halves. To disassociate the case halves, carefully disconnect the
keyboard ribbon cables from the PCB.

To remove the PCB from the lower case half, remove the board fixing screws and the fixings securing the
voltage regulator to the finned heatsink.

CAUTION: If the PCB is to be powered-up when separated from the case, the PCB, with heatsink
attached, should be removed as a complete assembly. The heatsink is secured to the case by
two screws. Take care not to damage the electrical connections to the regulator.

To change the keyboard membrane, bubble mat or any of the keys, remove the membrane tail clamps
followed by ten screws securing the keyboard reaction plate. Lift the plate clear followed by the
membrane and bubble mat below. Individual keys can be removed for cleaning by pressing the key and
gently prising the retaining sleeve off the underside of the key using a small screwdriver inserted under
the rim.

2.2 ASSEMBLY
Assembly is generally carried out using the reverse procedure to that of disassembly. Do not overtighten
the self-tapping fixing screws.

When replacing the keyboard components support the upper case half face down so that the keys are
clear of the work surface. Position the bubble mat, membrane and reaction plate so that the hole at
either end engages with the locating peg. Secure the fixing screws starting with the centre row. Tighten
fully and back off a 1/4 turn.

When clamping the membrane tails ensure that there is good electrical contact between the middle,
upper and lower tracks. This is achieved by correctly positioning the packing pieces (extensions of the
bubble mat) and ensuring that the ends of the middle tracks protrude 1mm beyond the clamps. On new
membranes, to prevent the possibility of short circuits, bond the upper and lower tracks together, close
to the edge connector end, using double sided tape.

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When replacing the PCB, ensure that the reset pushbutton is correctly located in the cut-out provided in
the end of the case.

Before final assembly reconnect the keyboard ribbon cables (they should lie in an ‘S’ shape) and ensure
that the legs and leg springs are in position.

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3 SETTING UP AND SYSTEM TEST

Setting Up Instructions

Sound Carrier Frequency

System Test

3.1 SETTING UP INSTRUCTIONS

TBD

3.2 SYSTEM TEST

TBD
(note: the above is as per the source manual and is intentionally reproduced as is)

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4 FAULT FINDING AND REPAIR

Introduction

Test Equipment

Fault Diagnosis

Techniques

Power Supply Unit

Initialisation

Symptomatic Faults

Repair

Illustrations

Test Oscillograms

4.1 INTRODUCTION

4.1.1 Test Equipment

Section 4 is intended as a guide to fault diagnosis and repair of the SPECTRUM 128. it is assumed that
users have a reasonable knowledge of electronic servicing, theory and standard fault-finding techniques
and have access to the test equipment and tools required to carry out the task. The table below contains
a list of the minimum recommended test equipment and materials.

Equipment Specification/Manufacturer
Storage Oscilloscope with x10 probe Rise Time: 0.02us/cm
Variable power supply unit 0 to 30V dc
Mono cassette recorder With Record and Playback facilities
Mains extension lead ‘Safebloc’ type
Multimeter General purpose
Colour Television and Monitor Open Market
ZX Printer Sinclair
Test tape

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Blank tape Open Market

Double-sided adhesive tape 12mm and 6mm wide, Tesafix 959 (B.D.F. Tesa) or 3M
equivalent

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Engineers who are already familiar with the Sinclair SPECTRUM+ will find some similarities in the
SPECTRUM 128. The SPECTRUM 128, however, is a more sophisticated device with improved colour and
sound circuitry.

4.2 FAULT DIAGNOSIS

4.2.1 Techniques
In a closed loop system such as a computer, because of the interdependence of numerous component
parts, fault diagnosis is not necessarily straight-forward. In addition, because of the high speed cyclic
operation, interpretation of any waveforms on control, data and address lines as being valid depends to
a large extent on practical experience of the system. There are however, certain checks with valid
waveforms and levels that can be carried out before substituting any integrated circuits. Experience has
shown that the best method of initially checking waveforms and levels can be to compare with the same
point in a known serviceable board. The following pages provide a basic fault-finding procedure and
furnish a list of possible faults along with suggested ways of curing them.

With a densely populated board such as the SPECTRUM 128, a careful physical examination of the board
can sometimes indicate an obvious fault. Burnt-out discrete components or an overheated track show
up immediately, as do the attentions of an enthusiastic amateur. Bearing in mind the latter, short
circuits caused by hairline solder 'splatter' can be of several ohms resistance and can cause some very
misleading fault symptoms.

Provided first principles are adhered to and a common-sense approach is adopted, it will be found after
a short space of time that fixing a faulty Spectrum is very much a routine operation.

4.2.2 Power Supply Unit

The unstabilised external power supply unit is a source of some problems. The design is such that, at
minimum input voltage (215V AC) and 1.4A output, the voltage trough should not be less than 7.0V; at
maximum input voltage (265V AC.) and 600mA output, the voltage peak should be less than 13V.

4.2.3 Initialisation
At switch-on the computer should automatically 'initialise' and produce a clear screen with the
statement.

© 1985 Sinclair Research Ltd

- displayed in the lower left section of the screen. This indicates that most of the system is working. If
the SPECTRUM 128 does not initialise, carry out the following basic checks.

Basic Checks: It is difficult to be specific in a fault-finding guide because of the large variety of fault
conditions which can occur, but the following procedure, starting with a table of checks set out in order
of priority, will however isolate the major fault area. The oscillograms reproduced on pages 4.6 and 4.7
are measured at points referenced on the circuit diagrams.

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Function Circuit Reference Voltage/Waveform

Voltage regulator input +ve side of C50 +9V DC +/- 2.0V. At less than
+7V the regulator may not
operate correctly
Voltage regulator output +ve side of C34 and IC15 pin 8 +5V DC +/- 0.25V, no
discernable ripple
On-board power supply IC33 pin 14 +12v DC +/- 0.5V
outputs: IC34 pin 1 -12V DC +/- 3V, -7V
D19 anode -5V DC
Clock pulses:
Crystal IC37 pin 6 17.73447MHz with no jitter;
check the oscillogram at point
(c)
Z80 IC2 pin 6 3.54689MHz with no jitter;
check the oscillograms at point
(d)
Colour encoder IC1 pins 46,47 8.8MHz with no jitter

If the basic tests prove satisfactory check the +5V and ground distribution to the ROM, Z80, ULA and the
RAM. Also check the following:

a) The /RD, /WR, /MREQ, D0-D7 and A0-A15 lines from the Z80. They should all be active
immediately following a reset.
b) The RAS/CAS lines to the uncontended RAM area IC15-IC22. The lines should be active
immediately following a reset.
c) The RAS/CAS lines to the contended RAM area IC6 to IC13. Compare with the oscillograms at
points (e) and (f). (The RESET pushbutton should be operated to obtain a clear trace).
d) The ROM IC5 is enabled by an active low signal at pin 20.
e) The bank register IC32 is loaded with the correct values. Immediately after reset, pins
2,5,7,10,12 and 15 should be low.
f) Check the outputs on the RGB connector.
g) Check the picture on a domestic television and listen for keyclicks each time the ENTER key is
pressed. Also check the following:
i. LUM0 output on IC36 pin 7; compare with the oscillogram at point (g) on the circuit.
ii. Sound carrier on IC38 pin 4; compare with the oscillogram at point (h) on the circuit. The
frequency should be within 2 KHz of 6.0 MHz for U.K operation or 5.5 MHz for European
operation. Adjust as per the ‘Setting Up Instructions’ if the tolerance is exceeded.
iii. Drive into the modulator; compare with the oscillogram at point (j) on the circuit. Note
the DC level at the bottom of the waveform (typically 185 mV).

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4.2.4 Symptomatic Faults

As with any complex digital equipment the possible permutations are vast, thus the following table is
not intended to be an exhaustive list of the faults that might occur on the Spectrum. It is intended as a
guide only to possible courses of action to follow when faults show up in particular areas of the circuit.
These areas are listed in the table with sub-headings, in no particular order of priority. It is envisaged
that the ZXTP test tape has been loaded, or an attempt has been made to load the tape, in order to
check for a faulty condition.

Area Symptom Action

TBD TBD TBD

Authors Note: Table details to follow when production and in-service history is known.

4.3 REPAIR
Renewal of components should be carried out using recognised desoldering/heatsinking techniques to
prevent damage to the component or to the printed circuit board. Other points to be noted are:

a) When replacing a keyboard matrix, take care that the ribbon connectors are fully inserted into
the board connectors, and are not kinked during insertion.
b) Make sure there is a good contact made between the voltage regulator body and the associated
heatsink in order to ensure adequate heat conduction.
c) When the regulator is being replaced it is recommended that a suitable proprietary thermal
grease is applied to the rear surface of the component body.
d) The modulator should be replaced as a complete unit.
e) When replacing plug-in IC’s, it is advisable to use the correct removal and insertion tools. Avoid
contaminating the connection pins by handling.
f) When handling IC’s take normal anti-static precautions. It is recommended that only a suitably
earthed, low power soldering iron be used.
g) After any component has been renewed the circuit board should be examined carefully, to
ensure that there are no solder 'splatters' which may cause short circuits between tracks and
connector pins.

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(a) TR4 Collector

(b) TR4 Base

(c) IC37 Pin 6

(d) TR3 Collector

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(e) IC1 Pin 42

(f) IC1 Pin 2

(g) IC36 Pin 7

(h) IC38 Pin 4

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(j) TR11 Emitter

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5 PARTS LIST

Introduction

Notes to Table 5.4

Spectrum 128 PCB Component Layout (Editor’s note: missing in available documentation)

Keypad PCB Component Layout (Editor’s note: missing in available documentation)

5.1 INTRODUCTION
Parts lists for the SPECTRUM 128 are provided in table form; one for the case assembly (Table 5.3), one
for the main PCB assembly (Table 5.4) and another for the keypad PCB assembly (Table 5.5). PCB layout
diagrams are given in figures 5.1 and 5.2; the notes to be found in Table 5.4 are explained below.

5.2 NOTES TO TABLE 5.4

1. All RAM chips should have 150ns access time and 128 row refresh. This includes parts from the
following manufacturers: Hitachi, Intel, Mitsubishi, Mostek, Motorola, NEC, OKI, Panasonic, Toshiba
and National.
2. If TR3 is of type KSC839, resistor R24 should be 15K.
3. Provision has been made on the PCB for a 2 to 22pF film dielectric trimmer should the need arise.
4. The ROM should be pin compatible with a 27256 EPROM and have an address access time of less
than 400ns. The output enable access time should be less than 250ns.
5. The crystal is series resonant with 20pm and accurate to 10ppm absolute, +/- 10ppm at 20 to 60°C,
+/- 5ppm per year.
6. If preferred, the 20pF capacitor used for C124 may be split into two parallel capacitors of 10pF +/-
2% in the positions C124 and C130.
7. For FTZ (German) version only.
8. 6.0MHz version (type no?) for use in the UK; 5.5MHz version (type no?) for use in most other
European countries.

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5.3 CASE ASSEMBLY COMPONENTS

Description Manufacturer
Base Assembly
Final PCB Assembly – Table 5.4
Heatsink
Retractable legs – 2 off
Leg Springs – 2 off
Bottom Case Moulding
Fixings –
¼ in self tap screw – 3 off
PCB
Fibre washer – 3 off

5/16 in self tap screw – 2 off Heatsink

M3 x 10mm pan hd screw – 1 off
M3 plain washer – 1 off
Voltage Regulator
M3 crinkle washer – 1 off
M3 hex nut – 1 off

Keyboard Assembly
Keyboard reaction plate
Spectrum + Membrane
Bubble Mat
Upper Case Moulding
Key Set
Tail Clamps – 2 off
Fixings –
Double sided adhesive tape
12mm wide (Tesafix 959)
¼ inch self tap screw – 4 off Tail clamps
5/16 inch self tap screw – 10 off Reaction plate

General Assembly Fixings

5/16 in self tap screw – 6 off
Base/keyboard
½ in self tap screw – 2 off

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5.4 MAIN PCB COMPONENTS

Capacitors (Unless otherwise stated, all capacitors are axial types):
Circuit Reference Value Rating/Tolerance Manufacturer/Type Notes
C1-C8 22nF 25V, 10% Ceramic
C9-C24 Not used
C25 100uF 10V, -10%+80% Electrolytic
C26 22nF 25V, 10% Ceramic
C27 1uF 50V, 10% Electrolytic
C28 22uF 10V, -10%+80% Electrolytic
C29, C31 22nF 25V, 10% Ceramic
C31 100nF 25V, 10% Ceramic
C32 100nF 25V, 10% Ceramic
C33 Not used
C34 22uF 10V, -10%+80% Electrolytic
C35 10nF 25V, 10% Ceramic
C36-C40 Not used
C41 22nF 25V, 10% Ceramic
C42 Not used
C43 100nF 25V, 10% Ceramic
C44, C45 100uF 10V, -10%+80% Electrolytic
C46-C48 Not used
C49 560pF 25V, 10% Ceramic
C50 22uF 10V, -10%+80% Electrolytic
C51-C54 Not used
C55-C62 22nF 25V, 10% Ceramic
C63-C65 Not used
C66 22nF 25V, 10% Ceramic
C67 100pF 25V, 10% Ceramic
C68-C73 Not used
C74 4.7uF 5V Min Electrolytic
C75 100nF 25V, 10% Ceramic
C76-C79 Not used
C80 22uF 10V, -10%+80% Electrolytic
C81-C99 Not used
C100 10nF 25V, 10% Ceramic
C101 22nF 25V, 10% Ceramic
C102, C103 Not used
C104 100nF 25V, 10% Ceramic
C105 180pF 25V, 10% Ceramic
C106-C110 22nF 25V, 10% Ceramic
C111, C112 47uF 16V, -10%+80% Electrolytic
C113, C114 47nF 25V, 10% Ceramic
C115 330pF 25V, 2% Ceramic
C116 10nF 25V, 10% Ceramic
C117 Not used
C118, C119 1nF 25v, 10% Ceramic
C120 100pF 25v, 10% Ceramic
C121 47pF 25v, 10% Ceramic
C122 1nF 25v, 10% Ceramic
C123 1uF 10V, -10%+80% Electrolytic
C124 20pF 25V, 2% Ceramic 3
C125 100nF 25V, 10% Ceramic
C126 22pF 25V, 10% Ceramic
C127 1uF 10V, -10%+80% Electrolytic
C128 47nF 25V, 10% Ceramic
C129 100pF 25V, 10% Ceramic
C130 (Note 6) 25V, 2% Ceramic 6

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Coils:
Circuit Reference Value Rating/Tolerance Manufacturer/Type Notes
COIL Spectrum TFR N Devon
L1/2 N Devon, Toroidal/2- 7
winding
L3 Toko, 7KL (PF291ACS-
1885Z)
L4 Toko, 7KL ( ? ) 8
L5 Not used
L6, 7 100Uh Taiyo, LAL04-0-101K

Connectors:
Circuit Reference Value Manufacturer/Part No
EAR, MIC 3.5mm jack socket N Devon
PWR 2.1mm co-axial socket Hoseiden
KB1 5-way ribbon connector BURNDY TE-5-5S1V3
KB2 8-way ribbon connector BURNDY TE-8-5S1V3
RGB 8-way DIN socket or 9-way D-
Type connector
KEYPAD, 6-way telephone jack socket BICC, BT Type, 603A
RS232

Crystals:
Circuit Reference Frequency Manufacturer/Type Notes
X1 17.734475MHz 5

Diodes:
Circuit Reference Device Manufacturer/Type Notes
D1-D8 1N4148 Signal
D9-D12 Not used
D13 1N4148 Signal
D14 Not used
D15 BA157 Rectifier
D16 Not used
D17 BA157 Rectifier
D18 Not used
D19 BZY88C5V1 Zener
D20-D27 1N4148 Signal
D28, D29 BA157 Rectifier
D30-D34 1N4148 Signal

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Integrated Circuits:
Circuit Reference Device Manufacturer/Type Notes
IC1 (ULA) 7C001 Ferranti
IC2 (CPU) Z80A/u780 Zilog/NEC
IC3, 4 Not used
IC5 (ROM) SPECTRUM 128 VTI 4
IC6-IC13 4164 150ns 1
IC14 Not used
IC15-IC22 4164 150ns 1
IC23-IC26 Not used
IC27 ZX8401 Mullard
IC28 74LS04 Texas
IC29 HAL10H8CN MMI, National
IC30 74LS157 Not National
IC31 74LS174 -
IC32 AY-3-8912A General Instrument
IC33 1488 -
IC34 1489 -
IC35 Not used
IC36 TEA2000 Philips
IC37 74S04 -
IC38 MC1376 Motorola

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Resistors (1/4W, 5% unless otherwise stated):

Circuit Reference Value Rating/Tolerance Manufacturer/Type Notes
R1-R8 470R
R9-R16 8K2
R17-R23 470R
R24 1K0 2
R25 180R
R26, R27 470R
R28-R30 10K0
R31 220K
R32 Not used
R33 680R
R34 15R 0.5W or 1W
R35 10K0
R36 680R
R37 1K0
R38-R57 Not used
R58 1K0 2%
R59 1K8 2%
R60 220R
R61 15R
R62-R64 Not used
R65-R67 10K0
R68 6K8
R69 10K0
R70-R72 Not used
R73 1K0
R74-R78 Not used
R79 2K2
R80-R86 Not used
R87 0R
R88 1K0
R89 8K2
R90 1K5
R91-R95 68R
R96-R98 10K0
R99 470R
R100 1K5
R101, R102 820R
R103 3K3
R104 470R
R105 1K0
R106 820R
R107 3K9
R108 6K8
R109 4K7
R110 15K0
R111 39K0
R112 68K0
R113 36K0 2%
R114 1K0
R115 10K0
R116 Not used
R117-R120 1K0
R121 Not used
R122 1K0
R123 180R
R124, R125 470R
R126 330R
R127 1K5

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Resistors (Continued):
Circuit Reference Value Rating/Tolerance Manufacturer/Type Notes
R128 8K2
R129 1K0
R130, R131 1K5
R132 39K0
R133 56R
R134 75R
R135 8K2
R136 Not used
R137 47R
R138 470R

Transistors:
Circuit Reference Device Alternative Notes
TR1, TR2 Not used
TR3 ZTX313 KSC839 2
TR4 ZTX650
TR5 ZTX213
TR6 ZTX313
TR7 Not used
TR8, TR9 Not used
TR10 BC308B BC213P/BC558B
TR11-TR13 BC239B BC184P/BC549B
TR14 ZTX313

Miscellaneous:
Reference Description Manufacturer / Part No.

REG 5V Regulator 7805

MOD UHF Modulator with E36 Vision ASTEC UM1233
Carrier (UK only)
Heatsink Special (Issue 4)
Regulator Fixings (1) Screw, ch hd. 4BA x 15/16 in
Regulator Fixings (2) Washer, shk prf, 4BA
Regulator Fixings (3) Nut, hex, 4BA
DIL SKT 48-way for IC1 (ULA) Airies, 48-511-10
Reset Switch P/B Switch Schadow, DPC0

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5.5 KEYPAD PCB COMPONENTS

Circuit Reference Value/Description Rating/Tolerance Manufacturer/Type Notes

Capacitors (axial types)
C1 1uf 10V, -10%+80% Electrolytic
C2, C3 47Pf 25V, 10% Ceramic

Coils
L1 68Uh +/-10% Toko, 348LS – 680K

Connectors
J1, J2 5-way ribbon connector BURNDY TE-5-5S1V3
J3 5-way connector Molex, 4494-05-04

Diodes
D1 BZY88C 5V1 Zener
D2 BZY88C 4V3 Zener

Integrated Circuits
IC1 PIC1652 General Instrument

Resistors (1/4W, 5%)

R1, R2 47R
R3 1K0
R4 100K
R5 1K0

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5.6 PART NUMBER REFERENCES

Number Description Part No.

1. IC Z80A/U780 X-1151
2. IC Multiplexer 16 pin X-1152
3. IC PCF1306P (ZX8401) X-1153
4. IC 74LS04 X-1016
5. IC ROM-28 PIN 256K MASK X-1154
6. IC ULA 7C001 X-1155
7. IC RAM 4164 X-1054
8. IC HAL10H8CN X-1156
9. IC 74LS174 X-1157
10. IC AY-3-8912A X-1158
11. IC 1488/MC1488P/SN 75188N X-1067
12. IC 1489/MC1489P/SN 75189N X-1068
13. IC TEA2000 X-1159
14. IC MC1376 X-1160
15. IC 74S04 X-1161
16. TR ZTX313 X-1017
17. TR BC184P/BC239B/BC49B X-1162
18. TR BC213/BC3088/BC5588 X-1163
19. TR ZTX 650 X-1164
20. DI BA157 X-1023
21. DI Zener 500mv X-1165
22. DI 1N4148 X-1022
23. COIL 5 pin Neosyd Former X-1166
24. CHOKE Bifilar Wound X-1167
25. COIL 7KL (6omh) X-1168
26. COIL 100mH X-1169
27. CRYSTAL 17.73447MHz X-1170
28. SOCKET ROM 28 pin X-1171
29. SOCKET EAR/MIC 3.5mm X-1031
30. SOCKET Power 3 Leg X-1172
31. SOCKET U.L.A. 48 pin X-1173
32. SOCKET 8 way pin X-1174
33. SOCKET 6 way pin X-1175
34. CONNECTOR 8 way X-1176
35. CONNECTOR 5 way X-1177

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Miscellaneous

Number Description Part No.

36. MODULATOR UK Type X-1178
37. Lower Case Moulding X-1179
38. Keyboard and Top case Sub-Assembly X-1180
39. Reset Switch Sub-Assembly X-1181
40. Foot Rubber X-1182
41. Reaction Plate Plastic X-1183

Accessories

Number Description Part No.

42. Power Supply 9V 1.85 Amp UK 1850 X-1220
43. Data Transfer Cable 3.5mm 3.5mm into-two X-1203
44. 128 Super Test Cassette X-1221
45. 128 Never Ending Story Cassette X-1222
46. R.F. Cord X-1100
47. Service Manual X-1223
48. Introduction Book X-1224
49. Carton Plain + SA Label X-1225
50. Poly Pack Set X-1226/PP

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6 APPENDICES

6.1 SPECTRUM 128 PCB REAR FOIL LAYOUT

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6.2 SPECTRUM 128 DIGITAL SCHEMATICS

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6.3 SPECTRUM 128 ANALOGUE SCHEMATICS

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6.4 SPECTRUM 128 BLOCK DIAGRAM

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