&

Logic gates Logic circuits

Logic gates Truth tables

2" (used to find the total (

ID-lAND Gate); possible combinations
-> ->

A 0, B 0,x 0A 1, B 0,X 0A
0,B 1,X 0A 1,B 1,X 1
= =
= = = =
= = = =

= =

Example
->

/Expressed with". "where A.B(

P, Q:i ntermediate outputs.
A
->

I)-lORGate); A 0, B 0, x
=
=

0
=
A 1, B 0,X 1
=
=
=
A 0, B 1,
=
=
X = A 1, B 1,X 1 =
= =
B

I Expressed with "+ "where A+ B( C Daz

-> & Expressed as ((A + B31.2) 2
=
)

-0-(NOTGate); A 0, =
x 1 =

A b,x=
0
=

Truth Table
I Expressed with a
"-
"where A ( =
->
2 2x2x2 =
8

->
ID--(MANDGate); A 0, B 0, x 1
=
=
=
A 1, B 0,X 1 A 0,B 1,X 1 A 1,B 1,X
=
=
= = = =
=
=
0
=

Input Intermediate output Output

(Expressed with a "- "where A.B( B
A C P Q Z

O 00 0 O O
A 1, B 0,X 0A 0,B 1,X 0A 1, B 1,X 0
IDo-(NORGate);A 0, B 0,
=
=

x 1
=
=
= =
= = =
-> = =
=

00 00 O
-

(Expressed with a "+"whereA B

+

(
01 0 1 0 O

I) (XORGate);A A 1, B 0,X 1 A 0,B 1,x 1A 1,B 1,X

=

0
-> 0, B 0, x 0
= =
= = =
= = =
= = =

I I I
=

0 I I

"*"where AGB)
(Expressed with a

100 I 0 O

10 I I I I

Boolean Expression 10 I 0 0

the 2. I I I I
1. Identify gates Write down the I I

.)"* Expression
OR Gate 42 I
->

->
NAND Gate -> A B +
Count up using binary
to fill the combinations

-> XOR Gate A.B

->

ID" -> A*B

Dix 3. Lable each section

1. A
-> ORgate, lable as
it

c. Jo B
(Intemidiate Outputs (
-> 2. NAND gate, lable it as B

3. XOR gate, lable

-> as C
it

(((A B(*(5e() c)
+ + x
=

4. OR gate, lable
->
ita s D

-
to show
Use brackets
->

which steps first.

4. Create
your expression
-> A* B 13.) -> As seen A is to A B
expanded
+

(
-> C + Input

This
Try
->
 Architecture
Computer
->
You Neumann Architecture Arithmetic Logic Unit

Secondary -> ALU (the shortform of the Arithmetic Unit) is the calculator of the CPU. It
Control
Storage
Logic
&
2.9. HDD, SSD
handles
ALU Clock
time, mathematical and logical operations thata re
required of an instruction.

e Clock
S ↳
Control to
The CPU contains an internal clock that is used regulate the number
m
->

Unit

< Cache, of
cycles carried outper second, and synchronise other components. Shown
Registers PC CIR

in
gigahertz, 2.4, 5GHz.
AC MAR MDR
-
Virtual Memory
Buses
Address

-> ACPU bus is of

a set
parallel wires thatc onnects other components

of the CPU together. Ranges from I bit to 64bit or more. The more bit

Fetch
-Cycle [FEDC]
Execute Decode information to
transport.
size, the it is able
-

more
-

Control Unit

Fetch Instructions are loaded into memory (Ram) before the -> Itunderstands the other
processor starts instructions and instructs components.

running the
program.
Each instruction is fetched from
memory (in Registers

order), and
put into
appropriate registers. The Control w ill
unit then -> Registers are small units of storage in the CPU thata re
extremely

the for the next fastbutexpensive. Located in the CPU and stores instructions
access instructions
stages.
or inputs from the user so that
i tcan be used
quickly.
HDD SSD -> Ram ->
(PUmemory

FED-Cycle
-
The Prog.) Setto 1 (memory address register (
Decode binary representation of
-

an instruction needs to be decoded

-

-> Incrementprogram Counter by 1

before it can run. This is the u ses to work
the control unit x
process
MDR -

Instruction fetched and stored in MDR (Memory Data Register (

need to do. Each
outwhatother
components processor will have slightly
↓
1
Each Input is a new
loop,
from MAR.
differentencodings for instructions. MDR -
CIR-stored in memory Data Register to data
current
register Calculation is a new
loop.
↓ ->
Program counter or

Decode -
Instruction from the CIR
MAR Increase

↓ each time
Execute Once the instruction is
understood, the instruction will be executed.
stops
-

Execute -
Moves on the cycle.
The control unitw ill tell other need to do
components what
they
o rder
in for the instructions to work.