Scribd
Upload
14 views5 pages

EE222 Midterm Examination

1. For low power CMOS circuits, the design principle is to reduce the power supply voltage VDD, voltage swing ΔV at outputs, switched capacitance Csw, and transistors' threshold voltage VTH. This minimizes power consumption. 2. Using a distributed L-type RC model, the Elmore delay from point A to C of the T-shaped metal interconnect is calculated to be [value] ps. 3. A super buffer can drive a large load capacitance CL instead of abruptly enlarging the gate size. For the given gate capacitance Cg and load capacitance CL, the minimum delay is [value] ps.

Uploaded by

成希
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
14 views5 pages

EE222 Midterm Examination

1. For low power CMOS circuits, the design principle is to reduce the power supply voltage VDD, voltage swing ΔV at outputs, switched capacitance Csw, and transistors' threshold voltage VTH. This minimizes power consumption. 2. Using a distributed L-type RC model, the Elmore delay from point A to C of the T-shaped metal interconnect is calculated to be [value] ps. 3. A super buffer can drive a large load capacitance CL instead of abruptly enlarging the gate size. For the given gate capacitance Cg and load capacitance CL, the minimum delay is [value] ps.

Uploaded by

成希
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 5

EE222 Midterm Examination

February 6, 2018
Name________________________ Student ID________________________
1. (20 points) For low power operation of CMOS circuits, describe the design principle in
terms of power supply voltage 𝑉𝑉𝐷𝐷𝐷𝐷 , voltage swing ΔV at output nodes, switched
capacitance 𝐶𝐶𝑠𝑠𝑠𝑠 (= product of switching frequency and capacitance), and MOST’s
threshold voltage 𝑉𝑉𝑇𝑇 .
2. (20 points) Let us consider a T shape metal interconnect configuration of a uniform
width 1 µm that connects three gates. Its horizontal length from point A to point B is
1000 µm and its vertical length starting at the center of the horizontal line is also 1000
µm long ending at point C.
Assuming that the line resistance is 0.1 Ω/square, and line capacitance including the
fringing field effect is 0.066 fF/ µm2 , find an Elmore delay from the top left corner
point A to the bottom most point C. Use a distributed L-type RC model for every 250
µm.
B
A

C
3. (30 points) A super buffer can be used to drive a large load capacitance 𝐶𝐶𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙 instead of
abruptly enlarging the driving gate’s transistor sizes. When the gate capacitance of an
intrinsic inverter is 𝐶𝐶𝑔𝑔 =0.166 fF and 𝐶𝐶𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙 = 3.655 pF,
find a minimum delay in picoseconds. Here the intrinsic inverter’s delay 𝜏𝜏𝑜𝑜 is calculated
from a 11-stage ring oscillator that has a frequency of 90.9 GHz.
(Hint: Find 𝜏𝜏𝑜𝑜 from the oscillation frequency as f= 1/(2 𝑋𝑋 11𝜏𝜏𝑜𝑜 ). Also 𝐶𝐶𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙 /𝐶𝐶𝑔𝑔 = 𝑒𝑒10 with
e= 2.718.)
4. 𝐚𝐚𝐚𝐚𝐚𝐚𝐚𝐚𝐚𝐚 𝐰𝐰𝐰𝐰𝐰𝐰𝐰𝐰𝐰𝐰𝐰𝐰𝐰𝐰𝐰𝐰 (𝐠𝐠𝐠𝐠𝐠𝐠𝐠𝐠 𝐯𝐯𝐯𝐯𝐯𝐯𝐯𝐯𝐯𝐯𝐯𝐯𝐯𝐯) 𝐢𝐢𝐢𝐢 𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬 𝐭𝐭𝐭𝐭 𝟐𝟐𝑽𝑽𝑫𝑫𝑫𝑫 . (30 points) A dynamic random
access memory (DRAM) cell is connected to its bitline (BL) with a total capacitance of
450 fF. The physical dimensions of the DRAM cell’s NMOS transistor is shown below.
The current driving power 𝑰𝑰𝑫𝑫𝑫𝑫 is described below. Let us assume that 𝑉𝑉𝐷𝐷𝐷𝐷 = 2𝑉𝑉 and
𝑽𝑽𝑫𝑫𝑫𝑫
𝑉𝑉𝑇𝑇𝑇𝑇 = 0.5 V, 𝐶𝐶𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 = 50 fF. Find the time it takes for BL, which was precharged to
𝟐𝟐
by a precharge pulse while 𝑪𝑪𝒔𝒔𝒔𝒔𝒔𝒔𝒔𝒔𝒔𝒔𝒔𝒔𝒔𝒔 𝐰𝐰𝐰𝐰𝐰𝐰 charged to 𝑽𝑽𝑫𝑫𝑫𝑫 , to reach the beginning of a
steady state value after the wordline (WL) signal which is the gate voltage of NMOS
transistor is switched to 𝟐𝟐𝑽𝑽𝑫𝑫𝑫𝑫 .

For simple calculation, assume that the parasitic drain capacitance can be neglected,
and WL is driven with a high voltage 2 𝑉𝑉𝐷𝐷𝐷𝐷 such that the NMOST is in its linear region,
i.e.,
𝟏𝟏
𝑰𝑰𝑫𝑫𝑫𝑫 = 𝒌𝒌𝒏𝒏 ′ 𝑾𝑾𝒏𝒏 ⁄𝑳𝑳𝒏𝒏 𝑽𝑽 ((𝑽𝑽𝑮𝑮𝑮𝑮 - 𝑽𝑽𝑻𝑻𝑻𝑻 ) 𝑽𝑽𝑫𝑫𝑫𝑫 – ½ 𝑽𝑽𝟐𝟐𝑫𝑫𝑫𝑫 ),
𝟏𝟏+ 𝑫𝑫𝑫𝑫
𝑬𝑬𝑪𝑪 𝑳𝑳𝒏𝒏
1
where 𝐸𝐸𝐶𝐶 = 105 V/cm, 𝐿𝐿𝑛𝑛 = 0.05 μm. The average value of 𝐼𝐼𝐷𝐷𝐷𝐷 = (𝐼𝐼𝐷𝐷𝐷𝐷 for 𝑉𝑉𝐷𝐷𝐷𝐷 = 2V +
2
𝐼𝐼𝐷𝐷𝐷𝐷 for 𝑉𝑉𝐷𝐷𝐷𝐷 = steady state value) can be used for calculation of the delay.

Source is
connected to BL
with its
Source capacitance of
Drain
n+
n+ 𝑊𝑊𝑛𝑛 450 fF
= 250𝑛𝑛𝑛𝑛
Drain is
connected to
the storage
capacitance of
𝐿𝐿𝑛𝑛 =50nm 50 fF
(for problem 4 continuation)

You might also like