Alt 2 Pads

SIEMENS EDA
PADS® Layout Translator

User’s Guide
Release PADS VX.2.10
Document Revision 7
Unpublished work. © 2021 Siemens
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Revision History ISO-26262
Revision Changes Status/Date

7 Modifications to title page to reflect the latest product version Released
supported. Approved by Kevin Chupp. September
All technical enhancements, changes, and fixes listed in the 2021
Personal Automation Design System Release Notes for this product
are reflected in this document. Approved by Mike Bare.
supported. Approved by Regis Krug. November
supported. Approved by Regis Krug. March 2020
All technical enhancements, changes, and fixes listed in the
supported. Approved by Regis Krug. September
Author: In-house procedures and working practices require multiple authors for documents. All
associated authors for each topic within this document are tracked within the Siemens
documentation source. For specific topic authors, contact the Siemens Digital Industries
Software documentation department.
Revision History: Released documents include a revision history of up to four revisions. For
earlier revision history, refer to earlier releases of documentation on Support Center.
PADS® Layout Translator User’s Guide, PADS VX.2.10
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4 PADS® Layout Translator User’s Guide, PADS VX.2.10
Table of Contents
Revision History ISO-26262
Chapter 1
Introduction to the PADS Layout Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 2
CADSTAR Design and Library Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CADSTAR Library Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CADSTAR Design Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Translating CADSTAR Designs and Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Combining CADSTAR Layout and Schematic Libraries into a Single PADS Library . . . . 14
CADSTAR to PADS Rule Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CADSTAR to PADS Layer Type Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CADSTAR to PADS Areas and Coppers Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Chapter 3
OrCAD Design and Library Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
OrCAD Library Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
OrCAD Design Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Translating OrCAD Designs and Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Combining OrCAD Layout and Schematic Libraries into a Single PADS Library . . . . . . . 24
OrCAD To PADS Design Rule Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
OrCAD to PADS Layer Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
OrCAD to PADS Obstacle Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Chapter 4
P-CAD Design and Library Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
P-CAD Library Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
P-CAD Design Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Translating P-CAD Designs and Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Combining P-CAD Layout and Schematic Libraries into a Single PADS Library. . . . . . . . 34
P-CAD to PADS Rule Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
P-CAD to PADS Default Layer Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
P-CAD Object Type to PADS Rule Owner Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Chapter 5
Altium/Protel Design and Library Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Altium/Protel Library Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Altium/Protel Design Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Altium Designer Translation Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Translating Altium/Protel Designs and Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Combining Altium/Protel Layout and Schematic Libraries into a Single PADS Library. . . 47
PADS® Layout Translator User’s Guide, PADS VX.2.10 5

Table of Contents
Altium/Protel to PADS Rule Owner Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Altium/Protel to PADS Rule Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Altium/Protel to PADS Layer Type and Name Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Chapter 6
Eagle Design and Library Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Eagle Library Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Eagle Design Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Eagle Translator Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Translating Eagle Designs and Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Eagle to PADS Rule Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Eagle to PADS Default Layer Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Third-Party Information

Chapter 1
Introduction to the PADS Layout Translator
The PADS Layout translator converts CADSTAR®, OrCAD®, P-CAD®, Protel®, Altium®, and
Eagle® PCB designs and libraries to PADS Layout designs and libraries.
This is a list of the input types and versions:
• CADSTAR design files in binary (*.pcb) formats and PCB Components, Parts, and
Documentation Symbols libraries in binary (*.lib) formats generated in CADSTAR up
to version 8.
• CADSTAR design files and PCB Components, Parts, and Documentation Symbols
libraries in ASCII (*.cpa) formats generated in CADSTAR up to version 18.
• OrCAD Layout design files in both binary (*.max) and ASCII (*.min) formats generated
in OrCAD Layout 9.X, 10.X.
• OrCAD PCB libraries in both binary (*.llb) and ASCII (*.min) formats generated in
OrCAD Layout 9.X, 10.X.
• P-CAD design files (*.pcb) in both binary and ASCII formats generated in P-CAD 2001,
2002, 2004, 2006.
• P-CAD PCB libraries in the binary format (*.lib) generated in P-CAD 2001, 2002, 2004,
2006.
• Protel 99 design files (*.pcb) in both binary and ASCII formats, including designs stored
in Protel Design Database (*.ddb) project files.
• Protel 99 PCB library files (*.lib), including PCB libraries stored in Protel Design
Database (*.ddb) project files.
• Altium design files (*.pcbdoc) in binary or ASCII format generated in Altium DXP,
2004, 2006, or in Altium Designer. Translation of Altium Designer files Winter09 and
later is supported at a Beta level, since this part of the translator is still under
development.
• Altium PCB library (*.pcblib) files, including libraries stored in Integrated Libraries
(*.intlib) generated in Altium DXP, 2004, 2006, or in Altium Designer. Translation of
Altium Designer files Winter09 and later is supported at a Beta level, as this part of the
translator is still under development.
• Eagle designs files (*.brd) in ASCII-XML format generated in Eagle Version 6.X or
later.
• Eagle library files (*.lbr) in ASCII-XML format generated in Eagle Version 6.X or later.
Introduction to the PADS Layout Translator
Chapter 2
CADSTAR Design and Library Translation
The PADS Layout translator converts the following categories of CADSTAR design and library
files:
• CADSTAR design files in binary (*.pcb) formats and PCB Components, Parts, and
Documentation Symbols libraries in binary (*.lib) formats generated in CADSTAR up
to version 8.
• CADSTAR design files and PCB Components, Parts, and Documentation Symbols
libraries in ASCII (*.cpa) formats generated in CADSTAR up to version 18.
Tip
The PADS Layout translator does not convert CADSTAR Schematic Symbols libraries. Use
the PADS Schematic translator to translate these libraries.
CADSTAR Library Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CADSTAR Design Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Translating CADSTAR Designs and Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Combining CADSTAR Layout and Schematic Libraries into a Single PADS Library 14
CADSTAR to PADS Rule Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CADSTAR to PADS Layer Type Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CADSTAR to PADS Areas and Coppers Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CADSTAR Library Translation Notes

The content of a single CADSTAR library is translated into the correct file section of a PADS
library.
PADS Layout Library Structure

A PADS Layout library consists of 4 files:
• Part Type (.pt9)

• PCB decal (.pd9)
• CAE Decal (.ld9)
• 2D Lines (.ln9)
CADSTAR Design Translation Notes
The translator automatically creates these files from the single CADSTAR source file. The
output Part Type and PCB Decal files contain data; the CAE Decal and 2D Lines files do not
contain data—their data is generated by the PADS Schematic Translator.
CADSTAR Libraries
CADSTAR library files can be one of the following types: Parts, PCB Components, Schematic
Symbols, and Documentation Symbols. Since part entries in the Parts library refer to symbols
located in a separate PCB Components library, make sure that the associated PCB Components
libraries are located in the same directory as the Parts library you are translating.

There are a number of differences between the structures of CADSTAR and PADS Layout
designs. Some elements do not translate and others require manual intervention.
Output File Names

The translator preserves the original file name while translating the file into PADS Layout
unless the original file extension is .pcb. If the original file extension is .pcb, then the translator
adds "_pads" to the original file name to get a translated design file name.
Design Rules Translation

See CADSTAR to PADS Rule Mapping for details of the mapping of CADSTAR design rules
to PADS Layout.
Layer Name and Type Translation

• Layer Name — The translator gives you the option of preserving the original
CADSTAR layer names, or changing them to the corresponding default PADS Layout
layer names.
• Layer Type — See CADSTAR to PADS Layer Type Mapping for details of design
layer mapping from CADSTAR to PADS Layout.
Note
If a CADSTAR layer has no equivalent layer type in PADS Layout, the translator uses the
CADSTAR name in the translated file.
Areas and Coppers Translation

Since PADS Layout does not support hatched coppers, the translator flags hatched Figures and
unattached Coppers as a warning in the log file, and translates them as regular pieces of drafting
copper in PADS Layout.
Since there are no equivalents in PADS Layout for CADSTAR’s Placement Area, Routing Area
and Area Cutout, these Areas and Area Cutouts are ignored by the translator and an appropriate
message is entered in the log-file.
See CADSTAR to PADS Areas and Coppers Mapping for information on how CADSTAR
Areas and Coppers are translated to PADS Layout.
Component Outline Color

Component outlines may be colored differently when loaded in PADS Layout and PADS
Router. PADS Router uses the Top Layer color to display the component outline, but PADS
Layout uses the color of the layer where the component outline was originally placed.
Flooding/Hatching
Translated copper pour and plane area objects aren’t automatically hatched when you load the
translated design in PADS Layout. They are automatically hatched when you load the translated
design in PADS Router.
Self-intersecting Copper Pours

Some copper pours that are self-intersecting, or that have areas too small for hatching, cannot be
flooded/hatched by PADS Layout. The translator detects these coppers, flags them in the log-
file as an error, and translates them as a 2D-line object in PADS Layout.
Figure Attributes
Since PADS Layout does not support attributes on geometry, keepouts, coppers and
connections, CADSTAR's Figure, Area, Copper, Template and Connection attributes are not
translated. If the Translate figure and copper labels as free text option is checked, the translator
creates the attributes’ values as free text objects.
Net Class Attributes

CADSTAR Net Class attributes are translated as net attributes for all nets included in the Net
Class. CADSTAR Spacing Classes are translated as PADS Layout Net Classes. CADSTAR Net
Spacing rules are translated as PADS Layout Net Class general and conditional rules.
Multi-line Labels and Attributes

A multiline free text object from a CADSTAR design becomes multiple single-line free text
objects in PADS Layout. A multiline attribute from a CADSTAR design is translated as a
single-line label or attribute to PADS Layout with concatenating multiple lines to single line.
Cross Hatch Patterns

Second Hatch Line parameters from CADSTAR design Hatching Assignments are ignored.
Translating CADSTAR Designs and Libraries
Dashed and Dotted Lines

Since PADS Layout does not support non-solid line styles, the translator emulates dashed and
dotted lines as drawing shapes with a set of small line and arc segments.

You can translate your CADSTAR designs and libraries into PADS Layout designs and
libraries.
Procedure
1. Start menu > PADS [Version] > PADS Layout Translator
2. Select the CADSTAR tab.
3. Populate the Files to translate file list:
a. In the Files to translate area, select the appropriate check box(es) to specify whether
to translate designs, libraries, or both. Then click Add.
b. In the Select Input Design(s) dialog box, browse to and select the source file(s) you
want to make available for translation.Then click Open. The selected files are added
to the Files to translate file list. Files newly added to the list are checked (enabled for
translation) by default.
If an added file’s format is not recognized, or is recognized as a PADS format, the
file is flagged in the list and is not translated.
To remove a file from the list, select it and click Remove.
Tip
If you are translating a CADSTAR Parts Library, all associated PCB
Components libraries must be located in the same directory as the Parts library.
4. Set the output location for translated files:

a. In the Designs box, accept the default output location for translated design files, or
click the ... button to browse to and specify a different one.
b. In the Libraries box, accept the default output location for translated library files, or
The default values are from the current FileDir (designs) and LibDir (libraries)
entries in the PADS Layout powerpcb.ini file.
Tip
If the output file is open in PADS Layout, the file is not translated and a message
is written to the output log.
5. In the Overwrite existing files drop-down list, select one of the following to specify how
the translator should proceed if it needs to overwrite an existing file:
• No — Leave the existing file intact; the source file is not translated.
• Yes — Overwrite the existing file.
• Ask — Display a prompt asking whether to overwrite the existing file.
6. In the CADSTAR tab, select the check boxes to set translation options.
• Select the Preserve net colors check box to preserve the colors of CADSTAR nets
for corresponding nets in PADS Layout.
Tip
Because PADS Layout net color applies to nets, pads, vias, and coppers, while
CADSTAR net color applies only to unroutes, the translated design colors may
not match the original design colors.
• Select the Rename layers check box to rename CADSTAR layer names to PADS
Layout names. See Translating CADSTAR Designs and LibrariesTranslating
CADSTAR Designs and Libraries for information on CADSTAR to PADS layer
name mapping.
• Select the Translate figure and copper labels as freetext check box to preserve the
CADSTAR figure, copper, template and connection attribute values as free text
objects in PADS Layout. If this check box is unselected, attributes of these types will
be ignored.
• Select the Explode doc symbols check box to allow exploding of CADSTAR
document symbols to collections of line, arc and text objects. If the box is
unchecked, document symbols are translated as component symbols in PADS
Layout.
7. (Optional) Click the Attributes Mapping button to display the Attributes Mapping
dialog, where you can add, delete and modify CADSTAR component and net attribute
names, and map them to PADS Layout equivalents. (The translator uses the attributes
mapping while translating part type, decal, component, net class, and pin attributes. The
mapping is preserved in the translator’s configuration ini-file.)
Tip
Attributes that are not listed are translated using the original name from the source
design; they have an attribute type of Free Text.
• To add a new item to the attributes map:

i. Select the Component Attributes, Net Attributes, or Pin Attributes tab.
ii. Type the CADSTAR attribute name in the Name box (or select it from the list
directly below the box.)
Combining CADSTAR Layout and Schematic Libraries into a Single PADS Library
iii. Select the corresponding PADS attribute name in the Map to box.
iv. Select the type of the attribute in the Type combo box and click the Add button.
Tip
To add an item with a new unit type, select Measure in the Type combo box,
type the new unit name in the Quantity combo box, click the Add button and
specify a unit abbreviation (for example, m or F) and a short unit name (for
example, meter or Farad) in the New Unit dialog box. Then click the Add button
again.
When you are finished adding, deleting and modifying items, Click OK to close the
Attributes Mapping dialog.
8. In the PADS Layout Translator dialog, click Translate. The displayed Translation
Progress indicator shows both current file and overall job progress.
When translation is complete, the Translation Results dialog box displays the content of
a log file created during translation. The log file contains the following information:
• Path of the translated files
• Number of errors and warnings
• Detailed description of each error or warning
Combining CADSTAR Layout and Schematic

Libraries into a Single PADS Library
You may want to have a single PADS library that includes all the Part Type, PCB Footprint, and
CAE Decal data.
Procedure
1. Using the Layout translator, translate the CADSTAR library.
2. Using the Schematic Translator, clear the Overwrite existing files check box, and
translate the CADSTAR library. Save the schematic library to the same directory where
you saved the library you translated in Layout.
Results
The Schematic translator does not overwrite Part Types created by the Layout translator, and it
creates records in the schematic symbol library file (.ld9).
CADSTAR to PADS Rule Mapping

A table mapping the translation of design rules from CADSTAR to PADS Layout helps you to
know what rules get translated and how find the rules in PADS Layout.
Note
CADSTAR design rules not listed in the table are not translated.
CADSTAR PADS Layout Comment / Value

Map
Category Name Category Name
Assignments / Comp Placement Clearance Body to Body Applies to Default
Design Rules to Comp rules from (Default)
Placement layer entries, All
against Layer.
Copper to Board Clearance Board to Copper Conditional rules
Copper to Clearance Copper to from layer
Copper Copper reassignment
entries.
Hole to Hole Clearance Drill to Drill
Pad to Board Clearance Board to Pad
Pad to Copper Clearance Copper to Pad
Drill to Copper
Text to Pad
Pad to Pad Clearance Pad to Pad
Drill to Pad
Pad to SMD Pad Clearance SMD to Pad
Drill to SMD
Pad to Via Clearance Pad to Via
Drill to Via
Route to Board Clearance Board to Trace
Route to Copper Clearance Copper to Trace
Text to Trace
Route to Pad Clearance Pad to Trace
Drill to Trace
Route to Route Clearance Trace to Trace

Map
Route to SMD Clearance SMD to Trace
Pad
Route to Via Clearance Via to Trace
SMD Pad to Clearance Board to SMD
Board
SMD Pad to Clearance Copper to SMD
Copper Text to SMD
SMD Pad to Clearance SMD to SMD
SMD Pad
Via to Board Clearance Board to Via
Via to Copper Clearance Copper to Via
Text to Via
Via to SMD Pad Clearance SMD to Via
Via to Via Clearance Via to Via
Assignments / First Spacing Clearance All clearance For each spacing
Net Spacing Class / Second values, except class, net class with
Spacing Class / Body to Body the same name is
Spacing and Drill to Drill created in PADS
Layout. Applies to
Default rules from
the (Default) layer
(Unclassed) -
Unclassed) entry,
All against Layer
Conditional rules
from layer
reassignment
(Unclassed) -
(Unclassed) entries,
Net Class rules from
(Default) layer
<SpcClass> -
(Unclassed) entries,
Net Class against
Net Class
Conditional rules
from <SpcClass1> -
<SpcClass2> entries
CADSTAR to PADS Layer Type Mapping

Map
Assignments / Optimal Width Clearance Trace Width Applies to Default
Routes Min Width rules from the
default Net Route
Max Width Code, Net rules
from the (Default)
layer entries, Nets
against Layer.
Conditional rules
from layer
reassignments
entries.
Defaults / Routing Layers Routing Selected layers Applies to Default
Routes rules.
Via Code Routing Selected vias
Net attributes net_max_length High Speed Maximum Applies to Net rules.
Length
net_max_delay High Speed Maximum Delay
net_max_stub High Speed Maximum Stub
length
net_shield High Speed Shielding
lengthen_size High Speed Parallelism
Length
lengthen_space High Speed Parallelism Gap
net_diff_pair Differential Gap
Pairs
CADSTAR to PADS Layer Type Mapping

A table showing how layers are mapped during the translation helps you to verify that your
layers translated properly from CADSTAR to PADS Layout.
Tip
To ensure that CADSTAR non-electrical layers are properly translated, make certain that
their layer subtypes are specified in the CADSTAR file.
CADSTAR to PADS Areas and Coppers Mapping
CADSTAR Layer Type PADS Layout Layer Type

Electrical Layer Electrical Layer (No Plane)
Powerplane Layer Electrical Layer (CAM Plane). If a CADSTAR design contains
a Split Power Plane object on this layer, then the translated layer
becomes Split/Mixed plane.
Non-Electrical Layer Paste Non-electrical Layer of type Paste Mask, the Top or Bottom
subtype electrical layers should be associated with this layer.
Non-Electrical Layer Non-electrical Layer of type Silk-Screen, the Top or Bottom
Silkscreen subtype electrical layers should be assocated with this layer.
Non-Electrical Layer Solder Non-electrical Layer of type Solder Mask, the Top or Bottom
Resist subtype electrical layers should be associated with this layer.
Non-Electrical Layer Non-electrical Layer of type Assembly, the Top or Bottom
Assembly subtype electrical layers should be assocated with this layer.
Non-Electrical Layer Non-electrical Layer 20 (or 120 for Max Layers). General type.
Placement subtype
Non-Electrical Layer Other Non-Electrical Layer of General type.
subtypes
Documentation Layer Non-Electrical Layer of General type.
Construction Layer Substrate or Prepreg Thickness and Dielectric (Layer Thickness
dialog box).
CADSTAR to PADS Areas and Coppers

Mapping
A table showing how areas and coppers are mapped during translation helps you to verify that
your shapes translated properly from CADSTAR to PADS Layout.
CADSTAR PADS Layout Comment

Closed Figure filled with the Closed polygon drawing
Clear pattern shape on non-electrical
layer
Closed Figure filled with the Fixed (non-poured) copper
Solid pattern outline on non-electrical
layer
Closed Figure filled with the Flags as a warning in the log
Hatching pattern file

Cutout within a shape filled Closed polygon drawing
with the Clear pattern shape on non-electrical
layer
Cutout within a shape filled Copper Cut Out area
with the Solid or Hatching
pattern
Unattached non-closed Open copper path that is not
Copper filled
Unattached Copper filled
with the Clear pattern
Unattached Copper filled Fixed (non-poured) copper
with the Solid pattern outline on electrical layer
Unattached Copper filled Flags as a warning in the log
with the Hatching pattern file
Cutout within an unattached Copper Cut Out area
Copper
Template Copper pour area outline The Template Fill Style is
with zero hatch spacing ignored without a warning
Copper attached to a Poured copper outline with Flags as a warning in the log
Template filled with the the maximum allowed hatch file
Clear pattern spacing
Copper attached to a Poured copper outline with
Template filled with the zero hatch spacing
Solid pattern
Copper attached to a Poured copper outline
Template filled with the
Hatching pattern
Keepout Area Keepout with the Placement The Area Fill Style and Line
restrictions Style are not used in PADS
Layout and ignored without
Placement Area with the Keepout with the Placement a warning
Height specified restrictions and specified
Component Height
No Routes Area Keepout with the Trace and
Copper restrictions
No Vias Area Keepout with the Via and
Jumper restrictions

Routing Area or Placement <not translated> Flags as a warning in the log
Area with no Height filee
specified
Cutout within an Area <not translated> Flags as a warning in the log
file
Chapter 3
OrCAD Design and Library Translation
The PADS Layout translator converts the following types of OrCAD design and library files:
• OrCAD Layout design files in binary (*.max) and ASCII formats (*.min) generated in
• OrCAD PCB libraries in the binary (*.llb) and ASCII formats (*.min) generated in
OrCAD Library Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
OrCAD Design Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Translating OrCAD Designs and Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Combining OrCAD Layout and Schematic Libraries into a Single PADS Library . . . 24
OrCAD To PADS Design Rule Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
OrCAD to PADS Layer Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
OrCAD to PADS Obstacle Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
OrCAD Library Translation Notes

The content of a single OrCAD library is translated into the correct file section of a PADS
library.


• 2D Lines (.ln9)
The translator automatically creates these files from the single OrCAD source file. The output
Part Type and PCB Decal files contain data; the CAE Decal and 2D Lines files do not contain
data—these files are generated by the PADS Schematic Translator.
OrCAD Design Translation Notes
OrCAD Design Translation Notes

There are a number of differences between the structures of OrCAD and PADS Layout designs.
Some elements translate to difference structures and others require manual intervention.
Output File Names

The translator uses the original OrCAD file name as the name of the newly-translated PADS
Layout file.

See OrCAD To PADS Design Rule Mapping for details of the mapping of Orcad design rules to
PADS Layout.
Layers Translation
The translator gives you the option of preserving the original OrCAD layer names or changing
them to the corresponding default PADS Layout layer names.
See OrCAD to PADS Layer Mapping for details of the mapping of OrCAD design layers to
PADS Layout.
Obstacles Translation
See OrCAD to PADS Obstacle Mapping for details of the mapping of OrCAD obstacles to
PADS Layout.
Track Translation
If a track object has no assigned nets in OrCAD, it is translated as a 2-d line object in PADS
Layout; otherwise, it becomes a trace in PADS Layout.
Cross Hatch Patterns

OrCAD Line Hatch patterns are translated to PADS Layout as Cross Hatching. Hatch angle
patterns are translated to either orthogonal or diagonal patterns.
Individual Character Rotations

The translator splits texts having defined individual character rotations into multiple different-
orientated single-character text objects.
Translating OrCAD Designs and Libraries

You can translate OrCAD designs and libraries to PADS Layout designs and libraries.
Translating OrCAD Designs and Libraries
Procedure
2. Select the OrCAD tab.
click the ... button to browse to and specify a different one. The default values are
from the current FileDir (designs) and LibDir (libraries) entries in the PADS Layout
powerpcb.ini file.
Tip
6. In the Translation options area, select the OrCAD tab, and then select the check boxes to
set translation options.
• Select the Preserve net colors check box to preserve the colors of OrCAD nets for
corresponding nets in PADS Layout.
Tip
Because PADS Layout net color applies to nets, pads, vias, and coppers, while
OrCAD net color applies only to unroutes, the translated design colors may not
match the original design colors.
Combining OrCAD Layout and Schematic Libraries into a Single PADS Library
• Select the Rename layers check box to rename OrCAD layer names to PADS Layout
names. See OrCAD to PADS Layer Mapping for information on OrCAD to PADS
layer name mapping.
Tip
If an OrCADlayer has a non-default name, the translator preserves the non-
default name in the translated file even if the Rename layers check box is
selected.
• Select the Flood copper pours check box to flood all copper pours on the translated
board. If this check box is not selected, only copper pour outlines and cutouts are
preserved.
• Select the Explode doc symbols check box to allow exploding of OrCAD document
symbols to collections of line, arc and text objects. If the box is unchecked,
document symbols are translated as component symbols in PADS Layout.
Results
When translation is complete, the Translation Results dialog box displays the content of a log
file created during translation. The log file contains the following information:
Combining OrCAD Layout and Schematic

CAE Decal data.
Procedure
1. Using the Layout translator, translate the OrCAD library.
translate the OrCAD library. Save the schematic library to the same directory where you
saved the library you translated in Layout.
Results
OrCAD To PADS Design Rule Mapping
OrCAD To PADS Design Rule Mapping

A table mapping the translation of design rules from OrCAD to PADS Layout helps you to
know what rules get translated and how find the rules in PADS Layout.
OrCAD PADS Layout Comment/Value map

Route Spacing Track to Track Clearance Trace to Trace Applies to Default
rules with most
Track to Via Clearance Via to Trace common value and All
Track to Pad Clearance Pad to Trace against layer
conditional rules with
Drill to Trace
layer specific values.
SMD to Trace
Via to Via Clearance Via to Via
Via to Pad Clearance Pad to Via
Drill to Via
SMD to Via
Pad to Pad Clearance Pad to Pad
Drill to Pad
Drill to SMD
SMD to SMD
SMD to Pad
OrCAD to PADS Layer Mapping
OrCAD PADS Layout Comment/Value map

Net Properties Min Width Clearance Trace Width Applies to Default
Conn Width rules with most
common value and Net
Max Width rules with net specific
values.
Net Width by Clearance Trace Width Applies to Nets against
Layer Recommended Layer Conditional
rules.
Net Spacing by Clearance Trace to Trace Applies to Nets against
Layer Layer Conditional
rules.
Layers Enabled Routing Selected layers Applies to Net rules.
for Routing
Weight Routing Priority
Routing Enabled Routing Auto route
Retry Enabled Routing Allow ripup
Shove Enabled Routing Allow shove
Layer Strategy Routing Enabled Routing Selected layers Applies to Default
/ Sweep Win/ rules.
Comp
Primary Layers Setup Routing
Direction Direction
Fanout Fanout power/ Fanout Nets/Plane
Settings gnd
Fanout signals Fanout Nets / Signal
IC fanout Fanout Direction
direction
Maximum Fanout Fanout length /
fanout distance Maximum
OrCAD to PADS Layer Mapping

The translator preserves the original OrCAD unique layer name unless the ”Rename layers”
check box is turned on. If this option is checked, the translator renames the default OrCAD layer
nickname (three-letter abbreviation for the layer name) to the corresponding default PADS
Layout layer name.
OrCAD to PADS Obstacle Mapping
The following conditions apply during the translation:
• Routing inner layers (IN1 through IN9, I10, I11, I12) are translated as additional
nonplane electrical layers.
• Plane layers are translated as Split/Mixed electrical layers,
• Documentation layers are translated as additional General nonelectrical layers.
Table 3-1. OrCAD to PADS Layer Renaming

OrCAD Name PADS Layout Name
TOP Top
BOT Bottom
PWR Power Plane
GND Ground Plane
SST Silkscreen Top
SSB Silkscreen Bottom
AST Assembly Drawing Top
ASB Assembly Drawing Bottom
SPT Paste Mask Top
SPB Paste Mask Bottom
SMT Solder Mask Top
SMB Solder Mask Bottom
DRD Drill Drawing

A table showing how obstacles are mapped during translation helps you to verify that your
obstacles translated properly from OrCAD to PADS Layout.
OrCAD PADS Layout Comment

Free track Open copper path that is not
filled
Solid Copper area Fixed (non-poured) copper
outline
Copper area filled with Flags as a warning in the
hatched lines log-file
Anti-copper Copper Pour Cut Out
OrCAD PADS Layout Comment

Board outline Board outline
Via keepout Keepout with the Via and
Jumper restrictions
Route-via keepout Keepout with the Trace,
Copper, Via and Jumper
restrictions
Route keepout Keepout with the Trace and
Copper restrictions
Detail Opened polygon drawing
shape
Comp height keepin <nothing> Flags as a warning in the
log-file
Comp height keepout Keepout with the Placement
restrictions and specified
Component Height
Comp group keepin <nothing> Flags as a warning in the
log-file
Comp group keepout <nothing> Flags as a warning in the
log-file
Place outline <nothing>
Insertion outline <nothing>
Copper pour Copper pour area outline
Chapter 4
P-CAD Design and Library Translation
The PADS Layout translator converts the following types of P-CAD design and library files:
• P-CAD design files in binary and ASCII formats (*.pcb) generated in P-CAD 2001,
2002, 2004, 2006.
• P-CAD PCB libraries in the binary format (*.lib) generated in P-CAD 2001, 2002, 2004,
2006.
P-CAD Library Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
P-CAD Design Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Translating P-CAD Designs and Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Combining P-CAD Layout and Schematic Libraries into a Single PADS Library. . . . 34
P-CAD to PADS Rule Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
P-CAD to PADS Default Layer Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
P-CAD Object Type to PADS Rule Owner Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
P-CAD Library Translation Notes

The content of a single P-CAD library is translated into the correct file section of a PADS
library.


• 2D Lines (.ln9)
The translator automatically creates these files from the single P-CAD source file. The output
Part Type and PCB Decal files contain data; the CAE Decal and 2D Lines files do not contain
data—these files are generated by the PADS Schematic Translator.
P-CAD Design Translation Notes

There are a number of differences between the structures of P-CAD and PADS Layout designs.
Some elements do not translate and others require manual intervention.
Output File Names

The translator preserves the original file name while translating the file into PADS Layout
unless the original file extension is .pcb. If the original file extension is .pcb, then the translator

See P-CAD Object Type to PADS Rule Owner Mapping for details of the mapping of P-CAD
design rule owners to PADS Layout.
See P-CAD to PADS Rule Mapping for details of the mapping of P-CAD design rules to PADS
Layout.
Layers Translation
Default Layers—The translator gives you the option to preserve the original P-CAD layer
names, or to change them to the corresponding default PADS Layout layer names.
See P-CAD to PADS Default Layer Mapping for details of the default mapping of P-CAD
design layers to PADS Layout.
CustomizedLayers — You can also customize layer mappings for individual layers by
specifying the P-CAD layer name and the PADS Layout layer number.
Pads Translation
• P-CAD Ellipse, Target, and Mounting Hole pads are translated as circle/oval shaped
pads in PADS Layout.
• P-CAD Thermal and NoConnect pads are translated as corresponding Thermal and
Antipad pad shapes.
• P-CAD 8-sided regular polygon pads are translated as chamfered rectangle pads in
PADS Layout.
• P-CAD 4-sided regular polygon pads are translated as square pads in PADS Layout.


Flooding/Hatching
Translated copper pour and plane area objects are not automatically hatched when you load the
Line keepouts
A P-CAD widthless Line Keepout is translated as a closed filled polygon keepout 1 mil wide in
PADS Layout.
Free pads
Free pads in the P-CAD design are translated as dummy components with no geometry and a
single pad stack in PADS Layout.
Copper Ties
P-CAD Copper Ties electrically connect two or more nets while maintaining the ability to route
them separately. These Copper Ties are translated in PADS Layout as regular pieces of drafting
copper with no net.
Board Outline and Board Cutouts

• P-CAD board cutouts are translated as 2-D lines in PADS Layout.
• Board outlines created by the P-CAD 2006 Place Board Outline tool are unsupported
and not translated.
Locked library file

When you open a library in the P-CAD Pattern Editor or add a library into the Library Setup
dialog list in the P-CAD PCB and have P-CAD PCB open, P-CAD locks that library file;
therefore, the translator cannot even open this file not to mention about translating. Usually, the
translator indicates that the library is locked by displaying the exclamation mark icon in the files
list. If you see this, close the P-CAD Pattern Editor or PCB application or remove the library
from the Library Setup dialog.
Room attributes
Since PADS Layout does not support P-CAD Rooms, room attributes and rules are translated as
component attributes for all components included in the room.
Translating P-CAD Designs and Libraries
Multiple Stroke Fonts

PADS Layout does not support multiple stroke fonts. Multiple stroke font families in the
original P-CAD file are all converted to the Romansim stroke font family in PADS Layout.
P-CAD System (TrueType) fonts are translated as corresponding System fonts in PADS
Layout.
Multiple Symbol Representations

P-CAD supports multiple graphical representations (Patterns) of a pcb symbol; PADS Layout
does not. Multiple pattern graphics for a single P-CAD pcb symbol are translated into PADS
Layout as multiple symbols, each identified by its corresponding P-CAD pattern graphic’s
name suffix.
Tip
The default P-CAD pattern graphic (usually “Primary”) is named without the suffix.
Multi-line Labels and Attributes

A multiline free text object from a P-CAD design becomes multiple single-line free text objects
in PADS Layout. A multiline attribute from a P-CAD design is translated as a single-line label
or attribute to PADS Layout with concatenating multiple lines to single line.

You can translate P-CAD designs and libraries to PADS Layout.
Procedure
2. Select the P-CAD tab.
3. Populate the file list:

powerpcb.ini file.
Tip
6. In the Translation options area, select the P-CAD tab, and then select the check boxes to
• Select the Preserve net colors check box to preserve the colors of P-CAD nets for
• Select the Rename layers check box to rename P-CAD layer names to PADS Layout
names. See P-CAD to PADS Default Layer Mapping for information on P-CAD to
PADS layer name mapping.
7. (Optional) Click the Layer Mapping button to customize the layer mapping. In the P-
CAD Layer Mapping dialog box, for each layer whose mapping you want to customize:
a. Enter the P-CAD layer name.
b. Enter the PADS Layout layer number.
c. When you are finished adding layers, click OK.
dialog, where you can add, delete and modify P-CAD component and net attribute
mapping is preserved in the translator’s configuration ini-file.)
Combining P-CAD Layout and Schematic Libraries into a Single PADS Library
Tip
design; they have an attribute type of Free Text. If you do not want to translate an
attribute, select the Do not translate check box. If the name of a file type is case
sensitive, select the Case sensitive check box.
To add a new item to the attributes map:

a. Select the Component Attributes or Net Attributes tab.
b. Type the P-CAD attribute name in the Name box (or select it from the list directly
below the box.)
c. Select the corresponding PADS attribute name in the Map to box.
d. Select the type of the attribute in the Type combo box and click the Add button.
Tip
To add an item with a new unit type, select Measure in the Type combo box, type
the new unit name in the Quantity combo box, click the Add button and specify
a unit abbreviation (for example, m or F) and a short unit name (for example, meter
or Farad) in the New Unit dialog box. Then click the Add button again.
When you are finished adding, deleting and modifying items, click OK to close the
a log file created during translation. The log file contains the following information
Combining P-CAD Layout and Schematic

CAE Decal data. To create a single PADS library, you use both the Layout and Schematic
Translators, in a specific order.
Procedure
1. Using this Translator, translate the P-CAD library.
P-CAD to PADS Rule Mapping
translate the P-CAD library.
3. Save the schematic library to the same directory where you saved the library you
translated in Layout.
Results

A table mapping the translation of design rules from P-CAD to PADS Layout helps you to
know what rules get translated and how find the rules in PADS Layout. Any P-CAD rules not
listed in the table are translated as attributes of the corresponding object.
P-CAD PADS Layout Comment /

Value map
Clearanc LineToLineClearance Clearance Trace to Trace Applies to:
e Copper to Trace Default rules from
Text to Trace Design attributes,
Net rules from Net
Clearanc ViaToLineClearance Clearance Via to Trace attributes,
e Copper to Via Net Class rules from
Text to Via Net Class attributes,
Clearanc ViaToViaClearance Clearance Via to Via Classes against Classes
e Conditional rules from
Class To Class
Clearanc PadToLineClearance Clearance Pad to Trace attributes,
e SMD to Trace All against Layer
Copper to Pad Conditional rules from
Copper to SMD Layer attributes
Drill to Track
Text to Pad
Clearanc ViaToPadClearance Clearance Pad to Via
e SMD to Via
Drill to Via
Clearanc PadToPadClearance Clearance Pad to Pad
e SMD to Pad
SMD to SMD
Drill to Pad
Clearanc Clearance Clearance Default clearance value
e
Physical Width Clearance Trace Width Applies to:
Clearanc BoardEdgeClearance Clearance Board to Trace Default rules from
e Design attributes,
Board to SMD
Net rules from Net
Board to Via attributes,
Board to Pad Net Class rules from
Net Class attributes
P-CAD to PADS Default Layer Mapping
P-CAD PADS Layout Comment /

Value map
Clearanc HoleToHoleClearanc Clearance Drill to Drill Applies to:
e e Default rules from
Clearanc SilkscreenClearance Clearance Body to Body Design attributes
e
Net MaxNetLength High Speed Maximum Length Applies to:
Net MinNetLength High Speed Minimum Length Default rules from
Design attributes,
Router NoAutoRoute Routing Auto Route flag
Net rules from Net
Router Ripup Routing Allow Ripup flag attributes,
Net Class rules from
Net Class attributes
P-CAD to PADS Default Layer Mapping

When P-CAD layers are translated, the original layer name is preserved unless you select the
Rename layers check box. If you choose to rename layers, layers are renamed.
Table 4-1. P-CAD to PADS Layout Layer Mapping

P-CAD Name PADS Layout Name
Top Top
Bottom Bottom
Top Paste Paste Mask Top
Bot Paste Paste Mask Bottom
Top Mask Solder Mask Top
Bot Mask Solder Mask Bottom
Top Silk Silkscreen Top
Bot Silk Silkscreen Bottom
Top Assy Assembly Drawing Top
Bot Assy Assembly Drawing Bottom
During translation, the following conditions apply:
• Custom signal layers are translated as additional nonplane electrical layers.

• Custom nonsignal layers are translated as additional General nonelectrical layers.
P-CAD Object Type to PADS Rule Owner Mapping
• Plane layers are translated as Split/Mixed electrical layers.
P-CAD Object Type to PADS Rule Owner

Mapping
Design rules are set per object; therefore, the objects to which rules apply must also map. PADS
Layout does not support P-CAD rooms when they are specified as a rule scope in the source P-
CAD design.
Table 4-2 maps rule owner translation from P-CAD to PADS Layout.
Table 4-2. P-CAD Object Type to PADS Layout Rule Owner Mapping
P-CAD Type PADS Layout Type
Design Default
Net Class Net Class
Net Net
Class to Class Classes against Classes
Layer All against Layer
Tip
If layers are specified in the P-CAD rule scope, then the rule translates to PADS Layout as a
conditional rule.
Chapter 5
Altium/Protel Design and Library Translation
The PADS Layout translator converts the following types of Altium/Protel design and library
files:
• Protel 99 design files (*.pcb) in the binary format as well as in the ASCII format,
including designs stored in Protel Design Database (*.ddb) project files.
• Protel 99 PCB library files (*.lib), including PCB libraries stored in Protel Design
Database (*.ddb) project files.
• Altium design files (*.pcbdoc) in binary or ASCII format generated in Altium DXP,
2004, 2006, or in Altium Designer.
Note
Translation of Altium Designer files Winter09 and later is supported at a Beta level,
since this part of the translator is still under development.
• Altium PCB library (*.pcblib) files, including libraries stored in Integrated Libraries
(*.intlib) generated in Altium DXP, 2004, 2006, or in Altium Designer.
Note
Translation of Altium Designer files Winter09 and later is supported at a Beta level,
since this part of the translator is still under development.
Altium/Protel Library Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Altium/Protel Design Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Altium Designer Translation Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Translating Altium/Protel Designs and Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Combining Altium/Protel Layout and Schematic Libraries into a Single PADS Library 47
Altium/Protel to PADS Rule Owner Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Altium/Protel to PADS Rule Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Altium/Protel to PADS Layer Type and Name Mapping . . . . . . . . . . . . . . . . . . . . . . . . 52
Altium/Protel Library Translation Notes

The content of a single Altium/Protel library is translated into the correct file section of a PADS
library.
Altium/Protel Design Translation Notes


• 2D Lines (.ln9)
The Layout translator automatically creates these files from the single Altium/Protel source file.
The output Part Type and PCB Decal files contain data; the CAE Decal and 2D Lines files do
not contain data—these files are generated by the PADS Schematic Translator.

There are a number of differences between the structures of Altium/Protel and PADS Layout
designs. Some elements do not translate directly and others require manual intervention.
Output File Names

The translator preserves the original file name while translating a file into PADS Layout and
If an Altium/Protel source file is stored in a MS Access database, the translator uses the stored
MS Access name as the name for the resulting PADS Layout design or library.
Padstack Translation
• Altium/Protel octagonal pads are translated as chamfered rectangle pads to PADS
Layout.
• Square holes are not supported in PADS. They are translated as round holes with
diameter equal to the square hole size.

Part Types
Since Altium/Protel PCB does not have the concept of Part Types, the translator creates a PADS
Layout part type object for each PCB Decal used in a design or a library. If the schematic library
reference is specified in Protel DXP, it is used as the part type name; otherwise the original PCB
Decal name is used, unless the "Use Comment attribute as part type name" check box is
selected.
When the "Use Comment attribute as part type name" check box is checked the translator
determines whether that attribute value is appropriate to be used as a part type name. If the
comment attribute value has any of the following characteristics, it will not be used as a part
type name:
• It is a floating-point number with an appended value unit name ("mils", "Hz" etc.)
• It contains white-spaces or lower-case characters.
• It is too long or too short.
• It has any other attribute inconsistent with what the PADS product might use as a part
type name.
Tip
The "Use Comment attribute as part type name" checkbox does not apply to the
translation of libraries. There are no attributes in libraries.
Track Translation
If a track object has no assigned nets in Altium/Protel, it is translated as a 2-d line object in
PADS Layout ; otherwise, it becomes a trace in PADS Layout.

Flooding/Hatching
Translated copper pour and plane area objects are not automatically hatched when you load the
PADS Layout does not support Altium/Protel vertical and horizontal hatching styles; they are
translated as pane hatching.
Solid regions
Solid regions in the Altium/Protel design are translated as solid coppers in PADS Layout.
Free pads
Free pads in the Altium/Protel design are translated as dummy components with no geometry
and a single pad stack in PADS Layout.
Multiple Stroke Fonts

PADS Layout supports only one stroke font. All fonts in the original Altium file are converted
to the single PADS Layout font.
Solder Mask and Paste Mask Expansion

When migrating designs with global solder mask and paste mask expansion rules, the following
conditions may apply:
• Global "SolderMaskExpansion" and "PasteMaskExpansion" rules are migrated from

Altium as "CAM.Solder mask.Adjust" and "CAM.Paste mask.Adjust" PCB level
attributes in PADS.
• If no global "SolderMaskExpansion" and "PasteMaskExpansion" rules were set in
Altium then they are considered 4mil/0mil. These are the defaults hardcoded in Altium.
• If a pad in Altium has local "SolderMaskExpansion" or "PasteMaskExpansion" values
different from the global rule (it could be overwritten or use another non global rule),
then an additional pad on the "Solder Mask" or "Paste Mask" layer is generated in
PADS.
• All designs migrated from Altium have "CAM.Apply Oversize To All Pads" attribute
set to "No" to make sure that these generated pads are not expanded one more time using
the global attributes.
Creation of Pads with Global Rules

Creation of pads with global rules is configured by new entries in the alt2pads.ini file [protel]
section:
LibrarySolderMaskExpansion=
LibraryPasteMaskExpansion=
By default those values are empty and pads are not created.
The Expansion value is set for the diameter (the same as in "CAM.Solder mask.Adjust",
"CAM.Paste mask.Adjust" attributes in PADS Layout; in Altium this value is set for the radius
(extension) in mils.
Example:
LibrarySolderMaskExpansion=8
LibraryPasteMaskExpansion=0
Pads with a local extension defined in the pads dialog are always translated.
Mounting Holes
In PADS Layout, no specific design object designation exists for mounting holes. A new
mechanism has been introduced in the alt2pads.ini file to allow specification of which pins are
mounting holes. Mounting holes (marked in the alt2pads.ini) are translated as unused pins and
"Pin number" name will start with a prefix which can be customized in alt2pads.ini file.
The new section in the alt2pads.ini file has been introduced to translate mounting holes:
1. Default
[Protel Mounting Holes]
PinNumberPrefix=@@MT
2. The user will need to indicate which pins within in a decal are mounting holes e.g.
[Protel Mounting Holes]
PinNumberPrefix=@@MT //default Pin Number Prefix
DECAL_NAME1="PIN_NUMBER1",PIN_NUMBER2" //RJ45-7499010211A=" ","1"
DECAL_NAME2="PIN_NUMBER1",PIN_NUMBER2"
Altium Designer Translation Restrictions
Note
Each PinNumber needs be added in "", separated by ',' and have no space between.
In Altium, the Pin Number is taken from the "Designator" field.
3. Mounting holes (marked in the alt2pads.ini) are translated as unused pins and "Pin
number" name will start with prefix which can be customized in the alt2pads.ini file.
Altium Designer Translation Restrictions

There are a few items that cannot be translated to PADS Layout.
The following items are not translated when translating Altium designs in any format:
• Embedded Board Arrays (board panels), which don’t exist in PADS Layout
Translating Altium/Protel Designs and Libraries
• Solid regions defined as Board cutouts

• Solid regions defined as Polygon cutouts
• Solid regions defined as Keepouts
The following restrictions apply when translating Altium designs in ASCII format only:
• Only the Simple and Top-Middle-Bottom padstack modes are fully supported. “Full
stack mode” (defining pads for individual layers) is translated as Top-Inner-Bottom
layer padstacks. (The Inner pad is taken from the first inner layer.)
• The following items are not translated:
o Slotted and square holes
o Rounded rectangle pads
o Solid region objects
Translating Altium/Protel Designs and

Libraries
You can translate Altium/Protel designs and libraries to PADS Layout designs and libraries.
Procedure
1. Start menu > PADS [Version] > PADS Layout Translator.
2. Select the Protel/Altium tab.
Tip: Since Protel 99 project files and Altium DXP integrated libraries may use an
MS Access database as file storage, the file list may be represented as a two level
hierarchy tree, where the top level is a file path to the source Altium/Protel DDB file,
and the second level is a list of .pcb and .lib files stored in this DDB or IntLib file.
Translating Altium/Protel Designs and Libraries

powerpcb.ini file.
Tip
6. In the Translation options area, select the Protel tab, and then select the check boxes to
• Select the Preserve net colors check box to preserve the colors of Protel nets for
Tip
The colors in the translated design may not match the original design colors
because, while Protel net color applies only to unroutes, PADS Layout net color
applies to nets, pads, vias, and coppers.
• Select the Rename layers check box to rename Protel layer names to PADS Layout
names. See Altium/Protel to PADS Layer Type and Name Mapping for information
on Protel to PADS layer name mapping.
Tip
If an Altium/Protel layer has a non-default name, the translator preserves the
non-default name in the translated file even if the Rename layers check box is
selected.
• Select the Merge adjacent coppers check box to enable merging of multiple adjacent
coppers in the Protel source design into a single copper in the resulting PADS
Layout design. (This feature increases PADS Layout graphics performance.)
Combining Altium/Protel Layout and Schematic Libraries into a Single PADS Library
8. When translation is complete, the Translation Results dialog box displays the content of
a log file created during translation. The log file contains the following information:
Combining Altium/Protel Layout and

Schematic Libraries into a Single PADS
Library
CAE Decal data. To create a single PADS library, you will use both the Layout and Schematic
Translators, in a specific order.
Procedure
1. Because Altium/Protel has separate files for schematic and library files, first use this
Translator to translate the PCB library.
2. Using the Schematic Translator, translate the schematic library, following the procedure
in Schematic help topic "Translating Libraries".
Tip
The Translator places translations of the two types of files in separate folders.
3. Copy the resulting PCB library file (.pd9) to the folder into which you saved the
translated schematic library.
4. Because part types are translated by the Schematic translator, and the Layout translator
generates part type data based on the PCB decal names, verify that the PCB decals are
assigned to the part types correctly.
Results
The Altium/Protel PCB library typically does not include part type information, so the Layout
translator creates part types based on PCB decal names.
Altium/Protel to PADS Rule Owner Mapping

Design rules are set per object; therefore, the objects to which rules apply must also map. PADS
Layout does not support all Altium/Protel object types.
Altium/Protel to PADS Rule Mapping
Table 5-1. Owner Mapping

Altium/Protel Type PADS Layout Type
Whole board Default
Footprint Decal
Component Component
Net Class Net Class
Net Net
From-to Class Pin Pair Group
From-to Pin Pair
Object Types Specified as Rule Scope

The translator does not support the following object types when they are specified as a rule
scope in the Altium/Protel design:
pad class
component class
via specification
pad specification
footprint-pad
pad
During translation, the following conditions apply:
• If layers are specified in the Protel rule scope, then the rule translates as a conditional
rule.
• The translator ignores disabled Protel rules.

A table mapping the translation of design rules from Altium/Protel to PADS Layout helps you
to know what rules get translated and how find the rules in PADS Layout. Any Altium/Protel
rules not listed in the table are not translated because no equivalent exists in PADS Layout. Any
rules that are not translated are noted in the .log file.
Altium/Protel PADS Layout Notes/Value

Map
Routing Width Constraint Clearance rule Trace Width
Routing Clearance Clearance rule The exact
Constraint PADS Layout
rule depends on
the object the
rule is assigned
to in Altium/
Protel (rule
scope).
Routing Routing Layers 1. Layers setup 1. Routing 1. Protel
dialog box direction "o'clock" values
settings 2. Layer Biasing are mapped to
2. Routing rule "Any" in PADS
Layout.
Routing
directions are
supported in
PADS Router.
2. If Protel type
is "Not used" or
"Fanout," the
layer is
removed from
Selected Layers
(Setup > Design
Rules > Default
> Routing).
Routing Routing Corners Design Miters 45 degree =
Preferences Diagonal
dialog box Rounded = Arc
settings
Routing Routing Priority Routing rule Priority

Map
Routing Routing Topology Routing rule Topology type Shortest,
Starburst,
Horizontal,
Vertical =
Minimized
Daisy-Simple =
Serial Source
Daisy-
MidDriven =
Mid-driven
Daisy-Balanced
= Parallel
source
Routing Routing VIA style Routing rule Selected vias
Routing SMD to Corner Clearance rule Same Net/SMD to
Constraint Corner
Manufacturing Polygon Connect Design Thermals Relief Connect:
Style Preferences • 90 Angle -
dialog box Orthogonal
• 45 Angle -
Diagonal
• Direct
Connect -
Flood over
• Conductors
num -
Spoke Min.
• Conductor
Width -
Spoke width
• Air Gap -
not
supported
Manufacturing Power Plane Not supported
Connect Style

Map
Manufacturing Power Plane Clearance Copper to via, pad Conditional
Clearance and SMD Clearance Rule
Drill to copper All:All for
Internal Plane
layers
Manufacturing Test point style DFT Audit dialog Minimum pad Top = PCB Top
box settings probing size Side
Testpoint grid
size = Test
Point grid
High Speed Daisy Chain Stub High Speed rule Stub Length
Length
High Speed Length Constraint High Speed rule Length
High Speed Matched Length High Speed rule Match Length Tolerance =
Tolerance
High Speed Parallel Segment High Speed rule Parallelism Same Layer =
Parallelism
Adjacent
Layers =
Tandem
High Speed Vias under SMD Pad Entry rule Via at SMD
Signal Integrity Flight Time High Speed rule Delay Min = 0
Max = Min
(Flight Time 1,
Flight Time 2)
Signal Integrity Impedance High Speed rule Impedance
Constraint
Signal Integrity Supply Nets Attributes PowerGround and This Protel rule
Voltage attributes is translated as
PADS Layout
attributes
assigned to nets
and net classes
specified in the
Protel rule
scope.
Altium/Protel to PADS Layer Type and Name Mapping

Map
Placement Component Clearance Body to Body Applies to
Clearance Default rules
only.
Altium/Protel to PADS Layer Type and Name

Mapping
When Altium/Protel layers are translated, the original layer name is preserved unless you select
the Rename layers check box.
If you choose to rename layers, layers are renamed as shown.
Table 5-2. Altium/Protel to PADS Layer Renaming
Altium/Protel Name PADS Layout Name
Top Layer Top
Bottom Layer Bottom
Top Paste Paste Mask Top
Bottom Paste Paste Mask Bottom
Top Solder Solder Mask Top
Bottom Solder Solder Mask Bottom
Top Overlay Silkscreen Top
Bottom Overlay Silkscreen Bottom
Tip
If a default Altium/Protel layer name has been changed to a different name, the translator
preserves the changed name even if the Rename layers check box is selected.
Layer types are also translated when you rename layers. Altium/Protel layer types are mapped
to PADS Layout layer types as shown in Table 5-3. PADS Layout layer types are set in the
Layers Setup dialog box (Setup > Layer Definition).
Table 5-3. Altium/Protel to PADS Layer Type Mapping
Altium/Protel Type PADS Layout Type Notes
Signal layer Electrical layer (No Plane)
Table 5-3. Altium/Protel to PADS Layer Type Mapping (cont.)

Altium/Protel Type PADS Layout Type Notes
Internal plane Electrical layer (CAM Plane) If the Protel layer contains a
split plane object, it is
translated to a Split/Mixed
Plane in PADS Layout.
Mechanical Nonelectrical layer (General)
Top Overlay Nonelectrical layer The top electrical layer is
(Silkscreen Top) associated with this layer.
Bottom Overlay Nonelectrical layer The bottom electrical layer is
(Silkscreen Bottom) associated with this layer.
Top Solder Nonelectrical layer (Solder The top electrical layer is
Mask Top) associated with this layer.
Bottom Solder Nonelectrical layer (Solder The bottom electrical layer is
Mask Bottom) associated with this layer.
Top Paste Nonelectrical layer (Paste The top electrical layer is
Mask Top) associated with this layer.
Bottom Paste Nonelectrical layer (Paste The bottom electrical layer is
Mask Bottom) associated with this layer.
Drill Drawing Nonelectrical layer (Drill
Drawing)
Drill Guide Nonelectrical layer
Keep Out All layers (Layer 0) 2D lines from this Protel
layer are applied to the board
outline object on Layer 0,
and to Keepout areas (<All
Layers>) in PADS Layout.
Multi Layer All layers (Layer 0)
Top Dielectric Properties Top coating properties The properties are assigned
(Thickness) as Thickness to the Top layer
in PADS Layout.
Bottom Dielectric Properties Bottom coating properties The properties are assigned
as Thickness to the Bottom
layer in PADS Layout.
Chapter 6
Eagle Design and Library Translation
The PADS Layout translator converts Eagle design and library files to PADS Layout designs
and libraries.
The PADS Layout translator converts the following types of Eagle design and library files:
• Eagle PCB design files in ASCII-XML format (*.brd) generated in Eagle Version 6.X
and later.
• Eagle PCB library files in ASCII-XML format (*.lbr) generated in Eagle Version 6.X
and later.
Eagle Library Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Eagle Design Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Eagle Translator Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Translating Eagle Designs and Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Eagle to PADS Rule Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Eagle to PADS Default Layer Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Eagle Library Translation Notes

The content of a single Eagle library is translated into the correct file section of a PADS library.


• 2D Lines (.ln9)
The PADS Layout translator automatically creates these files from the single Eagle source file.
The Part Type and PCB Decal files obtain data from the pcb design file.
Eagle Design Translation Notes

The structures of Eagle and PADS Layout designs have a number of differences. Some
elements do not translate while others require manual intervention.
Output File Names

The translator preserves the original file name while translating the file into PADS Layout.

In Eagle, rules are organized in a way that gives priority to the highest value. Eagle rules do not
have a formal rules hierarchy.
Clearance Rules
Clearance rules map to the PADS default Clearance Rules.
See “Eagle to PADS Rule Mapping” on page 67 for details on mapping Eagle design rules to
PADS Layout.
Net Class
The translator always creates a net class.
• Width values are set as in the Eagle General Rules on a class level.
• The Eagle drill value is not set on the PADS side.
• The clearances are set as class to class Conditional Rules between objects using the
Trace to all objects and the Copper to all objects settings.
Differential Pairs
Eagle recognizes differential pairs based upon the suffix _N and _P. Differential pairs are
assigned to the same class as in Eagle.
The translator observes the following rules when translating differential pairs:
• The trace length min/max is set as the PADS defaults of 0 and 448000.
• The width is taken from the Net Class associated with the nets.
• The gap is taken from the Conditional Rule TraceToTrace restriction (Eagle clearance
value).
Layers Translation
Default Layers — The translator preserves the original Eagle layer names.
See “Eagle to PADS Default Layer Mapping” on page 69 for details of the default mapping of
Eagle design layers to PADS Layout.
The library records the settings for the normal or extended layer modes. You cannot place a part
with extended mode settings into a design configured to normal layer mode.
By default, the translator always creates two electrical layers (Top and Bottom marked as
Component Layers) together with a base set of special layers that are required for every design.
Table 6-1. PADS Base Layer Mapping
Eagle Layer PADS Layout Layer PADS Layer Association
Eagle 1 - Tracks, Top Side Component Side, Top Silkscreen Top, Solder Mask
Top, Paste Mask Top,
Assembly Drawing Top
Eagle 16 - Tracks, Bottom Component Side, Bottom Silkscreen Bottom, Solder
Side Mask Bottom, Paste Mask
Bottom, Assembly Drawing
Bottom
Eagle 20 - Dimension Layer Layer_25 (or Layer_125 in N/A
extended layer mode).
Eagle 20 - tPlace Layer Silkscreen Top Component Side, Top
Eagle 21 - bPlace Layer Silkscreen Bottom Component Side, Bottom
Eagle 29 - tStop Layer Solder Mask Top Component Side, Top
Eagle 30 - bStop Layer Solder Mask Bottom Component Side, Bottom
Eagle 31 - tCream Layer Paste Mask Top Component Side, Top
Eagle 32 - bCream Layer Paste Mask Bottom Component Side, Bottom
No Eagle Equivalent Drill Drawing N/A
No Eagle Equivalent Assembly Drawing Top Component Side, Top
No Eagle Equivalent Assembly Drawing Bottom Component Side, Bottom
The translator creates electrical layers based on the layerSetup variable which defines the
padstacks. The electrical layers are always visible and set as Routing layers (except the Top and
Bottom layers which are set as Component layers).
The Eagle translator creates layers based upon the presence of objects on those layers. It is
possible that the translator could create certain layers that may not contain objects when the
translator subsequently places the translated objects on predefined PADS Layout layers (such as
keepouts, vias, or pads).
In Eagle, layers are defined as “object” layers meaning that they contain objects of a specific
type.
• Keepouts are translated according to the following rules:

o Objects on the Eagle layers tKeepout and bKeepout are translated to PADS Layout
Top/Bottom layers as keepouts with a placement restriction.
o Objects on the Eagle layers tRestrict and bRestrict are translated to PADS Layout
Top/Bottom layers as keepouts with a trace restriction.
o Objects on the Eagle layer vRestrict are translated to PADS Layout All Layers as
keepouts with a via restriction.
• Coppers/Drawings are translated according to the following rules:
o In Eagle there is no distinction between coppers and drawing objects, so the
translator will first try to translate the objects as coppers. If this is not possible, then
the object is translated as a drawing. These rules apply to rectangles, wires, and
polygons.
o Circle objects sre translated as drawings, coppers or keepouts.
The translated thickness is set based upon the mtCopper/msIsolate values. The Eagle dielectric
values are set to the PADS defaults.
Layer routing direction is set based upon the PrefDir variable:
• - = Horizontal
• | = Vertical
• / = 45
• \ = -45
• a, *, default: = any
PADS Layout - Import

You can import an Eagle design directly into PADS Layout. The schematic file (*.sch) needs to
have the same name as the design file and be placed in the same location as the board (*.brd)
file for the translator to use the schematic data for import.
Invalid Characters/Validation
You can define invalid characters for specific objects by modifying the alt2pads.ini file.
If an object name changes, the translator reports it as a warning.
The invalid characters list does not automatically synchronize with the schematic translator.
Before migration, all of the project lists need to be synchronized.
[Illegal Characters]
PartType=\{}*,.’@
Decal={}*,’
Symbol=!”%&*()/\?.,[]{}:<>|$=
RefDes={}*,.~
Net={}*,?
Pin=,.{}*?
Eagle Object Types

Eagle object types are translated to PADS according to a set of predefined rules.
Translated objects observe the following rules:
1. Rectangle:
a. Mirror is automatically converted
b. Width by default is set to 1
2. Wire (2D Line):
a. Cap - end of the line is not handled
b. Style:
i. Continuous = solid
ii. Longdash = dash
iii. Shortdash = dot
iv. Dashdot = dash-dot
3. Line segments are joined automatically (if possible). To manually join segments not
automatically joined, select the shapes and use the Join command to join them together.
Grids/Units
Grid/unit settings do not migrate from Eagle. The translator sets the default unit to mils.
Colors
Colors for layers are taken from the Eagle design. During the translation, the translator extracts
the specific Eagle colors and a custom color configuration palette is created in PADS Layout.
The translator assigns colors to specific design objects in PADS based upon the following rules:
• The Pads color is set based upon the Eagle Pads layer color.
• The Vias color is set based upon the Eagle Via layer color.
• The Connections (unroutes) color is set based upon the Eagle Unrouted layer color.
• Keepouts:
o The Top/Bottom Keepouts color is set based upon the Eagle tKeepout/bKeepout
layers colors
o The Keepouts color for all other layers is set based upon the Eagle tValues/bValues
layers colors.
• The RefDes color (RefDes column color for specific layers) is set based upon the Eagle
tNames/bNames layers colors.
• The Part Type and Attribute color (Type and Attribute column color for specific layers0
is set based upon the Eagle tValues/bValues layers colors.
In Eagle, colors for SMD pads are taken from the pads on the top/bottom layers. PADS does not
distinguish between through-hole and SMD pads for color assignments; the color is always
taken from the Eagle Pads object type.
RefDes and Part Types Attribute (Part Label Properties) visibility is always set to show.
Visibility is not set according to the Eagle Names and Values layer settings.
Parts
When translating the design, the translator can create a design Part Type based upon the
schematic definition. The schematic file is needed to associate same part types, swap gate, swap
pin and pin type definitions.
If there is no schematic file associated, the translator creates the Part Type definition from the
Value attributes in the .brd file (which could be different than the schematic).
Padstacks/Pads
The translator always translates pads on inner layers as round pads.
The translator observes the following rules when translating pads and padstacks:
1. Pad shapes are translated as they appear on the top/bottom layers; inner layers are
always round.
2. Diameter = 0 means auto-pad size = 3R, where R is half of the drill size (25% of drill
size on the left, 25% of drill size on the right of the pad). This method is the default
behavior in the library, but can be overwritten in Design rules. (Not applicable in the
library - always default.)
3. The translator does not recognize slotted holes.
4. First property — means that the pad shape will be overwritten by Design rules.
5. For long pads — the ratio is 2:1 by default. The configuration can be configured in the
Design rules. (In the library, the default is used.)
6. Pin names in Eagle are rotated according to the pin orientation. PADS does not rotate
the pin names.
Pin Type and Swap
The translator sets pin swap based upon the Eagle attribute swaplevel.
Pin types are defined based upon information in the symbol. The design translator needs to have
the associated schematic file available to correctly translate the pin types.
Table 6-2. Pin Types
Eagle Pin Types PADS Pin Types
in Load
out Source
io Bidirectional
pwr Power
hiz Tristate
sup Ground
nc Undefined
pas
<none> Open Collector
Or-Tieable Source
Terminator
“Reverse” Common Pins

Eagle allows one schematic pin to be associated with multiple layout pins e.g. EPIN = A B C D.
If the translator encounters schematic pins with multiple layout pin assignments, those pins will
be translated as pin name = name_<number>. The first name is unique so the incremental
numbering starts from the second pin:
Table 6-3. Pin Renumbering
Pin Name Pin Number
EPIN A
EPIN_1 B
EPIN_2 C
EPIN_3 D
Gate Swap
Gates are set to be swappable only if they have the same symbol. It is possible that gates could
be different depending upon the value defined in Eagle by the swaplevel attribute.
Components
In Eagle, it is possible to place a component without a part type; only a decal is required. In this
situation, the translator creates an artificial part type with the name “$$$” + decal name.
The translator does not support the Eagle “smashed property”.
Part Type and Ref Des

The translator interprets the component attribute >VALUE as the part type and >NAME as the
RefDes.
Logic Family
Logic Families identify specific groups of components in the design. If the translator cannot
find a matching Logic Family available, it attempts to create one.
Logic Families translate in the following order:
1. Existing Logic Families are loaded from the PowerPCB.ini file. If no Logic Families or
PowerPCB.ini file are found, the translator logs a warning and the uses the default Logic
Families instead.
2. The translator will first search for an existing Logic Family with the same RefDes prefix
AND with a part/decal/symbol name starting with the name of the Logic Family.
3. If the translator does not find a matching Logic Family, the translator searches for an
existing Logic Family with the same RefDes prefix.
4. If the translator still does not find an existing matching Logic Family, the translator
attempts to create a new Logic Family:
o The translator generates a unique 3-character name. If the translator cannot generate
a unique name, it writes an error, assigns “UND” as the Logic Family and continues.
o If the prefix is too long, it truncates to 6 characters. The translator logs a warning.
o The translator attempts to update the PowerPCB.ini file:
• The PowerPCB.ini file is not updated if more than 100 Logic Families exist (this
limit is used in other places). An error is written to the log file..
• The PowerPCB.ini file is not updated if the default Logic Families are being
used. A warning is written to the log file.
• Otherwise, the PowerPCB.ini file will be updated. A note is written to the log
file.
Mounting Holes
The translator translates holes in decals and design holes as one-pin components.
The name assigned to translated mounting holes is defined by the PinNumberPrefix entry in the
alt2pads.ini file section:
[Eagle Mounting Holes]

PinNumberPrefix=@@MH
Nets
Nets are translated according to the properties of the individual objects that make up the nets:
the connections/pin pairs, traces, coppers and vias.
Connections/Pin Pairs
Eagle pin pairs descriptions are not preserved and could be different in PADS Layout. The
connectivity of the pins should be the same as in the original design file.
Traces
The translator does not translate Eagle one-pin nets as they are not supported in the PADS flow.
In a case where a one-pin net has a trace attached, it translates as a copper.
Coppers
The translator recognizes polygons associated with signals and translates them as Copper
Planes. Additionally, the Flood Priority is set based upon the Eagle “rank” value. This value
defines how shapes are flooded in cases where they overlap.
Vias
The translator translates Eagle vias as through vias or as partial vias. The Eagle “extend”
property is used to determine onto which layers the vias are placed..
Attributes
The translator translates Eagle attributes and maps them to PADS attributes.
After the translation, it is possible that the direction of the attribute text could appear differently
than in Eagle.
Texts
The PADS default font is used for all texts.
Multiple lines of text are translated as one and a warning message is added to the log.
Dimensions
The translator does not support the translation of dimensions.
Variants
The translator does not support the translation of variants.
Decals
In Eagle board designs there could be different decals with the same name coming from
different libraries. If this is encountered, the translator renames these decals (except the first
one) as DECALNAME_LIBRARYNAME and a warning is added to the message log: “Decal
was renamed to avoid conflicts with another decal. Update Eagle decals to use the same library
definition to avoid forward annotation errors.”
Labels
In PADS Layout, labels are used to define the component RefDes and PartType placeholders.
The translator translates labels as follows:
• >NAME is translated as Name (RefDes placeholder)

• >VALUE is translated as Type (PartType placeholder)
Thermals
The translator recognizes thermals and uses a specific set of rules to translate them into PADS
Layout design objects.
Thermals translate according to the following rules:
1. Copper pour thermal translation:

a. If all copper pours in Eagle have thermals enabled, then thermals are set to
“Orthogonal” in Options.
b. If all copper pours in Eagle have thermals disabled, then thermals are set to “Flood
over” in Options (the translator writes one warning for each pour with disabled
thermals).
c. If some copper pours have thermals enabled and some have thermals disabled,
thermals are set to “Orthogonal” in Options (one warning for each pour with
thermals disabled is written to the log).
2. Vias thermals translation:
a. If via thermals are disabled in Eagle design rules, the translator disables them on all
Copper Planes in PADS Layout.
b. If via thermals are enabled in Eagle design rules, the translator enables them on all
Copper Planes in PADS Layout.
Eagle Translator Restrictions
3. Pin thermals translation:

o If thermals are disabled in Eagle design rules at the pads or SMD level, the translator
creates a “flood over” thermal in PADS Layout for these pins.
4. Thermals not translated:
o The Thermal Isolation Eagle design rule is not translated.
Eagle Translator Restrictions

The Eagle translator cannot translate certain design items into a PADS Layout design. If your
source design has objects that do not appear in your translated design, review this list to
determine whether or not the translator supports those items.
The following items are not translated when translating Eagle designs in any format.
• The translator does not support slotted holes.

• The translator does not support Eagle dimensions.
• Eagle Variants are not supported.
• Eagle pin pairs are not preserved and could be different in PADS Layout.
• Eagle one-pin nets are not supported in the PADS flow and are not translated.
• The translator does not translate the Eagle ThermalIsolation design rule.
• When translating net classes, the Eagle drill value is not set on the PADS side.
• Line segments are joined automatically (if possible). To manually join segments not
automatically joined, select the shapes and use the Join command to join them together.
• The translator does not support the Eagle “smashed” property.
• When translating wires (2D lines) cap-end is not handled.
Translating Eagle Designs and Libraries

You can translate Eagle designs and libraries to PADS Layout.
Procedure
2. Select the Eagle tab.
3. Populate the file list:
to translate designs, libraries, or both. Then click the Add button.
Translating Eagle Designs and Libraries
want to make available for translation.Then click Open. The translator adds the
selected files to the Files to translate file list. The translator enables (selects) any
newly added file in the list for translation.
Note
The translator uses the associated schematic file to generate the correct data for
forward annotation and back annotation of the part type names as well as the
definitions for gate swap, pin swap and pin types. In order to process this data, a
schematic file (*.sch) with the same name as the board file (*.brd) should reside in
the same folder as the pcb design file. The translator adds the file automatically
when you select the pcb design file.
If the schematic file is not in the same folder or is not the named the same as the
board file, it does not automatically load. Use the Eagle Sch... button to locate and
load the file. Information from the file is added to the log.

click the dialog box indicator button to browse to and specify a different one.
click the dialog box indicator button to browse to and specify a different one. The
default values are from the current FileDir (designs) and LibDir (libraries) entries in
the PADS Layout powerpcb.ini file.
Tip
If the output file is open in PADS Layout, the translator does not translate the file
but writes a message to the output log instead.
5. In the “Overwrite existing files” dropdown list, select one of the following to specify
how the translator should proceed if it needs to overwrite an existing file:
6. In the Translation options area, select the Eagle tab, and then select the check boxes to
• Select the “Update PADS Layout Logic Family list” check box to add any new logic
family types to list in PADS Layout.
• Select the “Use stop/cream” check box to use the stop/cream pad and via property
for creating pads on the solder and past mask layers.
Eagle to PADS Rule Mapping
dialog, where you can add, delete and modify Eagle component and design attribute
mapping is preserved in the translator’s configuration .ini file.)
Tip
design; they have a “Do not translate” attribute type of Free Text. If you do not want
to translate an attribute, select the “Do not translate” check box. If the name of a file type
is case sensitive, select the “Case sensitive” check box.
To add a new item to the attributes map:

a. Select the Component Attributes or Design Attributes tab.
b. Type the Eagle attribute name in the Name box (or select it from the list directly
below the box.)
c. Select the corresponding PADS attribute name in the Map to box.
d. Select the type of the attribute in the Type combo box and click the Add button.
Tip
To add an item with a new unit type, choose Measure in the Type combo box,
type the new unit name in the Quantity combo box, click the Add button and
specify a unit abbreviation (for example, m or F) and a short unit name (for example,
meter or Farad) in the New Unit dialog box. Then click the Add button again.
When you are finished adding, deleting and modifying items, click OK to close the
a log file created during translation. The log file contains the following information

The table that follows maps the translation of design rules from Eagle to PADS Layout. Any
Eagle rules not listed in the table translate as attributes of the corresponding object.
Eagle PADS Layout Comment /

Value map
Clearance Wire to Wire Clearance Trace to Trace Applies to default rules.
Clearance Trace to Copper
Copper to Copper
Clearance Wire to Pad Clearance Clearance Trace to Pad
Copper to Pad
Trace to SMD
Copper to SMD
Clearance Wire to Via Clearance Clearance Trace to Via
Copper to Via
Clearance Pad to Pad Clearance Clearance Pad to Pad
Pad to SMD
SMD to SMD
Clearance Pad to Via Clearance Clearance Pad to Via
SMD to Via
Clearance Via to Via Clearance Clearance Via to Via
Clearance Drill/Hole Clearance Drill to Drill
Clearance No Equivalent in Clearance Text to Trace Applies to default rules.
Eagle Text to Via These rules have no
Text to Pad equivalent in Eagle and
are set to the PADS
Texy to SMD default value of 12 mils.
Text to Copper
Drill to Trace
Drill to Via
Drill to Pad
Drill to SMD
Drill to Copper
Clearance Copper/Dimension Clearance Board to Trace Applies to default rules.
Clearance Board to Via
Board to Pad
Board to SMD
Board to Copper
Eagle to PADS Default Layer Mapping
Eagle PADS Layout Comment /

Value map
Clearance Width (msWidth) Clearance Trace Width: Minimum Set based upon msWidth
Trace Width: value.
Recommended
Trace Width: Set to default value of
Maximum 250 mils.
Clearance Same Net Clearance Clearance Same Net: SMD to Via Set based upon
(mdSmdVia) mdSmdVia value.
All other Same Net
clearances set to 12 mils.

When translating Eagle layers, the translator preserves the original name. If you require an
alternate naming scheme, you can choose to rename layers.
Note
The Eagle Translator creates layers based upon the presence of objects on those layers. It is
possible that the translator could create certain layers that may not contain objects when the
translator subsequently places the translated objects on predefined PADS Layout layers (such as
keepouts, vias, or pads).
Table 6-4. Eagle to PADS Layout Layer Mapping

Eagle Name Eagle Description PADS Layout Mapping
1 Top Tracks, Top Side Component Side, Top
2-15 Route (2-15) Inner Layer(s) Routing Layer_2 thru Layer_15
(as required)
16 Bottom Tracks, Bottom Side Component Side, Bottom
17 Pads Pads (through-hole) Pads are translated as equivalent
padstack shapes on the Top/
Bottom layers. On inner layers,
the pads are always translated as
round shapes.
18 Vias Vias (through-hole) All Eagle vias are translated as
through vias or partial vias. The
Eagle “extend” property is used
to determine onto which layers
the vias are placed
Table 6-4. Eagle to PADS Layout Layer Mapping (cont.)

19 Unrouted Airwires (rubberbands) Airwires are translated as PADS
unroutes objects.
20 Dimension Board Outlines (circles for holes) Board outline is translated as the
equivalent shape on <All
layers>. All other objects are
translated to Layer_25 (or
Layer_125 in extended layer
mode). Layer is named
“Dimension”.
21 tPlace Silk Screen, Top Side Silk Screen Top
22 bPlace Silk Screen, Bottom Side Silk Screen Bottom
23 tOrigins Origins, Top Side Translator creates tOrigins layer
if objects exist.
24 bOrigins Origins, Bottom Side Translator creates bOrigins layer
if objects exist.
25 tNames Service Print, Top Side RefDes on Top layer.
26 bNames Service Print, Bottom Side RefDes on Bottom layer.
27 tValues Component VALUE, Top side PartType Attribute on Top layer.
28 bValues Component VALUE, Bottom Side PartType Attribute on Bottom
layer.
29 tStop Solder Stop Mask, Top Side Soldermask Top
30 bStop Solder Stop Mask, Bottom Side Soldermask Bottom
31 tCream Solder Cream, Top Side Paste Mask Top
32 bCream Solder Cream, Bottom Side Paste Mask Bottom
33 tFinish Finish, Top Side Translator creates tFinish layer
if objects exist.
34 bFinish Finish, Bottom Side Translator creates bFinish layer
if objects exist.
35 tGlue Glue Mask, Top Side Translator creates tGlue layer if
objects exist.
36 bGlue Glue Mask, Bottom Side Translator creates bGlue layer if
objects exist.
37 tTest Test and Adjustment Info., Top Side Translator creates tTest layer if
objects exist.
Table 6-4. Eagle to PADS Layout Layer Mapping (cont.)

38 bTest Test and Adjustment Info., Bottom Translator creates bTest layer if
Side objects exist.
39 tKeepout Nogo Area for Components, Top Translated as keepouts on
Side Component Side Top layer with
a placement restriction.
40 bKeepout Nogo Area for Components, Bottom Translated as keepouts on
Side Component Side Bottom layer
with a placement restriction.
41 tRestrict Nogo Area for Tracks, Top Side Translated as keepouts on
Component Side Top layer with
a trace restriction.
42 bRestrict Nogo Area for Tracks, Bottom Side Translated as keepouts on
Component Side Bottom layer
with a trace restriction.
43 vRestrict Nogo Area for Via-Holes Translated as keepouts on All
layers with a via restriction.
44 Drills Conducting Through-Holes Drills translated as plated-
through holes in padstacks.
45 Holes Non-Conducting Through-Holes Holes translated as non-plated-
through holes in padstacks.
46 Milling Milling Translator creates Milling layer
if objects exist.
47 Measures Measures Translator creates Measures
layer if objects exist.
48 Document General Documentation Translator creates Document
49 tReferenceLC Reference Marks Translator creates tReferenceLC
50 bReferenceLS Reference Marks Translator creates bReferenceLS
51 tDocu Top Layer Documentation Translator creates tDocu layer if
objects exist.
52 bDocu Bottom Layer Documentation Translator creates bDocu layer if
objects exist.
Third-Party Information
Details on open source and third-party software that may be included with this product are available in the
<your_software_installation_location>/legal directory.

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SIEMENS EDA

PADS® Layout Translator

Support Center: support.sw.siemens.com

Revision Changes Status/Date

PADS® Layout Translator User’s Guide, PADS VX.2.10

Revision History ISO-26262

PADS® Layout Translator User’s Guide, PADS VX.2.10 5

Altium/Protel to PADS Rule Owner Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6 PADS® Layout Translator User’s Guide, PADS VX.2.10

PADS® Layout Translator User’s Guide, PADS VX.2.10 7

8 PADS® Layout Translator User’s Guide, PADS VX.2.10

CADSTAR Library Translation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CADSTAR Library Translation Notes

PADS Layout Library Structure

• Part Type (.pt9)

PADS® Layout Translator User’s Guide, PADS VX.2.10 9

CADSTAR Design Translation Notes

Output File Names

Design Rules Translation

Layer Name and Type Translation

Areas and Coppers Translation

10 PADS® Layout Translator User’s Guide, PADS VX.2.10

Component Outline Color

Self-intersecting Copper Pours

Net Class Attributes

Multi-line Labels and Attributes

Cross Hatch Patterns

PADS® Layout Translator User’s Guide, PADS VX.2.10 11

Dashed and Dotted Lines

Translating CADSTAR Designs and Libraries

4. Set the output location for translated files:

12 PADS® Layout Translator User’s Guide, PADS VX.2.10

• To add a new item to the attributes map:

PADS® Layout Translator User’s Guide, PADS VX.2.10 13

Combining CADSTAR Layout and Schematic

14 PADS® Layout Translator User’s Guide, PADS VX.2.10

CADSTAR to PADS Rule Mapping

CADSTAR PADS Layout Comment / Value

PADS® Layout Translator User’s Guide, PADS VX.2.10 15

CADSTAR PADS Layout Comment / Value

16 PADS® Layout Translator User’s Guide, PADS VX.2.10

CADSTAR PADS Layout Comment / Value

CADSTAR to PADS Layer Type Mapping

PADS® Layout Translator User’s Guide, PADS VX.2.10 17

CADSTAR Layer Type PADS Layout Layer Type

CADSTAR to PADS Areas and Coppers

CADSTAR PADS Layout Comment

18 PADS® Layout Translator User’s Guide, PADS VX.2.10

CADSTAR PADS Layout Comment

PADS® Layout Translator User’s Guide, PADS VX.2.10 19

CADSTAR PADS Layout Comment

20 PADS® Layout Translator User’s Guide, PADS VX.2.10

OrCAD Library Translation Notes

PADS Layout Library Structure

• Part Type (.pt9)

PADS® Layout Translator User’s Guide, PADS VX.2.10 21

OrCAD Design Translation Notes

Output File Names

Design Rules Translation