Allegro 2 Exp

SIEMENS EDA
Allegro® to PADS®
Professional Layout
Translator User Guide
Release PADS Professional VX.2.10
Document Revision 7
Unpublished work. © 2021 Siemens
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Revision History ISO-26262
Revision Changes Status/Date

7 Modifications to improve the readability and comprehension of the Released
content. Approved by Kevin Chupp. September
All technical enhancements, changes, and fixes listed in the PADS 2021
Professional Flow Release Notes for this product are reflected in
this document. Approved by Mike Bare.
content. Approved by Regis Krug. November
content. Approved by Regis Krug. March 2020
All technical enhancements, changes, and fixes listed in the PADS
4 Modifications to title page to reflect the latest product version Released
supported. Approved by Regis Krug. September
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associated authors for each topic within this document are tracked within the Siemens
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Revision History: Released documents include a revision history of up to four revisions. For
earlier revision history, refer to earlier releases of documentation on Support Center.
Allegro® to PADS® Professional Layout Translator User Guide, PADS Professional VX.2.10
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4 Allegro® to PADS® Professional Layout Translator User Guide, PADS Professional VX.2.10
Table of Contents
Revision History ISO-26262
Chapter 1
Before You Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Layout Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Current Translator Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Preparing for Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Allegro Design Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Constraint Migration Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Translator Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Windows Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chapter 2
Allegro Data Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
What is a SKILL Script? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Copying the Allegro SKILL Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Executing the Allegro SKILL Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
create_devices Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Remove Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Resolve Device Names that Contain an Equals Sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 3
Running the Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Translation Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Invoking the Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Translator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Translation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Opening the Translated Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Post Processing the Translated Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Appendix A
Translation Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Allegro Board Refresh Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Zero Size Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Exclamation Marks in the Design Board Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Resolving Drill Symbols With Multiple Alphabetic Characters . . . . . . . . . . . . . . . . . . . . . . 26
Multi-Hole Padstacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PDB/Cell Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PDB Cleanup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SKILL Script Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SMD Edge Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Allegro® to PADS® Professional Layout Translator User Guide, PADS Professional VX.2.10 5
Table of Contents
Long Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Forward Annotation Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Chapter 1
Before You Begin
You can translate Cadence® Allegro®PCB layout systems databases to Layout using the Allegro
to PADS Professional Layout translator.
Layout Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Current Translator Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Preparing for Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Allegro Design Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Constraint Migration Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Translator Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Windows Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Layout Software Requirements

To run the translator, you must have the correct version of Layout installed as an active
configuration. If you have multiple releases installed on your system, use the Configurator to
select and run the correct version for the translator.
Note
The translator is available with 64-bit and 32-bit installations. To run the translator in a 64-
bit version, you must also have PADS classic software installed on your machine. To run
the translator in a 32-bit version, you do not need to have PADS classic installed.
Current Translator Restrictions

Translator restrictions should be factored in your database preparation prior to translation.
UNIX/LINUX Platforms: The translator can only be executed in a Windows platform. If you
have Allegro files in a UNIX or LINUX platform, you must copy the files to Windows to
translate them.
ALLEGRO Support: This translator supports versions 16.6 and 17.2 of Allegro PCB.
Before You Begin
Preparing for Translation
Preparing for Translation

Before translating an Allegro design to Layout, review Allegro constraints to ensure smooth
constraint conversion and create the proper output files from the Allegro design database using
the Allegro SKILL scripts provided with this translator.
The execution of provided SKILL scripts is an essential part of the translation process. They
generate the output files from the Allegro design database. The output files contain the critical
electrical, component, and constraint data required to construct an intelligent Layout design
database. You can perform the Allegro PCB design extraction on one machine and the actual
translation of the extracted Allegro data on another machine.
Allegro Design Preparation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Constraint Migration Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Translator Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Windows Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Allegro Design Preparation

To best prepare an Allegro design for translation, make sure that the source schematic and PCB
design are synchronized and archived, then copy the Allegro design (.brd) file to an empty
directory (or container) on your system. The .brd file is the only file needed for the translation.
Board Outlines — To successfully translate a board outline into Layout, this element in
Allegro PCB must be contiguous. Ensure that there are no gaps or opens on your board outline
before beginning data translation.
Design Files — Typically your original Allegro PCB design file exists in a design tree location
on your system along with multiple files that were created during the original Allegro board
design. Many of these files are very large and are not required by the translator.
Before You Begin
Constraint Migration Preparation
Note
It is recommended you purge unused padstacks from the design prior to translation.
Your final Allegro translation directory structure should look as follows:
|-- Translations
|-- <current board name>
|-- board.brd
Tip
In Allegro, run the Tools > Database Check command (also known as dbdoctor) to check
for database problems.
User Layers — If you want to include user layers in the translation, create a file name called
aexuserlayers.txt in the same location as the Allegro board file. List each Allegro layer on a
separate line, using the syntax, “Class/Subclass”.
For example:
DRAWING FORMAT/TITLE_DATA
DRAWING FORMAT/TITLE_BLOCK
DRAWING FORMAT/REVISION_DATA
DRAWING FORMAT/NOTES_DATA
MANUFACTURING/PEN47
MANUFACTURING/PEN65

You must migrate Allegro constraints to Constraint Manager. Understanding the differences
between Allegro and Layout constraints can help you better prepare your design for translation.
Note
Some data requires that you run the “Allegro Constraint Manager Update” program after
upgrading the design to Constraint Manager. This is denoted by “*”.
Background
A Layout ‘Net Class’ specifies physical properties of routing, such as Trace Width, Via
Assignment or Diff Pair Gap. This is similar to the Allegro ‘Physical Constraint Set’. The
Allegro net has a Physical CSet assignment similar to the Layout net to Net Class assignment.
The Physical CSet is used as the basis for the Layout ‘Net Class’.
A Layout ‘Clearance Rule’ specifies object to object spacing. This is similar to the Allegro
‘Spacing Constraint Set’. Unlike Layout, the Allegro net can be explicitly assigned to specific
Spacing CSet, beyond the Physical CSet, so the nets of the same Physical CSet assignment may
Before You Begin
have different Spacing CSets. This has implications on the translation process which are
covered in the Net Class section.
The Allegro ‘Net Class’ represents different data than a Layout ‘Net Class’. In Allegro it is a
grouping of the constraint objects such as nets, or diff pairs used to assign a Physical CSet or
other constraints in bulk. It cannot be used to create the Layout ‘Net Class’ because it does not
by itself specify the physical properties of the routing.
Net Class
Naming Conventions
Net class names will use the Physical CSet name by default. If a net is seen referencing a
Spacing CSet other than DEFAULT then a new net class name will be created using a
combination of the two CSet names. This is needed so that a Net Class to Net Class Clearance
Rule can be created to point to the non-default Spacing CSet. This combined net class name
will be assigned to the net that had the non-default Spacing CSet reference.
Table 1-1. Allegro Examples
Physical CSet Spacing CSet xPCB NetClass Name
ABC DEFAULT ABC
ABC XYZ ABC&XYZ
ABC DEF ABC&DEF
Table 1-2. Layout Net Class to Net Class Clearances

Net Class All (Default) ABC ABC&XYZ ABC&DEF
All (Default Rule) - - - -
(Default) - - - - -
ABC - - - - -
ABC&XYZ XYZ - - - -
ABC&DEF DEF - - - -
The DEFAULT Physical CSet will populate the (Default) net class in Layout. The DEFAULT
Spacing CSet will populate the (Default Rule) clearance rule.
The Physical and Spacing CSets used for a net will be determined in the following order of
assignment:
1. Physical Net
2. Differential Pair
3. Bus
Before You Begin
4. Net Class
Via Assignments
Allegro allows multiple via assignments per Physical CSet. Layout allows only one active via
assignment per net class. The first via defined in the via list in Allegro for the Physical CSet is
used.
Table 1-3. Net Class Properties
Allegro Constraint Name Layout Constraint Name Comment
MIN_LINE_WIDTH Minimum Trace Width Used with Region/Rule Area.
MIN_LINE_WIDTH Typical Trace Width Used with Region/Rule Area.
MAX_LINE_WIDTH Expansion Trance Width If “0”, then min width.
MIN_NECK_WIDTH Minimum Trace Width
MIN_NECK_WIDTH Typical Trace Width
DIFFP_MIN_SPACE Differential Spacing
Clearances
Clearance rules are created from Allegro Spacing CSets and use the same name. Only
clearances that have a direct mapping to Layout clearances will be migrated. As an example
Line to Test Via will not be migrated as there is no test via object in Layout. The Allegro
NetClass-Class assignments are not migrated to Layout Class to Class rules due to the
differences in what Allegro considers a net class and what Layout considers a net class.
Table 1-4. Clearance Properties
Allegro Constraint Name Layout Constraint Name
LINE_TO_LINE_SPACING Trace To Trace
LINE_TO_SHAPE_SPACING Trace To Plane
LINE_TO_SMDPIN_SPACING Trace To SMD Pad
LINE_TO_THRUPIN_SPACING Trace To Pad
LINE_TO_THRUVIA_SPACING Trace To Via
SHAPE_TO_SHAPE_SPACING Plane To Plane
SHAPE_TO_THRUVIA_SPACING Via To Plane
SMDPIN_TO THRUVIA_SPACING Via To SMD Pad
THRUPIN_TO_SHAPE_SPACING Pad To Plane
THRUPIN_TO_THRUPIN_SPACING Pad To Pad
THRUPIN_TO_THRUVIA_SPACING Pad To Via
THRUVIA_TO_THRUVIA_SPACING Via To Via
Before You Begin
General Clearances
The following constraints are taken from the DEFAULT Spacing CSET and used to set one of
the General Clearance values in Layout’s Constraint Manager. The largest value found on any
layer is used.
Table 1-5. General Properties
HOLE_TO_HOLE_SPACING Contour, Cavity & Mounting Hole to Mounting Hole
HOLE_TO_LINE_SPACING Contour & Mounting Hole to Non_plane Conductor
TESTPIN_TO_TESTPIN_SPACING Testpoint Center to TestPoint Center
Schemes
The (Master) Scheme is created from data defined in the Physical and Spacing CSets. Other
Net Class Schemes are created from defined Regions in Allegro and apply the region overrides
for Physical and Spacing CSets. Region classes are not processed.
Nets
Net Properties
The following net constraints are migrated to Layout.
Table 1-6. Net Properties
MAX_VIA_COUNT #Vias
MAX_XTALK Max CrossTalk
STUB_LENGTH Stub Length
TOTAL_ETCH_LENGTH Min Length / Max Length
TOTAL_ETCH_LENGTH_MAX Max Length
TOTAL_ETCH_LENGTH_MIN Min Length
VOLTAGE Supply Voltage
Differential Pairs
Differential Pairs are created only for two physical nets. They are not created for two XNets or
other combinations. If the following constraints are not found on the diff pair object the
Electrical CSet referenced by the diff pair is checked for these constraints.
Table 1-7. Differential Pair Properties
DIFFP_PHASE_TOL Differential Pair Tol
Before You Begin
Table 1-7. Differential Pair Properties (cont.)

DIFFP_PHASE_MAX_LENGTH Distance Max Differential Pair Phase Tol *
DIFFP_PHASE_TOL_DYNAMIC Max Differential Pair Phase Tol *
DIFFP_UNCOUPLED_LENGTH Separation Pair Distance *
If in Allegro the Differential Pair is created from two xnets the Allegro Constraint Manager
Update program will need to be run to bring in these diff pairs. If the xnet seen in Allegro is
recreated in Layout as an electrical net, then the two electrical nets can be made into a diff pair.
If the xnets did not create an equivalent electrical net in Layout then the diff pair will not be
created. If the diff pair is created then the above constraints, if defined, will be applied to the
new diff pair.
Match Groups
Match Groups in Allegro can contain many different objects. Only physical nets are considered
when creating match groups for Layout. The RELATIVE_PROPAGATION_DELAY
constraint is mapped to Match Group Tolerance. If the RELATIVE_PROPAGATION_DELAY
constraint is not on the match group it is taken from the Electrical CSet referenced by the first
physical net it finds in the match group.
In Allegro the same net can belong to multiple match groups. In Layout the net will belong to
only one match group. Typically this is the last match group the net was seen in while
processing match groups.
Pin Pairs *
Only pin pairs defined directly on the physical net are migrated. The
PROPAGATION_DELAY constraint is migrated to Minimum and Maximum Delay.
In Allegro the same pin pair can belong to multiple match groups. In Layout the pin pair will
belong to only one match group. The match group used is seen in the log file.
Back Drill *
Physical nets with the BACKDRILL_MAX_PTH_STUB constraint will have the Backdrill
constraint set in Layout.
Constraint Class*
Constraint Classes in Layout are created based on Electrical CSets. Physical nets that reference
an Electrical CSet will be included in a constraint class. The physical net can reference the
Electrical CSet directly or by a bus or diff pair.
Before You Begin
Translator Installation
Translator Installation
The Allegro to PADS Professional Layout translator is included in the Layout software
installation.
Note
The translator is available with 64-bit and 32-bit installations. To run the translator in a 64-
bit version, you must also have PADS classic software installed on your machine. To run
the translator in a 32-bit version, you do not need to have PADS classic installed.
The translator installs into the targeted directory and creates the translators directory (under
SDD_HOME) that contains the following folders:
• skill_scripts — Location of the SKILL scripts used by the translator

• template — Location of the internal files used in Layout project creation
• win32 or win64 — Location of the translator programs
Windows Memory
Due to Windows OS limitations, if you plan to translate a very large design, the translator may
run out of memory and display an “unable to allocate enough memory to translate current
design” message. Should this occur, you should configure Windows to provide 3GB of virtual
address space.
To configure Windows to provide 3GB of virtual address space, refer to the Microsoft Articles
at the following locations:
• http://msdn.microsoft.com/en-us/windows/hardware/gg487508.aspx or
• http://www.microsoft.com/whdc/system/platform/server/PAE/PAEmem.mspx
Both of these locations describe how to add 3GB to the Windows boot.ini file.
After modifying the boot.ini file, reboot your computer for the allocation to take place.
Chapter 2
Allegro Data Extraction
Use the provided SKILL scripts to extract and manipulate data from Allegro PCB for use in
PADS Professional Layout.
What is a SKILL Script?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Copying the Allegro SKILL Scripts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Executing the Allegro SKILL Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
create_devices Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Remove Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Resolve Device Names that Contain an Equals Sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
What is a SKILL Script?

SKILL is a programming language developed to be used with Cadence® tool suites. This
scripting method provides an interface with the tool suites to quickly extract and manipulate
data.
SKILL scripts are executed in the Allegro PCB CIW (Command Interpreter Window).
The SKILL scripts provided with the Allegro to PADS Professional Layout translator are to be
used only with Allegro PCB.
Copying the Allegro SKILL Scripts

The SKILL script files must be copied to your Allegro system prior to running them on Allegro
PCB.
The skill scripts are located at: <install path>\MentorGraphics\<release_name>\SDD_HOME\
translators\skill_scripts
Procedure
1. Go to the <install path>\SDD_HOME\translators\skill_scripts directory.
Executing the Allegro SKILL Scripts
2. Group select all the *.il files.

3. Type Ctrl-C, or use the Copy popup menu item to copy the files.
4. Paste the files in the Allegro pcbenv directory.
Tip
The pcbenv directory is the storage location for SKILL scripts in the Cadence tools.
Executing the Allegro SKILL Scripts

Run SKILL scripts on the Allegro PCB system with the design active in the tool. The SKILL
script extracts the data and outputs it to the aexoutput directory in the design directory.
Prerequisites
• You have completed the “Translator Installation” on page 14, “Copying the Allegro
SKILL Scripts” on page 15 and “Allegro Design Preparation” on page 8 tasks.
Procedure
1. Open the Allegro layout (.brd) design file in the Allegro PCB Editor.
2. Check your Allegro design for errors.
a. In the Allegro CIW type the following commands:
skill load "transcheck.il"
transcheck
b. Check the resulting translatorcheck.log file (generated in the same directory as the
Allegro .brd file) to find any errors, warnings, or issues in the design that need to be
addressed and fix them prior to starting the translation.
3. In the Allegro CIW type the following commands:
skill load “all2layout.il”
all2layout
A message box appears showing the progress of the translation, while information about
the translation displays in the Allegro CIW.
4. When the SKILL scripts finish running, check the allegro.jrl file in the design directory
and the interfacelog.txt file in the aexoutput directory for errors.
Results
The extracted data in the aexoutput directory is ready for the next part of the translation process.
create_devices Command
create_devices Command
The SKILL scripts use the Allegro create_devices command to export device files to the
devices folder in the aexoutput directory.
This command fails when you encounter one-pin components that are no-connects or device
names that contain an equal sign (=). To complete the data export process, you must fix the
design so the create_devices command works.
Remove Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Resolve Device Names that Contain an Equals Sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Remove Components
To remove a geometry without leaving Allegro, use the SKILL command shown below.
In this example the device with reference designator “LB1M1” will be removed.
skill axlDeleteObject (axlDBFindByName (‘refdes “LB1M1”) )
Resolve Device Names that Contain an Equals Sign

If the SKILL script encounters an Allegro device name that contains an equals sign (=), you can
edit the device name in the Allegro Concept HDL schematic and forward annotate it to the
board, or you can remove the device from the Allegro PCB design.
Resolve Device Names that Contain an Equals Sign
Chapter 3
Running the Translator
Run the translator after you have installed Layout and set it as the active configuration.
Translation Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Invoking the Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Translator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Translation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Opening the Translated Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Post Processing the Translated Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Translation Process
The translation process uses the extracted Allegro data in the aexoutput file to import the design
into Layout.
This is referred to as Netlist Flow because the Layout project is not associated to any schematic
data at this time.
Invoking the Translator
Cell, Padstack, and Part information is generated during the translation, which you can then edit
using the Cell Editor and the Parts Database (PDB) Editor available with the Library Services in
Layout.
Invoking the Translator

Control the translation of the Allegro layout design using the Allegro to Layout Translator
dialog box.
Prerequisites
• The PADS Professional software has been installed on your machine.
Note
If a 64-bit version of PADS Professional has been installed, you must also have
PADS Classic installed to open the translator. If a 32-bit version of PADS
Professional has been installed, you do not need to have PADS Classic installed.
Procedure
From the Start menu, choose the PADS Pro Tools <release> > Administrative Tools > MGC
EBS CMD <version> menu item, then enter all2layout in the command window.
Note
To see a list of other commands available in the command window, choose the
PADS Pro Tools <release> > Translators and Features <version> menu item to
open a PDF of the command line functions for the PADS Professional flow.
The Allegro to Layout Translator opens.
Translator Interface
Translator Interface
Use the Allegro to Layout Translator interface to convert Allegro data to Layout data. Enter the
path names to the input directory, which contains the Allegro data output by the SKILL script,
and the output directory, which will contain the Layout project files after translation.
Output Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output Log
Check the all2layout.txt log file in the aexoutput directory for additional information on any
reported failures.
Translation Results
The Layout project files are created in the output (target) directory specified in the dialog box.
The resulting PCB file has the same name as the original Allegro design file.
Note
In pre-VX.2.10 versions of the Allegro Translator, the dynamic plane shape was brought
over. Currently the translator will bring over the original plane boundary shape. If the old
behavior is desired it can be recreated by creating an environment variable called
EBS_AEX_USE_DYNSHAPE. The value of the variable does not matter.
Opening the Translated Design

After translation completes, you must integrate the keyin netlist from the Layout design with the
schematic to verify that the design data is correct.
Prerequisites
• The translation has completed successfully.
Procedure
1. Double-click to open the \PCB\<allegro_design_name>.pcb Layout design file.
2. Click OK to dismiss the “Back annotation disabled” warning.
3. On the ECO menu, select “Run the Forward Annotate” to forward annotate the design.
4. In File Viewer, review the ForwardAnnotation.txt file.
Look for any errors that might have occurred (warnings are typically informational in
nature and do not require corrective action).
5. Open the Display Control dialog box (View > Display Control menu item).
Post Processing the Translated Design
6. Verify that the new pad and trace layers are displayed.
Tip
Turn off the less critical display data to help see the more important elements.

There are several things you can do after the design is translated to improve the quality of the
translation.
Constraint Manager
After translation, the new Layout design uses Net Class / Net Properties data. Layout has a more
robust constraint system in Constraint Manager. To upgrade the design to Constraint Manager,
run Forward Annotation on the design, then open the Project Integration dialog box
(Setup > Project Integration menu item). Click the Edit the Project File button to open the
Project Editor dialog box. Select the Netlist tab, then check the “Use Constraint Manager for
constraint entry” option. Click OK. The design will now be upgraded to Constraint Manager.
Constraint Update
Once the design has been migrated to Constraint Manager, you can bring over additional
constraint information. If you are interested in any of the data listed below, launch a MGC EBS
CMD window from the start menu and run the aexcmupdate file. When the program dialog
appears browse for the .pcb file of the newly upgraded design. The design must not be opened in
Layout when this process is run.Options on the dialog will enable if that type of data is detected
in the import file.
The following options are available:
• Back drill — Sets the back drill flag in Constraint Manager to indicate these nets should
have back drill data generated for them.
• Constraint Class — Creates Constraint Classes.
• Differential Pairs
o Updates the differential pair names to match Allegro
o Creates differential pairs that were defined as xnets in Allegro
o Adds additional constraints
• Match Group — Updates match group names to match Allegro
• Pin Pairs — Creates pin pairs.
Shorted Nets
Pins and vias that have shorted nets in Allegro are reported in the translatorcheck.txt log file. To
include the shorted nets information in Layout, run the shortednets.vbs script in Layout to apply
those shorts. The shortednets.vbs script is located in the <install_path>/SDD_HOME/
translators/examples directory.
Appendix A
Translation Troubleshooting
This appendix lists some frequently encountered issues that can impact your translation. Review
these items before translating your design because they may help prevent problems.
Allegro Board Refresh Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Zero Size Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Exclamation Marks in the Design Board Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Resolving Drill Symbols With Multiple Alphabetic Characters . . . . . . . . . . . . . . . . . . . 26
Multi-Hole Padstacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PDB/Cell Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PDB Cleanup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SKILL Script Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SMD Edge Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Long Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Forward Annotation Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Allegro Board Refresh Disabled

For better performance, design board refresh is disabled while exporting data from Allegro PCB
with SKILL scripts.
Zero Size Pads

Allegro has the ability to define a zero (0) size pad. However, the translator cannot locate and
correctly handle all of the possible cases where this situation can occur. If possible, adjust these
pads to make them as small as possible (1 DBU) and put a message in the log file stating the
intention of the pad before translating the design.
Exclamation Marks in the Design Board Path

SKILL scripts create a temporary Allegro macro file with commands exporting part of the data.
If your design board path contains an exclamation mark (!), the temporary macro file name also
contains an exclamation mark. This causes the SKILL script to try to execute the temporary
macro file with the replay command. To avoid this problem, ensure that your design board path
does not contain this character.
Resolving Drill Symbols With Multiple Alphabetic Characters
Resolving Drill Symbols With Multiple

Alphabetic Characters
In Allegro, the drill symbol can be defined as multiple characters. However, this will generate
an error message in the translator.
Symptoms
The following message appears in the import file.
ERROR - Too many Characters in the Drill Symbol specification for Hole
‘<hole name>’.
There must be exactly one alphabetic character.
Solution
Resolve this problem by editing the Padstack.hkp file located in the <design>_MGC/Work
directory to a single character for the drill symbol. Save the file and then re-run the Allegro to
PADS Professional Layout translation.
Multi-Hole Padstacks
Layout does not support multi-hole padstacks.
Any multi-hole padstacks found during the Skill extraction are reported in the interfacelog.txt
file in the MGC LogFiles directory. In Layout these padstacks have one hole at the center of the
padstack.
Symptoms
One of the following messages appear in the log file:
WARNING: Padstack CGA12_VIAX2_via has multiple holes

WARNING: Padstack MVIA1-2_35CI30C5DX4 has multiple holes
Solution
A sample script named multihole.vbs is provided in the <install path>\SDD_HOME\
translators\examples directory. When run in a Layout design, the script lists pins and vias that
referenced a multi-hole padstack. The script identifies these padstacks by looking for a property
that the translator adds to the padstack definition. The name of the property is
AEX_MULTI_HOLE and its format is
Grid:<num>X<num> OffsetX: <num> OffsetY: <num>
For example:
Grid:1X2 OffSetX: 0.5 OffSetY: 0.0
PDB/Cell Mismatch
Another example script named multiholeViaUpdate.vbs can be run to convert the former
multihole via padstacks into complex via patterns. If the multihole.vbs script identified vias in
your design, then try running multiholeViaUpdate.vbs to reconstruct those vias.
PDB/Cell Mismatch
There can be mismatches between the number of pins on a PCB cell and the number of pins
reported in the Parts Database. This causes a problem with editing the cell because the system
does not allow you to exit and save the cell if the false mismatch occurs.
Solution
Two workaround procedures exist for your use should you encounter this problem.
Workaround #1
Open the Parts Database (PDB) with the PDB Editor. Manually change the active cell name of
the parts using this cell by appending “_X” to the end of the name. Save the PDB and exit the
PDB Editor. This will cause an error to display during Forward Annotation of the design -
ignore the error. Open the cell for editing with the Cell Editor and Save the Cell. Re-open the
PDB, change the cell name back to the original name (meaning remove the “_X” from the
name) and then Save the PDB and close the PDB Editor. At this point all should now work
properly. However, if you have more than two or three cells exhibiting this problem, then
follow Workaround #2.
Workaround #2
This scenario is more time consuming because you have to start the translation process from the
beginning. Import the Padstack.hkp as stated in this document. But after closing the Import
ASCII dialog box, select the Setup > Library Services command from the pull-down menus.
This dialog box also allows you to import the Cell.hkp and PDB.hkp files. Import the cells first,
and then the PDB. You’ll discover that by using this method there are no issues with the pin
number mis-matches.
PDB Cleanup
The data compiled for generating the Parts Database (PDB) in Layout comes directly from the
Allegro database. This can cause problems if the PDB is to be shared and placed in a corporate
Central Library.
Solution
The PDB that is generated from the Allegro database directly has all the signal names associated
to the pins in that design that was translated and is therefore not a “true” generic PDB. At the
present time there is no workaround for this limitation so after design translation, and before
merging the data with a Central Library, you must spend time editing the PDB and correcting
any issues.
SKILL Script Location
SKILL Script Location

SKILL scripts must be run from an Allegro recognized SKILL directory.
This location can be either:
• The active directory where the Allegro *.brd file is located

• The Allegro generated directory $HOME\pcbenv
SMD Edge Connectors

At times the translator may not handle double-sided SMD edge connectors correctly. If your
design uses such a connector, double-check it after the translation in Layout. This problem
typically occurs on designs that have an AGP/PCI type connector.
Long Part Numbers

Layout supports part numbers only up to 64 characters. If your design has part numbers larger
than 64 characters, you can modify those part numbers and names in the partnum_mapping.txt
mapping file.
The partnum_mapping.txt is created in the PCB directory when you run the transcheck skill
program. Part numbers longer than 64 characters are truncated. You can then open this file in a
text editor and make any necessary edits before running the all2layout skill extraction script.
Forward Annotation Errors

If you receive an error indicating a missing part in the parts database, the translation may have
generated duplicate part number entries.
If Forward Annotation fails with the following type of error:
ERROR: There is not Part Number: ABC in the Parts

Database for symbols with Part Name: ABC and Part Label:
[Please add the Part Number to the PDB either directly
or by having a project file point to the PDB that contains it.]
1. Open the devices/create_devices.log file that was created during the skill extraction.
2. Search for the following messages:
WARNING(SPMHDF-67):Device 'ABC' occurs multiple times - check the
device file.
3. Remove the duplicate entries.
Using the example above, search the devices directory for a file named abc.txt and
additional files using the same part number (abc_1.txt, abc_2.txt, and so forth). Delete
the abc_<X>.txt files from the from the devices directory and the devices.map file.
4. Rerun the Allegro To PADS Professional Layout translator.

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Long Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Layout Software Requirements

Current Translator Restrictions

Preparing for Translation

Allegro Design Preparation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Allegro Design Preparation

Your final Allegro translation directory structure should look as follows:

Constraint Migration Preparation

Table 1-2. Layout Net Class to Net Class Clearances

Table 1-7. Differential Pair Properties (cont.)

• skill_scripts — Location of the SKILL scripts used by the translator

What is a SKILL Script?

Copying the Allegro SKILL Scripts

2. Group select all the *.il files.

Executing the Allegro SKILL Scripts

skill axlDeleteObject (axlDBFindByName (‘refdes “LB1M1”) )

Resolve Device Names that Contain an Equals Sign

Invoking the Translator

The Allegro to Layout Translator opens.

Opening the Translated Design

Post Processing the Translated Design

The following options are available:

Allegro Board Refresh Disabled

Zero Size Pads

Exclamation Marks in the Design Board Path

Resolving Drill Symbols With Multiple

WARNING: Padstack CGA12_VIAX2_via has multiple holes

Grid:<num>X<num> OffsetX: <num> OffsetY: <num>

Grid:1X2 OffSetX: 0.5 OffSetY: 0.0

SKILL Script Location

• The active directory where the Allegro *.brd file is located

SMD Edge Connectors

Long Part Numbers

Forward Annotation Errors

ERROR: There is not Part Number: ABC in the Parts

3. Remove the duplicate entries.

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