GRACE COLLEGE OF ENGINEERING

DEPARTMENT OF ECE

EC 8661 VLSI Design Laboratory

LAB MANUAL

YEAR : III ECE

SEMESTER 06
BATCH :2018-2022
ACADEMIC YEAR :2020-2021
 LAB MANUAL
Faculty name : V.SUSHMITHA

Faculty code 9503311

Subject code : EC 8661

Subject name : VLSI DESIGN LAB

Year : III

Semester : VI

Batch : 2018-2022

Programme : B.E.,

Department : ECE

Academic year : 2020-2021

PREPARED BY VERIFIED BY APPROVED BY

MS.V.SUSHMITHA.AP/ECE

(STAFF IN CHARGE) (HOD) (PRINCIPAL)

Ex. No: 1 Date:

DESIGN AN ADDER (MIN 8 BIT) USING HDL. SIMULATE IT USING

XILINX/ALTERA SOFTWARE AND IMPLEMENT BY XILINX/ALTERA FPGA

AIM:
To design an adder (min 8 bit) using HDL. Simulate it using Xilinx/Altera software and implement
by Xilinx/Altera FPGA

APPARATUS REQUIRED:

S.No Nameofthe equipment/ software Quantity

1. PC with Windows 1
2. Xilinx ISE 13.4 1
3 Spartan 3E FPGA Board 1
PROCEDURE:

1. Start theXilinxISE by using Start>Program files> XilinxISE>

project navigator

2. Click File>New Project

3. Enter the Project Name and select the location then click next

4. Select the Device and other category and click next twice and finish.

5. Click on the symbolof FPGAdevice and then right click>click on new source.

6. Select the Verilog Module and give the filename>click next and define ports

>click next and finish.

7. Type the Verilog Code in Verilog Editor.

8. Run the Check syntax>Process window >synthesize>double click check

syntax.If any errors found then remove the errors with proper syntax &coding.

9. Click on the symbol of FPGA device and then right click>click on new source.

10. Select the Test Bench Waveform and give the filename>select entity click next
and finish.
 11. Select the desired parameters for simulating your design.In this case combinational
circuit and simulation time click finish.

12. Assign all input signal using just click on graph and save file.

13. From the source process window. Click Behavioral simulation from drop-down
menu

14. Select the test bench file (.tbw) and click process button>double click
the Simulation Behavioral Model

15. Verify your design in wave window by seeing behavior of output signal with respect
to input signal
16. To assign package pins using corresponding CPLD manual via using constraint.
17. Assign package pins.
18. The pace file opened and give the pin details.
19. Go Implement design and generate the programming file and configure the device
(impact).
20. In configure device choose JTAG options and add the Xlinx device in boundary
scan and download the program and execute successfully.

CODING
8 BIT ADDER
module adder(s,cout,a,b,cin);
output[7:0]s;
outputcout;
input[7:0]a,b;
inputcin;
wirec1,c2,c3,c4,c5,c6,c7;
fulladd fa0(s[0],c1,a[0],b[0],cin);
fulladd fa1(s[1],c2,a[1],b[1],c1);
fulladd fa2(s[2],c3,a[2],b[2],c2);
fulladd fa3(s[3],c4,a[3],b[3],c3);
fulladd fa4(s[4],c5,a[4],b[4],c4);
fulladd fa5(s[5],c6,a[5],b[5],c5);
fulladd fa6(s[6],c7,a[6],b[6],c6);
fulladd fa7(s[7],cout,a[7],b[7],c7);
endmodule
modulefulladd(s,cout,a,b,cin);
outputs,cout;
inputa,b,cin; xor
 (s,a,b,cin);
assigncout= ((a&b)|(b&cin)|(a&cin)) ;
endmodule

MODEL OUTPUT: 8BIT ADDER

SIMULATION OUTPUT

RESULT

Thus an adder (min 8 bit) using HDL was simulated using Xilinx/Altera software and implement
by Xilinx/Altera FPGA.
Ex. No: 2 Date:

DESIGN AN MULTIPLIER (MIN 4 BIT) USING HDL. SIMULATE IT USING

XILINX/ALTERA SOFTWARE AND IMPLEMENT BY XILINX/ALTERA FPGA

AIM:
To design an multiplier (min 4 bit) using HDL. Simulate it using Xilinx/Altera software and
implement by Xilinx/Altera FPGA

APPARATUS REQUIRED:

S.No Nameofthe equipment/ software Quantity

1. PC with Windows 1
2. Xilinx ISE 13.4 1
3. Spartan 3E FPGA Board 1

PROCEDURE:

1. Start theXilinxISE by using Start>Program files> XilinxISE>

project navigator

2. Click File>New Project

3. Enter the Project Name and select the location then click next

4. Select the Device and other category and click next twice and finish.

5. Click on the symbolof FPGAdevice and then right click>click on new source.

6. Select the Verilog Module and give the filename>click next and define ports

>click next and finish.

7. Type the Verilog Code in Verilog Editor.

8. Run the Check syntax>Process window >synthesize>double click check

syntax.If any errors found then remove the errors with proper syntax &coding.

9. Click on the symbol of FPGA device and then right click>click on new source.

10. Select the Test Bench Waveform and give the filename>select entity click next
and finish.
 11. Select the desired parameters for simulating your design.In this case combinational
circuit and simulation time click finish.

12. Assign all input signal using just click on graph and save file.

13. From the source process window. Click Behavioral simulation from drop-down
menu

14. Select the test bench file (.tbw) and click process button>double click
the Simulation Behavioral Model

15. Verify your design in wave window by seeing behavior of output signal with respect
to input signal.
16. To assign package pins using corresponding CPLD manual via using constraint.
17. Assign package pins.
18. The pace file opened and give the pin details.
19. Go Implement design and generate the programming file and configure the device
(impact).
20. In configure device choose JTAG options and add the Xlinx device in boundary
scan and download the program and execute successfully.

COIDNG

4 BIT MULTIPLIER
modulemulti(m,a,b); input
[3:0]a;

input [3:0]b; output

[7:0]m;
wire[15:0]p;
wire[12:1]s;
wire[12:1]c;

and(p[0],a[0],b[0]);
and(p[1],a[1],b[0]);
and(p[2],a[0],b[1]);
and(p[3],a[2],b[0]);
and(p[4],a[1],b[1]);
and(p[5],a[0],b[2]);
and(p[6],a[3],b[0]);
and(p[7],a[2],b[1]);
and(p[8],a[1],b[2]);
and(p[9],a[0],b[3]);
and(p[10],a[3],b[1]);
and(p[11],a[2],b[2]);
and(p[12],a[1],b[3]);
and(p[13],a[3],b[2]);
and(p[14],a[2],b[3]);
and(p[15],a[3],b[3]);
half ha1(s[1],c[1],p[1],p[2]);

half ha2(s[2],c[2],p[4],p[3]);
half ha3(s[3],c[3],p[7],p[6]);
full fa4(s[4],c[4],p[11],p[10],c[3]);
full fa5(s[5],c[5],p[14],p[13],c[4]);
full fa6(s[6],c[6],p[5],s[2],c[1]);
full fa7(s[7],c[7],p[8],s[3],c[2]);
full fa8(s[8],c[8],p[12],s[4],c[7]);
full fa9(s[9],c[9],p[9],s[7],c[6]);
half ha10(s[10],c[10],s[8],c[9]);
full fa11(s[11],c[11],s[5],c[8],c[10]);
full fa12(s[12],c[12],p[15],s[5],c[11]);
buf(m[0],p[0]);
buf(m[1],s[1]);
buf(m[2],s[6]);
buf(m[3],s[9]);
buf(m[4],s[10]);
buf(m[5],s[11]);
buf(m[6],s[12]);
buf(m[7],c[12]);
endmodule
modulehalf(s,co,x,y);
inputx,y;
outputs,co;
xor (s,x,y);
and (co,x,y);
endmodule
module full(s,co,x,y,ci);
inputx,y,ci;
outputs,co;
wires1,d1,d2;
half ha_1(s1,d1,x,y);
half ha_2(s,d2,s1,ci);
oror_gate(co,d2,d1);
endmodule
 MODEL OUTPUT 4BIT MULTIPLIER

SIMULATION OUTPUT

RESULT

Thus a multiplier (min 4 bit) using HDL was simulated using Xilinx/Altera software and
implement by Xilinx/Altera FPGA.
Ex. No: 3 Date:

DESIGN AN ALU USING HDL. SIMULATE IT USING XILINX/ALTERA SOFTWARE

AND IMPLEMENT BY XILINX/ALTERA FPGA

AIM:
To design an ALU using HDL. Simulate it using Xilinx/Altera software and implement by
Xilinx/Altera FPGA

APPARATUS REQUIRED:

S.No Nameofthe equipment/ software Quantity

1. PC with Windows 1
2. Xilinx ISE 13.4 1
3. Spartan 3E FPGA Board 1

PROCEDURE:

1. Start theXilinxISE by using Start>Program files> XilinxISE>

project navigator

2. Click File>New Project

3. Enter the Project Name and select the location then click next

4. Select the Device and other category and click next twice and finish.

5. Click on the symbolof FPGAdevice and then right click>click on new source.

6. Select the Verilog Module and give the filename>click next and define ports

>click next and finish.

7. Type the Verilog Code in Verilog Editor.

8. Run the Check syntax>Process window >synthesize>double click check

syntax.If any errors found then remove the errors with proper syntax &coding.

9. Click on the symbol of FPGA device and then right click>click on new source.

10. Select the Test Bench Waveform and give the filename>select entity click next
and finish.
 11. Select the desired parameters for simulating your design.In this case combinational
circuit and simulation time click finish.

12. Assign all input signal using just click on graph and save file.

13. From the source process window. Click Behavioral simulation from drop-down
menu

14. Select the test bench file (.tbw) and click process button>double click
the Simulation Behavioral Model

15. Verify your design in wave window by seeing behavior of output signal with respect
to input signal.
16. To assign package pins using corresponding CPLD manual via using constraint.
17. Assign package pins.
18. The pace file opened and give the pin details.
19. Go Implement design and generate the programming file and configure the device
(impact).
20. In configure device choose JTAG options and add the Xlinx device in boundary
scan and download the program and execute successfully.

CODING

8 Bit ALU VERILOG CODING:

modulealu(clk, a, b, opcode, outp);

inputclk;
input [7:0] a, b;
input [2:0] opcode;
output [7:0] outp;
reg [7:0] outp;
always @(posedgeclk)
begin
case (opcode)
3'h0 :outp<= a + b;
3'h1 :outp<= a - b;
3'h2 :outp<= a & b;
3'h3 :outp<= a | b;
3'h4 :outp<= ~a;
 endcase end
endmodule

MODEL OUTPUT

SIMULATION OUTPUT

RESULT

Thusa ALU using HDL was simulated using Xilinx/Altera software and implement by
Xilinx/Altera FPGA
Ex. No: 4 Date:

DESIGN UNIVERSAL SHIFT REGISTER USING HDL. SIMULATE IT USING

XILINX/ALTERA SOFTWARE AND IMPLEMENT BY XILINX/ALTERA FPGA

AIM:
To design Universal Shift Register using HDL. Simulate it using Xilinx/Altera software and
implement by Xilinx/Altera FPGA

APPARATUS REQUIRED:

S.No Nameofthe equipment/ software Quantity

1. PC with Windows 1
2. Xilinx ISE 13.4 1
3. Spartan 3E FPGA Board 1

PROCEDURE:

1. Start theXilinxISE by using Start>Program files> XilinxISE>

project navigator

2. Click File>New Project

3. Enter the Project Name and select the location then click next

4. Select the Device and other category and click next twice and finish.

5. Click on the symbolof FPGAdevice and then right click>click on new source.

6. Select the Verilog Module and give the filename>click next and define ports

>click next and finish.

7. Type the Verilog Code in Verilog Editor.

8. Run the Check syntax>Process window >synthesize>double click check

syntax.If any errors found then remove the errors with proper syntax &coding.

9. Click on the symbol of FPGA device and then right click>click on new source.

10. Select the Test Bench Waveform and give the filename>select entity click next
and finish.
 11. Select the desired parameters for simulating your design.In this case combinational
circuit and simulation time click finish.

12. Assign all input signal using just click on graph and save file.

13. From the source process window. Click Behavioral simulation from drop-down
menu

14. Select the test bench file (.tbw) and click process button>double click
the Simulation Behavioral Model

15. Verify your design in wave window by seeing behavior of output signal with respect
to input signal
16. To assign package pins using corresponding CPLD manual via using constraint.
17. Assign package pins.
18. The pace file opened and give the pin details.
19. Go Implement design and generate the programming file and configure the device
(impact).
20. In configure device choose JTAG options and add the Xlinx device in boundary
scan and download the program and execute successfully.

SHIFT REGISTER:

The Shift Register is another type of sequential logic circuit that is used for the
storage or Transfer of data in the form of binary numbers and then "shifts" the data out once
every clock cycle, hence the name shift register. The data bits may be fed in or out of the register
serially. Shift Registers are used for data storage or data movement and are used in calculators or
computers to store data such as two binary numbers before they are added together, or to convert
the data from either a serial to parallel or parallel to serial format.
Generally, shift registers operate in one of four different modes
• Serial-in to Parallel-out (SIPO) - The register is loaded with serial data, one bit at a time,
with the stored data being available in parallel form.
• Serial-in to Serial-out (SISO) - The data is shifted serially "IN" and "OUT" of the register
one bit at a time in either a left or right direction under clock control.
• Parallel-in to Serial-out (PISO) - The parallel data is loaded into the register simultaneously
and is shifted out of the register serially one bit at a time under clock control.
• Parallel-in to Parallel-out (PIPO) - The parallel data is loaded simultaneously into the
register, and transferred together to their respective outputs by the same clock pulse.

4 BIT SERIAL IN SERIAL OUT SHIFT (SISO) REGISTER:

LOGIC DIAGRAM:
PROGRAM:

modulesiso(q,sout,clk,sin);
inputclk, sin;
outputq,sout;
regsout=1'b0;
reg[3:0]q=0;
always@(posedgeclk)
begin
q[3]=sin;
if(sout==1'b0)
q=q>>1;
else
q=q<<1;
sout=q[0];
end
endmodule
4 BIT SERIAL IN PARALLEL OUT SHIFT (SIPO) REGISTER:

LOGIC DIAGRAM:

PROGRAM:

modulesipo(pout,q, clk,sin);
inputclk, sin;
output pout, q;
reg pout=0;
reg[3:0]q=0;
always@(posedgeclk)
begin
if(pout==1'b0)
begin
q[0]=sin;
q=q<<1;
end
else
begin
q[3]=sin;
q=q>>1;
end
pout=q;
end
endmodule
4 BIT PARALLEL IN SERIAL OUT SHIFT (PISO) REGISTER:

LOGIC DIAGRAM

PROGRAM:

modulepiso(sout,q,pin,clk);
inputpin,clk;
outputsout,q;
regsout=1'b0;
reg[3:0]q=0;
always@(posedgeclk)
begin
q=pin;
case(sout)
0:q=q<<1;
1:q=q>>1;
endcase
sout=q[0];
end
endmodule
 4 BIT PARALLEL IN PARALLEL OUT SHIFT (PIPO) REGISTER:

LOGIC DIAGRAM:

PROGRAM:

modulepipo(pout, pin,clk);
input pin, clk;
output pout;
reg pout=0;
always@(posedgeclk)
begin
pout=pin;
end
endmodule
CODE – UNIVERSAL SHIFT REGISTER
Module univshift (data_out,clk,rst,mode,data_in);
Output reg[3:0]data_out;
Input[3:0]data_in;
Input[1:0]mode;
Input clk,rst;
Always @(posedge clk)
Begin
If(rst)
Data_out<=0;
Else
Begin
Case(mode)
2’b00:data_out<=data_out;
2’b01:data_out<={data_in[0],data_out[3:1]};
2’b10:data_out<={data_out[2:0],data_in[0]};
2’b00:data_out<=data_in;
Endcase
End
Endmodule
 MODEL OUTPUT

SIMULATION OUTPUT

RESULT

Thus Universal Shift Register using HDL was simulated using Xilinx/Altera software and
implement by Xilinx/Altera FPGA
Ex. No: 5 Date:

DESIGN FINITE STATE MACHINE USING HDL. SIMULATE IT USING

XILINX/ALTERA SOFTWARE AND IMPLEMENT BY XILINX/ALTERA FPGA

AIM:
To design Finite State Machine using HDL. Simulate it using Xilinx/Altera software and
implement by Xilinx/Altera FPGA

APPARATUS REQUIRED:
S.No Nameofthe equipment/ software Quantity
1. PC with Windows 1
2. Xilinx ISE 13.4 1
3. Spartan 3E FPGA Board 1

PROCEDURE:

• Start theXilinxISE by using Start>Program files> XilinxISE> project

navigator

• Click File>New Project

• Enter the Project Name and select the location then click next

• Select the Device and other category and click next twice and finish.

• Click on the symbolof FPGAdevice and then right click>click on new source.

• Select the Verilog Module and give the filename>click next and define ports

>click next and finish.

• Type the Verilog Code in Verilog Editor.

• Run the Check syntax>Process window >synthesize>double click check syntax.If

any errors found then remove the errors with proper syntax &coding.

• Click on the symbol of FPGA device and then right click>click on new source.

• Select the Test Bench Waveform and give the filename>select entity click next and
 finish.
• Select the desired parameters for simulating your design.In this case combinational
circuit and simulation time click finish.

• Assign all input signal using just click on graph and save file.

• From the source process window. Click Behavioral simulation from drop-down
menu

• Select the test bench file (.tbw) and click process button>double click the
Simulation Behavioral Model

• Verify your design in wave window by seeing behavior of output signal with respect to
input signal
• To assign package pins using corresponding CPLD manual via using constraint.
• Assign package pins.
• The pace file opened and give the pin details.
• Go Implement design and generate the programming file and configure the device
(impact).
• In configure device choose JTAG options and add the Xlinx device in boundary scan and
download the program and execute successfully.

CODING
module fsm( clk, rst, inp, outp);

input clk, rst, inp;

output outp;

reg [1:0] state;

reg outp;

always @( posedge clk, posedge rst )

begin
if( rst )
state <= 2'b00;
else
begin
case( state )
2'b00:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end

2'b01:
begin
if( inp ) state <= 2'b11;
 else state <= 2'b10;
end
2'b10:

begin
if( inp ) state <= 2'b01;
else state <= 2'b11;
end

2'b11:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end
endcase
end
end
always @(posedge clk, posedge rst)
begin
if( rst )
outp <= 0;
else if( state == 2'b11 )
outp <= 1;
else outp <= 0;

end
endmodule

TEST BENCH
`timescale 10ns/10ns
module fsm_test;

reg clk, rst, inp;

wire outp;
reg[15:0] sequence;
integer i;

fsm dut( clk, rst, inp, outp);

initial
begin

clk = 0;
rst = 1;
sequence = 16'b0101_0111_0111_0010;
#5 rst = 0;

for( i = 0; i <= 15; i = i + 1)

begin
inp = sequence[i];
#2 clk = 1;
#2 clk = 0;
$display("State = ", dut.state, " Input = ", inp, ", Output = ", outp);
 end
test2;

end
task test2;
for( i = 0; i <= 15; i = i + 1)
begin
inp = $random % 2;
#2 clk = 1;
#2 clk = 0;
$display("State = ", dut.state, " Input = ", inp, ", Output = ", outp);

end
endtask
endmodule

MODEL OUTPUT

SIMULATION OUTPUT –FSM

STATE DIAGRAM,

RESULT

Thus Finite State Machine using HDL was simulated using Xilinx/Altera software and
implement by Xilinx/Altera FPGA
Ex. No: 6 Date:

DESIGN MEMORIES USING HDL. SIMULATE IT USING XILINX/ALTERA

SOFTWARE AND IMPLEMENT BY XILINX/ALTERA FPGA

AIM:
To design Memories using HDL. Simulate it using Xilinx/Altera software and implement by
Xilinx/Altera FPGA

APPARATUS REQUIRED:

S.No Nameofthe equipment/ software Quantity

1. PC with Windows 1
2. Xilinx ISE 13.4 1
3. Spartan 3E FPGA Board 1

PROCEDURE:

1. Start theXilinxISE by using Start>Program files> XilinxISE>

project navigator

2. Click File>New Project

3. Enter the Project Name and select the location then click next

4. Select the Device and other category and click next twice and finish.

5. Click on the symbolof FPGAdevice and then right click>click on new source.

6. Select the Verilog Module and give the filename>click next and define ports

>click next and finish.

7. Type the Verilog Code in Verilog Editor.

8. Run the Check syntax>Process window >synthesize>double click check

syntax.If any errors found then remove the errors with proper syntax &coding.

9. Click on the symbol of FPGA device and then right click>click on new source.

10. Select the Test Bench Waveform and give the filename>select entity click next
and finish.

11. Select the desired parameters for simulating your design.In this case combinational
circuit and simulation time click finish.
 12. Assign all input signal using just click on graph and save file.

13. From the source process window. Click Behavioral simulation from drop-down
menu

14. Select the test bench file (.tbw) and click process button>double click
the Simulation Behavioral Model

15. Verify your design in wave window by seeing behavior of output signal with respect
to input signal
16. To assign package pins using corresponding CPLD manual via using constraint.
17. Assign package pins.
18. The pace file opened and give the pin details.
19. Go Implement design and generate the programming file and configure the device
(impact).
20. In configure device choose JTAG options and add the Xlinx device in boundary
scan and download the program and execute successfully.

MEMORY MODULE

A memory module is another name for a RAM chip. It is often used as a general term used to
describe SIMM, DIMM, and SO-DIMM memory. While there are several different types of
memory modules available, they all serve the same purpose, which is to store temporary data
while the computer is running.
TWO BASIC MEMORY OPERATIONS:
The memory unit supports two fundamental operations: Read and Write. The read
operation read a previously stored data and the write operation stores a value in memory.
MEMORY READ AND WRITE :
The following steps have to be followed in a typical read operation:
1. Place the address of the location to be read on the address line.

2. Activate the memory read control signal .

3. Wait for the memory to retrieve the data from the address memory location.
4. Read the data from the data line.
5. Drop the memory read control signal to terminate the read operation.
The following steps have to be followed in a typical write operation:
1. Place the address of the location to be written on the address line.
2. Place the data to be written on the data line.
3. Activate the memory write control signal .
4. Wait for the memory to store the data at the address location..
5. Drop the memory write control signal to terminate the write operation.
CODING
module memory( clk,
rst, read_rq, write_rq,
rw_address, write_data, read_data
);
inputclk; inputrst; inputread_rq; inputwrite_rq;
input[5:0] rw_address;
input[7:0] write_data;
output[7:0] read_data;
reg[7:0] read_data;

integer out, i;

// Declare memory 64x8 bits = 512 bits or 64 bytes

reg [7:0] memory_ram_d [63:0];
reg [7:0] memory_ram_q [63:0];

// Use positive edge of clock to read the memory

// Implement cyclic shift right
always @(posedgeclk or negedgerst)
begin
if (rst)
begin
for (i=0;i<64; i=i+1)
memory_ram_q[i] <= 0;
end
else
begin
for (i=0;i<64; i=i+1)
memory_ram_q[i] <= memory_ram_d[i];
end

end

always @(*)
begin
for (i=0;i<64; i=i+1)
memory_ram_d[i] = memory_ram_q[i];
if (write_rq==1 &&read_rq==0)
memory_ram_d[rw_address] = write_data;
if (write_rq==0 &&read_rq==1)
read_data = memory_ram_d[rw_address];
end

endmodule
MODEL OUTPUT

SIMULATIONOUTPUT

CODE
Module memo(input[7:0]data,input[5:0]addr,input rst,clk,output[7:0]q);
Reg[7:0]ram[63:0];
Reg[5:0]addr_reg;
always@(posedge clk)
begin
if(rst)
ram[addr]<=data;
addr_reg<=addr;
end
assign=ram[addr];
endmodule

RESULT

Thus Memory Modules using HDL was simulated using Xilinx/Altera software and implement
by Xilinx/Altera FPGA
Ex. No: 7 Date:

DESIGN AND SIMULATE A CMOS INVERTER USING DIGITAL FLOW

AIM:
To design and Simulate a CMOS Inverter using digital flow

APPARATUS REQUIRED:

S.No Nameofthe equipment/ software Quantity

1. PC with Windows 1
2. Micro wind Tools 1
PROCEDURE:
1. Open microwind by double clicking microwind2.
2. Create new design by Click on File New.
3. Select model file by Click on File Select Foundry and select the model file.
4. Create new text file and type the five transistor differential amplifier net list and save
as verilog file.
5. Click on Compile Compile Verilog File. Select the verilog text file and click on
Generate.
6. To Run Simulation Click Simulate Start Simulation.
7. View the output waveforms.
8. To extract the parasitic capacitance of the circuit diagram click simulate
Simulation parameters select Mos model and click extract.
RESULT

Thus the CMOS INVERTER using digitalflow was simulated and power,area timing are
analysed, pre and post layout simualtion was done
Ex. No: 8 Date:

DESIGN AND SIMULATE A CMOS BASIC GATES AND FLIPFLOPS

AIM:
To design and Simulate a CMOS basic Gates and Flipflops and to analyse power ,area and timing

APPARATUS REQUIRED:

S.No Nameofthe equipment/ software Quantity

1. PC with Windows 1
2. Micro wind Tools 1
PROCEDURE:
1. Open microwind by double clicking microwind2.
2. Create new design by Click on File New.
3. Select model file by Click on File Select Foundry and select the model file.
4. Create new text file and type the five transistor differential amplifier net list and save
as verilog file.
5. Click on Compile Compile Verilog File. Select the verilog text file and click on
Generate.
6. To Run Simulation Click Simulate Start Simulation.
7. View the output waveforms.
8. To extract the parasitic capacitance of the circuit diagram click simulate
Simulation parameters select Mos model and click extract.
RESULT

Thus the CMOS gates using digitalflow was simulated and power,area timing are analysed and
pre layout and post layout simulation was done
Ex. No: 9 Date:

DESIGN AND SIMULATE A 4-BIT SYNCHRONOUS COUNTER USING A FLIPFLOP

AIM:
To design and Simulate A 4-Bit Synchronous Counter Using Flipflops and to Analyse Power
,Area and Timing

APPARATUS REQUIRED:

S.No Nameofthe equipment/ software Quantity

1. PC with Windows 1
2. Micro wind Tools 1
PROCEDURE:
1. Open microwind by double clicking microwind2.
2. Create new design by Click on File New.
3. Select model file by Click on File Select Foundry and select the model file.
4. Create new text file and type the five transistor differential amplifier net list
and save as verilog file.
5. Click on Compile Compile Verilog File. Select the verilog text file and
click on Generate.
6. To Run Simulation Click Simulate Start Simulation.
7. View the output waveforms.
8. To extract the parasitic capacitance of the circuit diagram click simulate
Simulation parameters select Mos model and click extract.
 4 BIT SYNCHRONOUS COUNTER
JK FLIPFLOP SCHEMATIC

SYMBOL CREATION FROM SCHEMATICS

STEP 1:
STEP 2:

4BIT SYNCHRONOUS COUNTER USING JK FLIPFLOP

4BIT SYNCHRONOUS COUNTER PRE-LAYOUT SIMULATION

4BIT SYNCHRONOUS COUNTER LAYOUT

4BIT SYNCHRONOUS COUNTER POST-LAYOUT SIMULATIONS
VOLTAGE VS CURRENT

FREQUENCY VS VOLTAGE
 VOLTAGE VS TIME

EYE DIAGRAM

RESULT

Thus the 4-bit synchronous counter using digital flow was simulated and power, area,timing are
analysed,pre and post layout simualtion was done
Ex. No: 10 Date:

DESIGN AND SIMULATE A CMOS INVERTER AMPLIFIER

AIM:
To design and Simulate a CMOS Inverter and to analyze the input impedance, output impedance,
gain and bandwidth

APPARATUS REQUIRED:

S.No Nameofthe equipment/ software Quantity

1. PC with Windows 1
2. Tanner EDA Tools 1

PROCEDURE
1. Click the start menu and open tanner EDA software
2. Create a new directory and give name of new design
3. Draw and complete the circuit as required in s-edit.exe
4. Go to tools and click T Spice ,the Tspice modules open
5. Go to command and click file , choose the simulate file
6. There browse the path ;Tanner EDA/modules/m12-123md
7. Click edit, go to insert command,choose analysis and click taransient give the following
Values
Maximum time setup- 10ns
Simulation-10ns
Output start time -0sec
8.close Tspice tool dialog box
9.Again values for the following bit source give the terminal value and for bit input choose
option of bitstream
10.Repeat process of insert command for transient analysis, output->transient->choose
plot type:give node name then click add and save the file
11.click RUN button and start simulation
CMOS INVERTER AMPLIFIER
CMO
OUTPUT

RESULT
Thus a CMOS Inverter was designed and simulated and a the input impedance, output
impedance, gain and bandwidth are analysed
Ex. No: 11 Date:

DESIGN AND SIMULATE BASIC COMMON SOURCE COMMON GATE AND

COMMON DRAIN AMPLIFIERS.

AIM:
To design Basic Common Source Common Gate and Common Drain Amplifiers.
and Simulate and toanalyze the input impedance, output impedance, gain and bandwidth

APPARATUS REQUIRED:

S.No Nameofthe equipment/ software Quantity

1. PC with Windows 1
2. Tanner EDA Tools 1

PROCEDURE

1. Click the start menu and open tanner EDA software

2. Create a new directory and give name of new design
3. Draw and complete the circuit as required in s-edit.exe
4. Go to tools and click T Spice ,the Tspice modules open
5. Go to command and click file , choose the simulate file
6. There browse the path ;Tanner EDA/modules/m12-123md
7. Click edit, go to insert command,choose analysis and click taransient give the following
Values
Maximum time setup- 10ns
Simulation-10ns
Output start time -0sec
8.close Tspice tool dialog box
9.Again values for the following bit source give the terminal value and for bit input choose
option of bitstream
10.Repeat process of insert command for transient analysis, output->transient->choose
plot type:give node name then click add and save the file
11.click RUN button and start simulation
RESULT
Thus a common gate,common source amplifiliers was designed and simulated and a the input
impedance, output impedance, gain and bandwidth are analysed
Ex. No: 12 Date:

DESIGN AND SIMULATE SIMPLE 5 TRANSISTOR DIFFERENTIAL AMPLIFIER

AIM:
To design simple 5 transistor differential amplifier and Simulate and to analyze the gain
bandwidth and CMRR

APPARATUS REQUIRED:

S.No Nameofthe equipment/ software Quantity

1. PC with Windows 1
2. Tanner EDA Tools 1

PROCEDURE

1. Click the start menu and open tanner EDA software

2. Create a new directory and give name of new design
3. Draw and complete the circuit as required in s-edit.exe
4. Go to tools and click T Spice ,the Tspice modules open
5. Go to command and click file , choose the simulate file
6. There browse the path ;Tanner EDA/modules/m12-123md
7. Click edit, go to insert command,choose analysis and click taransient give the following
Values
Maximum time setup- 10ns
Simulation-10ns
Output start time -0sec
8.close Tspice tool dialog box
9.Again values for the following bit source give the terminal value and for bit input choose
option of bitstream
10.Repeat process of insert command for transient analysis, output->transient->choose
plot type:give node name then click add and save the file
11.click RUN button and start simulation
DIFFERENTIAL AMPLIFIER:
RESULT
Thus a five transistor differential amplifiliers was designed and simulated and a the input
impedance, output impedance, gain and bandwidth are analysed