RT6940
RT6940
RT6940
RT6940
This device is suitable for OLED TV panels. Many functions Adjustable Switching Frequency from 500kHz to
VGH voltage, VGL voltage, VPRED OP-Amplifier, BDP VCCT3.3 Async-Buck Converter
Comparator, BDP start/end delay time, switching 3V to 3.6V, Programmable Output
frequency, and integrated multiple-time programmable Adjustable Switching Frequency from SVDD
Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
PGNDH
COMPL
VGHM1
VGHM2
GND
VINL
VGH
VGL
RE1
RE2
LXH
LXL
NC
NC
56 55 54 53 52 51 50 49 48 47 46 45 44 43
LXT 1 42 SVDD
CBT 2 41 SVDDI
VINT 3 40 EGDS
NC 4 39 GND
GND 5 38 COMPH
COMPT 6 37 CSS
NC 7 36 COMPS
GND
VCCT 8 35 SSS
PGNDO 9 34 DRS
LXO 10 33 PGNDS
VCCO 11 57 32 VD
COMPO 12 31 ED_SNS
BGND 13 30 ED_MR
VPRED 14 29 ED_RST
15 16 17 18 19 20 21 22 23 24 25 26 27 28
VL
SCL
FLK2
VRG
RST
SDA
VIN
NMOS_CON
BDP
BD_SNS
AGND
FLK1
ES_ON
BD_REF
WQFN-56L 7x7
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L5 D4 C18
6.8uH SK54 22uF*6
C20 C19
47nF 4.7nF
C21
Input Supply
22uF*6
VIN 12V
L4
C1 10uH
41
37
34
40
42
10uF*5 15
D3
3
VIN
SK54
DRS
CSS
SVDDI
SVDD
EGDS
VINT 44
53 LXH VGH
VCCT3.3V L1 VINL C17
2.2uH 45 4.7uF*5
1 VGH
LXT
C2 C3 D1 VCCT
10uF*5 0.1uF SR26 2
CBT R19 R20 R21
8 4.7K 4.7K 4.7K
VCCT
C4 R1 28
NMOS_CON NMOS_CON
220pF 100K 24
6 COMPT BDP BDP
23
L2 RST RST
VCCO1.8V 2.2uH VCCT
10
LXO
C5 R17 R18
10uF*3 11 19 4.7K 4.7K
VCCO SDA
Interface
C6 R2 20
100pF 100K SCL
RT6940
12 COMPO D2
C7 SK34
55
10uF LXL VGL
14 VPRED C16
C8 L3 10uF*2
1uF 10uH
18
VL
56
VCCT VGL
VCCT
R3
10K 17 R16
R4
VRG 29 4.7K
ED_RST To SET
10K
30
ED_MR From SET
21 FLK1 EVDD
FLK1
22 R14
FLK2 FLK2 31 100K
26 ED_SNS R15
BD_SNS BD_SNS
19.5K
ES_ON 25 ES_ON GND
VL PGNDO
BGND
R5 AGND 5,9,13,16,33,39,43,54
100K PGNDS
27 PGNDH
VGHM1
VGHM2
COMPH
BD_REF
COMPL
COMPS
R6
100K
RE1
RE2
SSS
VD
32
35
38
51
36
46
47
49
48
R7 R8 C14 C15
R11 R12 R13 47nF 1uF
120R 120R 100K 100K
270K
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UVLO_R
VIN 12V
1ms
1ms T1 1ms
VCCT3.3 T3
T5
2ms
SVDDI
SVDDI/EGDS EGDS
VGH
SVDD
SVDD/VGH 2ms 5ms T6
(SVDDI-EGDS) >
4.5V
ASIC Reset
FLK1/2
Floating
VGH
VGHM1/2
VRG
ES_ON
(From T-
CON)
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ED_SNS ED_SNS
BD_REF
BD_REF
BD_SNS BD_SNS
BDPSTR BDPSTR
BDPEND BDPEND
NMOS_CON
Open Open GND Open NMOS_CON Open Open GND GND
1ms 1ms
ED_RST ED_RST
BDP
BDP
■ Power ON BDP Sequence @ Vin12V, EVDD 24V Sequence reverse ■ Power ON BDP Sequence @ Vin12V DIP
ED_RST Reference
ED_RST Reference
ED_SNS ED_SNS
BD_REF BD_REF
BD_SNS BD_SNS
BDPSTR BDPSTR
BDPEND BDPEND
NMOS_CON Open Open Open Open NMOS_CON Open Open Open Open
1ms 1ms
ED_RST ED_RST
BDP BDP
BD_REF BD_REF
BD_SNS BD_SNS
ED_RST ED_RST
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Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
10k
10uA
Internal
VL Regulator VD
VL(5.2V)
ASync. Boost DRS
Controller
SVDD
Internal CSS
VD Regulator COMPS
VD(7V) SSS
LXH
VINT
ASync. VINL
Async. Buck Inverting
LXT
VCCT(3.3V) VGL LXL
CBT
COMPT VGL
COMPL
VCCT
RST
Sequence
Sync. Buck
LXO Control
VCCO(1.8V)
FLK1
VGH DC/DC
MTP
DAC GND
GPM1
PGNDS,
VGHM1 PGNDO,
BDND,
RE1 PGNDH
VRG
FLK2 AGND
VGH
GPM2
VGHM2
BDP
RE2 BDP Logic
BD_SNS NMOS_CON
BD_REF NMOS_CON
Logic
ED_SNS ED_RST
1.2V ED_RST
VCCT Logic
ED_MR
Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Electrical Characteristics
(VIN = 12V, GND = PGND = 0V, VCCT = 3.3V, VCCO = 1.8V, SVDD = 16.8V, VGH = 26V, VGL = −8V, VPRED = 6.5V, TA = 25°C,
unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
General
Supply Voltage VIN 9.6 12 15.4 V
VIN Under Voltage Rising VUVLO VIN rising 8.5 9 9.5 V
VIN Under Voltage Falling VIN falling 7.5 8 8.5 V
VIN Over Voltage
VIN_OVP VIN rising, hysteresis = 1.5V 18 18.5 19.5 V
Protection
VIN = 12V, all converters switching
IIN Quiescent Current IQVIN 10 15 20 mA
and no loading
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Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-
thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the
exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Efficiency (%)
60 60
50 50
40 40
30 30
20 20
10 10
VIN = 12V, VSVDD = 16.8V, f = 700kHz VIN = 12V, VVCCT = 3.3V, f = 700kHz x 2
0 0
0 0.5 1 1.5 2 2.5 3 0 0.2 0.4 0.6 0.8 1
Load Current (A) Load Current (A)
VCCO Efficiency vs. Load Current VGH Efficiency vs. Load Current
100 100
90 90
80 80
70 70
Efficiency (%)
Efficiency (%)
60 60
50 50
40 40
30 30
20 20
VGL Efficiency vs. Load Current VCCT Voltage vs. Load Current
100 3.6
90
3.5
80
VCCT Voltage (V)
70
Efficiency (%)
3.4
60
50 3.3
40
3.2
30
20
3.1
10
VIN = 12V, VGL = −8V, f = 700kHz x 1.33 VIN = 12V, VVCCT = 3.3V, f = 700kHz x 2
0 3.0
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5 0.6
Load Current (A) Load Current (A)
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VCCO Voltage vs. Load Current SVDD Voltage vs. Load Current
2.2 20
2.1 19
2.0 18
VCCO Voltage (V)
1.8 16
1.7 15
1.6 14
VGH Voltage vs. Load Current VGL Voltage vs. Load Current
30 -5
29
-6
28
VGH Voltage (V)
-7
27
26 -8
25
-9
24
-10
23
VSVDD = 16.8V, VGH = 26V, f = 700kHz x 1.33 VIN = 12V, VGL = −8V, f = 700kHz x 1.33
22 -11
0 0.05 0.1 0.15 0.2 0.25 0.3 0 0.05 0.1 0.15 0.2 0.25 0.3
Load Current (A) Load Current (A)
VCCT Voltage vs. Input Voltage VCCO Voltage vs. Input Voltage
3.6 2.2
2.1
3.5
2.0
VCCT Voltage (V)
3.4
1.9
3.3 1.8
1.7
3.2
1.6
3.1
1.5
VVCCT = 3.3V, Load = 0.5A VVCCO = 1.8V, Load = 0.5A
3 1.4
9.6 10.4 11.2 12 12.8 13.6 14.4 15.2 16 3 3.1 3.2 3.3 3.4 3.5 3.6
Input Voltage (V) Input Voltage (V)
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SVDD Voltage vs. Input Voltage VGH Voltage vs. Input Voltage
20 30
19 29
18 28
SVDD Voltage (V)
16 26
15 25
14 24
13 23
VSVDD = 16.8V, Load = 1.5A VGH = 26V, Load = 0.3A
12 22
9.6 10.4 11.2 12 12.8 13.6 14.4 15.2 16 15 16 17 18 19 20
Input Voltage (V) Input Voltage (V)
-6 3.5
VCCT Voltage (V)
VGL Voltage (V)
-7 3.4
-8 3.3
-9 3.2
-10 3.1
2.0 19
SVDD Voltage (V)
VCCO Voltage (V)
1.9 18
1.8 17
1.7 16
1.6 15
VIN = 12V, VCCT = 3.3V, VVCCO = 1.8V VIN = 12V, VSVDD = 16.8V
1.5 14
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)
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29 -5
28 -6
VGH Voltage (V)
26 -8
25 -9
24 -10
23 -11
VSVDD = 16.8V, VGH = 26V VIN = 12V, VGL = −8V
22 -12
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)
7 25
Quiescent Current (mA)
VL Voltage (V)
6 20
5 15
4 10
3 5
(2V/Div) (2V/Div)
V VCCO V VCCO
VVCCO
V VCCO
(2V/Div) IIN (2V/Div)
I IN I IN
(1A/Div) VVGL (1A/Div) IIN
VVGH VVGH VVGH
VVGL
(5V/Div) (10V/Div) VVGL
VVGH VVGL
(10V/Div) VSVDD (5V/Div) VSVDD
VSVDD VSVDD
(10V/Div) (10V/Div)
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VVCCT VVCCO
(200mV/Div) (200mV/Div)
ILOAD ILOAD
(500mA/Div) (500mA/Div)
VSVDD VVGH
(200mV/Div) (500mV/Div)
ILOAD ILOAD
(500mA/Div) (500mA/Div)
VVGL
(200mV/Div)
ILOAD
(500mA/Div)
Time (500μs/Div)
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Write Command
(a) Write single byte of data to Register
Slave Address Register Address Data From Master
Slave Slave Slave
Start 1 0 1 0 1 0 0 0 ACK
0 0 0 0 0 R2 R1 R0 ACK
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Stop
Read Command
(a) Read single byte of data from Register
Slave Address Register Address Data From Master
Slave Slave Slave
Start 1 0 1 0 1 0 0 0 ACK
1 1 1 1 1 1 1 1 ACK
0 0 0 0 0 0 0 0 ACK
Stop
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Note : CR Data
00h : Read data from DAC register (DR).
01h : Read data from EEPROM.
80h : Write all DAC register (DR) into EEPROM.
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Address : 01
Factor
Volatile/
Name Function Address (Power-Up MSB LSB
Nonvolatile
Default)
T1 Delay 2bit
T1 0 0 X X X X X X
Time Nonvolatile
T3 Delay 2bit
T3 0x01h 08h X X X X 1 0 X X
Time Nonvolatile
T4 Delay 2bit
T4 X X X X X X 0 0
Time Nonvolatile
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SVDD SW 2bit
FREQ X X 0 1 X X X X
Frequency Nonvolatile
0x02h 15h
VGH SW 2bit
FREQH X X X X 0 1 X X
Frequency Nonvolatile
VGL SW 2bit
FREQL X X X X X X 0 1
Frequency Nonvolatile
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VPRED 1bit
OP-Amp_OFF X X X X X X X 1
Enable Nonvolatile
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Address : 05
Factor
Volatile/
Name Function Address (Power-Up MSB LSB
Nonvolatile
Default)
VPRED 3bit
VPRED 1 1 1 X X X X X
Output Nonvolatile
VPRED
1bit
VPRED_Mode Mode X X X 1 X X X X
Nonvolatile
Select
0x05h FAh
VGL BDP 2bit
VGL_BDP X X X X 1 0 X X
Level Nonvolatile
VGH BDP 2bit
VGH_BDP X X X X X X 1 0
Level Nonvolatile
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Address : 07
Factor
Volatile/
Name Function Address (Power-Up MSB LSB
Nonvolatile
Default)
BDP End 3bit
BDP_END 1 0 1 X X X X X
Delay Time Nonvolatile
0x07h A8h
VGL 5bit
VGL X X X 0 1 0 0 0
Output Nonvolatile
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VGH Boost Converter where η is the efficiency of the Boost converter, ILIM is the
VGH channel is the asynchronous Boost converter with a value of the current limit and tS is the switching period. If
current mode topology and fixed frequency operation. inductor current peak reaches current limit, the SVDD
Moreover, user can adjust switching frequency by register channel will be keep current limit level.
address 02h respectively. The Boost converter can operate
VGH Boost Short-Circuit Protection
in either Continuous Conduction Mode (CCM) or
Discontinuous Conduction Mode (DCM), depending on The VGH has an advanced short-circuit protection
the load current to gain optimum efficiency and minimum mechanism which prevents the device from damage by
output ripple. It performs fast transient responses to unexpected applications. An error condition is detected if
generate source driver supplies for OLED display. The high the voltage on the converter's VGH pin remains below VGH
operation frequency allows use of smaller components to x 20% for longer than 10μs, IC will be shut down and then
minimize the thickness of the OLED panel restart three times. If the failure information is still not
released, the chip will be shutdown. Once shut down, the
VGH Boost Output Voltage Setting boost converter can only be enabled after the chip is
A VGH asynchronous Boost converter has the I 2 C powered on again.
adjustable output voltage from 22V to 32V in 0.5V
VGH Boost Fault Protection
increments. The default VGH voltage is 26V. User can
control the VGH output voltage by register address 06h The VGH Boost converter has a fault protection function,
respectively. if VGH pin is detected to be below VGH x 65% for longer
than 50ms. The SVDD, VGH, VGL, VCCT and VCCO will
be shut down. Once the SVDD shuts down, the Boost
converter can only be enabled after the chip is powered
on again.
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L D IOUT
∆VOUT1
0.4 VOUT IOUT MAX fOSC
2
η COUT fOSC
where fOSC is the switching frequency. For better system where D is the duty cycle and η is the Boost converter
performance, a shielded inductor is preferred to avoid EMI efficiency. Finally, taking ESR into consideration, the
problems. overall output ripple voltage can be determined by the
following equation :
Boost Converter Diode Selection
D IOUT
Schottky diode is a good choice for an asynchronous ∆VOUT ∆VESR
η COUT fOSC
Boost converter due to its small forward voltage. However,
when selecting Schottky diodes, important parameters where ΔVESR = ΔIC x RC_ESR = IPEAK x RC_ESR
such as power dissipation (PD = VF x Id), reverse voltage The output capacitor, COUT, should be selected accordingly.
rating and pulsating peak current should all be taken into
consideration. For better performance, it is recommended
to choose a suitable diode with reverse voltage rating
greater than the maximum output voltage.
The VCCT asynchronous Buck converter is high efficiency where η is the efficiency of the Buck converter, ILIM is the
PWM architecture with 1.4MHz (typ.) operation frequency value of the current limit and fSW is the switching frequency.
and fast transient response. Moreover, user can adjust
switching frequency by register address 03h respectively. VCCT Asynchronous Buck Short-Circuit Protection
The converter drives an internal 2.5A (typ.) N-MOSFET The VCCT has an advanced short-circuit protection
which is connected between the VIN and LXT pin. Connect mechanism which prevents the device from damage by
a 100nF low ESR ceramic capacitor between the CBT unexpected applications. An error condition is detected if
and LXT pins to provide gate driver voltage for the high- the voltage on the converter's VCCT pin remains below
side MOSFET. VCCT x 20% for longer than 10μs, IC will be shut down
and then restart three times. If the failure information is
still not released, the chip will be shutdown. Once shut
down, the boost converter can only be enabled after the
chip is powered on again.
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The VCCO synchronous converter is high efficiency PWM Where η is the efficiency of the Buck converter, ILIM is the
architecture with 1.4MHz (typ.) operation frequency and value of the current limit and fSW is the switching frequency.
fast transient response. Moreover, user can adjust
switching frequency by register address 03h respectively. VCCO Synchronous Buck Short-Circuit Protection
VCCO converter has one internal P-MOSFET and one The VCCO has an advanced short-circuit protection
internal N-MOSFET as synchronous rectifier and do not mechanism which prevents the device from damage by
require Schottky diode on the switching Pin. The high- unexpected applications. An error condition is detected if
side MOSFET is connected between the VIN and switching the voltage on the converter's VCCO pin remains below
pins, while the low-side MOSFET is connected between VCCO x 20% for longer than 10μs, IC will be shut down
the switching pin and GND. The synchronous Buck and then restart three times. If the failure information is
converter's loop compensation network is builds in inside still not released, the chip will be shutdown. Once shut
RT6940. down, the boost converter can only be enabled after the
chip is powered on again.
VCCO Synchronous Buck Soft-Start
The VCCO synchronous Buck converter has an internal VCCO Synchronous Buck Fault Protection
soft-start to reduce the input inrush current respectively. The VCCO synchronous Buck converter has a fault
When the converter is enabled, the output voltage rises protection feature to protect the IC when the output
slowly from zero to target output voltage. The typical soft- becomes shorted to GND. This is achieved by using the
start time is around 1ms. comparator to monitor the VCCO voltage. If VCCO remains
below VCCO x 65% for 50ms, the VCCO Buck converter
VCCO Synchronous Buck Output Voltage Setting will be disabled. Once shut down, the regulator can only
VCCO synchronous Buck converter has the I2C adjustable be enabled after the chip is powered on again.
output voltage from 1.5V to 2.8V in 0.1V increments. The
default VCCO voltage is 1.8V. User can control the Buck Buck Inductor Selection
output voltage by register address 04h respectively. The inductor value and operating frequency determine the
ripple current according to a specific input and output
VCCO Synchronous Buck Over-Voltage Protection voltage. The ripple current, ΔIL, will increase with higher
The VCCO synchronous Buck converter has the over- VIN and decrease with higher inductance, as shown in the
voltage protection to protect the main switch at the VCCO equation below :
pin. When the VCCO pin voltage rises above (VCCO x
∆IL OUT 1 OUT
V V
120%) V (typ.), VCCO will be shut down. As soon as the
fOSC L VIN
output voltage falls below the over-voltage threshold, the
VCCO will resume operation. Having a lower ripple current reduces not only the ESR
losses in the output capacitors but also the output voltage
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Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
VGL Buck-Boost Short-Circuit Protection Figure 2. The Buck-Boost Input Signature in BCM
The VGL has an advanced short-circuit protection The inductance can eventually be determined according
mechanism which prevents the device from damage by to the following equation :
unexpected applications. An error condition is detected if
2
the voltage on the converter's VGL pin remains below − VOUT VIN
Lcritical
1.3V for longer than 10μs, IC will be shut down and then 2 fOSC IOUT VIN VOUT
restart three times. If the failure information is still not
released, the chip will be shutdown. Once shut down, the As a general rule, the inductor ripple current range is 20%
boost converter can only be enabled after the chip is to 40% of the average DC inductor current. If 40% is
powered on again. selected as an example, the inductor ripple current can
be calculated according to the following equations :
VGL Buck-Boost Output Voltage Setting
2
VGL Buck-Boost converter has the I2C adjustable output VOUT VIN
L
voltage from −4V to −13V in 0.5V increments. The default 0.4 fOSC IOUT VIN VOUT
VGL voltage is −8V. User can control the Buck-Boost
output voltage by register address 07h respectively. Buck-Boost Converter Diode Selection
To achieve high efficiency, a Schottky diode should be
Buck-Boost Converter Inductor Selection
used. The reverse voltage rating should be higher than
The buck-boost converter is able to operate with 10μH to the maximum output voltage of the buck-boost converter.
47μH inductors, but a 10μH inductor is typical. The main The average rectified forward current, IAVG, the Schottky
parameter for inductor selection is the saturation current diode needs to be rated for, is equal to the output current,
of the inductor which should be higher than the peak switch IOUT.
current as calculated in the Design Procedure section with
PD = IAVG x VFORWARD
additional margin to cover for heavy load transients. As
for inductance, we are going to derive the transition point, Buck-Boost Converter Output Capacitor Selection
where the converter toggles from CCM to DCM. We need
For the best output voltage filtering, low ESR ceramic
to define the point at which the inductor current ripple
capacitors are recommended. One 22μF or two 10μF
touches zero, and as the power switch is immediately
output capacitors with sufficient voltage ratings in parallel
reactivated, the current ramps up again. Figure 2 portrays
are adequate for most applications. Additional capacitors
the input current activity of the Buck-Boost converter.
can be added to improve load transient regulation.
To calculate the output voltage ripple, the following equation
can be used :
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Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0 25 50 75 100 125
Ambient Temperature (°C)
Figure 3. Derating Curve of Maximum Power Dissipation
Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
GND
COMPL
VGHM1
VGHM2
43 PGNDH
Minimize the size of the LXT node and
VGL
LXL
NC
GND
VINL
NC
RE1
RE2
VGH
LXH
keep it wide and shorte. Keep the LXT
node away from the VCCT pin.
VCCT
48
47
56
55
54
53
52
51
50
49
46
45
44
L1
LXT 1 42 SVDD
R C3
C20 Q1
D4
EGDS
C25 C24 C23 C22 C2 CBT 2 41 SVDDI
GND
C21 C*
VINT 3 40 EGDS GND
D3
VIN NC 4 39 GND
L5
C1 R18 C16
VIN
Q2
GND 5 38 COMPH R
DRS
C4 R1 C30 C31 C32
GND
The compensation network must
COMPT 6 37 CSS
R17 C15
near the COMP pin. The trace NC 7 36 COMPS
must be short and avoid the trace WQFN 7x7 56L
C13
GND
near any switching nodes.
VCCT 8 PGND 35 SSS GND
C42 C41 R
PGNDO 9 34 DRS
C28 C27 C5 L2
LXO 10 33 PGNDS
VCCO R3
11 32 VD The Q2, D3 and LX trace should be
VCCO GND
C11 very close to prevent lager amount of
Minimize the size of the LXO
EMI. The Trace from DRS should also
node and keep it wide and 12 31 ED_SNS
COMPO be short to decrease the noise of the
shorte. Keep the LXO node R2
C6 driver output signals.
away from the VCCO pin.
BGND 13 30 ED_MR
C7
VPRED 14 29 ED_RST The CSS and PGND PCB traces should be routed
parallel to one another with minimum spacing in
between all the way to the sense resistor. These
VIN 15
AGND 16
VRG 17
VL 18
SDA 19
SCL 20
FLK1 21
FLK2 22
RST 23
BDP 24
ES_ON 25
BD_SNS 26
BD_REF 27
28
GND C45
traces should far away any high frequency switching
nodes in the layout, in order to avoid the sense error
NMOS_CON
HAVDD due to parasitic PCB resistance IR drops.
Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
2 1 2 1
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.