RT6940

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®

RT6940

Multi-Channel PMIC with I2C Interface for OLED Panels


General Description Features
The RT6940 includes one SVDD Boost converter, one VGH  9.6V to 15.4V Input Voltage Range
boost converter, one Async-Buck converter, one Sync-  SVDD Boost Converter
Buck converter and one VGL negative inverting converter.  15V to 20V, Programmable Output

This device is suitable for OLED TV panels. Many functions Adjustable Switching Frequency from 500kHz to

can be programmable by I2C interface including Buck 900kHz


VCCO/VCCT converters voltage, SVDD converter voltage, 0.2V/0.4V Over-Current Protection

VGH voltage, VGL voltage, VPRED OP-Amplifier, BDP  VCCT3.3 Async-Buck Converter
Comparator, BDP start/end delay time, switching  3V to 3.6V, Programmable Output

frequency, and integrated multiple-time programmable Adjustable Switching Frequency from SVDD

(MTP) non-volatile memory. Frequency x 1 to SVDD Frequency x 2


2A Over-Current Protection
The RT6940 also integrates complete protection functions
 VCCO1.8 Sync-Buck Converter
including, OVP, UVP, OCP, and OT protection. The device
 1.5V to 2.8V, Programmable Output
is used for OLED in the WQFN-56L 7x7 package.
Adjustable Switching Frequency from SVDD

Frequency x 1 to SVDD Frequency x 2


Applications 1.5A Over-Current Protection

 OLED Panels  VGH Boost Converter


 22V to 32V, Programmable Output

Adjustable Switching Frequency from SVDD


Ordering Information Frequency x 1 to SVDD Frequency x 2
RT6940
1.5A Over-Current Protection
Package Type  VGL Negative Inverting Converter
QW : WQFN-56L 7x7 (W-Type)  -4V to -13V, Programmable Output
Lead Plating System Adjustable Switching Frequency from SVDD
G : Green (Halogen Free and Pb Free)
Frequency x 1 to SVDD Frequency x 2
Note :
1.5A Over-Current Protection
Richtek products are :
 Programmable VGH BDP Current from 600mA to
 RoHS compliant and compatible with the current require-
1050mA
ments of IPC/JEDEC J-STD-020.
 Programmable VGL BDP Current from 450mA to
 Suitable for use in SnPb or Pb-free soldering processes.
900mA
 Programmable BDP Start/End Delay Time
Marking Information  Adjustable VPRED from 3V to 6.5V
RT6940GQW : Product Number  Programmable Delay Time of T1,T3,T4 and T6
RT6940 YMDNN : Date Code  Integrated MTP Memory
GQW
 I2C-Compatible Interface for Register Control
YMDNN
 Under-Voltage Protection
 Over-Temperature Protection

Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS6940-00 July 2017 www.richtek.com


1
RT6940
Pin Configuration
(TOP VIEW)

PGNDH
COMPL

VGHM1

VGHM2
GND
VINL

VGH
VGL

RE1

RE2

LXH
LXL

NC

NC
56 55 54 53 52 51 50 49 48 47 46 45 44 43
LXT 1 42 SVDD
CBT 2 41 SVDDI
VINT 3 40 EGDS
NC 4 39 GND
GND 5 38 COMPH
COMPT 6 37 CSS
NC 7 36 COMPS
GND
VCCT 8 35 SSS
PGNDO 9 34 DRS
LXO 10 33 PGNDS
VCCO 11 57 32 VD
COMPO 12 31 ED_SNS
BGND 13 30 ED_MR
VPRED 14 29 ED_RST
15 16 17 18 19 20 21 22 23 24 25 26 27 28
VL

SCL

FLK2
VRG

RST
SDA
VIN

NMOS_CON
BDP

BD_SNS
AGND

FLK1

ES_ON

BD_REF

WQFN-56L 7x7

Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

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2
RT6940
Typical Application Circuit
SVDDI SVDD

L5 D4 C18
6.8uH SK54 22uF*6
C20 C19
47nF 4.7nF
C21
Input Supply
22uF*6
VIN 12V
L4
C1 10uH

41
37
34

40

42
10uF*5 15
D3
3
VIN
SK54
DRS

CSS

SVDDI

SVDD
EGDS
VINT 44
53 LXH VGH
VCCT3.3V L1 VINL C17
2.2uH 45 4.7uF*5
1 VGH
LXT
C2 C3 D1 VCCT
10uF*5 0.1uF SR26 2
CBT R19 R20 R21
8 4.7K 4.7K 4.7K
VCCT
C4 R1 28
NMOS_CON NMOS_CON
220pF 100K 24
6 COMPT BDP BDP
23
L2 RST RST
VCCO1.8V 2.2uH VCCT
10
LXO
C5 R17 R18
10uF*3 11 19 4.7K 4.7K
VCCO SDA
Interface
C6 R2 20
100pF 100K SCL

RT6940
12 COMPO D2
C7 SK34
55
10uF LXL VGL
14 VPRED C16
C8 L3 10uF*2
1uF 10uH
18
VL
56
VCCT VGL
VCCT
R3
10K 17 R16
R4
VRG 29 4.7K
ED_RST To SET
10K
30
ED_MR From SET
21 FLK1 EVDD
FLK1
22 R14
FLK2 FLK2 31 100K
26 ED_SNS R15
BD_SNS BD_SNS
19.5K
ES_ON 25 ES_ON GND
VL PGNDO
BGND
R5 AGND 5,9,13,16,33,39,43,54
100K PGNDS
27 PGNDH
VGHM1

VGHM2

COMPH

BD_REF
COMPL

COMPS

R6
100K
RE1
RE2

SSS

VD
32
35
38
51

36
46
47

49

48

R7 R8 C14 C15
R11 R12 R13 47nF 1uF
120R 120R 100K 100K
270K

C11 C12 C13


C9 C10 180pF 1nF 1nF
4.7nF 4.7nF
R9 R10
9.1K 9.1K

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DS6940-00 July 2017 www.richtek.com


3
RT6940
Timing Diagram

Typ Power Sequence UVLO_F

UVLO_R

VIN 12V
1ms

1ms T1 1ms
VCCT3.3 T3

VCCO1.8 T4 2ms 5ms

T5: Adjust By Cap.


VGL

T5
2ms

SVDDI

SVDDI/EGDS EGDS
VGH

SVDD
SVDD/VGH 2ms 5ms T6

(SVDDI-EGDS) >
4.5V

ASIC Reset

FLK1/2

Floating

VGH
VGHM1/2
VRG

ES_ON
(From T-
CON)

Case 1 set by I2C


VPRED Case 2 set by I2C
Output
Under
1600ms

Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

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4
RT6940
■ Power ON BDP Sequence @ On, normal case ■ Power ON BDP Sequence @ On, BDP Detect case

Vin 12V Vin 12V

ED_RST Reference ED_RST Reference

ED_SNS ED_SNS

BD_REF
BD_REF

BD_SNS BD_SNS

BDPSTR BDPSTR
BDPEND BDPEND
NMOS_CON
Open Open GND Open NMOS_CON Open Open GND GND

1ms 1ms
ED_RST ED_RST

BDP
BDP

■ Power ON BDP Sequence @ Vin12V, EVDD 24V Sequence reverse ■ Power ON BDP Sequence @ Vin12V DIP

UVLO Release UVLO Release


UVLO Lock
Vin 12V Vin 12V

ED_RST Reference
ED_RST Reference
ED_SNS ED_SNS

BD_REF BD_REF

BD_SNS BD_SNS

BDPSTR BDPSTR

BDPEND BDPEND

NMOS_CON Open Open Open Open NMOS_CON Open Open Open Open

1ms 1ms
ED_RST ED_RST

BDP BDP

■ Power ON BDP Sequence @ Off case

UVLO Lock UVLO Lock


Vin 12V Vin 12V

ED_RST Reference ED_RST Reference


ED_SNS ED_SNS

BD_REF BD_REF

BD_SNS BD_SNS

NMOS_CON Open Open NMOS_CON Open Open

ED_RST ED_RST

Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

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5
RT6940
Functional Pin Description
Pin No Pin Name Pin Function
1 LXT VCCT3.3 buck converter switching node.
2 CBT VCCT3.3 buck converter bootstrap pin.
3 VINT VCCT3.3 buck converter supply power.
4, 7, 50, 52 NC No internal connection.
5 GND Common ground.
6 COMPT1 VCCT3.3 buck converter compensation pin.
8 VCCT VCCT3.3 buck converter output sensing and VCCO1.8 supply power.
9 PGNDO VCCO1.8 buck converter power ground.
10 LXO VCCO1.8 buck converter switching node.
11 VCCO VCCO1.8 buck converter output sensing.
12 COMPO VCCO1.8 buck converter compensation pin.
13 BGND VPRED OP-AMP ground.
14 VPRED VPRED OP-AMP output.
15 VIN IC & VPRED OP-AMP supply power.
16 AGND Analog ground.
17 VRG GPM1/2 level setting pin DC level.
18 VL Internal regulator output.
19 SDA I2C data I/O.
20 SCL I2C clock input.
21 FLK1 GPM1 control signal.
22 FLK2 GPM2 control signal.
23 RST ASIC reset signal.
24 BDP BDP output.
25 ES_ON VPRED OP-AMP EN input.
26 BD_SNS BDP sensing input.
27 BD_REF BDP reference input.
28 NMOS_CON NMOS control output.
29 ED_RST EVDD reset output.
30 ED_MR EVDD masking input.
31 ED_SNS EVDD sensing input.
32 VD Internal regulator output for SVDD external FET driver power.
33 PGNDS SVDD MAIN FET power ground.
34 DRS SVDD MAIN FET control pin.
35 SSS SVDD soft-start control pin.

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6
RT6940
Pin No Pin Name Pin Function
36 COMPS SVDD compensation pin.
37 CSS SVDD MAIN FET current sensing pin.
38 COMPH VGH boost converter compensation pin.
39 GND Common ground.
40 EGDS SVDD ISO FET control pin.
41 SVDDI SVDD ISO FET input.
42 SVDD SVDD ISO FET output sensing.
43 PGNDH VGH Boost converter power ground.
44 LXH VGH Boost converter switching node.
45 VGH VGH Boost converter output sensing and GPM1,2 supply power.
46 VGHM2 GPM2 output.
47 RE2 GPM2 slope control pin.
48 VGHM1 GPM1 output.
49 RE1 GPM1 slope control pin.
51 COMPL VGL compensation pin.
53 VINL VGL inverting converter supply power.
54 GND Common ground.
55 LXL VGL inverting converter switching node.
56 VGL VGL inverting converter output sensing.
57 Ground. The exposed pad must be soldered to a large PCB and connected to
GND
(Exposed Pad) GND for maximum power dissipation.

Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

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7
RT6940
Functional Block Diagram
VIN SVDDI EGDS SVDD

10k
10uA

Internal
VL Regulator VD
VL(5.2V)
ASync. Boost DRS
Controller
SVDD
Internal CSS
VD Regulator COMPS
VD(7V) SSS

LXH

OP-AMP ASync. Boost


VPRED
VPRED VGH
ES_ON VGH
COMPH

VINT
ASync. VINL
Async. Buck Inverting
LXT
VCCT(3.3V) VGL LXL
CBT
COMPT VGL
COMPL
VCCT
RST
Sequence
Sync. Buck
LXO Control
VCCO(1.8V)

VCCO I2C Interface SDA


COMPO SCL

FLK1
VGH DC/DC
MTP
DAC GND
GPM1
PGNDS,
VGHM1 PGNDO,
BDND,
RE1 PGNDH
VRG
FLK2 AGND
VGH

GPM2
VGHM2
BDP
RE2 BDP Logic

BD_SNS NMOS_CON
BD_REF NMOS_CON
Logic
ED_SNS ED_RST
1.2V ED_RST
VCCT Logic

ED_MR

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8
RT6940
Absolute Maximum Ratings (Note 1)
 VIN, VINT, VINL, LXT to GND -------------------------------------------------------------------------------------- −0.3V to 19.5V
 VPRED to GND -------------------------------------------------------------------------------------------------------- −0.3V to 16.5V
 SVDDI, SVDD, EGDS to GND ------------------------------------------------------------------------------------- −0.3V to 21V
 SVDDI to SVDD ------------------------------------------------------------------------------------------------------- −0.3V to 18V
 CBT to GND ------------------------------------------------------------------------------------------------------------ −0.3V to (LXT+7V)
 VL, VCCT, VCCO, LXO, COMPT, COMPO, COMPS, COMPH, COMPL, SSS, VRG,
BD_SNS, BD_REF, ED_SNS, ED_RST, ED_MR, SDA, SCL, FLK1, FLK2, RST,
BDP, ES_ON, NMOS_CON to GND ------------------------------------------------------------------------------ −0.3V to 6V
 VD, DRS, CSS to GND ---------------------------------------------------------------------------------------------- −0.3V to 7V
 VGH, LXH, VGHM1, RE1, VGHM2, RE2 to GND -------------------------------------------------------------- −0.3V to 36V
 VGL to GND ------------------------------------------------------------------------------------------------------------ −16V to +0.3V
 LXL to VINL ------------------------------------------------------------------------------------------------------------ −36V to +0.3V
 PGNDO, BGND, PGNDS, PGNDH, AGND to GND ----------------------------------------------------------- −0.3V to +0.3V
 Power Dissipation, PD @ TA = 25°C
WQFN-56L 7x7 -------------------------------------------------------------------------------------------------------- 3.7W
 Package Thermal Resistance (Note 2)
WQFN-56L 7x7, θJA -------------------------------------------------------------------------------------------------- 27°C/W
WQFN-56L 7x7, θJC -------------------------------------------------------------------------------------------------- 7°C/W
 Junction Temperature ------------------------------------------------------------------------------------------------ 150°C
 Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------- 260°C
 Storage Temperature Range ---------------------------------------------------------------------------------------- −65°C to 150°C
 ESD Susceptibility (Note 3)
HBM (Human Body Model) ----------------------------------------------------------------------------------------- 2kV
MM (Machine Model) ------------------------------------------------------------------------------------------------- 200V

Recommended Operating Conditions (Note 4)


 Supply Input Voltage ------------------------------------------------------------------------------------------------- 9.6V to 15.4V
 Junction Temperature Range --------------------------------------------------------------------------------------- −40°C to 125°C
 Ambient Temperature Range --------------------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics
(VIN = 12V, GND = PGND = 0V, VCCT = 3.3V, VCCO = 1.8V, SVDD = 16.8V, VGH = 26V, VGL = −8V, VPRED = 6.5V, TA = 25°C,
unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
General
Supply Voltage VIN 9.6 12 15.4 V
VIN Under Voltage Rising VUVLO VIN rising 8.5 9 9.5 V
VIN Under Voltage Falling VIN falling 7.5 8 8.5 V
VIN Over Voltage
VIN_OVP VIN rising, hysteresis = 1.5V 18 18.5 19.5 V
Protection
VIN = 12V, all converters switching
IIN Quiescent Current IQVIN 10 15 20 mA
and no loading

Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

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9
RT6940
Parameter Symbol Test Conditions Min Typ Max Unit
VL Output Voltage VL 5% 5.2 5% V
VD Output Voltage VD 5% 7 5% V
Fault Detection
Fault Trigger Duration 40 50 60 ms
Thermal Shutdown OT Temperature rising -- 150 -- C
Thermal Shutdown
OT_Hys -- 30 -- C
Hysteresis
Open Drain Output (RST, BDP, ED_RST, NMOS_CON)
RST, BDP, ED_RST Output
Open drain (3.3V I/F), sink 10mA -- -- 0.4 V
Low Voltage
NMOS_CON Output Low
Open drain (3.3V I/F), sink 15mA -- -- 0.2 V
Voltage
Power on RST Delay Time tDLY6 After VGH 100%. 2 bits. 4 steps. 1 -- 7 ms
Logic Input (SDA, SCL, FLK1, FLK2, ES_ON, ED_MR)
High-level Input Voltage VIH 1.3 -- -- V
Low-level Input Voltage VIL -- -- 0.8 V
Except ED_MR (There is internal
pull high resistor on ED_MR). SDA,
Input Leakage Current 2 0.01 2 A
SCL, FLK1, FLK2, ES_ON
0V or 3.3V
Input Capacitance SDA, SCL -- 5 -- pF
SDA Output Low Voltage VACK ISDA = 6mA -- -- 0.45 V
I2C Timing Characteristics
SCL Frequency f SCL 1 -- 400 kHz
Bus Free Time Between
STOP and START tBUF 1.3 -- -- s
Conditions
Hold Time (Repeated)
tHD_STA 0.6 -- -- s
START Condition
SCL Pulse-Width Low tLOW 1.3 -- -- s
SCL Pulse-Width High tHIGH 0.6 -- -- s
Setup Time for a Repeated
tSU_STA 0.6 -- -- s
START Condition
Data Hold Time tHD_DAT 0 -- 800 ns
Data Setup Time tSU_DAT 100 -- -- ns
SDA and SCL Receiving 20 +
tR -- 300 ns
Rising Time 0.1CB
SDA and SCL Receiving 20 +
tF -- 300 ns
Falling Time 0.1CB
20 +
SDA Transmitting Fall Time tFF -- 250 ns
0.1CB

Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

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10
RT6940
Parameter Symbol Test Conditions Min Typ Max Unit
Setup Time for STOP
tSU_STO 0.6 -- -- s
Condition
Bus Capacitance CB -- -- 400 pF
Pulse width of Suppressed
tSP -- 85 -- ns
Spike
Internal Oscillator
SVDD Switching 2bits, 3 steps. 500kHz / 700kHz /
fOSC1 15% 700 15% kHz
Frequency 900kHz
2bits, 4 steps. f OSC1 x 1 / f OSC1 x fOSC1
VGH Switching Frequency fOSC2 15% 15% kHz
1.33 / fOSC1 x 1.66/ f OSC1 x 2 x 1.33
2bits, 4 steps. f OSC1 x 1 / f OSC1 x fOSC1
VGL Switching Frequency fOSC3 15% 15% kHz
1.33 / fOSC1 x 1.66/ f OSC1 x 2 x 1.33
VCCT Switching 1bits, 2 steps. fOSC1
fOSC4 15% 15% kHz
Frequency fOSC1 x 1 / fOSC1 x 2 x1
VCCO Switching 1bits, 2 steps. fOSC1
fOSC5 15% 15% kHz
Frequency fOSC1 x 1 / fOSC1 x 2 x2
SVDD Boost Converter (SVDD)
6 bits, 51 steps. SVDD > VIN +
Output Voltage Range VS_SVDD 15 -- 20 V
2.5V
Output Regulation SVDD No load, 2% error, default output 2 -- 2 %
6 bits, 51 steps. SVDD > VIN +
Output Resolution Reso_SVDD -- 0.1 -- V
2.5V
Maximum Duty Cycle DMAX_SVDD 81 90 99 %
Load Regulation 0 < ILOAD <1.5A 1 -- 1 %
Line Regulation VIN = 9.6V to 15.4V, ILOAD = 1.5A -- -- 0.4 %/V
SVDDI falling. After 10us, IC
Short Circuit Protection VSCP_SVDD restarts. If IC restarts 3 times, IC 15 20 25 %
shutdown.
SVDD falling. After 50ms, IC
Fault Trip Level VFT_SVDD 60 65 75 %
shutdown.
Over-Voltage Protection VOVP_SVDD SVDDI rising, hysteresis = 0.5V 20.5 21 22.5 V
SVDD–GND Discharging
RSVDD VIN = 5V -- 4.7 -- k
Resistance
Soft-Start Charge Current ISSS 20% 9.5 20% A
SSS charges external capacitor
Soft-Start Period tSS_SVDD 47nF from 0V to reference of 0.5 5 20 ms
SVDD.
Power on SVDD Delay time After VGL 100% 0.5 2 8 ms
External N-MOSFET Gate Driver (DRS of SVDD)
DRS High Voltage DRS_OH 4 7 9 V

DRS Low Voltage DRS_OL -- -- 0.3 V

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11
RT6940
Parameter Symbol Test Conditions Min Typ Max Unit
External NMOS Switch
VCSS_OCP 1 bit, 2 steps. 0.2V/0.4V 20% 0.2 20% V
Current Limit
DRS to VD High-Side
RDSON_DRSH 1 3 7 
On-Resistance
DRS to GND Low-Side
RDSON_DRSL 1 3 7 
On-Resistance
External Isolation P-MOSFET Switch (EGDS of SVDD)
EGDS Output High Voltage -- SVDDI -- V
SVDDI
EGDS Output Low Voltage -- -- V
5.8
EGDS Gate Pull High
-- 12 -- k
Resistor
EGDS Gate Sink Current IEGDS_SINK 4 10 20 A
When external isolation MOSFET
EGDS Soft Start time tSS_EXTGD -- 20 -- ms
Cgs = 47nF
VGH Boost Converter (VGH)
Output Voltage Range VS_VGH 5 bits, 21 steps. 22 -- 32 V
Output Regulation VGH No load, 3% error, default output 3 -- 3 %
Output Resolution Reso_VGH 5 bits, 21 steps. -- 0.5 -- V
Maximum Duty Cycle DMAX_VGH 81 90 99 %
Minimum On-Time tMOT_VGH 10 100 160 ns
Load Regulation 0 < ILOAD <0.1A. 1 -- 1 %
Line Regulation SVDD = 15V to 20V (ILOAD = 0.1A) -- -- 0.4 %/V
LXH Current Limit 1.5 2 -- A
Based on SVDD = 16V, VGH = 27V,
inductor = 10uH, FOSC2 = 1.4MHz,
ILOAD = 200mA / 300mA / 400mA /
LXH Current Limit for BDP 600 -- 1050 mA
500mA, BDP can be set ILXH to
detect 600mA / 750mA / 900mA /
1050mA
LXH Current Limit for BDP
2bits, 4 steps -- 150 -- mA
Resolution
VGH falling. After 10s, IC restarts.
Short Circuit Protection VSCP_VGH 15 20 25 %
If IC restarts 3 times, IC shutdown.
VGH falling. After 50ms, IC
Fault Trip Level VFT_VGH 60 65 70 %
shutdown.
Over-Voltage Protection VOVP_VGH VGH rising, hysteresis = 1.5V 34 35 36 V
LXH On-Resistance RDSON_LXH ILXH = 100mA 300 500 700 m
LXH Leakage Current ILK_LXH VLXH = 32V -- -- 10 A
VGH–GND Discharging
RVGH VIN = 5V 3 4.7 6 k
Resistance
Soft-Start Period tSS_VGH From SVDD to VGH 2 5 8 ms
Power on VGH Delay time After (SVDDI – EGDS) > 4.5V 0.5 2 7 ms

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12
RT6940
Parameter Symbol Test Conditions Min Typ Max Unit
ASync. Inverting Converter (VGL)
Output Voltage Range VS_VGL 5 bits, 19 steps 13 -- -4 V
Output Regulation VGL No load, 3% error, default output 3 -- 3 %
Output Resolution Reso_VGL 5 bits, 19 steps -- 0.5 -- V
Maximum Duty Cycle DMAX_VGL 81 90 99 %
Load Regulation 1mA < ILOAD < 0.1A 1 -- 1 %
Line Regulation VINL = 9.6V to 15.4V , ILOAD = 0.1A 1 -- 1 %
LXL Positive Current Limit 1.5 2 -- A
Based on VINL = 12V, VGL = -6V,
inductor = 10uH, FOSC3 = 1.4MHz,
LXL Positive Current Limit ILOAD = 200mA / 300mA / 400mA
450 -- 900 mA
for BDP / 500mA, BDP can be set ILXL to
detect 450mA / 600mA / 750mA /
900mA
LXL Positive Current Limit
2bits, 4 steps -- 150 -- mA
for BDP Resolution
VGL rising. After 10us, IC restarts.
Short Circuit Protection VSCP_VGL 1.6 1.3 1 V
If IC restarts 3 times, IC shutdown.
VGL rising. After 50ms, IC
Fault Trip Level VFT_VGL 63 70 77 %
shutdown.
Over-Voltage Protection VOVP_VGL VGL falling. Hysteresis = 0.5V 16 14 13.5 V
LXL High Side
RDSON_LXH ILXL = 100mA 300 550 800 m
On-Resistance
LXL Leakage current High ILK_LXLH VINL = 12V,VLXL = VGL -- -- 10 A
LXL Leakage current Low ILK_LXLL VINL = 12V,VLXL = 12V -- -- 10 A
VGL–GND Discharging
RVGL VIN = 5V 3 4.7 6.5 k
Resistance
Soft-Start Period tSS_VGL 2 5 8 ms
After VCCO 100%+2ms. 2 bits. 4
Power on VGL Delay Time tDLY4 1 -- 7 ms
steps.
ASync. Buck Converter (VCCT)
Output Voltage Range VS_VCCT 3 bits, 7 steps 3 -- 3.6 V
Output Regulation VCCT No load, 3% error, default output 3 -- 3 %
Output Resolution Reso_VCCT 3 bits, 7 steps -- 0.1 -- V
Maximum Duty Cycle DMAX_VCCT 81 90 99 %
Load Regulation 0 < ILOAD < 1A 1 -- 1 %
VINT = 9.6V to 15.4V , (ILOAD =
Line Regulation 1 -- 1 %
0.4A)
LXT Positive Current Limit 2 2.5 -- A
VCCT falling. After 10s, IC
Short Circuit Protection VSCP_VCCT restarts. If IC restarts 3 times, IC 15 20 25 %
shutdown.

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13
RT6940
Parameter Symbol Test Conditions Min Typ Max Unit
VCCT falling. After 50ms, IC
Fault Trip Level VFT_VCCT 60 65 70 %
shutdown.
VCCT rising , hysteresis = 0.1 x
Over-Voltage Protection VOVP_VCCT 115 120 125 %
VCCT
LXT High Side
RDSON_LXTH ILXT = 100mA 100 150 200 m
On-Resistance
VINT = 12V, VLXT = GND (CBT =
LXT Leakage current High ILK_LXTH -- -- 10 A
LXT)
LXT Leakage current Low ILK_LXTL VLXT = 12V (CBT = LXT) -- -- 10 A
VCCT–GND Discharging
RVCCT VIN = 5V 1.5 2.5 3.5 k
Resistance
Soft-Start Period tSS_VCCT 0.3 1 3 ms
Power on VCCT Delay After VIN UVLO + 1ms. 2 bits. 4
tDLY1 1 -- 7 ms
Time steps.
Sync. Buck Converter (VCCO)
4 bits, 14 steps. While VCCO is set
Output Voltage Range VS_VCCO to 2.8V, VCCT must be set larger 1.5 -- 2.8 V
than 3.3V.
Output Regulation VCCO No load, 2% error, default output 2 -- 2 %
Output Resolution Reso_VCCO 4 bits, 14 steps -- 0.1 -- V
Load Regulation 0 < ILOAD < 0.5A 1 -- 1 %
Line Regulation VCCT = 3V to 3.6V , (ILOAD = 0.4A) 1 -- 1 %
LXO Positive Current Limit 1.5 2 -- A
VCCO falling. After 10s, IC
Short Circuit Protection VSCP_VCCO restarts. If IC restarts 3 times, IC 15 20 25 %
shutdown.
VCCO falling. After 50ms, IC
Fault Trip Level VFT_VCCO 55 65 75 %
shutdown.
VCCO rising , hysteresis = 0.1 x
Over-Voltage Protection VOVP_VCCO 110 120 130 %
VCCO
LXO High Side
RDSON_LXOH ILXO = 200mA 50 120 170 m
On-Resistance
LXO Low Side
RDSON_LXOL ILXO = 200mA 50 120 170 m
On-Resistance
VINT = 12V, VCCT = 3.3V, VLXO =
LXO Leakage current High ILK_LXOH -- -- 10 A
GND
VINT = 12V, VCCT = 3.3V, VLXO =
LXO Leakage current Low ILK_LXOL -- -- 10 A
3.3V
VCCO–GND Discharging
RVCCO VIN = 5V 1.5 2.5 3.5 k
Resistance
Soft-Start Period tSS_VCCO 0.3 1 3 ms
Power on VCCO Delay
tDLY3 After VCCT 100%. 2 bits. 4 steps. 1 -- 7 ms
Time

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14
RT6940
Parameter Symbol Test Conditions Min Typ Max Unit
OP-Amp (VPRED)
Output Voltage Range VS_VPRED 3 bits, 8 steps 3 -- 6.5 V
Output Regulation VPRED No load, +-2% error, default output 2 -- 2 %
Output Resolution Reso_VPRED 3 bits, 8 steps -- 0.5 -- V
Short-Circuit Current IVPRED_SC -- ±300 -- mA
VPRED falling. After 10s, IC
Short Circuit Protection VSCP_VPRED restarts. If IC restarts 3 times, IC 15 20 25 %
shutdown.
Slew Rate SR_VPRED -- 30 -- V/us
Gate Pulse Modulation (GPM1, GPM2)
Adjustable GPM Stop 10xVR
-- -- V
Voltage Level G
VGH-GPMx On-Resistance RDSON_GPMH VGH = 27V/-20mA at FLKx = High 1.5 2.5 3.75 
GPMx-REx On-Resistance RDSON_GPML VGH = 27V/+20mA at FLKx = Low 1.5 2.5 3.75 
FLK Frequency -- -- 400 kHz
FLKx to GPMx Rising
tPGPMLH -- 100 200 ns
Propagation Delay
FLKx to GPMx Falling
tPGPMHL -- 100 450 ns
Propagation Delay
External REx-GND
80 -- -- 
Resistance
EVDD Voltage Detector
Reference Voltage of
VED_REF 5% 1.2V 5% V
EVDD
EVDD Comparator
ED_SNS falling -- 100 -- mV
Hysteresis
ED_MR Pull High
RED_MR Pull high to VCCT 7 10 13 k
Resistance
BDP Comparator
BDP_REF Range of BDP
BDP_REF 1 -- 4 V
Comparator
BDP Comparator While BDP_REF = 2.5V, BDP_SNS
30 100 250 mV
Hysteresis falling hysteresis

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-
thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the
exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.

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15
RT6940
Typical Operating Characteristics
SVDD Efficiency vs. Load Current VCCT Efficiency vs. Load Current
100 100
90 90
80 80
70 70
Efficiency (%)

Efficiency (%)
60 60
50 50
40 40
30 30
20 20
10 10
VIN = 12V, VSVDD = 16.8V, f = 700kHz VIN = 12V, VVCCT = 3.3V, f = 700kHz x 2
0 0
0 0.5 1 1.5 2 2.5 3 0 0.2 0.4 0.6 0.8 1
Load Current (A) Load Current (A)

VCCO Efficiency vs. Load Current VGH Efficiency vs. Load Current
100 100

90 90

80 80
70 70
Efficiency (%)
Efficiency (%)

60 60

50 50

40 40

30 30
20 20

10 VIN = 12V, VCCT = 3.3V, 10


VVCCO = 1.8V, f = 700kHz x 2 VSVDD = 16.8V, VGH = 26V, f = 700kHz x 1.33
0 0
0 0.2 0.4 0.6 0.8 1 0 0.1 0.2 0.3 0.4 0.5
Load Current (A) Load Current (A)

VGL Efficiency vs. Load Current VCCT Voltage vs. Load Current
100 3.6
90
3.5
80
VCCT Voltage (V)

70
Efficiency (%)

3.4
60
50 3.3
40
3.2
30
20
3.1
10
VIN = 12V, VGL = −8V, f = 700kHz x 1.33 VIN = 12V, VVCCT = 3.3V, f = 700kHz x 2
0 3.0
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5 0.6
Load Current (A) Load Current (A)

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16
RT6940

VCCO Voltage vs. Load Current SVDD Voltage vs. Load Current
2.2 20

2.1 19

2.0 18
VCCO Voltage (V)

SVDD Voltage (V)


1.9 17

1.8 16

1.7 15

1.6 14

1.5 VIN = 12V, VCCT = 3.3V, 13


VVCCO = 1.8V, f = 700kHz x 2 VIN = 12V, VSVDD = 16.8V, f = 700kHz
1.4 12
0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6
Load Current (A) Load Current (A)

VGH Voltage vs. Load Current VGL Voltage vs. Load Current
30 -5

29
-6
28
VGH Voltage (V)

VGL Voltage (V)

-7
27

26 -8

25
-9
24
-10
23
VSVDD = 16.8V, VGH = 26V, f = 700kHz x 1.33 VIN = 12V, VGL = −8V, f = 700kHz x 1.33
22 -11
0 0.05 0.1 0.15 0.2 0.25 0.3 0 0.05 0.1 0.15 0.2 0.25 0.3
Load Current (A) Load Current (A)

VCCT Voltage vs. Input Voltage VCCO Voltage vs. Input Voltage
3.6 2.2

2.1
3.5
2.0
VCCT Voltage (V)

VCCO Voltage (V)

3.4
1.9

3.3 1.8

1.7
3.2
1.6
3.1
1.5
VVCCT = 3.3V, Load = 0.5A VVCCO = 1.8V, Load = 0.5A
3 1.4
9.6 10.4 11.2 12 12.8 13.6 14.4 15.2 16 3 3.1 3.2 3.3 3.4 3.5 3.6
Input Voltage (V) Input Voltage (V)

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17
RT6940

SVDD Voltage vs. Input Voltage VGH Voltage vs. Input Voltage
20 30

19 29

18 28
SVDD Voltage (V)

VGH Voltage (V)


17 27

16 26

15 25

14 24

13 23
VSVDD = 16.8V, Load = 1.5A VGH = 26V, Load = 0.3A
12 22
9.6 10.4 11.2 12 12.8 13.6 14.4 15.2 16 15 16 17 18 19 20
Input Voltage (V) Input Voltage (V)

VGL Voltage vs. Input Voltage VCCT Voltage vs. Temperature


-5 3.6

-6 3.5
VCCT Voltage (V)
VGL Voltage (V)

-7 3.4

-8 3.3

-9 3.2

-10 3.1

VGL = −8V, Load = 0.3A VIN = 12V, VVCCT = 3.3V


-11 3
9.6 10.4 11.2 12 12.8 13.6 14.4 15.2 16 -50 -25 0 25 50 75 100 125
Input Voltage (V) Temperature (°C)

VCCO Voltage vs. Temperature SVDD Voltage vs. Temperature


2.1 20

2.0 19
SVDD Voltage (V)
VCCO Voltage (V)

1.9 18

1.8 17

1.7 16

1.6 15

VIN = 12V, VCCT = 3.3V, VVCCO = 1.8V VIN = 12V, VSVDD = 16.8V
1.5 14
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

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18
RT6940

VGH Voltage vs. Temperature VGL Voltage vs. Temperature


30 -4

29 -5

28 -6
VGH Voltage (V)

VGL Voltage (V)


27 -7

26 -8

25 -9

24 -10

23 -11
VSVDD = 16.8V, VGH = 26V VIN = 12V, VGL = −8V
22 -12
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

VL Voltage vs. Temperature Quiescent Current vs. Temperature


8 30

7 25
Quiescent Current (mA)
VL Voltage (V)

6 20

5 15

4 10

3 5

VIN = 12V, VVL = 5V VIN = 12V


2 0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)
VVCCO = 1.8V, VVGH = 26V, VVGL = −8V, ISVDD = 1.5A,

VVCCO = 1.8V, VVGH = 26V, VVGL = −8V, ISVDD = 1.5A,


Power On Power Off
IVCCT = 0.5A, IVCCO = 0.5A, IVGH = 0.3A, IVGL = 0.3A

IVCCT = 0.5A, IVCCO = 0.5A, IVGH = 0.3A, IVGL = 0.3A


VIN VIN
(5V/Div) V IN V IN
(5V/Div)
VVCCT
V VCCT VVCCT V VCCT
VIN = 12V, VSVDD = 16.8V, VVCCT = 3.3V,

VIN = 12V, VSVDD = 16.8V, VVCCT = 3.3V,

(2V/Div) (2V/Div)
V VCCO V VCCO
VVCCO
V VCCO
(2V/Div) IIN (2V/Div)
I IN I IN
(1A/Div) VVGL (1A/Div) IIN
VVGH VVGH VVGH
VVGL
(5V/Div) (10V/Div) VVGL
VVGH VVGL
(10V/Div) VSVDD (5V/Div) VSVDD
VSVDD VSVDD
(10V/Div) (10V/Div)

Time (10ms/Div) Time (10ms/Div)

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19
RT6940

VCCT Load Transient VCCO Load Transient


VIN =12V, VVCCT = 3.3V, L1 = 2.2μH, VIN =12V, VVCCT = 3.3V, VVCCO = 1.8V,
R1 = 100k, C4 = 220pF L2 = 2.2μH, R2 = 100k, C6 = 220pF

VVCCT VVCCO
(200mV/Div) (200mV/Div)

ILOAD ILOAD
(500mA/Div) (500mA/Div)

Time (500μs/Div) Time (500μs/Div)

SVDD Load Transient VGH Load Transient


VIN =12V, VSVDD = 16.8V, VIN =12V, VSVDD = 16.8V, VGH = 26V,
L5 = 6.8μH, R12 = 100k, C12 = 1nF L4 = 10μH, R13 = 100k, C13 = 1nF

VSVDD VVGH
(200mV/Div) (500mV/Div)

ILOAD ILOAD
(500mA/Div) (500mA/Div)

Time (500μs/Div) Time (500μs/Div)

VGL Load Transient


VIN =12V, VGL = −8V,
L3 = 10μH, R11 = 270k, C11 = 180pF

VVGL
(200mV/Div)

ILOAD
(500mA/Div)

Time (500μs/Div)

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20
RT6940
I2C Command
Slave Address (PMIC)
7 6 5 4 3 2 1 0 = LSB
1 0 1 0 1 0 0 R/ W

Write Command
(a) Write single byte of data to Register
Slave Address Register Address Data From Master
Slave Slave Slave
Start 1 0 1 0 1 0 0 0 ACK
0 0 0 0 0 R2 R1 R0 ACK
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Stop

(b) Write multiple bytes of data to Registers

Slave Address Register Address nth nth Data From Master


Slave Slave
Start 1 0 1 0 1 0 0 0 ACK
0 0 0 0 0 R2 R1 R0 ACK
D7 D6 D5 D4 D3 D2 D1 D0 Slave
ACK

(n+1)th Data From Master Last Data From Master


Slave Slave
D7 D6 D5 D4 D3 D2 D1 D0 ACK
D7 D6 D5 D4 D3 D2 D1 D0 ACK Stop

(c) Write All Registers into EEPROM


Slave Address Register Address Data From Master
Slave Slave Slave
Start 1 0 1 0 1 0 0 0 ACK
1 1 1 1 1 1 1 1 ACK
1 0 0 0 0 0 0 0 ACK
Stop

Read Command
(a) Read single byte of data from Register
Slave Address Register Address Data From Master
Slave Slave Slave
Start 1 0 1 0 1 0 0 0 ACK
1 1 1 1 1 1 1 1 ACK
0 0 0 0 0 0 0 0 ACK
Stop

Slave Address Register Address


Slave Slave
Start 1 0 1 0 1 0 0 0 ACK
0 0 0 0 0 R2 R1 R0 ACK

Slave Address Data From RT6940


Re- Slave Master
start
1 0 1 0 1 0 0 1 ACK
D7 D6 D5 D4 D3 D2 D1 D0 NACK
Stop

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21
RT6940
(b) Read multiple bytes of data from Registers

Slave Address Register Address Data From Master

Start 1 0 1 0 1 0 0 0 Slave 1 1 1 1 1 1 1 1 Slave


0 0 0 0 0 0 0 0 Slave
Stop
ACK ACK ACK

Slave Address Register Address


Slave Slave
Start 1 0 1 0 1 0 0 0 ACK
0 0 0 0 0 R2 R1 R0 ACK

Slave Address n th Data From RT 6940 Last Data From RT6940


Re- Slave Master Master
start
1 0 1 0 1 0 0 1 ACK
D7 D6 D5 D4 D3 D2 D1 D0 NACK D7 D6 D5 D4 D3 D2 D1 D0 NACK
Stop

(c) Read data from EEPROM


Slave Address Register Address Data From Master
Slave Slave Slave
Start 1 0 1 0 1 0 0 0 ACK
1 1 1 1 1 1 1 1 ACK
0 0 0 0 0 0 0 1 ACK
Stop

Slave Address Register Address


Slave Slave
Start 1 0 1 0 1 0 0 0 ACK
0 0 0 0 0 R2 R1 R0 ACK

Slave Address Data From RT6940


Re- Slave Master
start
1 0 1 0 1 0 0 1 ACK
D7 D6 D5 D4 D3 D2 D1 D0 NACK
Stop

(d) Read multiple bytes of data from EEPROM

Slave Address Register Address Data From Master

Start 1 0 1 0 1 0 0 0 Slave 1 1 1 1 1 1 1 1 Slave


0 0 0 0 0 0 0 1 Slave
Stop
ACK ACK ACK

Slave Address Register Address


Slave Slave
Start 1 0 1 0 1 0 0 0 ACK
0 0 0 0 0 R2 R1 R0 ACK

Slave Address n th Data From RT 6940 Last Data From RT6940


Re- Slave Master Master
start
1 0 1 0 1 0 0 1 ACK
D7 D6 D5 D4 D3 D2 D1 D0 NACK D7 D6 D5 D4 D3 D2 D1 D0 NACK
Stop

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22
RT6940
Register Map
Factor
Volatile/
Name Function Address
(Power-Up MSB LSB
Nonvolatile
Default)
SVDD Current 1bit
SVDD_CS 0 X X X X X X X
Sense Nonvolatile
BDP COMP 1bit
COMP OFF 0x00h 52h X 1 X X X X X X
ON/OFF Nonvolatile
6bit
SVDD SVDD Output X X 0 1 0 0 1 0
Nonvolatile
T1 Delay 2bit
T1 0 0 X X X X X X
Time Nonvolatile
T3 Delay 2bit
T3 0x01h 08h X X X X 1 0 X X
Time Nonvolatile
T4 Delay 2bit
T4 X X X X X X 0 0
Time Nonvolatile
T6 Delay 2bit
T6 0 0 X X X X X X
Time Nonvolatile
SVDD SW 2bit
FREQ X X 0 1 X X X X
Frequency Nonvolatile
0x02h 15h
VGH SW 2bit
FREQH X X X X 0 1 X X
Frequency Nonvolatile
VGL SW 2bit
FREQL X X X X X X 0 1
Frequency Nonvolatile
Channel
5bit
DSC_On_Off Discharge 1 1 1 1 1 X X X
Nonvolatile
Enable
VCCO SW 1bit
FREQVCCO X X X X X 1 X X
Frequency 0x03h Nonvolatile FFh
VCCT SW 1bit
FREQVCCT X X X X X X 1 X
Frequency Nonvolatile
VPRED 1bit
OP-Amp_OFF X X X X X X X 1
Enable Nonvolatile
4bit
VCCO1.8 VCCO Output 0 0 1 1 X X X X
Nonvolatile
3bit
VCCT3.3 VCCT Output 0x04h 37h X X X X 0 1 1 X
Nonvolatile
VGHVGL BDP VGHVGL 1bit
X X X X X X X 1
OFF BDP ON/OFF Nonvolatile
VPRED 3bit
VPRED 1 1 1 X X X X X
Output Nonvolatile
VPRED Mode 1bit
VPRED_Mode X X X 1 X X X X
Select Nonvolatile
0x05h FAh
VGL_BDP 2bit
VGL_BDP X X X X 1 0 X X
Level Nonvolatile
VGH_BDP 2bit
VGH_BDP X X X X X X 1 0
Level Nonvolatile

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23
RT6940
Factor
Volatile/
Name Function Address (Power-Up MSB LSB
Nonvolatile
Default)
BDP Start 3bit
BDP_STR 0 0 1 X X X X X
Delay Time Nonvolatile
0x06h 28h
5bit
VGH VGH Output X X X 0 1 0 0 0
Nonvolatile
BDP End 3bit
BDP_END 1 0 1 X X X X X
Delay Time Nonvolatile
0x07h A8h
5bit
VGL VGL Output X X X 0 1 0 0 0
Nonvolatile
Control EE
CR 0xFFh Volatile -- WED X X X X X X
Register (DR)

Note : CR Data
00h : Read data from DAC register (DR).
01h : Read data from EEPROM.
80h : Write all DAC register (DR) into EEPROM.

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24
RT6940
Output Table
Register Code SVDD VGH VGL VCCT VCCO VPRED
00h 15 22 -4 3 1.5 3
01h 15.1 22.5 -4.5 3.1 1.6 3.5
02h 15.2 23 -5 3.2 1.7 4
03h 15.3 23.5 -5.5 3.3 1.8 4.5
04h 15.4 24 -6 3.4 1.9 5
05h 15.5 24.5 -6.5 3.5 2 5.5
06h 15.6 25 -7 2.1 6
3.6
07h 15.7 25.5 -7.5 2.2 6.5
08h 15.8 26 -8 2.3
09h 15.9 26.5 -8.5 2.4
0Ah 16 27 -9 2.5
0Bh 16.1 27.5 -9.5 2.6
0Ch 16.2 28 -10 2.7
0Dh 16.3 28.5 -10.5
0Eh 16.4 29 -11 2.8
0Fh 16.5 29.5 -11.5
10h 16.6 30 -12
11h 16.7 30.5 -12.5
12h 16.8 31
13h 16.9 31.5
14h 17
15h 17.1
16h 17.2
17h 17.3
18h 17.4
-13
19h 17.5
32
1Ah 17.6
1Bh 17.7
1Ch 17.8
1Dh 17.9
1Eh 18
1Fh 18.1

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25
RT6940
Register Code SVDD VGH VGL VCCT VCCO VPRED
20h 18.2
21h 18.3
22h 18.4
23h 18.5
24h 18.6
25h 18.7
26h 18.8
27h 18.9
28h 19
29h 19.1
2Ah 19.2
2Bh 19.3
2Ch 19.4
2Dh 19.5
2Eh 19.6
2Fh 19.7
30h 19.8
31h 19.9
32h
33h
34h
35h
36h
37h
38h
20
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh

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26
RT6940
Address : 00
Factor
Volatile/
Name Function (Power-Up MSB
Address LSB
Nonvolatile
Default)
SVDD Current 1bit
SVDD_CS 0 X X X X X X X
Sense Nonvolatile
COMP BDP COMP 1bit
0x00h 52h X 1 X X X X X X
OFF ON/OFF Nonvolatile
6bit
SVDD SVDD Output X X 0 1 0 0 1 0
Nonvolatile

SVDD Current Sense Setting


00h x <7>
 Data Function
0 0.2
1 0.4

BDP COMP ON/OFF Setting


00h x <6>
 Data Function
0 OFF
1 ON

Address : 01
Factor
Volatile/
Name Function Address (Power-Up MSB LSB
Nonvolatile
Default)
T1 Delay 2bit
T1 0 0 X X X X X X
Time Nonvolatile
T3 Delay 2bit
T3 0x01h 08h X X X X 1 0 X X
Time Nonvolatile
T4 Delay 2bit
T4 X X X X X X 0 0
Time Nonvolatile

T1 Delay Time Setting T4 Delay Time Setting


01h x <7:6> 01h x <1:0>
 Data Function  Data Function
0 1ms 0 1ms
1 3ms 1 3ms
2 5ms 2 5ms
3 7ms 3 7ms

T3 Delay Time Setting


01h x <3:2>
 Data Function
0 1ms
1 3ms
2 5ms
3 7ms

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27
RT6940
Address : 02
Factor
Volatile/
Name Function Address (Power-Up MSB LSB
Nonvolatile
Default)
T6 Delay 2bit
T6 0 0 X X X X X X
Time Nonvolatile

SVDD SW 2bit
FREQ X X 0 1 X X X X
Frequency Nonvolatile
0x02h 15h
VGH SW 2bit
FREQH X X X X 0 1 X X
Frequency Nonvolatile

VGL SW 2bit
FREQL X X X X X X 0 1
Frequency Nonvolatile

T6 Delay Time Setting


02h x <7:6>
 Data Function
0 1ms
1 3ms
2 5ms
3 7ms

SVDD SW Frequency Setting


02h x <5:4>
 Data Switching Frequency
0 500KHz
1 700KHz
2 900KHz
3 900KHz

VGH SW Frequency Setting


02h x <3:2>
 Data Switching Frequency
0 SVDD Frequency *1
1 SVDD Frequency *1.33
2 SVDD Frequency *1.66
3 SVDD Frequency *2

VGL SW Frequency Setting


02h x <1:0>
 Data Switching Frequency
0 SVDD Frequency *1
1 SVDD Frequency *1.33
2 SVDD Frequency *1.66
3 SVDD Frequency *2

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28
RT6940
Address : 03
Factor
Volatile/
Name Function Address (Power-Up MSB LSB
Nonvolatile
Default)
Channel
5bit
DSC_On_Off Discharge 1 1 1 1 1 X X X
Nonvolatile
Enable
VCCO SW 1bit
FREQVCCO X X X X X 1 X X
Frequency Nonvolatile
0x03h FFh
VCCT SW 1bit
FREQVCCT X X X X X X 1 X
Frequency Nonvolatile

VPRED 1bit
OP-Amp_OFF X X X X X X X 1
Enable Nonvolatile

Channels Discharge Enable (Low:No Discharge, High:Dicharge) Setting


03h x <7:3>
 Data Function
0 ALL_OFF
1 SVDD
2 VGH
4 VGL
8 VCCT
16 VCCO

VCCO SW Frequency Setting


03h x <2>
 Data Function
0 SVDD Frequency *1
1 SVDD Frequency *2

VCCT SW Frequency Setting


03h x <1>
 Data Function
0 SVDD Frequency *1
1 SVDD Frequency *2

VPRED Enable Setting


03h x <0>
 Data Function
0 OFF
1 ON

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RT6940
Address : 04
Factor
Volatile/
Name Function Address (Power-Up MSB LSB
Nonvolatile
Default)
VCCO 4bit
VCCO1.8 0 0 1 1 X X X X
Output Nonvolatile
VCCT 3bit
VCCT3.3 X X X X 0 1 1 X
Output 0x04h Nonvolatile 37h
VGHVGL
VGHVGL 1bit
BDP X X X X X X X 1
BDP OFF Nonvolatile
ON/OFF

VGHVGL BDP ON/OFF Setting


04h x <0>
 Data Function
0 OFF
1 ON

Address : 05
Factor
Volatile/
Name Function Address (Power-Up MSB LSB
Nonvolatile
Default)
VPRED 3bit
VPRED 1 1 1 X X X X X
Output Nonvolatile
VPRED
1bit
VPRED_Mode Mode X X X 1 X X X X
Nonvolatile
Select
0x05h FAh
VGL BDP 2bit
VGL_BDP X X X X 1 0 X X
Level Nonvolatile
VGH BDP 2bit
VGH_BDP X X X X X X 1 0
Level Nonvolatile

VPRED Mode Select VGH BDP Level Setting


05h x <4> 05h x <1:0>
 Data Function  Data Slew Rate
0 CASE1 0 600mA
1 CASE2 1 750mA
2 900mA
VGL BDP Level Setting 3 1050mA
05h x <3:2>
 Data Function
0 450mA
1 600mA
2 750mA
3 900mA

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RT6940
Address : 06
Factor
Volatile/
Name Function Address (Power-Up MSB LSB
Nonvolatile
Default)
BDP Start 3bit
BDP_STR 0 0 1 X X X X X
Delay Time Nonvolatile
0x06h 28h
VGH 5bit
VGH X X X 0 1 0 0 0
Output Nonvolatile

BDP Start Delay Time Setting


06h x <7:5>
 Data Function
0 0ms
1 10ms
2 20ms
3 30ms
4 40ms
5 50ms
6 50ms
7 50ms

Address : 07
Factor
Volatile/
Name Function Address (Power-Up MSB LSB
Nonvolatile
Default)
BDP End 3bit
BDP_END 1 0 1 X X X X X
Delay Time Nonvolatile
0x07h A8h
VGL 5bit
VGL X X X 0 1 0 0 0
Output Nonvolatile

BDP End Delay Setting


07h x <7:5>
 Data Function
0 0ms
1 45ms
2 75ms
3 120ms
4 150ms
5 300ms
6 300ms
7 300ms

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RT6940
Protection Function
Work
Block Protection Action Remark
Condition
Cycle by cycle limit.
OCP 2.0A(min) LXT peak current > 2.0A, LXT stops switching. Auto recovery
LXT peak current < 2.0A, LXT resumes switching
VCCT > 120%, LXT stops switching.
OVP VCCT > 120% Auto recovery
VCCT < 110%, LXT resumes switching.
VCCT
VCCT < 65%, Release < VIN
UVP After 50ms, all channels shut down.
Freq Freq/2 UVLO
After 10us, all channels shut down.
Release < VIN
SCP VCCT < 20% After shutdown 50ms, restarts all channels.
UVLO
IC maintains shutdown state after IC restarts 3 times.
Cycle by cycle limit.
OCP 1.5A(min) LXO peak current > 1.5A, LXO stops switching. Auto recovery
LXO peak current < 1.5A, LXO resumes switching
VCCO > 120%, LXO stops switching.
OVP VCCO > 120% Auto recovery
VCCO < 110%, LXO resumes switching.
VCCO
Release < VIN
UVP VCCO < 65% After 50ms, all channels shut down.
UVLO
After 10us, all channels shut down.
Release < VIN
SCP VCCO < 20% After shutdown 50ms, restarts all channels.
UVLO
IC maintains shutdown state after IC restarts 3 times.
Cycle by cycle limit.
CSS peak current > 0.2V/RCS, DRS stops switching.
OCP CSS=0.2V/0.4V Auto recovery
CSS peak current < 0.2V/RCS, DRS resumes
switching
SVDDI > 21V, DRS stops switching.
OVP SVDDI > 21V Auto recovery
SVDD SVDDI < 20.5V, DRS resumes switching.
Release < VIN
UVP SVDD < 65% After 50ms, all channels shut down.
UVLO
After 10us, all channels shut down.
Release < VIN
SCP SVDDI < 20% After shutdown 50ms, restarts all channels.
UVLO
IC maintains shutdown state after IC restarts 3 times.
Cycle by cycle limit.
OCP 1.5A(min) LXH peak current > 1.5A, LXH stops switching. Auto recovery
LXH peak current < 1.5A, LXH resumes switching
600mA/750mA/ LXH peak current > BDP setting current after 1ms,
BDP Release < POR
900mA/1050mA BDP out latched high.

VGH VGH > 35.0V, LXH stops switching.


OVP VGH > 35V Auto recovery
VGH < 33.5V, LXH resumes switching.
Release < VIN
UVP VGH < 65% After 50ms, all channels shut down.
UVLO
After 10us, all channels shut down.
Release < VIN
SCP VGH < 20% After shutdown 50ms, restarts all channels.
UVLO
IC maintains shutdown state after IC restarts 3 times.

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32
RT6940
Work
Block Protection Action Remark
Condition
Cycle by cycle limit.
OCP 1.5A(min) LXL peak current > 1.5A, LXL stops switching. Auto recovery
LXL peak current < 1.5A, LXL resumes switching
450mA/600mA/ LXL peak current > BDP setting current after 1ms,
BDP Release < POR
750mA/900mA BDP out latched high.
VGL < -14.0V, LXL stops switching.
VGL OVP VGL < -14V Auto recovery
VGL > -13.5V, LXL resumes switching.
Release < VIN
UVP VGL < 65% After 50ms, all channels shut down.
UVLO
After 10us, all channels shut down.
Release < VIN
SCP VGL > -1.3V After shutdown 50ms, restarts all channels.
UVLO
IC maintains shutdown state after IC restarts 3 times.
OCP ±300mA Continuously limit Auto recovery

VPRED After 10us, all channels shut down.


Release < VIN
SCP VPRED < 20% After shutdown 50ms, restarts all channels.
UVLO
IC maintains shutdown state after IC restarts 3 times.
VGHM < 20%, Release < VIN
All channels shut down after FLK switches 8 times.
FLK switching UVLO
GPM SCP
VGHM < 20%, Release < VIN
All channels shut down after FLK keeps high 16us.
FLK keeps high UVLO

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RT6940
Application Information
The RT6940 is an I2C interface programmable power Soft-Start Function
management IC. Main function includes one SVDD Boost All channels has soft-start function to reduce input rush
converter, one VGH boost converter, one Async-Buck current such that the switching duty is increased linearly.
converter, one Sync- Buck converter, one VGL negative As a result, all channels rises up smoothly while the input
inverting converter, one VPRED OP- amplifier and BDP current stays limited for the entire soft-start interval.
compactor. This device is suitable for OLED TV panels.
SVDD Boost Converter
All channels of converters can be used to program such
as output voltage, switching frequency of converter, delay SVDD channel is the asynchronous Boost converter with
time, BDP COMP selection, VPRED mode selection, a current mode topology and fixed frequency operation.
Current sense selection of SVDD, VGH BDP level Moreover, user can adjust switching frequency by register
selection, VGL BDP level selection and discharge function address 02h respectively. The Boost converter can operate
of SVDD/VGH/VGL/VCCT/VCCO. in either Continuous Conduction Mode (CCM) or
Discontinuous Conduction Mode (DCM), depending on
After VIN voltage rises above UVLO rising threshold, the
the load current to gain optimum efficiency and minimum
IC will download data from MTP to set the initial
output ripple. It performs fast transient responses to
parameters of RT6940. After MTP data download are
generate source driver supplies for OLED display. The high
finished, all channels will start soft-start procedure
operation frequency allows use of smaller components to
individually.
minimize the thickness of the OLED panel.
Under-Voltage Lockout
SVDD Boost Output Voltage Setting
The UVLO circuit divides the input voltage from VIN pin
An SVDD asynchronous Boost converter has the I2C
with the UVLO threshold (9V rising, typ.) to ensure that
adjustable output voltage from 15V to 20V in 0.1V
the input voltage is high enough for reliable operation.
increments. The default SVDD voltage is 16.8V. User can
The 1V (typ.) hysteresis of UVLO prevents shutdown
control the SVDD output voltage by register address 00h
caused by supply transients. Once the input voltage
respectively.
exceeds the UVLO rising threshold, start-up begins. When
the input voltage falls below the UVLO falling threshold, SVDD Boost Over-Voltage Protection
all IC internal functions will be turned off by the controller. The SVDD Boost converter has an over-voltage protection
to protect the SVDD switch at the SVDDI pin. When the
Over-Temperature Protection
SVDDI pin voltage rises above 21V (typ.), the Boost
The RT6940 equips an Over-Temperature Protection (OTP)
converter turns the MOSFET switch off. As soon as the
circuitry to prevent overheating due to excessive power
output voltage falls below the over-voltage threshold, the
dissipation. The OTP will shut down switching operation
converter will resume operation.
when junction temperature exceeds 150°C. Once the
junction temperature cools down by approximately 30°C, SVDD Boost Over-Current Protection
the main converter will resume operation. To maintain The SVDD can limit the peak current to achieve over-current
continuous operation maximum, the junction temperature protection. The IC senses the inductor current that is
should be prevented from rising above 120°C. flowing into the CSS sense resistor during an ON period.
The external N-MOSFET will be turned off if CSS pin
Fast Discharge Function
voltage reaches 0.2V (typ.).
The SVDD, VGH, VCCT, VCCO and VGL channels
embedded discharge function to discharge the remaining
output to 0V rapidly, preventing phenomena such as
residual image on the display during shutdown.
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34
RT6940
If inductor current peak reaches current limit, the SVDD VGH Boost Over-Voltage Protection
channel will be keep current limit level. The VGH Boost converter has an over-voltage protection
to protect the VGH switch at LXH pin in case the feedback
SVDD Boost Short-Circuit Protection
(VGH) pin is floating. When the VGH pin voltage reaches
The SVDD has an advanced short-circuit protection 35V (typ.), the VGH Boost converter turns off the N-
mechanism which prevents the device from damage by MOSFET switch. As soon as the output voltage falls below
unexpected applications. An error condition is detected if the over voltage threshold, the converter will resume
the voltage on the converter's SVDD pin remains below operation.
SVDD x 20% for longer than 10μs, IC will be shut down
and then restart three times. If the failure information is VGH Boost Over-Current Protection
still not released, the chip will be shutdown. Once shut The VGH inductor current is flowing into the LXH pin. When
down, the boost converter can only be enabled after the peak inductor current reaches current limit 1.5A (min.).The
chip is powered on again. internal N-MOSFET will be turned off, forcing inductor
current to leave charging state and enter discharging state,
SVDD Boost Fault Protection
Therefore, the inductor current can be kept below current
The SVDD Boost converter has a fault protection, if SVDD limit. The output current at the current limit boundary,
pin voltage is detected to be below SVDD x 65% for longer denoted as IOUT(LIM), can be calculated according to the
than 50ms. The SVDD, VGH, VGL, VCCT and VCCO will following equation :
be shut down. Once the SVDD shuts down, the Boost
converter can only be enabled after the chip is powered VIN  VIN   VOUT  VIN  t S 
IOUTLIM  η    ILIM  1   
on again. VOUT  2 VOUT L
 

VGH Boost Converter where η is the efficiency of the Boost converter, ILIM is the
VGH channel is the asynchronous Boost converter with a value of the current limit and tS is the switching period. If
current mode topology and fixed frequency operation. inductor current peak reaches current limit, the SVDD
Moreover, user can adjust switching frequency by register channel will be keep current limit level.
address 02h respectively. The Boost converter can operate
VGH Boost Short-Circuit Protection
in either Continuous Conduction Mode (CCM) or
Discontinuous Conduction Mode (DCM), depending on The VGH has an advanced short-circuit protection
the load current to gain optimum efficiency and minimum mechanism which prevents the device from damage by
output ripple. It performs fast transient responses to unexpected applications. An error condition is detected if
generate source driver supplies for OLED display. The high the voltage on the converter's VGH pin remains below VGH
operation frequency allows use of smaller components to x 20% for longer than 10μs, IC will be shut down and then
minimize the thickness of the OLED panel restart three times. If the failure information is still not
released, the chip will be shutdown. Once shut down, the
VGH Boost Output Voltage Setting boost converter can only be enabled after the chip is
A VGH asynchronous Boost converter has the I 2 C powered on again.
adjustable output voltage from 22V to 32V in 0.5V
VGH Boost Fault Protection
increments. The default VGH voltage is 26V. User can
control the VGH output voltage by register address 06h The VGH Boost converter has a fault protection function,
respectively. if VGH pin is detected to be below VGH x 65% for longer
than 50ms. The SVDD, VGH, VGL, VCCT and VCCO will
be shut down. Once the SVDD shuts down, the Boost
converter can only be enabled after the chip is powered
on again.

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RT6940
Boost Converter Inductor Selection requirement. Note that the voltage rating of the input
The inductance depends on the maximum input current. capacitor must be greater than the maximum input voltage.
As a general rule, the inductor ripple current range is 20%
Boost Converter Output Capacitor Selection
to 40% of the maximum input current. If 40% is selected
as an example, the inductor ripple current can be The output ripple voltage is an important index for
calculated according to the following equations : estimating chip performance. This portion consists of two
parts. One is the product of with the ESR of the output
VOUT  IOUT MAX  capacitor, while the other part is formed by the charging
IINMAX  
η  VIN and discharging process of the output capacitor. As shown
IRIPPLE = 0.4 x IIN(MAX) in following figure, ΔVOUT1 can be evaluated based on the
ideal energy equalization. According to the definition of
where η is the efficiency of the Boost converter, IIN(MAX) is
Q, the Q value can be calculated as the following equation:
the maximum input current, and IRIPPLE is the inductor
ripple current. The input peak current can then be obtained  
Q  1   IIN  1 ∆IL  IOUT    IIN  1 ∆IL  IOUT  
by adding the maximum input current with half of the 2  2   2 
V
inductor ripple current as shown in the following equation:  IN  1  COUT  ∆VOUT1
VOUT fOSC
IPEAK = 1.2 x IIN(MAX)
Note that the saturated current of the inductor must be where fOSC is the switching frequency and ΔIL is the
greater than IPEAK. The inductance can eventually be inductor ripple current. Move COUT to the left side to
determined according to the following equation : estimate the value of ΔVOUT1 according to the following
equation :
η   VIN    VOUT  VIN 
2

L D  IOUT
∆VOUT1 
0.4   VOUT   IOUT MAX   fOSC
2
η  COUT  fOSC

where fOSC is the switching frequency. For better system where D is the duty cycle and η is the Boost converter
performance, a shielded inductor is preferred to avoid EMI efficiency. Finally, taking ESR into consideration, the
problems. overall output ripple voltage can be determined by the
following equation :
Boost Converter Diode Selection
D  IOUT
Schottky diode is a good choice for an asynchronous ∆VOUT  ∆VESR 
η  COUT  fOSC
Boost converter due to its small forward voltage. However,
when selecting Schottky diodes, important parameters where ΔVESR = ΔIC x RC_ESR = IPEAK x RC_ESR
such as power dissipation (PD = VF x Id), reverse voltage The output capacitor, COUT, should be selected accordingly.
rating and pulsating peak current should all be taken into
consideration. For better performance, it is recommended
to choose a suitable diode with reverse voltage rating
greater than the maximum output voltage.

Boost Converter Input Capacitor Selection


Low ESR ceramic capacitors are recommended for input
capacitor applications. Low ESR will effectively reduce
the input ripple voltage caused by switching operation.
Two 22μF low ESR ceramic capacitors are sufficient for
most applications. Nevertheless, this value can be
decreased for applications with lower output current
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36
RT6940
VCCT Asynchronous Buck Soft-Start
The VCCT asynchronous Buck converter has an internal
soft-start to reduce the input inrush current respectively.
ΔIL
When the converter is enabled, the output voltage rises
Input Current
Inductor Current slowly from zero to target output voltage. The typical soft-
start time is around 1ms.
Output Current
VCCT Asynchronous Buck Output Voltage Setting
Time VCCT asynchronous Buck converter has the I 2 C
(1-D)TS Output Ripple adjustable output voltage from 3V to 3.6V in 0.1V
Voltage (ac)
increments. The default VCCT voltage is 3.3V. User can
Time control the Buck output voltage by register address 04h
ΔVOUT1
respectively.

VCCT Asynchronous Buck Over-Voltage Protection


Figure 1. The Output Ripple Voltage without the The VCCT asynchronous Buck converter has the over-
Contribution of ESR voltage protection to protect the main switch at the VCCT
Boost Converter Loop Compensation pin. When the VCCT pin voltage rises above (VCCT x
120%) V (typ.), VCCT will be shut down. As soon as the
The voltage feedback loop can be compensated with an
output voltage falls below the over-voltage threshold, the
external compensation network consisting of R and C.
VCCT will resume operation.
Choose R to set the high frequency integrator gain for
fast transient response and C to set the integrator zero to
VCCT Asynchronous Buck Over-Current Protection
maintain stability. The frequency of the zero set by the
The VCCT senses the inductor current that is flowing out
compensation components can be calculated using the
the LXT pin. The internal MOSFET will be turned off if the
following equation :
peak inductor current reaches 2A (min.). Thus, the output
fZ  1 current at the current limit boundary, denoted as IOUT(LIM),
2  π R  C can be calculated according to the following equation :
where R and C are the COMP pin outer resistance and
 VOUT 
capacitance.  1 η  VIN   VOUT
IOUTLIM  ILIM   
VCCT Asynchronous Buck Converter 2  L  fSW

The VCCT asynchronous Buck converter is high efficiency where η is the efficiency of the Buck converter, ILIM is the
PWM architecture with 1.4MHz (typ.) operation frequency value of the current limit and fSW is the switching frequency.
and fast transient response. Moreover, user can adjust
switching frequency by register address 03h respectively. VCCT Asynchronous Buck Short-Circuit Protection
The converter drives an internal 2.5A (typ.) N-MOSFET The VCCT has an advanced short-circuit protection
which is connected between the VIN and LXT pin. Connect mechanism which prevents the device from damage by
a 100nF low ESR ceramic capacitor between the CBT unexpected applications. An error condition is detected if
and LXT pins to provide gate driver voltage for the high- the voltage on the converter's VCCT pin remains below
side MOSFET. VCCT x 20% for longer than 10μs, IC will be shut down
and then restart three times. If the failure information is
still not released, the chip will be shutdown. Once shut
down, the boost converter can only be enabled after the
chip is powered on again.
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37
RT6940
VCCT Asynchronous Buck Fault Protection VCCO Synchronous Buck Over-Current Protection
The VCCT asynchronous Buck converter has a fault The VCCO senses the inductor current that is flowing out
protection feature to protect the IC when the output the LXO pin. The internal MOSFET will be turned off if the
becomes shorted to GND. This is achieved by using the peak inductor current reaches 1.5A (min.). Thus, the output
comparator to monitor the VCCT voltage. If VCCT remains current at the current limit boundary, denoted as IOUT(LIM),
below VCCT x 65% for 50ms, the VCCT Buck converter can be calculated according to the following equation :
will be disabled. Once shut down, the regulator can only
be enabled after the chip is powered on again.  VOUT 
 1 η  VIN   VOUT
IOUTLIM  ILIM   
VCCO Synchronous Buck Converter 2  L  fSW

The VCCO synchronous converter is high efficiency PWM Where η is the efficiency of the Buck converter, ILIM is the
architecture with 1.4MHz (typ.) operation frequency and value of the current limit and fSW is the switching frequency.
fast transient response. Moreover, user can adjust
switching frequency by register address 03h respectively. VCCO Synchronous Buck Short-Circuit Protection
VCCO converter has one internal P-MOSFET and one The VCCO has an advanced short-circuit protection
internal N-MOSFET as synchronous rectifier and do not mechanism which prevents the device from damage by
require Schottky diode on the switching Pin. The high- unexpected applications. An error condition is detected if
side MOSFET is connected between the VIN and switching the voltage on the converter's VCCO pin remains below
pins, while the low-side MOSFET is connected between VCCO x 20% for longer than 10μs, IC will be shut down
the switching pin and GND. The synchronous Buck and then restart three times. If the failure information is
converter's loop compensation network is builds in inside still not released, the chip will be shutdown. Once shut
RT6940. down, the boost converter can only be enabled after the
chip is powered on again.
VCCO Synchronous Buck Soft-Start
The VCCO synchronous Buck converter has an internal VCCO Synchronous Buck Fault Protection
soft-start to reduce the input inrush current respectively. The VCCO synchronous Buck converter has a fault
When the converter is enabled, the output voltage rises protection feature to protect the IC when the output
slowly from zero to target output voltage. The typical soft- becomes shorted to GND. This is achieved by using the
start time is around 1ms. comparator to monitor the VCCO voltage. If VCCO remains
below VCCO x 65% for 50ms, the VCCO Buck converter
VCCO Synchronous Buck Output Voltage Setting will be disabled. Once shut down, the regulator can only
VCCO synchronous Buck converter has the I2C adjustable be enabled after the chip is powered on again.
output voltage from 1.5V to 2.8V in 0.1V increments. The
default VCCO voltage is 1.8V. User can control the Buck Buck Inductor Selection
output voltage by register address 04h respectively. The inductor value and operating frequency determine the
ripple current according to a specific input and output
VCCO Synchronous Buck Over-Voltage Protection voltage. The ripple current, ΔIL, will increase with higher
The VCCO synchronous Buck converter has the over- VIN and decrease with higher inductance, as shown in the
voltage protection to protect the main switch at the VCCO equation below :
pin. When the VCCO pin voltage rises above (VCCO x
∆IL   OUT    1  OUT 
V V
120%) V (typ.), VCCO will be shut down. As soon as the
 fOSC  L   VIN 
output voltage falls below the over-voltage threshold, the
VCCO will resume operation. Having a lower ripple current reduces not only the ESR
losses in the output capacitors but also the output voltage

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38
RT6940
ripple. High frequency with small ripple current can achieve Buck-Boost Converter
the highest efficiency operation. However, it requires a The inverting buck-boost non-synchronous converter uses
large inductor to achieve this goal. For the ripple current a peak current mode topology and fixed frequency
selection, the value of IL(MAX) / ΔIL = 0.4 is a reasonable operation. Moreover, user can adjust switching frequency
starting point. The largest ripple current occurs at the by register address 02h respectively. Inverting buck-boost
highest VIN. To guarantee that the ripple current stays converter generates the negative voltage VGL for scan
below the specified maximum, the inductor value should driver.
be chosen according to the following :
The converter drives an internal 2A (typ.) P-MOSFET which
 VOUT   VOUT  is connected between the VINL and LXL pin.
L   1 V 
 fOSC  ∆IL MAX    INMAX  
Buck-Boost Converter Design Procedure
The first step in the design procedure is to verify whether
Buck Input Capacitor Selection
the maximum possible output current of the buck-boost
To prevent large ripple current, a low ESR input capacitor
converter supports the specific application requirements.
sized for the maximum RMS current should be used. The
To simplify the calculation, the fastest approach is to
RMS current is given by :
estimate converter efficiency by taking the efficiency
VOUT VIN numbers from the provided efficiency curves or to use a
IRMS  IOUT MAX    1
VIN VOUT worst case assumption for the expected efficiency,
This formula has a maximum at VIN = 2 VOUT, where IRMS e.g.,80%. The calculation must be performed for the
= IOUT / 2. This simple worst-case condition is commonly minimum assumed input voltage where the peak switch
used for design because even significant deviations do current is the highest. The inductor and external Schottky
not offer much relief. Choose a capacitor rated at a higher diode have to be able to handle this current.
temperature than required. Several capacitors may also 1. Converter Duty Cycle :
be paralleled to meet size or height requirements in the
-VOUT
design. For the input capacitor, a 10μF low ESR ceramic D=
VIN  - VOUT
capacitor is recommended.
2. Maximum output current :
Buck Output Capacitor Selection
 VIN  D 
The selection of COUT is determined by the required ESR IOUT =  ILXLPEAK    1  D 
 2  fOSC  L 
to minimize voltage ripple. Moreover, the amount of bulk
capacitance is also a key for COUT selection to ensure 3. Peak switch current :
that the control loop is stable. Loop stability can be
IOUT VIN  D
checked by viewing the load transient response. The ILXLPEAK = 
1 D 2  fOSC  L
output ripple, VOUT, is determined by :

∆VOUT  ∆IL   ESR  1  Buck-Boost Over-Voltage Protection


 8  fOSC  COUT  The VGL Buck-Boost converter has an over voltage
The output ripple will be the highest at the maximum input protection to protect the VGL switch at LXL pin in case
voltage since IL increases with input voltage. Multiple the feedback (VGL) pin is floating. When the VGL pin
capacitors placed in parallel may be needed to meet the voltage reaches -14V (typ.), the VGL Buck-Boost converter
ESR and RMS current handling requirements. turns off the P-MOSFET switch. As soon as the output
voltage falls below the over voltage threshold, the converter
will resume operation.

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Buck-Boost Fault Protection
The VGL Buck-Boost converter has a fault protection
feature to protect the IC when the output becomes shorted
to GND. This is achieved by using the comparator to
monitor the VGL voltage. If VGL remains below VGL x
65% for 50ms, the VGL Buck-Boost converter will be
disabled. Once shut down, the regulator can only be
enabled after the chip is powered on again.

VGL Buck-Boost Short-Circuit Protection Figure 2. The Buck-Boost Input Signature in BCM
The VGL has an advanced short-circuit protection The inductance can eventually be determined according
mechanism which prevents the device from damage by to the following equation :
unexpected applications. An error condition is detected if
2
the voltage on the converter's VGL pin remains below − VOUT    VIN 
Lcritical   
1.3V for longer than 10μs, IC will be shut down and then 2  fOSC  IOUT  VIN  VOUT 
restart three times. If the failure information is still not
released, the chip will be shutdown. Once shut down, the As a general rule, the inductor ripple current range is 20%
boost converter can only be enabled after the chip is to 40% of the average DC inductor current. If 40% is
powered on again. selected as an example, the inductor ripple current can
be calculated according to the following equations :
VGL Buck-Boost Output Voltage Setting
2
VGL Buck-Boost converter has the I2C adjustable output VOUT    VIN 
L  
voltage from −4V to −13V in 0.5V increments. The default 0.4  fOSC  IOUT  VIN  VOUT 
VGL voltage is −8V. User can control the Buck-Boost
output voltage by register address 07h respectively. Buck-Boost Converter Diode Selection
To achieve high efficiency, a Schottky diode should be
Buck-Boost Converter Inductor Selection
used. The reverse voltage rating should be higher than
The buck-boost converter is able to operate with 10μH to the maximum output voltage of the buck-boost converter.
47μH inductors, but a 10μH inductor is typical. The main The average rectified forward current, IAVG, the Schottky
parameter for inductor selection is the saturation current diode needs to be rated for, is equal to the output current,
of the inductor which should be higher than the peak switch IOUT.
current as calculated in the Design Procedure section with
PD = IAVG x VFORWARD
additional margin to cover for heavy load transients. As
for inductance, we are going to derive the transition point, Buck-Boost Converter Output Capacitor Selection
where the converter toggles from CCM to DCM. We need
For the best output voltage filtering, low ESR ceramic
to define the point at which the inductor current ripple
capacitors are recommended. One 22μF or two 10μF
touches zero, and as the power switch is immediately
output capacitors with sufficient voltage ratings in parallel
reactivated, the current ramps up again. Figure 2 portrays
are adequate for most applications. Additional capacitors
the input current activity of the Buck-Boost converter.
can be added to improve load transient regulation.
To calculate the output voltage ripple, the following equation
can be used :

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RT6940
D  VOUT
V   VESR VGH ready

fOSC  RLOAD  COUT


VGH
where ΔVESR = ΔIC x RC_ESR = IPEAK x RC_ESR
ΔVESR can be neglected in many cases since ceramic FLK1/2

capacitors provides very low ESR. Floating


VGH
VGHM1/2
VGHM1/2 limit voltage
VPRED OP-Amplifier set by the VRG pin
external resistor.
VPRED OP-Amplifier has the I2C adjustable mode select
and output voltage from 3V to 6.5V in 0.5V increments.
BDP Comparator
The default VPRED voltage is 6.5V. User can control the
amplifier mode and output voltage by register address 05h The BDP function is open drain contains an independent
respectively. current-limit mechanism. It prevents large current from
damaging the inductor and diode. If the inductor current
VPRED OP-Amplifier Short-Circuit Condition exceeds the current limit of BDP or BS_SNS voltage
An internal short-circuit protection circuit is implemented exceeds the BD_REF, BDP voltage will be pulling high.
to protect the device from output short circuit. The amplifier Once pull high, the open drain can only be enabled after
limits the short circuit current to ±300mA if the output is the chip is powered on again.
directly shorted to positive/negative supply rails. An error
BDP Start Delay Time
condition is detected if the voltage on the amplifier VPRED
pin remains below VPRED x 20% for longer than 10μs, IC BDP start has the I2C adjustable delay time from 0ms to
will be shut down and then restart three times. If the failure 50ms in 10ms increments. User can control the BDPSTR
information is still not released, the chip will be shutdown. delay time by register address 06h respectively.
Once shut down, the amplifier can only be enabled after
BDP End Delay Time
the chip is powered on again.
BDP end has the I2C adjustable delay time from 0ms to
Gate Pulse Modulation 300ms. User can control the BDPEND delay time by
The gate modulation is controlled by FLK1/2 signal, except register address 07h respectively.
during startup where it is kept at low state until VGH build
EVDD Voltage Detector
up is ready. The discharge slope is set by the RE1/2 pin
The ED_RST and NMOS_CON function are open-drain
external resistor, the internal MOSFET and the VGHM1/2
architecture. While VIN and ED_SNS power on sequence
pin gate line capacitance. A gate pulse modulation limited
are normal, once the ED_SNS voltage exceeds the
voltage can be set by VRG pin external resistor. When
ED_REF rising threshold (Typ. 1.2V), IC will count delay
the limit voltage is reached, the discharging of VGHM1/2
time of BDPSTR and BDPEND. After count delay time of
through RE1/2 is stopped and the VGHM1/2 output is
BDPSTR is finished, NMOS_CON voltage will pull low.
high impedance until FLK1/2 goes high again.
After count delay time of BDPEND is finished,
NMOS_CON voltage will pull high. After NMOS_CON
voltage pull high is finished, ED_RST voltage will pull high
after count delay time (1ms). If VIN and ED_SNS power
on sequence are reverse, NMOS_CON voltage will kept
high. After count delay time of BDPEND is finished,
ED_RST voltage will pull high after count delay time (1ms).
The EVDD detector function can be determined according
to page 5.

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Thermal Considerations
The junction temperature should never exceed the
absolute maximum junction temperature TJ(MAX), listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction-to-ambient
thermal resistance.
For continuous operation, the maximum operating junction
temperature indicated under Recommended Operating
Conditions is 125°C. The junction-to-ambient thermal
resistance, θJA, is highly package dependent. For a
WQFN-56L 7x7, the thermal resistance, θJA, is 27°C/W
on a standard JEDEC 51-7 high effective-thermal-
conductivity four-layer test board. The maximum power
dissipation at TA = 25°C can be calculated as below :
PD(MAX) = (125°C − 25°C) / (27°C/W) = 3.7W for a
WQFN-56L 7x7 package.
The maximum power dissipation depends on the operating
ambient temperature for the fixed TJ(MAX) and the thermal
resistance, θJA. The derating curves in Figure 3 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
5.0
Four-Layer PCB
Maximum Power Dissipation (W)1

4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0 25 50 75 100 125
Ambient Temperature (°C)
Figure 3. Derating Curve of Maximum Power Dissipation

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RT6940
Minimize the size of the LXH
Minimize the size of the LXL node and
keep it wide and shorte. Keep the LXL
node and keep it wide and
short. Keep the LXH node
GND
node away from the VGL pin.
GND away from the VGH pin.

VIN VGH C39 C38 C37 C36 C17


C35
The sense voltage must be near the
sense pin. The sense voltage pin
D2 L4 SVDD
C40 C12 D1 L3
trace must be short and avoid the

C19 C18 C30 C31 C32 C33 C34


trace near any switching nodes. VGL C43

GND

COMPL

VGHM1

VGHM2

43 PGNDH
Minimize the size of the LXT node and

VGL

LXL

NC
GND

VINL

NC

RE1

RE2

VGH

LXH
keep it wide and shorte. Keep the LXT
node away from the VCCT pin.
VCCT

48

47
56

55

54

53

52

51

50

49

46

45

44
L1

LXT 1 42 SVDD
R C3

C20 Q1
D4
EGDS
C25 C24 C23 C22 C2 CBT 2 41 SVDDI
GND

C21 C*
VINT 3 40 EGDS GND

D3
VIN NC 4 39 GND
L5
C1 R18 C16
VIN

Q2
GND 5 38 COMPH R
DRS
C4 R1 C30 C31 C32
GND
The compensation network must
COMPT 6 37 CSS
R17 C15
near the COMP pin. The trace NC 7 36 COMPS
must be short and avoid the trace WQFN 7x7 56L
C13
GND
near any switching nodes.
VCCT 8 PGND 35 SSS GND
C42 C41 R
PGNDO 9 34 DRS
C28 C27 C5 L2

LXO 10 33 PGNDS
VCCO R3
11 32 VD The Q2, D3 and LX trace should be
VCCO GND
C11 very close to prevent lager amount of
Minimize the size of the LXO
EMI. The Trace from DRS should also
node and keep it wide and 12 31 ED_SNS
COMPO be short to decrease the noise of the
shorte. Keep the LXO node R2
C6 driver output signals.
away from the VCCO pin.
BGND 13 30 ED_MR

C7
VPRED 14 29 ED_RST The CSS and PGND PCB traces should be routed
parallel to one another with minimum spacing in
between all the way to the sense resistor. These
VIN 15

AGND 16

VRG 17

VL 18

SDA 19

SCL 20

FLK1 21

FLK2 22

RST 23

BDP 24

ES_ON 25

BD_SNS 26

BD_REF 27

28
GND C45
traces should far away any high frequency switching
nodes in the layout, in order to avoid the sense error

NMOS_CON
HAVDD due to parasitic PCB resistance IR drops.

Separate power ground (PGND) and C8


analog ground (AGND). Connect
AGND and PGND islands at a single VIN GND Connect the exposed pad to a strong ground
end. Make sure there are no other C27
The all of filter capacitors as plane for maximum thermal dissipation
connections between these separate
ground planes.The PGND should be possible as close to IC pin.
wide and short enough to connect
ground plane.

Figure 3. PCB Layout Guide

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RT6940
Outline Dimension

2 1 2 1

DETAIL A
Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,


but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches


Symbol
Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.150 0.250 0.006 0.010
D 6.900 7.100 0.272 0.280
D2 5.150 5.250 0.203 0.207
E 6.900 7.100 0.272 0.280
E2 5.150 5.250 0.203 0.207
e 0.400 0.016
L 0.350 0.450 0.014 0.018

W-Type 56L QFN 7x7 Package

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RT6940

Richtek Technology Corporation


14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

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45

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