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UC3842/UC3843/UC3844/UC3845
SMPS Controller

Features Description
• Low Start Up Current The UC3842/UC3843/UC3844/UC3845 are fixed fre-
• Maximum Duty Clamp quency current-mode PWM controller. They are specially
• UVLO With Hysteresis designed for Off - Line and DC-to-DC converter applica-
• Operating Frequency Up To 500KHz tions with minimum external components. These inte-
grated circuits feature a trimmed oscillator for precise duty
cycle control, a temperature compensated reference, high
gain error amplifier. current sensing comparator, and a high
current totempole output Ideally suited for driving a power
MOSFET. Protection circuity Includes built in under-volt-
age lockout and current limiting. TheUC3842 and UC3844
have UVLO thresholds of 16V (on) and 10V (off) The
UC3843 and UC3845 are 8.5V (on) and 7.9V (off) The
UC3842 and UC3843 can operate within 100% duty cycle.
The UC3844and UC3845 can operate with 50% duty cycle.

8-DIP

1
14-SOP

Internal Block Diagram

Rev. 5.0
©2000 Fairchild Semiconductor International
UC3842/UC3843/UC3844/UC3845

Absolute Maximum Ratings

Parameter Symbol Value Unit
Supply Voltage VCC 30 V
Output Current IO ±1 A
Analog Inputs (Pin 2.3) V(ANA) -0.3 to 6.3 V
Error Amp Output Sink Current ISINK (E.A) 10 mA
Power Dissipation (TA = 25°C) PD 1 W

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 UC3842/UC3843/UC3844/UC3845

Electrical Characteristics
(VCC=15V, RT=10KΩ, CT=3.3nF, TA= 0°C to +70°C, unless otherwise specified)

Parameter Symbol Conditions Min. Typ. Max. Unit

REFERENCE SECTION
Reference Output Voltage VREF TJ = 25°C, IREF = 1mA 4.90 5.00 5.10 V
Line Regulation ∆VREF 12V≤VCC≤25V - 6 20 mV
Load Regulation ∆VREF 1mA≤IREF≤20mA - 6 25 mV
Short Circuit Output Current ISC TA = 25°C - -100 -180 mA
OSCILLATOR SECTION
Oscillation Frequency f TJ = 25°C 47 52 57 KHz
Frequency Change with Voltage ∆f/∆VCC 12V≤VCC≤25V - 0.05 1 %
Oscillator Amplitude VOSC - - 1.6 - VP-P
ERROR AMPLIFIER SECTION
Input Bias Current IBIAS - - -0.1 -2 µA
Input Voltage VI(E>A) V1 = 2.5V 2.42 2.50 2.58 V
Open Loop Voltage Gain GVO 2V≤ VO ≤4V 65 90 - dB
Power Supply Rejection Ratio PSRR 12V≤ VCC ≤25V 60 70 - dB
Output Sink Current ISINK V2 = 2.7V, V1 = 1.1V 2 7 - mA
Output Source Current ISOURCE V2 = 2.3V, V1 = 5V -0.6 -1.0 - mA
High Output Voltage VOH V2 = 2.3V, RL = 15KΩ to GND 5 6 - V
Low Output Voltage VOL V2 = 2.7V, RL = 15KΩ to Pin 8 - 0.8 1.1 V
CURRENT SENSE SECTION
Gain GV (Note 1 & 2) 2.85 3 3.15 V/V
Maximum Input Signal VI(MAX) V1 = 5V(Note 1) 0.9 1 1.1 V
Power Supply Rejection Ratio PSRR 12V≤ VCC ≤25V (Note 1) - 70 - dB
Input Bias Current IBIAS - - -3 -10 µA
OUTPUT SECTION
VOL ISINK = 20mA - 0.08 0.4 V
Low Output Voltage
ISINK = 200mA - 1.4 2.2 V
High Output Voltage ISOURCE = 20mA 13 13.5 - V
VOH
ISOURCE = 200mA 12 13.0 - V
Rise Time tR TJ = 25°C, CL= 1nF (Note 3) - 45 150 ns
Fall Time tF TJ = 25°C, CL= 1nF (Note 3) - 35 150 ns
UNDER-VOLTAGE LOCKOUT SECTION
Start Threshold UC3842/UC3844 14.5 16.0 17.5 V
VTH(ST)
UC3843/UC3845 7.8 8.4 9.0 V
Min. Operating Voltage UC3842/UC3844 8.5 10.0 11.5 V
VOPR(MIN)
(After Turn On) UC3843/UC3844 7.0 7.6 8.2 V

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UC3842/UC3843/UC3844/UC3845

Electrical Characteristics (Continued)

(VCC=15V, RT=10KΩ, CT=3.3nF, TA= 0°C to +70°C unless otherwise specified)

Parameter Symbol Conditions Min. Typ. Max. Unit

PWM SECTION
Max. Duty Cycle D(max) UC3842/UC3843 95 97 100 %
D UC3844/UC3845 47 48 50 %
Min. Duty Cycle D(MIN) - - - 0 %
TOTAL STANDBY CURRENT
Start-Up Current IST - - 0.45 1 mA
Operating Supply Current ICC(OPR) V3=V2=ON - 14 17 mA
Zener Voltage VZ ICC = 25mA 30 38 - V

Adjust VCC above the start threshould before setting at 15V

Note:
1. Parameter measured at trip point of latch
2. Gain defined as:
∆V
A = ----------1
∆V 3
,0 ≤ V3 ≤ 0.8V

3.These parameters, although guaranteed, are not 100 tested in production.

UC3842

Figure 1. Open Loop Test Circuit

High peak currents associated with capacitive loads necessitate careful grounding techniques Timing and bypass capacitors
should be connected close to pin 5 in a single point ground. The transistor and 5KΩ potentiometer are used to sample the
oscillator waveform and apply an adjustable ramp to pin 3.

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 UC3842/UC3843/UC3844/UC3845

UC3842/44 UC3843/45

Figure 2. Under Voltage Lockout

During Under-Voltage Lock-Out, the output driver is biased to a high impedance state. Pin 6 should be shunted to ground with
a bleeder resistor to prevent activating the power switch with output leakage current.

Figure 3. Error Amp Configuration

Figure 4. Current Sense Circuit

Peak current (IS) is determined by the formula:

1.0V
I S ( MAX ) = ------------
RS

A small RC filter may be required to suppress switch transients.

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UC3842/UC3843/UC3844/UC3845

Figure 5. Oscillator Waveforms and Maximum Duty Cycle

Oscillator timing capacitor, CT, is charged by VREF through RT, and discharged by an internal current source. During the dis-
charge time, the internal clock signal blanks the output to the low state. Selection of RT and CT therefore determines both
oscillator frequency and maximum duty cycle. Charge and discharge times are determined by the formulas:

tc = 0.55 RT CT
0.0063R T – 2.7
t D = R T C T I n  ----------------------------------------
0.0063R T – 4

Frequency, then, is: f=(tc + td)-1

1.8
ForRT > 5KΩ ,f = ---------------
RT CT

Figure 6. Oscillator Dead Time & Frequency Figure 7. Timing Resistance vs Frequency
(Deadtime vs CT RT > 5kΩ)

Figure 8. Shutdown Techniques

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 UC3842/UC3843/UC3844/UC3845

Shutdown of the UC3842 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two
diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The
PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins
1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SOR which will be
reset by cycling Voc below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset.

UC3842/UC3843

Figure 9. Slope Compensation

A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for
converters requiring duty cycles over 50%. Note that capacitor, C, forms a filter with R2 to suppress the leading edge switch
spikes.

TEMPERATURE (°C) TEMPERATURE (°C)

Figure 10. TEMPERATURE DRIFT (Vref) Figure 11. TEMPERATURE DRIFT (Ist)

TEMPERATURE (°C)
Figure 12. TEMPERATURE DRIFT (Icc)

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UC3842/UC3843/UC3844/UC3845

Mechanical Dimensions
Package

8-DIP

)
6.40 ±0.20

0.031
0.79
0.252 ±0.008

1.524 ±0.10
0.060 ±0.004
0.018 ±0.004
0.46 ±0.10
(
#1 #8
0.362 ±0.008
MAX

9.20 ±0.20
0.378
9.60

#4 #5

0.100
2.54

5.08 3.30 ±0.30

MAX 0.130 ±0.012
0.200
7.62
0.300 3.40 ±0.20 0.33
MIN
0.134 ±0.008 0.013

+0.10
0.25 –0.05
+0.004
0.010 –0.002
0~15°

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 UC3842/UC3843/UC3844/UC3845

Mechanical Dimensions (Continued)

Package

14-SOP

0.05
MIN
0.002
1.55 ±0.10

)
0.061 ±0.004

0.019
0.47
(
#1 #14

MAX

0.337 ±0.008

+0.004
8.56 ±0.20

+0.10

0.016 -0.002
0.406 -0.05
0.343
8.70

#7 #8

0.050
1.27
6.00 ±0.30 1.80
0.236 ±0.012 MAX
0.071
+0.004
+0.10

0.008 -0.002
0.20 -0.05

MAX0.004
MAX0.10

3.95 ±0.20
0.156 ±0.008

5.72
8°
0~

0.225
0.60 ±0.20
0.024 ±0.008

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UC3842/UC3843/UC3844/UC3845

Ordering Information

Product Number Package Operating Temperature

UC3842N
UC3843N
8 DIP
UC3844N
UC3845N
0 ~ + 70°C
UC3842D
UC3843D
14 SOP
UC3844D
UC3845D

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UC3842/UC3843/UC3844/UC3845

11
UC3842/UC3843/UC3844/UC3845

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
INTERNATIONAL. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be
or (b) support or sustain life, and (c) whose failure to reasonably expected to cause the failure of the life support
perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.

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 2000 Fairchild Semiconductor International