Fall 2022 Harrisburg University of Science & Technologies

CISC 530 – Computer Systems Architecture

Fall 2022
Midterm Exam
Krapi Vani
1. What decimal number does the bit pattern 0x0C00000C represent if it is a
floating-point number? Use the IEEE 754 standard. Explain in detail how you get
your answer.

Solution :
IEEE-754 standard define a single (32 bits) and double (64 bits) precision float point format
as follows:

 Step 1: translate the hexadecimal value of 0x0C000000 to binary value.

Hexadecimal: 0 C 0 0 0 0 0 C
Binary: 0000 1100 0000 0000 0000 0000 0000 1100
This is a single precision (32 bit) floating point.

 Step 2: Consider the sign bit.

0000 1100 0000 0000 0000 0000 0000 1100

Since the first bit to the (most significant bit) is zero, the value is unsigned (or non-negative
or positive)

 Step 3: consider the exponent

0000 1100 0000 0000 0000 0000 0000 1100
The value of the Exponent, 0001 1000 is
Exponent = 0x18 = 1*161 + 8*160 = 16 + 8 = 24
Exponent –Bias = 24 – 127 = -103

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Step 4: consider the Fraction (or Mantissa or the significand)

Since the Exponent is neither 0000 0000 nor 1111 1111, it is normalized. In other
word the fraction represents a 1.(Fraction) as shown in figure above.
0000 1100 0000 0000 0000 0000 0000 1100
The value of Fraction is 000 0000 0000 0000 0000 1100 is

Fraction = 1 * 2^2 + 1*2^3 = 4 + 8 = 12 ( the rest are multiplied by zero.)

-1^0 * (1 + 12) * (2^(24-127))

- Answer: 0x0C00000C=13×2^−103 ≅ 1.28189897 ×10-30

2. Assume $t0 holds the value 0x10101000 and $t1 0x00101001. What is the
value of $t0 after the following instructions?

slt $t2, $0, $t0

    bne $t2, $0, ELSE
     j DONE
ELSE: addi $t0, $t1, 5
DONE:

Solution:

 Step 1 consider slt $t2,$0,$t0

Instruction slt $t2,$0,$t0 tells the CPU to compare the content of register $0 and the
temporary register $t0. If $0 is less than $t0, the temporary register $t2 is set to a value
of 1. Otherwise, register $t2 is set to 0 (see page 99 HP MIPS 6th edition; section 2.7
Instructions for Making Decisions)
We also know that register $0 is hardwired to be always zero (0).
$t0 = 0x10101000 = 27+ 25+ 23 = 128 + 64 + 8 = 200
Obviously, $0 or 0 is less than $t0 or 100. Thus, $t2 will be set to a value of 1.

 Step 2 consider bne $t2,$0,ELSE

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Instruction bne $t2,$0,ELSE tells the CPU to compare the temporary register $t2 to
the zero register $0. If the two registers are not equal, jump to the instruction at the ELSE
label. Indeed, zero (0) is not equal to (1), the PC is set to the location of ELSE and continue.

 Step 3 consider addi $t0,$t1,5

Instruction addi $t0, $t1, 5 adds a value of 5 to the temporary register $t1 and
store the result into the same register $t0. Since $t2 has a 1, thus, after the execution of
this instruction, register $t0 has a value of 6.
Answer: $t0 = 6

3. Translate 0xfeab0101 into decimal. You may simply assume that it is an

unsigned integer.

Solution :

The most significant digit has a value of f*167 where the hexadecimal value of f is
15.
- The least significant digit has a value of 2*160.
feab010116= 15 * 167 + 14 * 166 + 10 * 165 + 11* 164 + 0*163 + 1*162 + 0*161 + 1*160
= 4026531840 + 234881024 + 10485760 + 720896 + 0 +256 + 0 + 1
= 4272619777

Answer : 0xfeab010116 = 42726197772

4. For the following C statement, what is the corresponding MIPS assembly code?
Assume that the variables f, g, h, i, and j are assigned to registers $s2, $s3,
$s5, $s6, and $s7, respectively. Assume that the base address of the arrays D
and C are in registers $s0 and $s1, respectively.

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D[12] = C[i*j]

Solution:

- Assume that the type is int that requires a word or four (4) bytes.

- To locate the address of C[i*j], we compute the following:

Compute, v = i*j
compute, y = $s1 + v x 4

- To locate the address of D[12], we compute the following:

o $s0 + 12 x 4 = $s0 + 48

mul $t0,$s6,$s7 #i*j.

sll $t0,2 #(i*j)*4
add $t0,$s1,$t0 #$s1+(i*j)*4
lw $t1,0($t0) # get the content of C[i*j] into $t1 register
sw $t1,48($s0) # store the content of $t1 into D[12] or $s0+48

5. Consider three different processors C1, C2, and C3, executing the same
instruction set:
• C1 has a 1.5 GHz clock rate and a CPI of 2.1
• C2 has a 4.5 GHz clock rate and a CPI of 1.2
• C3 has a 1.1 GHz clock rate and has a CPI of 2.1
a. Which processor has the poorest performance expressed in instructions per
second?
b. If the processors each execute a program in 12 seconds, find the number of
cycles and the number of instructions.
c. We are trying to reduce the execution time by 31% but this leads to an
increase of 19% in the CPI. What clock rate should we have to get this time
reduction?

Solution:

a)
Instructions per second = 𝑐𝑙𝑜𝑐𝑘 𝑟𝑎𝑡𝑒𝑐𝑦𝑐𝑙𝑒𝑠 𝑝𝑒𝑟 𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛
GHz: 109 Hertz or cycles per second
• • C1: instructions per second = 1.5 × 109 / 2.1 = 0.79×109

• • C2: instructions per second = 4.5 × 109 / 1.2 = 3.75×109

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• • C3: instructions per second = 1.1 × 109 / 2.1 =0.52×109

Process C3 performs poorest 0.52×109 instructions per second.

b)
Number of cycles in 12 seconds = 12 × 𝑐𝑙𝑜𝑐𝑘 _𝑟𝑎𝑡𝑒

C1 takes 12 X 1.5 × 109 = 18 X 109 c𝑦𝑐𝑙𝑒𝑠 to run the program.

C2 takes 12 X 4.5 × 109 = 54 X 109 c𝑦𝑐𝑙𝑒𝑠 to run the program.
C3 takes 12 X 1.1 × 109 = 13.2X109 c𝑦𝑐𝑙𝑒𝑠 to run the program.

Number of instructions = 𝑛𝑢𝑚𝑏𝑒𝑟 _𝑜𝑓 _𝑐𝑦𝑐𝑙𝑒𝑠/ 𝑛𝑢𝑚𝑏𝑒𝑟 _𝑜𝑓 _𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑠 _𝑝𝑒𝑟 _𝑐𝑦𝑐𝑙𝑒 _

In 12 seconds,

C1 runs 18×109 𝑐𝑦𝑐𝑙𝑒𝑠 /2.1 𝑐𝑦𝑐𝑙𝑒 𝑝𝑒𝑟 𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑠 = 8.5×109 instructions

C2 runs 54×109 𝑐𝑦𝑐𝑙𝑒𝑠/1.2 𝑐𝑦𝑐𝑙𝑒 𝑝𝑒𝑟 𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑠 = 45×109 instructions

C3 runs 13.2×109 𝑐𝑦𝑐𝑙𝑒𝑠/2.1 𝑐𝑦𝑐𝑙𝑒 𝑝𝑒𝑟 𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑠 = 6.28 ×109 instructions

c)

It used to take 12 seconds to run and now it takes only 8.28 seconds, a 31% reduction in
execution time.

CPInew = 1.19 x CPUold: It takes more cycles to execute an instruction with the new
architecture.
Clock rate = 𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑠 × 𝑐𝑦𝑐𝑙𝑒𝑠 𝑝𝑒𝑟 𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑡𝑖𝑚𝑒 𝑡𝑜 𝑟𝑢𝑛 (𝑠𝑒𝑐𝑜𝑛𝑑𝑠)

CPI (C1) = 1.19 x 2.1 = 2.49

CPI (C2) = 1.19 x 1.2 = 1.42
CPI (C3) = 1.19 x 2.1 = 2.49

Clock rate (C1) = 8.5×109 ×2.49 / 8.28 = 2.55×109𝐻𝑧=2.55 𝐺𝐻𝑧

Clock rate (C2) = 45×109 X1.42 /8.28 = 7.71×109𝐻𝑧=7.71 𝐺𝐻𝑧

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Clock rate (C1) = 6.28 ×109 ×2.49/8.28= 1.88×109𝐻𝑧=1.88 𝐺𝐻𝑧

6.Compilers can have a profound impact on the performance of an application. Assume

that for a program:
 compiler A results in a dynamic instruction count of 1.3E 9 and has an
execution time of 1.2s
 compiler B results in a dynamic instruction count of 1.5E9 and an execution
time of 2.5s

a. Find the average CPI for each program given that the processor has a clock
cycle time of 1.3ns
b. Assume the compiled programs run on two different processors. If the
execution times on the two processors are the same, how much faster is
the clock of the processor running compiler B's code versus the clock of
the processor running compiler A's code?
c. A new compiler is developed that uses only .7E9 instructions and has an
average CPI of 1.3. What is the speedup of using this new compiler versus
using compiler A or B on the original processor?
Solution:

a)
With a clock cycle of 1.3 ns (nanosecond) (10-9), we have a clock rate of 1x109 cycles
per second or Hz
𝐶𝑃𝐼 (𝑐𝑦𝑐𝑙𝑒𝑠 𝑝𝑒𝑟 𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛)=𝑒𝑥𝑒𝑐𝑢𝑡𝑖𝑜𝑛 𝑡𝑖𝑚𝑒 × 𝑐𝑙𝑜𝑐𝑘 𝑟𝑎𝑡𝑒/𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑠

• 𝐶𝑃𝐼𝐴 = 1.2 × 1.3×109/1.3×109=1.2

• 𝐶𝑃𝐼𝐵 = 2.5 × 1.3×109/1.5×109=2.16

b)

𝑐𝑙𝑜𝑐𝑘 𝑐𝑦𝑐𝑙𝑒𝑠=𝐼𝐶 (𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛 𝑐𝑜𝑢𝑛𝑡) ×𝐶𝑃𝐼 (𝑐𝑦𝑐𝑙𝑒𝑠 𝑝𝑒𝑟 𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛)

• Speed (A) = 1.3×109 ×1.2=1.5×109
• Speed (B) = 1.5×109 ×2.5=3.75×109

𝑠𝑝𝑒𝑒𝑑A/𝑠𝑝𝑒𝑒𝑑B=1.5×109 /3.75×109=0.4

c)

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𝑇𝑖𝑚𝑒𝑛𝑒𝑤𝐴= 𝐼𝐶𝑛𝑒𝑤/𝐶𝑃𝐼𝐴= 0.7×109/1.2 = 0.58×109

𝑇𝑖𝑚𝑒𝑛𝑒𝑤𝐵=𝐼𝐶𝑛𝑒𝑤/𝐶𝑃𝐼𝐵= 0.7×109/2.16 =0.32×109

𝑇𝑖𝑚𝑒𝐴=𝐼𝐶A/𝐶𝑃𝐼𝐴= 1.3×109/1.2 = 1.08 X 109

𝑇𝑖𝑚𝑒B=𝐼𝐶B/𝐶𝑃𝐼B= 1.5×109/2.5 = 0.6 X 109

TimeA/TimenewA = 1.08 X 109 / 0.58×109 = 1.86

TimeA/TimenewA = 0.6 X 109 / 0.32×109 = 1.87

7.Solve the following problem:

An application that has a component takes up about 5% of the runtime and
it is not parallelizable. The program is running on a 50 cores system.
Assume that the program runs at the same speed on all those cores and
there are no additional overheads, what is the parallel speedup?

Solution :

B = 0.05 (%5 not parallelizable)

n = 50

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Based on Amdahl’s Law, we get value of S = 14.49

8. Copy the following code segment to this website https://godbolt.org/:

/**
Generate a mips gcc 5.4 assembly code for the following C code. Copy
the mips assembly code into a file.

Fix it up so that you can run using JsSpim software located here:

https://shawnzhong.github.io/JsSpim/. You can also use QtSPIM installed

on your VM.

Describe important content of sp, fp and related contents at the

following state:

1. main(): Before executing the first line.

2. main(): The line before you invoke the function special_formula()
3. special_formula(): The first line
4. special_formula(): The last line before you return to main()
5. main(): The line when you return from special_formula()
6. main(): Before it exits

*/

int special_formula(int f1, int f2, int f3, int f4, int f5) {
int f9 = 1234;

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int result = (f1 + f2) * (f3 - f4) + f5;

result *= f9;
return result;
}

int main() {
int f1 = 123;
int f2 = 456;
int f4 = special_formula(12.0, 11.0, f1, f2, 0.5);
}

 Generate a mips gcc 5.4 assembly code for the following C code. Copy the mips
assembly code into a file.
 Fix it up so that you can run using JsSpim software located here:
https://shawnzhong.github.io/JsSpim/.
You can also use QtSPIM installed on your VM instead.

 Describe thoroughly the state of $sp, $fp and related registers and memory
content (pointed by $sp and $fp).

1. main(): Before executing the first line.

2. main(): The line before you invoke the function special_formula()
3. special_formula(): The first line
4. special_formula(): The last line before you return to main()
5. main(): The line when you return from special_formula()
6. main(): Before it exits

 It is best to simply copy and paste screen using Windows Snipping or the like.

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Solution

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Useful formulas
clock rate
Instructions per second =
cycles per instruction

number of cycles
Number of instructions =
number of instructions per cycle

number of instructions × cycles per instruction

Clock rate = run( seconds)¿
time ¿

execution time ×clock rate

CPI (cycles per instruction)=
number of instructions

clock cycles=IC ( instruction count ) × CPI (cycles per instruction)

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