Module2b BEE
Module2b BEE
Definition: FET is a three terminal electronic device used for variety of applications that
match with BJT. In FET, an electric field is established by the charges present, which
controls the conduction path of the output circuit without the need for direct contact between
controlling and controlled quantities. In a Field effect device current is controlled by the
action of an electron field, rather than carrier injection.
TYPES OF FETS:
1. Junction Field Effect Transistors(JFETs)
2. Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).
2.2.1 OPERATION: Fig 2.2 shows the working of n-channel JFET for different gate-source
voltage (VGS) and drain to source voltage (VDS) = 0V.
As VDS is increased further, the drain current increases. When VDS = VP, the depletion
region widens causing reduction in the channel width.
The reduced path of conduction causes the resistance to increase and the current
saturates.
When VDS is further increased, the two deletion regions touch resulting in pinch-off
condition.
The drain characteristics plot of ID vs VDS for VGS = constant is as shown in fig 2.3.
The region to the left of pinch off locus is called ohmic region and the region to the
right of pinch-off locus is saturation region.
This region of JFET is employed for linear amplifiers. In ohmic region JFET can be
employed as a variable resistor.
The resistance is controlled by VGS. As VGS becomes more and more negative, the
slope of the characteristics becomes more and more horizontal indicating increasing
Lokeshwari H S, Asst. Prof., Dept. of ECE, RIT, Hassan 3
MODULE-2 FET
resistance level.
The resistance is given by the equation 1.
The resulting saturation level for ID is reduced and will continue to decrease as VGS
is made more and more positive.
The drain characteristics are as shown in fig 8 for different values of VGS. When
VGS = -VP, pinch-off condition occurs resulting in ID = 0. VP is called pinch off
voltage.
Symbols of JFET: Fig 2.9(a) and 2.9 (b) shows the symbols of n-channel and p- channel
FET respectively.
Fig 2.9: JFET Symbols. (a) n-Channel JFET (b) p-channel JFET
Condition1: VGS = 0
Therefore ID = IDSS.
Condition 2:VGS = VP
Therefore from equation 1, ID = 0mA.
Condition 3: VGS = VP/2
Therefore from equation 1
ID = IDSS/4
Case ii: VGS = -ve Voltage and VDS = +ve small voltage
The negative potential at the gate will cause the electrons to move towards p-type
substrate as charges repel while holes from p-type substrate are attracted toward gate.
Depending on the magnitude of negative bias established by VGS, a level of
recombination between electrons and holes will occur that will reduce the number of
Case iii: VGS = +ve Voltage and VDS = +ve small voltage
For positive values of VGS, the +ve gate will draw additional electrons from p-type
substrate as minority charge carriers are attracted towards gate.
New carriers are generated due to collisions and ID will increase at a rapid rate.
Thus, application of +VGS has enhanced the level of free carriers in the channel
compared to VGS = 0V.
The region of +ve gate voltage on the drain or transfer characteristics is referred as
enhancement region.
The region between the cut-off and the saturation level of IDSS is refereed as the
depletion region.
Transfer characteristics are a plot of ID as a function of VGS with VDS as constant.
Shockley Equation as in equation 2 is used to plot transfer characteristics.
Case ii: VGS = +ve Voltage and VDS = -ve small voltage
The positive potential at the gate will cause the holes to move towards n-type
substrate as charges repel while electrons from n-type substrate are attracted toward
gate.
Depending on the magnitude of positive bias established by VGS, a level of
Case iii: VGS = -ve Voltage and VDS = -ve small voltage
For positive values of VGS, the -ve gate will draw additional holes from n-type
substrate as minority charge carriers are attracted towards gate.
New carriers are generated due to collisions and ID will increase at a rapid rate.
Thus, application of -VGS has enhanced the level of free carriers in the channel
compared to VGS = 0V.
Transfer characteristics are a plot of ID as a function of VGS with VDS as constant.
Shockley Equation as in equation 2 is used to plot transfer characteristics
Fig 13 (a) n-channel depletion type MOSFET (b) p-channel depletion type MOSFET
The source and drain terminals are taken out through metallic contacts to n- doped
regions as shown in fig 2.14.
Metal is deposited on SiO2 to create Gate.
The presence of SiO2 between gate and p-substrate provides electrical isolation
between the two regions.
No channel exists between source and drain in E-MOSFET.
A positive VGS has caused a thin layer of negative charges to be formed in the
substrate under the gate. Thus, channel is said to be created.
The value of VGS which causes channel to be formed under the gate is called threshold
voltage (VT).
A small ID flows.
When VGS is increased above VT, conductivity of the channel is enhanced and thus
pulling more electrons into the channel.
Thus ID increases steadily when VGS> VT and ID is zero when VGS< VT.
A negative VGS has caused a thin layer of positive charges to be formed in the
substrate under the gate. Thus, channel is said to be created.
The value of VGS which causes channel to be formed under the gate is called
threshold voltage (VT). A small ID flows.
When VGS is decreased below VT, conductivity of the channel is enhanced and thus
pulling more electrons into the channel.
When VGS>VT, there is no channel. Since channel is formed by the application of -
VGS, the type of MOSFET isEnhancement type.
The drain characteristics are as shown in fig 2.17 (c).
2.8.3 E-MOSFET SYMBOLS: Fig 2.18 (a) and 2.18(b) shows the symbols of n-channel and
p-channel E-MOSFET