CDCDB 803

CDCDB803
SNAS820A – AUGUST 2021 – REVISED MAY 2022
CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6
1 Features 2 Applications
• Microserver & tower server
• 8 LP-HCSL outputs with programmable integrated
• Storage area network & host bus adapter card
85-Ω (default) or 100-Ω differential output
• Network attached storage
terminations
• Hardware accelerator
• 8 hardware output enable (OE#) controls
• Rack server
• Additive phase jitter after PCIE Gen 6 filter: 20 fs,
RMS (maximum) 3 Description
• Additive phase jitter after PCIE Gen 5 filter: 25 fs,
The CDCDB803 is a 8-output LP-HCSL, DB800ZL-
RMS (maximum)
compliant, clock buffer capable of distributing the
• Additive phase jitter after DB2000Q filter: 38 fs,
reference clock for PCIe Gen 1-6, QuickPath
RMS (maximum)
Interconnect (QPI), UPI, SAS, and SATA interfaces.
• Supports Common Clock (CC) and Individual
The SMBus interface and eight output enable pins
Reference (IR) architectures
allow the configuration and control of all eight
– Spread spectrum-compatible outputs individually. The CDCDB803 is a DB800ZL
• Output-to-output skew: < 50 ps derivative buffer and meets or exceeds the system
• Input-to-output delay: < 3 ns parameters in the DB800ZL specification. It also
• Fail-safe input meets or exceeds the parameters in the DB2000Q
• Programmable output slew rate control specification. The CDCDB803 is packaged in a 6-mm
• 9 selectable SMBus addresses × 6-mm, 48-pin VQFN package.
• 3.3-V core and IO supply voltages
• Hardware-controlled low power mode (PD#) Device Information
• Current consumption: 72 mA maximum PART NUMBER PACKAGE(1) BODY SIZE (NOM)
• 6-mm × 6-mm, 48-pin VQFN package CDCDB803 VQFN (48) 6.00 mm × 6.00 mm
(1) For all available packages, see the orderable addendum at

the end of the data sheet.
PCIe PHY
PCIe Gen 4-5 LP-HCSL 8 PCIe PHY
CDCDB803 PCIe PHY
Clock PCIe PHY
8x LP-HSCL Output Buffer PCIe PHY
Generator PCIe PHY
PCIe Device
LP-HCSL
SMBus OE#
Control Control
Control Interface
CDCDB803 System Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCDB803
SNAS820A – AUGUST 2021 – REVISED MAY 2022 www.ti.com
Table of Contents
1 Features............................................................................1 8.5 Programming............................................................ 14
2 Applications..................................................................... 1 8.6 Register Maps...........................................................16
3 Description.......................................................................1 9 Application and Implementation.................................. 20
4 Revision History.............................................................. 2 9.1 Application Information............................................. 20
5 Pin Configuration and Functions...................................3 9.2 Typical Application.................................................... 20
6 Specifications.................................................................. 6 10 Power Supply Recommendations..............................22
6.1 Absolute Maximum Ratings ....................................... 6 11 Layout........................................................................... 23
6.2 ESD Ratings .............................................................. 6 11.1 Layout Guidelines................................................... 23
6.3 Recommended Operating Conditions ........................6 11.2 Layout Examples.....................................................23
6.4 Thermal Information ...................................................6 12 Device and Documentation Support..........................25
6.5 Electrical Characteristics ............................................7 12.1 Device Support....................................................... 25
6.6 Timing Requirements ................................................. 9 12.2 Receiving Notification of Documentation Updates..25
6.7 Typical Characteristics.............................................. 10 12.3 Support Resources................................................. 25
7 Parameter Measurement Information.......................... 11 12.4 Trademarks............................................................. 25
8 Detailed Description......................................................12 12.5 Electrostatic Discharge Caution..............................25
8.1 Overview................................................................... 12 12.6 Glossary..................................................................25
8.2 Functional Block Diagram......................................... 12 13 Mechanical, Packaging, and Orderable
8.3 Feature Description...................................................12 Information.................................................................... 25
8.4 Device Functional Modes..........................................13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (August 2021) to Revision A (May 2022) Page

• Changed the data sheet title...............................................................................................................................1
• Added PCIe Gen 6 to the data sheet..................................................................................................................1
• Changed the pin descriptions for pins 5, 8 and 46............................................................................................. 3
2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CDCDB803

CDCDB803
www.ti.com SNAS820A – AUGUST 2021 – REVISED MAY 2022
5 Pin Configuration and Functions
SMBWRTLOCK
CK7_N
CK7_P
OE7#
OE6#
VDD
VDD
VDD
NC
NC
NC
NC
48
47
46
45
44
43
42
41
40
39
38
37
CKPWRGD_PD# 1 36 CK6_N
VDDR 2 35 CK6_P
CLKIN_P 3 34 VDD
CLKIN_N 4 33 CK5_N
SADR0 5 32 CK5_P
SMBDAT 6 31 OE5#
GND
SMBCLK 7 30 OE4#
SADR1 8 29 CK4_N
NC 9 28 CK4_P
NC 10 27 VDD
VDD 11 26 CK3_N
OE0# 12 25 CK3_P
13
14
15
16
17
18
19
20
21
22
23
24
CK0_P
CK0_N
VDD
CK1_P
CK1_N
OE1#
VDD
NC
CK2_P
CK2_N
OE2#
OE3#
Not to scale
Figure 5-1. CDCDB803 RSL Package 48-Pin VQFN Top View
Table 5-1. Pin Functions

PIN
TYPE(2) DESCRIPTION
NAME NO.
INPUT CLOCK
CLKIN_P 3 I LP-HCSL differential clock input. Typically connected directly to the differential
CLKIN_N 4 I output of clock source.
OUTPUT CLOCKS
CK0_P 13 O LP-HCSL differential clock output of channel 0. Typically connected directly to PCIe
CK0_N 14 O differential clock input. If unused, the pins can be left no connect.
Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3

CDCDB803
Table 5-1. Pin Functions (continued)

PIN
TYPE(2) DESCRIPTION
NAME NO.
MANAGEMENT AND CONTROL (1)

Clock Power Good and Power Down multi-function input pin with internal 180-kΩ
pulldown. Typically connected to GPIO of microcontroller. If unused, the pin can
be left no connect. After PWRGD has been asserted high for the first time, the pin
CKPWRGD_PD# 1 I, S, PD
becomes a PD# pin and it controls power-down mode:
LOW: Power-down mode, all output channels tri-stated.
HIGH: Normal operation mode.
Output Enable for channel 0 with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
OE0# 12 I, S, PD
LOW: enable output channel 0.
HIGH: disable output channel 0.
OE1# 18 I, S, PD
OE2# 23 I, S, PD
Output Enable for channel 3, with internal 180-kΩ pulldown, active low. Typically
OE3# 24 I, S, PD
OE4# 30 I, S, PD
OE5# 31 I, S, PD
OE6# 37 I, S, PD
OE7# 41 I, S, PD
SMBUS AND SMBUS ADDRESS

CDCDB803
Table 5-1. Pin Functions (continued)

PIN
TYPE(2) DESCRIPTION
NAME NO.
SMBus address strap bit[0]. This is a 3-level input that is decoded in conjunction
with pin 8 to set SMBus address. It has internal 180-kΩ pullup / pulldown network
biasing to GND when no connect.
For a high-level input configuration, the pin should be pulled up to 3.3-V VDD
SADR0 5 I, S, PU / PD through an external pullup resistor from 1k to 5k with 5% tolerance.
For a low-level input configuration input, the pin should be pulled down to ground
through an external pulldown resistor from 1k to 5k with 5% tolerance.
For a mid-level input configuration, the pin should be left floating and not
connected to VDD or ground.
Data pin of SMBus interface. Typically pulled up to 3.3-V VDD using external pullup
SMBDAT 6 I/O
resistor. The recommended pullup resistor value is > 8.5k.
Clock pin of SMBus interface. Typically pulled up to 3.3-V VDD using external
SMBCLK 7 I
pullup resistor. The recommended pullup resistor value is > 8.5k.
SMBus address strap bit[1]. This is a 3-level input that is decoded in conjunction
with pin B4 to set SMBus address. It has internal 180-kΩ pullup / pulldown network
biasing to GND when no connect.
For a high-level input configuration, the pin should be pulled up to 3.3-V VDD
SADR1 8 I, S, PU / PD through an external pullup resistor from 1k to 5k with 5% tolerance.
For a low-level input configuration, the pin should be pulled down to ground
through an external pulldown resistor from 1k to 5k with 5% tolerance.
For a mid-level input configuration, the pin should be left floating and not
connected to VDD or ground.
SMBWRTLOCK: Disables write commands on SMBus. All writes will be ignored
when SMBWRTLOCK is asserted (reads are not affected). Internal 180-kΩ
SMBWRTLOCK 46 I, PD pulldown, active high.
0 = SMBus write enabled.
1 = SMBus write disabled.
SUPPLY VOLTAGE AND GROUND
Power supply input for input clock receiver. Connect to 3.3-V power supply rail with
VDDR 2 P decoupling capacitor to GND. Place a 0.1-µF capacitor close to each supply pin
between power supply and ground.
11, 15, 19, 27, 34,
VDD P 3.3-V power supply for output channels and core voltage.
38, 42, 44
GND DAP G Ground. Connect ground pad to system ground.
NO CONNECT
NC 9, 10, 20, 43, 45 — Do not connect to GND or VDD.
No connect. Pins may be connected to GND, VDD, or otherwise tied to any
NC 47, 48 —
potential within the Supply Voltage range stated in the Absolute Maximum Ratings.
(1) The “#” symbol at the end of a pin name indicates that the active state occurs when the signal is at a low voltage level. When “#” is not
present, the signal is active high.
(2) The definitions below define the I/O type for each pin.
• I = Input
• O = Output
• I / O = Input / Output
• PU / PD = Internal 180-kΩ Pullup / Pulldown network biasing to VDD/2
• PD = Internal 180-kΩ Pulldown
• S = Hardware Configuration Pin
• P = Power Supply
• G = Ground

CDCDB803
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD, VDD_R Power supply voltage −0.3 3.6 V
VIN IO input voltage −0.3 3.6 V
TJ Junction temperature 125 °C
Tstg Storage temperature −65 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
±3500
JS-001, all pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC
±1000
specification JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD IO, Core supply voltage 3 3.3 3.6 V
VDD_R Input supply voltage 3 3.3 3.6 V
TA Ambient temperature −40 105 °C
6.4 Thermal Information

Device Package
THERMAL METRIC(1) RSL (QFN) UNIT
48 PINS
RθJA Junction-to-ambient thermal resistance 32.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 22.3 °C/W
RθJB Junction-to-board thermal resistance 14.3 °C/W
ΨJT Junction-to-top characterization parameter 0.5 °C/W
ΨJB Junction-to-board characterization parameter 14.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 6.1 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

CDCDB803
6.5 Electrical Characteristics

VDD, VDD_R = 3.3 V ± 5 %, −40°C ≤ TA ≤ 105°C. Typical values are at VDD = VDD_R = 3.3 V, 25°C (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT CONSUMPTION
Active mode. CKPWRGD_PD# = 1 9
IDD_R Core supply current mA
Power-down mode. CKPWRGD_PD# = 0 2.2
All outputs disabled 18
IDD IO supply current All outputs active, 100MHz (Per output) 7.8 mA
Power-down mode. CKPWRGD_PD# = 0 1.5
CLOCK INPUT
fIN Input frequency 50 100 250 MHz
Differential voltage between CLKIN_P and mVDiff-
VIN Input voltage swing 200 2300
CLKIN_N(1) peak
dV/dt Input voltage edge rate 20% - 80% of input swing 0.7 V/ns
DVCROSS Total variation of VCROSS Total variation across VCROSS 140 mV
DCIN Input duty cycle 40 60 %
Differential capacitance between CLKIN_P
CIN Input capacitance(2) 2.2 pF
and CLKIN_N pins
CLOCK OUTPUT
fOUT Output frequency 50 100 250 MHz
Differential capacitance between CKx_P
COUT Output capacitance(1) 4 pF
and CKx_N pins
VOH Output high voltage 225 270
Single-ended(2) (3)
VOL Output low voltage 10 150
Measured into an AC load as defined in
VHIGH Output high voltage 660 850
DB800ZL
VLOW Output low voltage –150 150
DB800ZL
VMAX Output Max voltage 1150
DB800ZL
(3) (4) mV
VCROSS Crossing point voltage 130 200
VCROSSAC Crossing point voltage (AC load) 250 550
DB800ZL
DVCROSS Total variation of VCROSS Variation of VCROSS (3) (4) 35 140
Vovs Overshoot voltage (3) VOH+75
Measured into an AC load as defined in VHIGH+30
Vovs(AC) Overshoot voltage (AC load)
DB800ZL 0
Vuds Undershoot voltage (3) VOL–75
Measured into an AC load as defined in VLOW–
Vuds(AC) Undershoot voltage mV
DB800ZL 300
Vrb Ringback Voltage DB800ZL and taken from Single Ended -0.2 0.2 V
waveform (relative to VHIGH and VLOW)
Differential impedance (Default
Measured at VOL/VOH 81 85 89
setting, 85 Ω)
ZDIFF
Differential impedance (Output
Measured at VOL/VOH 95 100 105
impedance selection bit =1, 100 Ω)
Ω
Differential impedance (Default
Measured at VCROSS 68 85 102
ZDIFF_CROS setting, 85 Ω)
S Differential impedance (Output
Measured at VCROSS 80 100 120
impedance selection bit = 1, 100 Ω)

CDCDB803
noted)
tEDGE Differential edge rate Measured (+-150 mV) around VCROSS (7) 2 4 V/ns
DtEDGE Edge rate matching Measured (+-75 mV) VCROSS (7) 20 %
Measured
when
CKPWRGD_PD# pin
Power good assertion to stable clock positive
tSTABLE transitions from 0 to 1, fIN = 1.8 ms
output output
100 MHz
reaches
0.2V
Measured
when
CKPWRGD_PD# pin
Power good assertion to outputs positive
tDRIVE_PD# transitions from 0 to 1, fIN = 300 µs
driven high output
100 MHz
reaches
0.2V
Output enable assertion to stable
tOE OEx# pin transitions from 1 to 0 10
clock output
Output enable de-assertion to no CLKIN
tOD OEx# pin transitions from 0 to 1 10
clock output Periods
Power-down assertion to no clock
tPD CKPWRGD_PD# pin transitions from 1 to 0 3
output
tDCD Duty cycle distortion Differential; fIN = 100MHz, fIN_DC = 50% –1 1 %
tDLY Propagation delay (5) 0.5 3 ns
tSKEW Skew between outputs (6) 50 ps
tDELAY(IN- Input-to-output delay variation at 100 MHz
Input to output delay variation –250 250 ps
OUT) across voltage and temperature
JCKx_DB2000 DB2000Q filter, for input of 200 mV
(7) Additive jitter for DB2000Q 0.038 ps, RMS
Q differential swing @ 1.5 V/ns
Input clock
PLL BW: 0.5 - 1 MHz; CDR =
Additive jitter for PCIe6.0 slew rate = 0.02
10 MHz
2 V/ns
Additive jitter for PCIe5.0 PCIe5.0 filter 0.025
JCKx_PCIE Input clock
(7) ps, RMS
Additive jitter for PCIe4.0 slew rate ≥ 0.06
PLL BW = 2 - 5 MHz; CDR = 1.8 V/ns
10 MHz Input clock
Additive jitter for PCIe3.0 slew rate ≥ 0.1
0.6 V/ns
fIN = 100 MHz; slew rate ≥ 3 V/ns; 12 kHz to
JCKx Additive jitter 100 160 fs, RMS
20 MHz integration bandwidth.
Input clock
NF Noise floor fIN = 100 MHz; fOffset ≥ 10 MHz slew rate ≥ –160 -155 dBc/Hz
3 V/ns
SMBUS INTERFACE, OEx#, CKPWRGD_PD#
VIH High level input voltage 2.0
V
VIL Low level input voltage 0.8
GND ≤ VIN
IIH Input leakage current With internal pull-up/pull-down –30 30 µA
≤ VDD
GND ≤ VIN
IIL Input leakage current With internal pull-up/pull-down –30 30 µA
≤ VDD
Without internal pull-up/pull- GND ≤ VIN
IIH Input leakage current −5 5 µA
down ≤ VDD
Without internal pull-up/pull- GND ≤ VIN
IIL Input leakage current −5 5 µA
down ≤ VDD

CDCDB803
noted)
CIN Input capacitance 4.5 pF
COUT Output capacitance 4.5 pF
3-LEVEL DIGITAL INTERFACE (SADR0, SADR1)
VIH High level input voltage 2.3
VIM Mid level input voltage 1.25 VDD/2 1.725 V
VIL Low level input voltage 0.85
IIH Input leakage current With internal pull-up/pull-down VIN = VDD –30 30 µA
IIL Input leakage current With internal pull-up/pull-down VIN = GND –30 30 µA
CIN Input capacitance(1) 4.5 pF
(1) Voltage swing includes overshoot.

(2) Not tested in production. Ensured by design and characterization.
(3) Measured into DC test load.
(4) VCROSS is single-ended voltage when CKx_P = CKx_N with respect to system ground. Only valid on rising edge of CKx, when CKx_P
is rising.
(5) Measured from rising edge of CLK_IN to any CKx output.
(6) Measured from rising edge of any CKx output to any other CKx output.
(7) Measured into AC test load.
6.6 Timing Requirements

VDD, VDD_R = 3.3 V ± 5 %, −40°C ≤ TA ≤ 105°C. Typical values are at VDD = VDD_A = 3.3 V, 25°C (unless otherwise
noted)
MIN NOM MAX UNIT
SMBUS-COMPATIBLE INTERFACE TIMING
fSMB SMBus operating frequency 10 400 kHz
tBUF Bus free time between STOP and START 4.7
tHD_STA START condition hold time SMBCLK low after SMBDAT low 4
µs
tSU_STA START condition setup time SMBCLK high before SMBDAT low 4.7
tSU_STO STOP condition setup time 4
tHD_DAT SMBDAT hold time 300
ns
tSU_DAT SMBDAT setup time 250
tTIMEOUT Detect SMBCLK low timeout In terms of device input clock frequency 1e6 cycles
tLOW SMBCLK low period 4.7
µs
tHIGH SMBCLK high period 4 50
tF SMBCLK/SMBDAT fall time(1) 300
ns
tR SMBCLK/SMBDAT rise time(2) 1000
(1) TF = (VIHMIN + 0.15) to (VILMAX - 0.15)

(2) TR = (VILMAX - 0.15) to (VIHMIN + 0.15)

CDCDB803
6.7 Typical Characteristics

Figure 6-1 shows both the phase noise of the source as well as the output of the DUT (CDCDB803). It can be seen from the
phase noise plot that the DUT has a very low phase noise profile with total jitter of 71 fs, rms. If we rms subtract the clock
reference noise, the additive jitter of CDCDB803 under typical conditions would be lower than 71 fs, rms.
Figure 6-1. CDCDB803 Clock Out (CK0:8) Phase Noise

CDCDB803
7 Parameter Measurement Information
10 inches/ 25.4 cm < 1 pF

CK+ GND
DUT Differential impedance 85 >100 k

CK-
High
< 1 pF
2 pF 2 pF
Impedance
GND
Probe
Figure 7-1. AC Test Load (Referencing Intel DB2000QL Document)
0.75 V
85
R1 SMA
CK+
R2
0.75 V
DUT
85
CK- R1 GND SMA
R2
50
42.5 85 GND
R1 = 47 Ω and R2 = 147 Ω.
Figure 7-2. DC Simulation Load (Referencing Intel DB2000QL Document)

CDCDB803
8 Detailed Description
8.1 Overview
The CDCDB803 is a low additive-jitter, low propagation delay clock buffer designed to meet the strict
performance requirements for PCIe Gen 1-6, QPI, UPI, SAS, and SATA reference clocks. The CDCDB803
allows buffering and replication of a single clock source to up to eight individual outputs in the LP-HCSL format.
The CDCDB803 also includes status and control registers accessible by an SMBus version 2.0 compliant
interface. The device integrates a large amount of external passive components to reduce overall system cost.
8.2 Functional Block Diagram
CLKIN_P CK0_P
CLKIN_N CK0_N
CK1_P
CK1_N
CK2_P
CK2_N
CK3_P
CK3_N
OE[7:0]# Glitch
Free
Output
.....
Control
Logic
CK7_P
SMBDAT
SMBCLK CK7_N
SMBWRTLOCK
SADR0 Control
SADR1 Logic
CKPWRGD_PD#
8.3 Feature Description

8.3.1 Fail-Safe Input
The CDCDB803 is designed to support fail-safe input operation feature. This feature allows the user to drive the
device inputs before VDD is applied without damaging the device. Refer to the Absolute Maximum Ratings table
for more information on the maximum input supported by the device.
8.3.2 Output Enable Control
The CDCDB803 uses SMBus and OE# to control the state of the output channels. The OE# pins control the
state of the output with the same number. For example, the OE5# pin controls the state of the CK5 output driver.
The SMBus registers may enable or disable the output when the corresponding OE# pin is held low.
8.3.3 SMBus
The CDCDB803 has an SMBus interface that is active only when CKPWRGD_PD# = 1. The SMBus allows
individual enable/disable of each output.
When CKPWRGD_PD# = 0, the SMBus pins are placed in a Hi-Z state, but all register settings are retained. The
SMBus register values are only retained while VDD remains inside of the recommended operating voltage.
8.3.3.1 SMBus Address Assignment
The SMBus address is assigned by configuration of two pins (SADR1 and SADR0) that each support three
levels. This configuration allows the CDCDB803 to assume nine different SMBus addresses.

CDCDB803
The SMBus address pins are sampled when PWRGD is set to 1. See Table 8-1 for address pin configuration.
The address can only be changed by power cycling the device.
Table 8-1. SMBus Address Assignment
SMBus ADDRESS : WRITE SMBus ADDRESS : READ
SADR1 SADR0
OPERATION (READ/WRITE=0) OPERATION (READ/WRITE=1)
L L 0xD8 0xD9
L M 0xDA 0xDB
L H 0xDE 0xDF
M L 0xC2 0xC3
M M 0xC4 0xC5
M H 0xC6 0xC7
H L 0xCA 0xCB
H M 0xCC 0xCD
H H 0xCE 0xCF
8.4 Device Functional Modes

8.4.1 CKPWRGD_PD# Function
The CKPWRGD_PD# pin is used to set two state variables inside of the device: PWRGD and PD#. The PWRGD
and PD# variables control which functions of the device are active at any time, as well as the state of the input
and output pins.
The PWRGD and PD# states are multiplexed on the CKPWRGD_PD# pin. CKPWRGD_PD# must remain below
VOL and not exceed VDDR + 0.3 V until VDD and VDDR are present and within the recommended operating
conditions. After CKPWRGD_PD# is set high, a valid CLKIN must be present to use PD#.
The first rising edge of the CKPWRGD_PD# pin sets PWRGD = 1. After PWRGD is set to 1, the
CKPWRGD_PD# pin is used to assert PD# mode only. PWRGD variable will only be cleared to 0 with the
removal of VDD and VDDR.
VDD/VDDR
CKPWRGD_PD#
PWRGD
PD#
Figure 8-1. PWRGD and PD# State Changes

CDCDB803
8.4.2 OE[7:0]# and SMBus Output Enables

Each output channel, 0 to 7, can be individually enabled or disabled by a SMBus control register bit, called
SMB enable bits. Additionally, each output channel has a dedicated, corresponding, OE[7:0]# hardware pin. The
OE[7:0]# pins are asynchronously asserted-low signals that may enable or disable the output.
Refer to Table 8-2 for enabling and disabling outputs through the hardware and software. Note that both the
SMB enable bit must be a 1 and the OEx# pin must be an input low voltage 0 for the output channel to be active.
Table 8-2. OE[7:0]# Functionality
Power State Variables OE[7:0]# HARDWARE PINS AND SMBus
Control Inputs
(Internal) CONTROL REGISTER BITS CK[7:0]_P/
CLKIN
CKPWRGD_P OUT_EN_CLK[ DRIVE_OP_ST CK[7:0]_N
PWRGD PD# OE[7:0]#
D# 7:0] ATE_CTRL
0 0 0 X X X X LOW/LOW
0 LOW/LOW
X 0
1 TRI-STATE
X(1)
1 1 0 LOW/LOW
1 X
1 1 TRI-STATE
Running(1) 0 1 X Running
0 LOW/LOW
0 0 X(2) X X
1 TRI-STATE
(1) To enter the power-down state, CLKIN must remain active for at least 3 clock cycles after CKPWRGD_PD# transitions from 1 to 0.
(2) To enter the powered-up state with active clock outputs, CLKIN must be active before CKPWRGD_PD# transitions from 0 to 1.
8.4.3 Output Slew Rate Control

The CDCDB803 provides output slew rate control feature which customer can use to compensate for increased
output trace length based on their board design. The slew rate of a bank of 4 outputs 0 to 3 and 4 to 7, can
be changed within a given range by a SMBus control register called CAPTRIM. Refer to Table 8-16 for more
information.
8.4.4 Output Impedance Control
The integrated termination on the CDCDB803 can be programmed either for 85 Ω or 100 Ω. This flexibility
ensures that the customer can use the same device across various applications irrespective of the characteristic
board impedance which is typically either 85 Ω or 100 Ω. This termination resistor can be changed for all the
outputs as whole using bit 5 of a register called OUTSET. Refer to Table 8-14 for more information.
8.5 Programming
The CDCDB803 uses SMBus to program the states of its eight output drivers. See SMBus for more information
on the SMBus programming, and Register Maps for information on the registers.
Table 8-3. Command Code Definition
BIT DESCRIPTION
0 = Block Read or Block Write operation
7
1 = Byte Read or Byte Write operation
(6:0) Register address for Byte operations, or starting register address for Block, operations

CDCDB803
1 7 1 1 8 1 1
S Peripheral Address R/W A Data Byte A P
MSB LSB MSB LSB
S Start Condition
Sr Repeated Start Condition
R/W 1 = Read (Rd); 0 = Write (Wr)

A Acknowledge (ACK = 0 and NACK =1)
P Stop Condition
Controller-to-Peripheral Transmission
Peripheral-to-Controller Transmission
Figure 8-2. Generic Programming Sequence

1 7 1 1 8 1 8 1 1
S Peripheral Address Wr A CommandCode A Data Byte A P
Figure 8-3. Byte Write Protocol
1 7 1 1 8 1 1 7 1 1
S Peripheral Address Wr A CommandCode A S Peripheral Address Rd A
8 1 1
Data Byte A P
1
Figure 8-4. Byte Read Protocol
1 7 1 1 8 1 8 1
S Peripheral Address Wr A CommandCode A Byte Count = N A
8 1 8 1 8 1 1
Data Byte 0 A Data Byte 1 A … Data Byte N-1 A P
Figure 8-5. Block Write Protocol
1 7 1 1 8 1 1 7 1 1
S Peripheral Address Wr A CommandCode A S Peripheral Address Rd A
8 1 8 1 8 1 1
Data Byte N A Data Byte 0 A Data Byte N-1 A P
1 1 1
Figure 8-6. Block Read Protocol
tLOW
tR tF
VIH
SMBCLK
VIL
tHD_STA tHIGH tSU_STA tSU_STO
ttBUFt tHD_DAT tSU_DAT
VIH
SMBDAT
VIL
P S P
Figure 8-7. SMBus Timing Diagram

CDCDB803
8.6 Register Maps

8.6.1 CDCDB803 Registers
Table 8-4 lists the CDCDB803 registers. All register locations not listed in Table 8-4 should be considered as
reserved locations and the register contents should not be modified.
Table 8-4. CDCDB803 Registers
Address Acronym Register Name Section
0h RCR1 Reserved Control Register 1 Go
1h OECR1 Output Enable Control 1 Go
2h OECR2 Output Enable Control 2 Go
3h OERDBK Output Enable# Pin Read Back Go
4h RCR2 Reserved Control Register 2 Go
5h VDRREVID Vendor/Revision Identification Go
6h DEVID Device Identification Go
7h BTRDCNT Byte Read Count Control Go
8h OUTSET Output Setting Control Go
4Ch CAPTRIM Slew Rate Capacitor Cluster 1 & 2 Go
Complex bit access types are encoded to fit into small table cells. Table 8-5 shows the codes that are used for
access types in this section.
Table 8-5. CDCDB803 Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value
8.6.1.1 RCR1 Register (Address = 0h) [reset = 47h]

RCR1 is shown in Table 8-6.
Return to the Summary Table.
The RCR1 register contains reserved bits.
Table 8-6. RCR1 Register Field Descriptions
Bit Field Type Reset Description
7-4 Reserved R 4h Reserved.
3-0 Reserved R/W 7h Writing to these bits will not affect the functionality of the device.
8.6.1.2 OECR1 Register (Address = 1h) [reset = FFh]

OECR1 is shown in OECR1 Register Field Descriptions.
The OECR1 register contains bits that enable or disable individual output clock channels [5:0].

CDCDB803
Table 8-7. OECR1 Register Field Descriptions

7 OUT_EN_CLK5 R/W 1h This bit controls the output enable signal for output channel CK5_P/
CK5_N.
0h = Output Disabled
1h = Output Enabled
CK4_N.
1h = Output Enabled
CK3_N.
1h = Output Enabled
CK2_N.
1h = Output Enabled
3 Reserved R/W 1h Writing to this bit will not affect the functionality of the device.
CK1_N.
1h = Output Enabled
CK0_N.
1h = Output Enabled
8.6.1.3 OECR2 Register (Address = 2h) [reset = 0Fh]

OECR2 is shown in OECR2 Register Field Descriptions.
The OECR2 register contains bits that enable or disable individual output clock channels [7:6].
Table 8-8. OECR2 Register Field Descriptions
CK7_N.
1h = Output Enabled
CK6_N.
1h = Output Enabled
8.6.1.4 OERDBK Register (Address = 3h) [reset = 0h]

OERDBK is shown in Table 8-9.

CDCDB803
The OERDBK register contains bits that report the current state of the OE[7:0]# input pins.
Table 8-9. OERDBK Register Field Descriptions
7 RB_OE7 R 0h This bit reports the logic level present on the OE7# pin.
8.6.1.5 RCR2 Register (Address = 4h) [reset = 0h]

RCR2 is shown in RCR2 Register Field Descriptions.
The RCR2 register contains reserved bits.
Table 8-10. RCR2 Register Field Descriptions
8.6.1.6 VDRREVID Register (Address = 5h) [reset = 0Ah]

VDRREVID is shown in Table 8-11.
The VDRREVID register contains a vendor identification code and silicon revision code.
Table 8-11. VDRREVID Register Field Descriptions
7-4 REV_ID R 0h Silicon revision code.
Silicon revision code bits
[3:0] map to register bits
[7:4] directly.
3-0 VENDOR_ID R Ah Vendor identification code.
Vendor ID bits
[3:0] map to register bits
[3:0] directly.
8.6.1.7 DEVID Register (Address = 6h) [reset = E7h]

DEVID is shown in Table 8-12.
The DEVID register contains a device identification code.
Table 8-12. DEVID Register Field Descriptions
7-0 DEV_ID R E7h Device ID code.
Device ID bits[7:0] map to register bits[7:0] directly.

CDCDB803
8.6.1.8 BTRDCNT Register (Address = 7h) [reset = 8h]

BTRDCNT is shown in Table 8-13.
The BTRDCNT register contains bits [4:0] which configure the number of bytes which will be read back.
Table 8-13. BTRDCNT Register Field Descriptions
4 BYTE_COUNTER R/W 0h
Writing to this register configures how many bytes will be read back.
3-0 BYTE_COUNTER R/W 8h
8.6.1.9 OUTSET Register (Address = 8h) [reset = 0h]

OUTSET is shown in Table 8-14.
Bit5 of the OUTSET register sets the termination for all the outputs while bit4 can be used to set the power-down
state for all outputs. The remaining bits for this register are reserved.
Table 8-14. OUTSET Register Field Descriptions
5 CH_ZOUT_SEL R/W 0h Select between 85 Ω (0) and 100 Ω (1) Output impedance
4 d_DRIVE_OP_STATE_CTRL R/W 0h Power-down state of all output clocks.
0: LOW/LOW
1: TRI_STATE
3-0 Reserved R/W 0h Register bits can be written to 0. Writing a different value than 0
will affect device functionality.
8.6.1.10 CAPTRIM Register (Address = 4Ch) [reset = 66h]

CAPTRIM is shown in Table 8-16.
Bits [7:4] of the CAPTRIM register is used to control the slew rate for output channel cluster 2. Bits [3:0] control
the slew rate for output channel cluster 1. Refer below for cluster identification.
Table 8-15. Cluster Identification
Cluster Outputs
1 CK3, CK2, CK1, CK0
2 CK7, CK6, CK5, CK4
Table 8-16. CAPTRIM Register Field Descriptions

7-4 CLUSTER2_CAP_TRIM R/W 6h Slew Rate Reduction Cap Trim for Cluster 2. Default value of 6h.
0: minimum
F: maximum
3-0 CLUSTER1_CAP_TRIM R/W 6h Slew Rate Reduction Cap Trim for Cluster 1. Default value of 6h.
0: minimum
F: maximum

CDCDB803
9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information

The CDCDB803 is a fanout buffer that supports PCIe generation 4 and PCIe generation 5 REFCLK distribution.
The device is used to distribute up to eight copies of a typically 100-MHz clock.
9.2 Typical Application
Figure 9-1 shows a CDCDB803 typical application. In this application, a clock generator provides a 100-MHz
reference to the CDCDB803 which then distributes that clock to PCIe endpoints. The clock generator may be
a discrete clock generator like the CDCI6214 or it may be integrated in a larger component such as a Platform
Controller Hub (PCH) or application processor.
PCIe PHY
PCIe Gen 4-5 LP-HCSL 8 PCIe PHY
CDCDB803 PCIe PHY
Clock PCIe PHY
8x LP-HSCL Output Buffer PCIe PHY
Generator PCIe PHY
PCIe Device
LP-HCSL
SMBus OE#
Control Control
Control Interface
Figure 9-1. Typical Application
9.2.1 Design Requirements

Consider a typical server motherboard application which must distribute a 100-MHz PCIe reference clock from
the PCH of a processor chipset to multiple endpoints. An example of clock input and output requirements is:
• Clock Input:
– 100-MHz LP-HCSL
• Clock Output:
– 2x 100-MHz to processors, LP-HCSL
– 3x 100-MHz to riser/retimer, LP-HCSL
– 3x 100-MHz to DDR memory controller, LP-HCSL

CDCDB803
9.2.2 Detailed Design Procedure

The following items must be determined before starting design of a CDCDB803 socket:
• Output Enable Control Method
• SMBus address
9.2.2.1 Output Enable Control Method
The device provides an option to either use SMBus programmed registers (software) to control the outputs or by
using the hardware OE# pins. In case of using software to control the outputs, the hardware OE# pins can be left
floating as each of these pins have a pulldown to ground. Refer to Table 8-2 and the Register Maps section for
more information on programming the register.
When the user wants to control the outputs with the hardware OE# pins, they can do so for example by
connecting these pins to a GPIO controller and follow the Pin Configuration and Functions section to set the
outputs to HIGH/LOW. The bits OUT_EN_CLK7 to OUT_EN_CLK0 used to control the outputs are shown in
registers OECR1 (Table 8-7) and OECR2 (Table 8-8). These register bits are set to 1 by default to ensure that
the outputs are "software enabled" and their state is therefore set by hardware OE# pins.
9.2.2.2 SMBus Address
An SMBus address should be selected from the listed potential addresses in Table 8-1. The appropriate pullup or
pulldown resistor should be placed on the SADRx pins as indicated in the table. Ensure the SMBus address is
not already in use to avoid conflict.
9.2.3 Application Curves
Figure 6-1 in the Typical Characteristics section can be used as both an application curve and a typical
characteristics plot in this example.
The Figure 9-2 and Figure 9-3 show characterization data for the Output slew rate for various CAPTRIM codes
and across temperature. Customers can use these plots as reference for choosing the appropriate output slew
rate based on their system requirement.
5
Slew Rate (V/ns)
2
0 - 3.3 V 4 - 3.3 V 8 - 3.3 V 12 - 3.3 V
1 - 3.3 V 5 - 3.3 V 9 - 3.3 V 13 - 3.3 V
1 2 - 3.3 V 6 - 3.3 V 10 - 3.3 V
3 - 3.3 V 7 - 3.3 V 11 - 3.3 V
0
120 100 80 60 40 20 0 -20 -40 -60
Temperature (qC) D002
. .
Figure 9-2. Output Slew Rate vs. CAPTRIM Code Figure 9-3. Slew Rate Variation Across
Temperature for Different CAPTRIM Code

CDCDB803
10 Power Supply Recommendations

High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
the jitter and phase noise is critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guards the power-supply system
against induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by
the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, place
the capacitors very close to the power-supply terminals and lay out with short loops to minimize inductance. TI
recommends to insert a ferrite bead between the board power supply and the chip power supply that isolates the
high-frequency switching noises generated by the clock buffer. These beads prevent the switching noise from
leaking into the board supply. It is imperative to choose an appropriate ferrite bead with very low DC resistance
to provide adequate isolation between the board supply and the chip supply, as well as to maintain a voltage at
the supply terminals that is greater than the minimum voltage required for proper operation.
Figure 10-1 shows the recommended power supply filtering and decoupling method.
3.3 V VDD
10 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F
3.3 V VDDR
2.2
10 F 0.1 F
Figure 10-1. Power Supply Decoupling

CDCDB803
11 Layout
11.1 Layout Guidelines
The following section provides the layout guidelines to ensure good thermal performance and power supply
connections for the CDCDB803.
In Layout Examples, the CDCDB803 has 85-Ω differential output impedance LP-HCSL format drivers as per
register default settings. All transmission lines connected to CKx pins should be 85-Ω differential impedance,
42.5-Ω single-ended impedance to avoid reflections and increased radiated emissions. If 100-Ω output
impedance is enabled, the transmission lines connected to CKx pins should be 100-Ω differential impedance,
50-Ω single-ended impedance. Take care to eliminate or reduce stubs on the transmission lines.
11.2 Layout Examples
Figure 11-1 through Figure 11-3 are printed circuit board (PCB) layout examples that show the application of
thermal design practices and a low-inductance ground connection between the device DAP and the PCB.
Figure 11-1. PCB Layout Example for CDCDB803, Top layer

CDCDB803
Figure 11-2. PCB Layout Example for CDCDB803, GND Layer
Figure 11-3. PCB Layout Example for CDCDB803, Bottom Layer

CDCDB803
12 Device and Documentation Support

12.1 Device Support
12.1.1 TICS Pro
TICS Pro is an offline software tool for EVM programming and also for register map generation to program a
device configuration for a specific application. For TICS Pro, go to https://www.ti.com/tool/TICSPRO-SW.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 10-Apr-2023
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
CDCDB803RSLR ACTIVE VQFN RSL 48 4000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 CDCB803 Samples
CDCDB803RSLT ACTIVE VQFN RSL 48 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 CDCB803 Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Apr-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDCDB803RSLR VQFN RSL 48 4000 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2
CDCDB803RSLT VQFN RSL 48 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CDCDB803RSLR VQFN RSL 48 4000 367.0 367.0 35.0
CDCDB803RSLT VQFN RSL 48 250 210.0 185.0 35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RSL0048B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
6.1 A
B 5.9
PIN 1 INDEX AREA

6.1
5.9
1 MAX
SEATING PLANE
0.05 0.08 C
0.00
4.4
13 24
44X 0.4
12 23
49 SYMM
4.4 4.5
4.3
1 36
48X 0.25
0.15
PIN 1 IDENTIFICATION
48 37 0.1 C A B
(OPTIONAL)
SYMM
48X 0.5
0.3
0.05 C
4219205/A 02/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
(5.8)
( 4.4)
SYMM
48 37
48X (0.6)
48X (0.2)
1
36
44X (0.4)
10X (1.12) 49 SYMM

(5.8)
6X (0.83) 12 25
(R0.05) TYP
13 24 (Ø0.2) VIA
6X (0.83) 10X (1.12) TYP
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 12X
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND METAL UNDER
METAL
SOLDER MASK
EXPOSED METAL SOLDER MASK EXPOSED SOLDER MASK

OPENING METAL OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS 4219205/A 02/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
(5.8)
SYMM
48 37
48X (0.6)
48X (0.2)
1 49
36
44X (0.4)
16X
( 0.92)
8X (0.56) SYMM
(5.8)
8X (1.12) 12 25
(R0.05) TYP
13 24
METAL TYP
8X (1.12) 8X (0.56)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
70% PRINTED COVERAGE BY AREA
SCALE: 12X
4219205/A 02/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated

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CDCDB803

SNAS820A – AUGUST 2021 – REVISED MAY 2022

CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

(1) For all available packages, see the orderable addendum at

CDCDB803 System Diagram

Changes from Revision * (August 2021) to Revision A (May 2022) Page

2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CDCDB803

5 Pin Configuration and Functions

Figure 5-1. CDCDB803 RSL Package 48-Pin VQFN Top View

Table 5-1. Pin Functions

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3

Table 5-1. Pin Functions (continued)

MANAGEMENT AND CONTROL (1)

4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CDCDB803

Table 5-1. Pin Functions (continued)

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CDCDB803

6.5 Electrical Characteristics

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7

8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CDCDB803

(1) Voltage swing includes overshoot.

6.6 Timing Requirements

(1) TF = (VIHMIN + 0.15) to (VILMAX - 0.15)

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9

6.7 Typical Characteristics

Figure 6-1. CDCDB803 Clock Out (CK0:8) Phase Noise

10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CDCDB803

7 Parameter Measurement Information

10 inches/ 25.4 cm < 1 pF

DUT Differential impedance 85 >100 k

Figure 7-1. AC Test Load (Referencing Intel DB2000QL Document)

CK- R1 GND SMA

Figure 7-2. DC Simulation Load (Referencing Intel DB2000QL Document)

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11

8.3 Feature Description

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Product Folder Links: CDCDB803

8.4 Device Functional Modes

Figure 8-1. PWRGD and PD# State Changes

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13

8.4.2 OE[7:0]# and SMBus Output Enables

8.4.3 Output Slew Rate Control

14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CDCDB803

R/W 1 = Read (Rd); 0 = Write (Wr)

Figure 8-2. Generic Programming Sequence

Figure 8-3. Byte Write Protocol

Figure 8-4. Byte Read Protocol

Figure 8-5. Block Write Protocol

Figure 8-6. Block Read Protocol

Figure 8-7. SMBus Timing Diagram