ECOM 4311

Digital Systems Design

Eng. Monther Abusultan

Computer Engineering Dept.
Islamic University of Gaza

ECOM 4311 - DIGITAL SYSTEMS DESIGN Lecture #17

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 ECOM 4311 - DIGITAL SYSTEMS DESIGN

Lecture #17

• Agenda

1. Counters

ECOM 4311 - DIGITAL SYSTEMS DESIGN Lecture #17

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 Counters

• Counters
- special name of any clocked sequential circuit whose state diagram is a circle

- there are many types of counters, each suited for particular applications

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 Counters

• Binary Counter
- state machine that produces a straight binary count

- for n-flip-flops, 2n counts can be produced

- the Next State Logic "F" is a combinational SOP/POS circuit

- the speed will be limited by the Setup/Hold and Combinational Delay of "F"

- this gives the maximum number of counts for n-flip flops

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 Counters

• Toggle Flop
- a D-Flip-Flop can produce a "Divide-by-2" effect by feeding back Qn to D

- this topology is also called a "Toggle Flop"

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 Counters

• Ripple Counter
- Cascaded Toggle Flops
can be used to form
rippled counter

- this is slower than

a straight binary counter
due to waiting for
the "ripple"

- this is good for low

power, low speed
applications

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 Counters

• Shift Register
- a chain of D-Flip-Flops
that pass data to one
another

- this is good for

"pipelining"

- also good for

Serial-to-Parallel
conversion

- for n-flip-flops, the data

is present at the final
state after n clocks

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 Counters

• Ring Counter
- feeding the output of a
shift register back to the
input creates a
"ring counter"

- also called a
"One Hot"

- The first flip-flop needs

to set to 1, while
the others reset to 0

- for n flip-flops, there

will be n counts

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 Counters

• Johnson Counter
- feeding the inverted
output of a shift register
back to the input creates
a "Johnson Counter"

- this gives more states

with the same reduced
gate count

- all flip-flops can

reset to 0

- for n flip-flops, there

will be 2n counts

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 Counters

• Counters in VHDL
- strong type casting in VHDL can make modeling counters difficult
(at first glance)

- the reason for this is that the STANDARD and STD_LOGIC Packages
do not define "+", "-", or inequality operators for BIT_VECTOR
or STD_LOGIC_VECTOR types

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 Counters

• Counters in VHDL
- there are a couple ways that we get around this

1) Use the STD_LOGIC_UNSIGNED Package

- this package defines "+" and "-" functions for

STD_LOGIC_VECTOR

- we can use +1 just like normal

- the vector will wrap as suspected (1111 - 0000)

- one catch is that we can't assign to a Port

- we need to create an internal signal of STD_LOGIC_VECTOR

for counting

- we then assign to the Port at the end

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 Counters

• Counters in VHDL using STD_LOGIC_UNSIGNED

use IEEE.STD_LOGIC_UNSIGNED.ALL; -- call the package

entity counter is
Port ( Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Direction : in STD_LOGIC;
Count_Out : out STD_LOGIC_VECTOR (3 downto 0));
end counter;

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 Counters

• Counters in VHDL using STD_LOGIC_UNSIGNED

architecture counter_arch of counter is

signal count_temp : std_logic_vector(3 downto 0); -- Notice internal signal

begin
process (Clock, Reset) begin
if (Reset = '0') then
count_temp <= "0000";
elsif (Clock='1' and Clock'event) then
if (Direction='0') then
count_temp <= count_temp + '1';
else
count_temp <= count_temp - '1';
end if;
end if;
end process;
Count_Out <= count_temp; -- assign to Port after the process
end counter_arch;

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 Counters

• Counters in VHDL
2) Use integers for the counter and then convert back to
STD_LOGIC_VECTOR

- STD_LOGIC_ARITH is a Package that defines

a conversion function

- the function is: conv_std_logic_vector (ARG, SIZE)

- functions are defined for ARG = integer, unsigned, signed,

STD_ULOGIC

- SIZE is the number of bits in the vector to convert to, given

as an integer

- we need to keep track of the RANGE and Counter Overflow

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 Counters

• Counters in VHDL using STD_LOGIC_ARITH

use IEEE.STD_LOGIC_ARITH.ALL; -- call the package

entity counter is
Port ( Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Direction : in STD_LOGIC;
Count_Out : out STD_LOGIC_VECTOR (3 downto 0));
end counter;

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 Counters

• Counters in VHDL using STD_LOGIC_ARITH

architecture counter_arch of counter is

signal count_temp : integer range 0 to 15;

begin
process (Clock, Reset) begin
if (Reset = '0') then
count_temp <= 0; -- integer assignment doesn't requires quotes
elsif (Clock='1' and Clock'event) then
if (count_temp = 15) then
count_temp <= 0; -- we manually check for overflow
else
count_temp <= count_temp + 1;
end if; end if;
end process;

Count_Out <= conv_std_logic_vector (count_temp, 4);

end counter_arch;

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 Counters

• Counters in VHDL
3) Use UNSIGNED data types #'s

- STD_LOGIC_ARITH also defines "+", "-", and equality for

UNSIGNED types

- UNSIGNED is a Data type defined in STD_LOGIC_ARITH

- UNSIGNED is an array of STD_LOGIC

- An UNSIGNED type is the equivalent to a STD_LOGIC_VECTOR type

- the equality operators assume it is unsigned (as opposed to 2's

comp SIGNED)
• Pro's and Cons

- using integers allows a higher level of abstraction and more functionality can be included

- easier to write a non-synthesizable code or code that produces unwanted logic

- both are synthesizable when written correctly

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 Counters

• Ring Counters in VHDL

- to mimic the shift register behavior, we need access to the signal value before and
after clock'event

- consider the following concurrent signal assignments:

architecture ….
begin
Q0 <= Q3;
Q1 <= Q0;
Q2 <= Q1;
Q3 <= Q2;

end architecture…

- since they are executed concurrently, it is equivalent to Q0=Q1=Q2=Q3, or a simple wire

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 Counters

• Ring Counters in VHDL

- since a process doesn't assign the signal values until it suspends, we can use this to model
"before and after" behavior of a clock event.

process (Clock, Reset)

begin
if (Reset = '0') then
Q0<='1'; Q1<='0'; Q2<='0'; Q3<='0';
elsif (Clock'event and Clock='1') then
Q0<=Q3; Q1<=Q0; Q2<=Q1; Q3<=Q2;
end if;
end process

- notice that the signals DO NOT appear in the sensitivity list. If they did the process would
continually execute and not be synthesized as a flip-flop structure

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 Counters

• Johnson Counters in VHDL

process (Clock, Reset)

begin
if (Reset = '0') then
Q0<='0'; Q1<='0'; Q2<='0'; Q3<='0';
elsif (Clock'event and Clock='1') then
Q0<=not Q3; Q1<=Q0; Q2<=Q1; Q3<=Q2;
end if;
end process

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