UG0750

I/O Editor User Guide

Libero SoC v12.3
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respective owners.

50200750. 7.0 12.19

Revision History

The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.

Revision Changes
Revision 7.0 Revsion 7.0 includes the following changes:
(December 2019) • Updated Resistor Pull information in Chapter 2, Port View and Chapter 3, Pin
View
Revision 6.0 Revsion 6.0 includes the following changes:
(August 2019) • Updated to reflect latest software changes
• Added Chapter 11, Export Physical Constraints (PDC)
Revision 5.0 Revision 5.0 includes the following changes:
(December 2018) • Document template updates
• Text edit and updates
Revision 4.0 Revision 4.0 includes the following changes:
(May 2018) • Updated I/O information in Chapter 2, Port View, and Chapter 3, Pin View
• Minor edits for clarification in Chapter 4, Package View, Chapter 7, XCVR View,
Chapter 8, IOD View, Chapter 9, Floorplanner View
Revision 3.0 Revision 3.0 includes the following changes:
(October 2017) • Added Chapter 9, Floorplanner View
• Added Chapter 10, Other Windows
• Updated I/O attribute information in Chapter 3, Pin View
• Updated figures to reflect new tab order and naming
• Added information about Signal Integrity View in Chapter 7, XCVR View
Revision 2.0 Revision 2.0 includes the following changes:
(May 2017) • Updated Memory View and IOD View
• Updated graphics
Revision 1.0 Revision 1.0 is the first publication of this document.
(January 2017)

UG0750 User Guide Revision 7.0 3

Contents

1 I/O Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 Invoking the I/O Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Port View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Port Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 I/O Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5 Locked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6 Macro Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7 Bank Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.8 User I/O Lock Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.9 I/O State in Flash Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.10 Clamp Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.11 Resistor Pull . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.12 I/O available in Flash*Freeze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.13 Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.14 Vcm Input Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.15 On-Die Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.16 Odt Static . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.17 ODT Dynamic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.18 ODT Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.19 Odt Imp (ohm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.20 Low Power Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.21 Input Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.22 Slew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.23 Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.24 Output Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.25 Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.26 Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.27 Source Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.28 Output Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Pin View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Port Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Macro Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 Bank Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7 Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8 Locked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9 User Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10 Dedicated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

UG0750 User Guide Revision 7.0 4

 3.11 Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.12 User I/O Lock Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.13 I/O State in Flash Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.14 Clamp Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.15 Resistor Pull . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.16 I/O available in Flash*Freeze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.17 Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.18 Vcm Input Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.19 On-Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.20 ODT Static . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.21 ODT Dynamic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.22 ODT Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.23 ODT Imp (ohm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.24 Low Power Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.25 Input Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.26 Slew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.27 Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.28 Output Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.29 Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.30 Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.31 Source Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.32 Output Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4 Package View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Interface-Specific I/Os and Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Interface-Specific I/O Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6 Memory Interface View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.1 Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2 Edge_Anchors for Memory Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3 Memory Interface View Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.4 Making I/O Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.5 IO_PDC File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.6 Removing I/O Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7 XCVR View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1 XCVR Interface I/O Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2 Direct Versus Cascaded Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.3 Reference Clock (REFCLK) I/O Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.4 Transmit PLL Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.5 Placement DRC Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.5.1 DRC - TXPLL to LANES Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.5.2 DRC - REFCLK to TXPLL Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.5.3 REFCLK To Lanes Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8 IOD View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1 Generic I/O Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2 DRC Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9 Floorplanner View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

UG0750 User Guide Revision 7.0 5

 9.1.1 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1.2 Floorplanner View Icons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.1.3 Region Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.2 Netlist Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.2.1 Netlist Viewer - Hier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.2.2 Netlist Viewer - Flat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.2.2.1 Display Across Multiple Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.2.3 Netlist Viewer Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.2.4 Chip Planner Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10 Other I/O Editor Windows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.1 World View Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.2 Log Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.3 Object Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.4 Display Options Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.5 Properties Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

11 Export Physical Constraints (PDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

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List of Figures

Figure: 1 I/O Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure: 2 Port View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure: 3 Pin View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure: 4 Package View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure: 5 I/O Editor - XCVR View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure: 6 Memory Interface Type Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure: 7 Memory Interface View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure: 8 DRC Checks In Log Window 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure: 9 Memory Interface Assignments Accepted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure: 10 PDC File Generation after Memory Interface I/O Assignment in I/O Editor . . . . . . . . . . . . . . . . . . 28
Figure: 11 Removing Memory Interface I/O Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure: 12 XCVR Interface - Schematic View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure: 13 XCVR Interface - Graphical Placement View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure: 14 I/O Editor - XCVR View - Signal Integrity View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure: 15 Direct Dedicated Path and Cascade Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure: 16 XCVR View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure: 17 Legal and Accepted Reference Clock I/O Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure: 18 Illegal I/O Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure: 19 Log Window Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure: 20 Illegal Transmit PLL to Lane Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure: 21 Log Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure: 22 TXPLL Connection To All Four Lanes Before Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure: 23 TXPLL Connection To All Four Lanes After Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure: 24 TXPLL Connection To Two Lanes (Before Placement) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure: 25 TXPLL Connection To Two Lanes (After Placement) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure: 26 Q1_TXPLL1 to Four Lanes Connection (Before Placement) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure: 27 Q1_TXPLL1 to Four Lanes Connection (After Placement) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure: 28 Illegal Connection From REFCLK to TXPLL Up the Cascade Path . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure: 29 REFCLK To Lanes Connection - Legal (Down the Cascade Path) and Illegal (Up the Cascade
Path) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure: 30 IOD View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure: 31 Floorplanner View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure: 32 Floorplanner View Icons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure: 33 Floorplanner View - Successful Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure: 34 Floorplanner View - Unsuccessful Placement Attempt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure: 35 Select Region Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure: 36 Netlist Viewer - Hier View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure: 37 Netlist Viewer - Flat View (Flattened Netlist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure: 38 Status Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure: 39 World View Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure: 40 Log Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure: 41 Floating Object Window Tab Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure: 42 Export I/O Constraints PDC File Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure: 43 Export Floorplanner Constraints PDC File Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

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List of Tables

Table 1: Floorplanner View Icons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 2: Object Window Icons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

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I/O Editor

1 I/O Editor

The I/O Editor displays all assigned and unassigned I/O macros and their attributes in a spreadsheet-like
format. Use the I/O Editor to view, sort, filter, select and set I/O attributes of the SmartFusion2, IGLOO2,
RTG4, or PolarFire device.
The I/O attributes can be viewed by port name or by package pin. Click the Ports View tab to view I/O
attributes by port name. Click the Pin View tab to view I/O attributes by pin name.
The I/O Editor provides the following views for I/O assignment and planning:
• Port View - I/O spreadsheet sorted by port name
• Pin View - I/O spreadsheet sorted by pin number
• Package View - Package pin graphical view of the device
Note: The following views are available for PolarFire devices only:
• Memory View - I/O view specific to the memory interface
• IOD View - I/O view specific to the IOD Lane Controller interface
• XCVR View - I/O view specific to the transceiver interface
• Floorplanner View - Detailed cell level device view of the entire chip

Note: This user guide shows a PolarFire device in the example figures.

1.1 Invoking the I/O Editor

The design must be in the post-synthesis state before the I/O Editor can be invoked. A warning message
appears if the I/O Editor is invoked in the pre-synthesis state.
The I/O Editor can be invoked in two ways:
1. Invoke I/O Editor from the Constraint Manager (Design Flow window > Manage Constraints >
Open Manage Constraints View > Constraint Manager > I/O Attributes > Edit > Edit with I/O
Editor).
2. Invoke I/O Editor from the Constraint Manager (Design Flow window > Manage Constraints >
Open Manage Constraints View > Constraint Manager > I/O Attributes > View).
The Edit with I/O Editor option in the Constraint Manager allows you to save or commit your changes to
PDC files, whereas the View option shows the post-Place and Route design including the final
placement and the I/O attributes in read-only mode. You cannot save or commit any changes made in
the I/O Editor opened using the View option.
However, you can export and save the physical constraints using File > Export Physical Constraint
(PDC) in both options and save them. These constraints can later be used in your design as input files,
depending on the design's requirement.

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I/O Editor

The I/O Editor opens with view tabs across the top of the graphical interface, as shown in the following
figure.
Figure 1 • I/O Editor

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Port View

2 Port View

The Port view displays the I/O attributes in a spreadsheet-like format. Each row corresponds to an I/O
port in the design, sorted by the port name.The column headings specify the names of the I/O attributes
in your design. The first few column headings are standard and common for all families. The remaining
columns display family-specific attributes. Only attributes applicable to a specific device appear in the I/O
Editor attributes table.For some I/O attributes, you will choose from a drop-down menu; for others, you
might enter a value and for others, the field is read-only and not editable.
The display in the columns can be sorted alphabetically, numerically or filtered.
In the I/O Editor, the ports are displayed in a spreadsheet-like format and also in the Design Tree View
window under the Port tab. A port selected in the Port tab in the Design Tree view is also selected in the
Port View spreadsheet and vice versa. Figure 2 · Port View shows the DM[0] selected in the spreadsheet
and the Design Tree port view.
The Port View also displays the memory width and data rate of the DDR instance in the design (if it exists
in the design) in the top left row under the Port Name column as shown in the following figure.
Figure 2 • Port View

Note: Refer to the following documents for more information about the I/O standards supported by each
attribute:
PDC Commands User Guide (SmartFusion2, IGLOO2, and RTG4)
PDC Commands User Guide (PolarFire)

2.1 Port Name

This is the port list of the design. The ports of the design are displayed in a structured manner according
to group name/functions. Ports can be expanded or collapsed. The port list can be sorted, or filtered, in a
way similar to the Windows spreadsheet operations. Take for example, entering RESET in the match
field in the filter returns a list of port names with the RESET in the port name.

2.2 Direction
Non-editable field that denotes Input, Output, or Inout.

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Port View

2.3 I/O Standard

This field specifies the I/O standard the device supports. Different I/O types have different I/O standards.
The pull-down list displays the valid I/O standards for that particular type of I/Os. The list of valid I/O
standards is limited to what the I/O bank (to which the I/O belongs) can support.

2.4 Pin Number

This is the package pin number specific to the die and package of the device.

2.5 Locked
Set this option to lock all I/O banks so the I/O Bank Assigner cannot unassign and reassign the
technologies in the design.

2.6 Macro Cell

This is a read-only field that identifies the name of the Macro cell associated with the Port.

2.7 Bank Name

This is a read-only field to identify the I/O bank the I/O pin is associated with. Depending on the device
size, devices may have, six, or eight I/O Banks (Bank 0 through Bank 7) user I/O banks, Each pin is
associated with an I/O bank. The I/O banks on the north side of the device support only HSIO. Each I/O
bank has dedicated I/O supplies and grounds. Each I/O within a given bank shares the same VDDI power
supply, and the same VREF reference voltage. Only compatible I/O standards can be assigned to a given
I/O bank.

2.8 User I/O Lock Down

If checked, the current pin assignment cannot be changed during layout.

2.9 I/O State in Flash Freeze Mode

By default, all I/Os become tristated when the device goes into Flash*Freeze mode. You can override this
default behavior by setting one of the following two values:
• LAST_VALUE - When set to this value, it preserves the previous state of the I/O. This means the I/O
remains in the same state in which it was functioning before the device went into Flash*Freeze
mode.
• LAST VALUE_WP - When set to this value, it preserves the last value with weak pull-up.

2.10 Clamp Diode

PolarFire devices have internal PCI clamp diodes for both HSIO and GPIO. PCI clamp diodes help
reduce the voltage level at the input, and are mainly used when the voltage overshoot exceeds the
maximum allowable limit. If signaling levels of the receiver are greater than the VDDIx of the bank, the
clamp diode must be off to support hot-socketing insertion.
For GPIO, use this field to program the clamp diode to be ON or OFF.
For HSIO, the internal clamp diode is always ON by default.

2.11 Resistor Pull

Use this field to allow inclusion of a weak resistor for either pull-up or pull-down of the input or output
buffer. The available options are None, Up (pull-up), Down (pull-down), or Hold. The default value is
None.
Note: Not all I/O standards have a selectable resistor pull option.

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Port View

2.12 I/O available in Flash*Freeze mode

Use this field to indicate if the I/O is available or unavailable in Flash*Freeze mode. The default value is
“no” and the I/O is unavailable in Flash*Freeze mode.

2.13 Schmitt Trigger

GPIO and HSIO can be configured as a Schmitt Trigger input. When configured as ON, it exhibits a
hysteresis that helps to filter out the noise at the receiver and prevents double-glitching caused by noisy
input edges. Default configuration is OFF (Schmitt Trigger disabled).by noisy input edges.

2.14 Vcm Input Range

Use this field to set the Vcm input range.
TDirection: Input

2.15 On-Die Termination

On-Die Termination (ODT) is an option used to terminate input signals in PolarFire devices. Terminating
input signals helps to maintain signal quality, save board space, and reduces external component costs.
In SmartFusion2, IGLOO2, RTG4, and PolarFire FPGAs, ODT is available in receive mode and also in
bidirectional mode when the I/O acts as an input. If ODT is not used or not available, the I/O standards
may require external termination for better signal integrity.
ODT can be a pull-up, pull-down, differential, or Thévenin termination with both static and dynamic
control available, and is set using either the Libero SoC software I/O attribute editor or by using a PDC
command.
In addition, ODT can be controlled dynamically for individual I/Os as well as for all I/Os in a lane
simultaneously on a per-lane basis.

2.16 Odt Static

On-die termination (ODT) is the technology where the termination resistor for impedance matching in
transmission lines is located inside a semiconductor chip instead of on a printed circuit board. Possible
values are listed in the table below.

Value Description

on Yes, the termination resistor for impedance matching is located inside the chip.

off No, the termination resistor is on the printed circuit board.

2.17 ODT Dynamic

Note: This option is supported for RTG4 production devices only.
This option is used to opt in or out of the dynamic odt set on a bank. Possible value are listed in the table
below.

Value Description

ODT_STATIC=On Illegal
ODT_DYNAMIC=On

ODT_STATIC=On The ODT resistor is always turned on.

ODT_DYNAMIC=Off

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Port View

Value Description

ODT_STATIC=Off The ODT resistor is always turned off.

ODT_DYNAMIC=Off

ODT_STATIC=Off The ODT resistor is On or Off based on the ODT Dynamic bank
ODT_DYNAMIC=On setting.

The following I/O standards are supported:

LVDS, RSDS, MINILVDS, LVPECL, HSTLI, HSTLII, SSTL15I, SSTL15II, SSTL18I, SSTL18II, HSTL18I,
HSTL18II, LPDDRI, LPDDRII

2.18 ODT Value

If the ODT option is turned on, the ODT Value (ohm) field can be set to any one of the values in the pull-
down list. The ODT Value varies with different I/O standards.

2.19 Odt Imp (ohm)

On-die termination (ODT) is the technology where the termination resistor for impedance matching in
transmission lines is located inside a semiconductor chip instead of on a printed circuit board.
Port Configuration (PC) bits are static configuration bits set during programming to configure the I/O(s) as
per your choice. Refer to your device datasheet for a full range of possible values.

2.20 Low Power Exit

For single ended I/Os, the Lower Power Exit value can be set from the drop-down list. The supported
values for Single Ended IOs are Off, Wake On Change, Wake On 0, Wake On 1. The default is Off.
The diff I/Os are marked as read-only fields and will be set to off.

2.21 Input Delay

Sets the Input Delay.
Input Delay applies to all I/O standards. The range of values supported varies depending on the device
selected. The default value is OFF.
Note: This attribute will not appear in the I/O attributes and cannot be used in the PDC for some I/Os with
dynamic delays, such as DDR I/Os.

2.22 Slew
The slew rate is the amount of rise or fall time an input signal takes to get from logic low to logic high or
vice versa. It is commonly defined to be the propagation delay between 10% and 90% of the signal's
voltage swing. The I/O Editor supports slew rate control in non-differential output mode. Turning the slew
rate on results in faster slew rate, which improves the available timing margin. When slew rate is turned
off, the device uses the default slew rate to reduce the impact of simultaneous switching noise (SSN). By
default, the slew control is OFF.Not all I/O standards support the slew rate control.

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Port View

2.23 Pre-Emphasis
The pre-emphasis rate is the amount of rise or fall time an input signal takes to get from logic low to logic
high or vice versa. It is commonly defined to be the propagation delay between 10% and 90% of the
signal's voltage swing. Possible values are shown in the table below.

Value Description

NONE Sets to none (default)

MIN Sets to minimum

MEDIUM Sets to medium

MAX Sets to maximum

2.24 Output Drive

Use the Output Drive (mA) field to set the output drive strength. The output drive strength that can be set
is different with different I/O standards and can vary from 1 to 20 mA. Select the drive strength value from
the list of valid values in the pull-down list.

2.25 Impedance
Use the Impedance (Ohm) field in the I/O Editor to program the output impedance values. Note that the
Impedance value is different with different I/O standards and can vary from 22 to 240 Ohm. Click on this
field to open the pull-down list to see the valid values.

2.26 Output Load

The Output Load (pF) field indicates the output capacitance value based on the I/O standard. If
necessary, you can double-click on the respective I/O port to change the output capacitance value to
improve timing definition and analysis. Output capacitance affects output propagation delay.
SmartTime, Timing-driven layout, and Backannotation automatically uses the modified delay model for
delay calculations.

2.27 Source Termination

The Source Termination (Ohm) field is the Near End termination for a differential output I/O. The default
is OFF.
Direction: Output

2.28 Output Delay

Sets the Output Delay.
Output Delay applies to all I/O standards. The default value is OFF.
Direction: Output
Note: This attribute will not appear in the I/O attributes and cannot be used in the PDC for some I/Os with
dynamic delays, such as DDR I/Os.

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Pin View

3 Pin View

The Pin view displays the I/O attributes of I/O attributes in a spreadsheet-like format. Each row
corresponds to an I/O macro (port) in the design, sorted by Pin number.The column headings specify the
names of the I/O attributes in your design. The first few column headings are standard and common for
all families. The remaining columns display family-specific attributes. Only attributes applicable to a
specific device appear in the I/O Editor attributes. For some I/O attributes, you will choose from a drop-
down menu; for others, you may enter a value and for the rest, the field is read-only and not editable.
The display in the columns can be sorted alphabetically, numerically or filtered. See the following figure.
Figure 3 • Pin View

Note: Refer to the following documents for more information about the I/O standards supported by each
attribute:
PDC Commands User Guide (SmartFusion2, IGLOO2, and RTG4)
PDC Commands User Guide (PolarFire)

3.1 Pin Number

This is the read-only package pin number specific to the die and package of the device.

3.2 Port Name

This is an editable field for the assignment of a port to that particular pin number. It contains a pull-down
list of the assignable and available Ports for the pin. Select Unassigned to leave the pin unassigned.

3.3 Direction
Non-editable field that denotes Input, Output, or Inout.

3.4 Macro Cell

This is a read-only field that identifies the name of the macro cell associated with the port.

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Pin View

3.5 Bank Name

This is a read-only field to identify the I/O bank the I/O pin is associated with. Devices may five, six, or
eight I/O banks (Bank 0 through Bank 7) user I/O banks, depending on the device size. Each pin is
associated with an I/O bank. The I/O banks on the north side of the device support only HSIO. Each I/O
bank has dedicated I/O supplies and grounds. Each I/O within a given bank shares the same VDDI power
supply, and the same VREF reference voltage. Only compatible I/O standards can be assigned to a given
I/O bank.

3.6 Function
The function name identifies the functions of the pin/port. This is the same as what is listed in the Public
Pin Assignment Table (PPAT) for the selected device and package. For details, see the device datasheet
of the die/package.
The function name may contain the following information:
• Type of I/O: GPIO or HSIO
• Special-purpose IOs: for example, XCVR
• The I/O Bank Number
• Positive/Negative Pad of differential IOs
• VSS or Ground

3.7 Info
3.8 Locked
Set this option to lock all I/O banks, so the I/O Bank Assigner cannot unassign and re-assign the
technologies in the design.

3.9 User Reserved

For the I/O pin you want to reserve for use in another design, check the User Reserved checkbox to
reserve it. When a pin is reserved, you cannot assign it to a port.

3.10 Dedicated
If checked, the pin is reserved for some special functionality, such as UJTAG, Power, XVCR Reference
Clock, device reset, and clock functions.

3.11 Vref
Any GPIO and HSIO pad on the device can be configured to act as an external VREF to supply all inputs
within a bank. Use this field to configure the I/O as VREF to other I/Os. When an I/O pad is configured as
Vref (voltage referenced), all I/O buffer modes and terminations on that pad are disabled.

3.12 User I/O Lock Down

If checked, the current pin assignment cannot be changed during layout.

3.13 I/O State in Flash Freeze Mode

By default, all the I/Os become tristated when the device goes into Flash*Freeze mode. You can over-
ride this default behavior by setting its value to one of the following two values:
• LAST_VALUE - When set to this value, it preserves the previous state of the I/O. This means the I/O
remains in the same state in which it was functioning before the device went into Flash*Freeze
mode.
• LAST VALUE_WP - When set to this value, it preserves the last value with weak pull-up.

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3.14 Clamp Diode

PolarFire devices have internal PCI clamp diodes for both HSIO and GPIO. PCI clamp diodes help
reduce the voltage level at the input, and are mainly used when the voltage overshoot exceeds the
maximum allowable limit. If signaling levels of the receiver are greater than the VDDIx of the bank, the
clamp diode must be off to support hot-socketing insertion.
For GPIO, use this field to program the clamp diode to be ON or OFF.
For HSIO, the internal clamp diode is always on by default.

3.15 Resistor Pull

Use this field to allow inclusion of a weak resistor for either pull-up or pull-down of the input or output
buffer. The available options are None, Up (pull-up), Down (pull-down), or Hold. The default value is
None.
Note: Not all I/O standards have a selectable resistor pull option.

3.16 I/O available in Flash*Freeze mode

Use this field to indicate if the I/O is available or unavailable in Flash*Freeze mode. The default value is
“no” and the I/O is unavailable in Flash*Freeze mode.

3.17 Schmitt Trigger

GPIO and HSIO can be configured as a Schmitt Trigger input. When enabled as such (YES), it exhibits a
hysteresis that helps to filter out the noise at the receiver and prevents double-glitching caused by noisy
input edges. Default value is OFF

3.18 Vcm Input Range

Values for all I/O standards are MID, LOW. The default is MID.

3.19 On-Die Termination

On-Die Termination (ODT) is an option used to terminate input signals in PolarFire devices. Terminating
input signals helps to maintain signal quality, save board space, and reduces external component costs.
In PolarFire FPGAs, ODT is available in receive mode and also in bidirectional mode when the I/O acts
as an input. If ODT is not used or not available, the I/O standards may require external termination for
better signal integrity.
ODT can be a pull-up, pull-down, differential, or Thévenin termination with both static and dynamic
control available, and is set using either the Libero SoC software I/O attribute editor or by using a PDC
command.
In addition, ODT can be controlled dynamically for individual I/Os as well as for all I/Os in a lane
simultaneously on a per-lane basis.

3.20 ODT Static

On-die termination (ODT) is the technology where the termination resistor for impedance matching in
transmission lines is located inside a semiconductor chip instead of on a printed circuit board. Possible
values are listed in the table below.

Value Description

on Yes, the termination resistor for impedance matching is located inside the chip.

off No, the termination resistor is on the printed circuit board.

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3.21 ODT Dynamic

Note: This option is supported for RTG4 production devices only.
This option is used to opt in or out of the dynamic odt set on a bank. Possible value are listed in the table
below.

Value Description

ODT_STATIC=On Illegal
ODT_DYNAMIC=On

ODT_STATIC=On The ODT resistor is always turned on.

ODT_DYNAMIC=Off

ODT_STATIC=Off The ODT resistor is always turned off.

ODT_DYNAMIC=Off

ODT_STATIC=Off The ODT resistor is On or Off based on the ODT Dynamic bank
ODT_DYNAMIC=On setting.

The following I/O standards are supported:

LVDS, RSDS, MINILVDS, LVPECL, HSTLI, HSTLII, SSTL15I, SSTL15II, SSTL18I, SSTL18II, HSTL18I,
HSTL18II, LPDDRI, LPDDRII

3.22 ODT Value

If ODT option is turned on, the ODT Value (Ohm) field can be set to any one of the values in the pull-
down list. The ODT Value varies with different I/O standards.
Values vary depending on the I/O standard.

3.23 ODT Imp (ohm)

On-die termination (ODT) is the technology where the termination resistor for impedance matching in
transmission lines is located inside a semiconductor chip instead of on a printed circuit board.
Port Configuration (PC) bits are static configuration bits set during programming to configure the I/O(s) as
per your choice. Refer to your device datasheet for a full range of possible values.

3.24 Low Power Exit

For single ended I/Os, the Lower Power Exit value can be set from the drop-down list. The supported
values for Single Ended IOs are Off, Wake On Change, Wake On 0, Wake On 1. The default is Off.
The diff I/Os are marked as read-only fields and will be set to off.

3.25 Input Delay

Sets the Input Delay.
Input Delay applies to all I/O standards. The range of values supported varies depending on the device
selected. The default value is OFF.
Note: This attribute will not appear in the I/O attributes and cannot be used in the PDC for some I/Os with
dynamic delays, such as DDR I/Os.

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3.26 Slew
The slew rate is the amount of rise or fall time an input signal takes to get from logic low to logic high or
vice versa. It is commonly defined to be the propagation delay between 10% and 90% of the signal's
voltage swing. The I/O Editor supports slew rate control in non-differential output mode. Turning the slew
rate on results in faster slew rate, which improves the available timing margin. When slew rate is turned
off, the device uses the default slew rate to reduce the impact of simultaneous switching noise (SSN). By
default, the slew control is OFF.Not all I/O standards support the slew rate control.
Note: Slew rate control is not available in PolarFire HSIO buffers. However, these buffers have built-in PVT-
compensated slew rate controllers for optimized signal integrity.

3.27 Pre-Emphasis
The pre-emphasis rate is the amount of rise or fall time an input signal takes to get from logic low to logic
high or vice versa. It is commonly defined to be the propagation delay between 10% and 90% of the
signal's voltage swing. Possible values are shown in the table below.

Value Description

NONE Sets to none (default)

MIN Sets to minimum

MEDIUM Sets to medium

MAX Sets to maximum

3.28 Output Drive

Use the Output Drive (mA) field to set the output drive strength. The output drive strength that can be set
is different with different I/O standards and can vary from 1 to 20 mA. Select the drive strength value from
the list of valid values in the pull-down list.

3.29 Impedance
Use the Impedance (Ohm) field in the I/O Editor to program the output impedance values. Note that the
Impedance value is different with different I/O standards and can vary from 22 to 240 Ohm. Click on this
field to open the pull-down list to see the valid values.

3.30 Output Load

The Output Load (pF) field indicates the output capacitance value based on the I/O standard. If
necessary, you can double-click on the respective I/O port to change the output capacitance value to
improve timing definition and analysis. Output capacitance affects output propagation delay.
SmartTime, Timing-driven layout and Backannotation automatically uses the modified delay model for
delay calculations.

3.31 Source Termination

The Source Termination (Ohm) field is the Near End termination for a differential output I/O.
The default is OFF.
Direction: Output

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3.32 Output Delay

Sets the Output Delay.
Output Delay applies to all I/O standards. The range of values supported varies depending on the device
selected. The default value is OFF.The default value is OFF.
Direction: Output
Note: This attribute will not appear in the I/O attributes and cannot be used in the PDC for some I/Os with
dynamic delays, such as DDR I/Os.

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4 Package View

The Package View displays the Package pin views of the particular die/package of the PolarFire
device.The color for the display of the pins are determined by the settings in Display Options. The
following figure shows the regular pins in green, special pins in blue, reserved pins in red and
unconnected pins in grey.
Figure 4 • Package View

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Interface-Specific I/Os and Views

5 Interface-Specific I/Os and Views

The PolarFire architecture is designed and optimized to support Memory interface, IOD interface and
Transceiver interface. The I/O Editor for PolarFire provides three special views specifically for I/O
assignments of these interfaces.
For optimal QOR (Quality of Result) and timing performance, the architecture of the PolarFire silicon
requires the Memory Interface, IOD Interface and Transceiver Interface be placed in specific and pre-
defined locations of the chip. Assignment of these interfaces are checked against PolarFire DRC rules
and illegal assignments are flagged.
The I/O Editor is a graphical user interface (GUI) tool designed to make Interface I/O pin assignments
graphically and user-friendly, as an alternative to writing PDC commands. When the pin assignment is
committed and saved in I/O Editor, a PDC file is created. This PDC file can then be passed to the Place
and Route tool as a Physical Design Constraint.

5.1 Interface-Specific I/O Views

In addition to the Pin view, Port view and Package view, the I/O Editor provides three views specific to
PolarFire-supported interfaces I/Os:
• Memory View - for I/O pin assignments of Memory interfaces such as DDR2/3/4,LPDDR2/3, QDR,
and RLDRAMII.
• XCVR View - Presents a physical view of the Transceiver connectivity, including Transceiver lanes,
and Reference Clock (REFCLK), and TransmitPLL lines.
• IOD Lane Controller View - Presents the I/O Digital block view, used for non-memory interfaces
using the FPGA I/Os.
Figure 5 • I/O Editor - XCVR View

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Memory Interface View

6 Memory Interface View

The Memory Interface view presents a spreadsheet-like view of the I/Os available in the PolarFire silicon
for different Memory interface types.

6.1 Memory Type

The supported Memory Interface types include:
• DDR2
• DDR3
• DDR4
• LPDDR2
• LPDDR3
• QDRII+
• RLDRAMII
• SDR
Use the pull-down menu to select the type of Memory Interface used in the design. Only the specific type
of memory used in the design are displayed in the pull-down list.
The Ports view also displays the memory width and data rate of the DDR instance in the design (if it
exists in the design) in the top left row under the Port Name column, as shown in the following figure.
Figure 6 • Memory Interface Type Menu

6.2 Edge_Anchors for Memory Placement

The PolarFire silicon architecture requires that the Memory interface be placed in specific and pre-
defined locations of the chip to achieve optimal QOR (Quality of Result) and timing performance. These
specific location are called Edge_Anchors and are used to identify the specific location in the PolarFire
chip for optimal Memory Interface I/O placement. See the PolarFire FPGA DDR Memory Controller User
Guide for a mapping of DDR memory interface types to Edge_Anchor locations. The Edge_Anchors are
as follows:
• NORTH_NE
• NORTH_NW
• SOUTH_SE
• SOUTH_SW
• WEST_NW
• WEST_SW
The ports for each Edge_Anchor is represented by a different color for easy identification. The list of
possible Edge_Anchors is context-sensitive to the Memory Interface type and represents the legal and

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Memory Interface View

optimal locations for the specific Memory interface type. The list of Edge_Anchors for DDR4, for
example, is different from the list for DD2/DDR3. DDR4 has fewer locations (Edge_Anchors) for I/O
placement than DDR2/DD3.

6.3 Memory Interface View Columns

The Memory Interface view detects the type of Memory Interface in the design and presents the ports in
the Ports View. The Memory Interface view displays the following I/O information in the view. Each of the
column can be sorted (ascending/descending order) or filtered:
• Port Function - The formal port name of the Memory Interface. The ports specific to the memory
interface type are loaded into the Port view.
• Port Name - The port name of the Memory Interface instance in the design.
• Pin Number - The package pin number assigned to the port of the Memory Interface
• Function - A more descriptive function name of the Port which identifies the type of I/O (for
example, HSIO for High-speed I/Os or GPIO (General-purpose IO)
• Max Memory Width - The maximum memory width of the DDR. This is a fixed read-only value
specific to the Edge_Anchor and is different with different Edge_Anchors.
• Max Data Rate - The maximum data rate in Mbps. This is a fixed read-only value specific to the
Edge_Anchor and is different with different Edge_Anchors.
Note: When making DDR placement, refer to the memory width and data rate of the DDR Memory used in the
design (as displayed in the Ports View). Make sure that the Edge_Anchor location where you want to
place the DDR memory can accommodate the DDR memory in terms of the memory width and the data
rate. This will avoid invalid placement.
• Bank Name - the I/O bank name of the port
• High-speed I/O Clocks - specifies the number of High Speed I/O clocks
The Pin Number and Function are the same as what are listed in the PPAT for the selected device and
package. The PPAT for each PolarFire package are provided in the PolarFire_<package> Pinouts file on
the PolarFire Documentation web page.
Figure 7 • Memory Interface View

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Memory Interface View

6.4 Making I/O Assignments

To make I/O assignment for the Memory Interface instance in the design:
1. Select the Memory Interface type from the drop-down menu.
2. From the Ports tab in the Design Tree View, drag the Memory Interface instance and let the mouse
hover over one of the Edge_Anchor locations available for the Memory Interface type. A tooltip
reports whether it is a legal or illegal location for the Interface instance.
3. Drop the Interface instance into a legal Edge_Anchor location.
Notes: DRC rules are enforced. Drag-and-drop I/O placement that violates the DRC rules are
reported in the Log window. For Memory Interface, the DRC checks the Data Width and the
Data Rate compliance*. If the specific location cannot accommodate the Data Width or the
Data Rate of the Memory interface, no I/O assignment is made. An error is reported in the
Log Window with a message that explains why the assignment is not accepted. In the
following figure, the DRC error message reports that the ddr3 instance requires 64 ports, but
the SOUTH_SE location can accommodate only 58 pins.
Note:*Data Rate compliance will be enforced in a later release.
Figure 8 • DRC Checks In Log Window

4. Check that no DRC error messages are reported in the Log window and the I/O assignments are
accepted (Figure 9 · Memory Interface Assignments Accepted). The Lock icon in the Ports tab
indicates that the I/O assignment is accepted and locked.

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Memory Interface View

Figure 9 • Memory Interface Assignments Accepted

6.5 IO_PDC File

When the I/O assignment is committed and saved in the I/O Editor, the assignment is saved in a PDC file
in the <project_folder/constraints/io/user.pdc file. The PDC file contains set_io commands on each of the
the DDR Memory Interface I/O.

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Memory Interface View

The following figure shows PDC file generation after Memory interface I/O assignment in the I/O Editor.
Figure 10 • PDC File Generation after Memory Interface I/O Assignment in I/O Editor

6.6 Removing I/O Assignments

To remove a DDR Memory Interface I/O assignment:
1. Select the Port tab in the Design Tree view.
2. Right-click the Memory Interface in the Design Tree view.
3. Select Unplace <memory_interface_name>
See the following figure.

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Memory Interface View

Figure 11 • Removing Memory Interface I/O Assignment

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XCVR View

7 XCVR View

The XCVR View allows the user to make assignments for Transceiver Lanes, Reference Clocks and
Transmit PLLs. It presents the following views:
• A schematic view of the Reference Clock (REFCLK), the TransmitPLL and the Transceiver
Lanes they drive (Figure 12 · XCVR Interface - Schematic View).
• A graphical placement view of the REFCLK, its connection from the PADS, to the TransmitPLL,
to the Transceiver Lanes.(Figure 13 · XCVR Interface - Graphical Placement View).
• A Signal Integrity View for a Transceiver Lane, showing TX Emphasis Amplitude, TX
Impedance, TX Transmit Common Mode Adjustment, RX and TX Polarity, RX Insertion Loss,
RX CTLE, RX Termination, RX P/N Board Connection, and RX Loss of Signal Detector (Low
and High) (Figure 14 · I/O Editor - XCVR View - Signal Integrity View).

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XCVR View

Figure 12 • XCVR Interface - Schematic View

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XCVR View

Figure 13 • XCVR Interface - Graphical Placement View

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XCVR View

Figure 14 • I/O Editor - XCVR View - Signal Integrity View

The Signal Integrity View for a Transceiver Lane shows the following:
• TX Emphasis Amplitude
• TX Impedance
• TX Transmit Common Mode Adjustment
• RX and TX Polarity, RX Insertion Loss, RX CTLE
• RX Termination
• RX P/N Board Connection
• RX Loss of Signal Detector (Low and High)

7.1 XCVR Interface I/O Assignment

To make XCVR Interface I/O assignment, use the XCVR view in the I/O Editor to make assignment in the
following order:
1. Transceiver Lanes
2. TX PLL
3. REFCLK

7.2 Direct Versus Cascaded Connection

The PolarFire XCVR reference clock network provides rich connectivity to the TX_PLL and Transceiver
lanes. The connectivity allows the user to share common reference clock inputs to reduce fanout buffers
on the board and reduce costs.
The two types of connections between the reference clock and the TX _PLL and Transceiver lanes are
as follows:
• Direct Connection
• Cascaded Connection
Direct connections are used when the reference clock pin and the TX_PLL or the Transceiver lanes are
in the same Quad location.
Cascaded connections are used when the reference clock pin and the TX_PLL or the Transceiver lanes
are not in the same quad location. Cascade connections are only available going from the top of the
device towards the bottom.

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XCVR View

The cascaded connection is denoted in the XCVR view by the black vertical line down the middle of the
placement view.
Note: A REFCLK can connect to all the lanes beside or below it in any quad (down the cascade path) but not
those above it (up the cascade path).
The red lines denote cascaded REFCLK connection to the TX_PLL and the Transceiver lanes in the
quad.
Connection/Assignment up the Cascade path (from REFCLK to TX_PLL and Transceiver lanes which
are above the REFCLK) are illegal and indicated by red lines in the XCVR view.
Each Reference Clock (REFCLK) has a direct dedicated connection to its corresponding TX_PLL and to
the lane that the TX_PLL drives in the same quad.
Selecting a dedicated connection or a cascaded connection depends on the trade-off you want to make.
A direct dedicated connection from the REFCLK to the TX_PLL gives better signal integrity for the
Transceiver whereas a cascaded connection reduces external components and reduces overall power.

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XCVR View

Figure 15 • Direct Dedicated Path and Cascade Path

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XCVR View

Figure 16 • XCVR View

7.3 Reference Clock (REFCLK) I/O Assignments

To make I/O assignments, click and drag the REFCLK pin from the Schematic View to the pin location
you desire in the Graphical Placement View. If the assignment is legal (no DRC violations), green lines
appear to denote the accepted connection between the REFCLK pin through the Q(x)_TXPLL_SSC to
the Transceiver lanes.
Figure 17 • Legal and Accepted Reference Clock I/O Assignment

If the I/O assignment violates the DRC rule, the assignment is not accepted. Red arrows denotes DRC
violations.The following figure shows two illegal assignments:
• From the Reference Clock (REFCLK) to the Lanes (Red arrow from REFCLK to the Q2_Lane0)
• From the Transmit PLL to the lanes (Red arrow from TXPLL_SSC to Q2_Lane0)

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XCVR View

Figure 18 • Illegal I/O Assignment

An error message appears in the Log window to identify the DRC rules violated. In this case, there is no
feasible dedicated connection from the REFCLK to the Lane and from the Transmit PLL to the Lanes.
Figure 19 • Log Window Message

Notes: I/O assignments can be made for REFCLK, TXPLL and Transceiver Lanes for all Transceiver protocols except
the PCIe Protocol. For the PCIe Protocol, Transceiver Lanes are assigned to pre-defined locations and cannot
be removed.

7.4 Transmit PLL Assignment

Drag and drop the Transmit PLL instance into the desired location. Illegal locations are flagged with error
messages in the Log window and the illegal connections are indicated by red lines.

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XCVR View

Figure 20 • Illegal Transmit PLL to Lane Assignment

The Log window displays two error messages about the illegal assignments, one for each illegal
connection. In this case, the assignment is illegal because there are no feasible dedicated connections.
Figure 21 • Log Window

7.5 Placement DRC Rules

The I/O Editor enforces the DRC rules when Transceivers are placed. Any illegal connection is
highlighted as a red line in the Placement View and a corresponding message is displayed in the Log
window.
Lane assignments are always legal. DRC rules are enforced for the following:
• Connection from Transmit PLL (TXPLL) to the Lanes

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XCVR View

• Connection from the Reference Clock (REFCLK) to the Transmit PLL (TXPLL)
• Connection from the Reference Clock (REFCLK) to the Lanes

7.5.1 DRC - TXPLL to LANES Connectivity

A TXPLL_SSC can connect to all the lanes of a quad (shown in brown lines in the Placement View).
Figure 22 • TXPLL Connection To All Four Lanes Before Placement

Figure 23 • TXPLL Connection To All Four Lanes After Placement

A TXPLL (non-SSC) can connect to two lanes beside it normally (shown in blue lines in the Placement
View)

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XCVR View

Figure 24 • TXPLL Connection To Two Lanes (Before Placement)

Figure 25 • TXPLL Connection To Two Lanes (After Placement)

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XCVR View

Figure 26 • Q1_TXPLL1 to Four Lanes Connection (Before Placement)

Figure 27 • Q1_TXPLL1 to Four Lanes Connection (After Placement)

7.5.2 DRC - REFCLK to TXPLL Connectivity

A REFCLK can connect to all the TXPLLs beside and below it (down the Cascade Path) in the
Placement View. A REFCLK cannot connect to a TXPLL above it (up the Cascade Path).
A cascade path (represented by the vertical line beside the REFCLKs) is used for the REFCLK to
connect to all the TXPLLs below it and the Lanes below it in the Placement View.

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XCVR View

Figure 28 • Illegal Connection From REFCLK to TXPLL Up the Cascade Path

7.5.3 REFCLK To Lanes Connectivity

The REFCLK of a quad can connect to all Lanes of the TXPLL (in addition to that which the REFCLK can
connect to), and also all the other Lanes below it (from different quads as well). Connection up the
Cascade path is illegal.
Green arrows indicate legal connection and red arrows indicate illegal connection from the REFCLK to
the Lanes.
Figure 29 • REFCLK To Lanes Connection - Legal (Down the Cascade Path) and Illegal (Up the Cascade Path)

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IOD View

8 IOD View

The IOD lane controller handles the complex operations necessary for the high-speed interfaces, such
as DDR memory interfaces and CDR interfaces. To bridge the lane clock to the bank clock, the lane
controller is used to control an I/O FIFO in each IOD. This I/O FIFO interfaces with DDR memory by
utilizing the DQS strobe on the lane clock. The lane controller can also delay the lane clock using a PVT-
calculated delay code from the DLL to provide a 90° shift. Certain I/O interfaces require a lane controller
to handle the clock-domain that results with higher gear ratios.
The lane controller also provides the functionality for the IOD CDR. Using the four phases from the CCC
PLL, the lane controller creates eight phases and selects the proper phase for the current input condition
with the input data. A divided-down version of the recovered clock is provided to the fabric (DIVCLK).
In the I/O Editor, the IOD View allows I/O assignments for IOD (I/O Digital) Interface blocks. Libero SoC
currently supports CDR and RX_DDR_L_A/TX_DDR_G_A generic IOD interface. Future releases will
add in more interfaces. The IOD views presents a hierarchical view of the generic IOD based on Bank
and Lanes. In PolarFire silicon, there may be up to eight banks per chip and six lanes per bank. Bigger
dies may have even more lanes per bank.
Notes: The actual number of banks and the number of lanes per bank vary with the die.
When the I/O Editor opens the IOD view, it detects the specific IOD Interface standards, groups the I/Os
into specific banks/lanes and populates the spreadsheet-like table with the I/O names (specific to the
IOD Interface) accordingly.
See the following figure for an example of the IOD View.

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IOD View

Figure 30 • IOD View

8.1 Generic I/O Assignments

Drag the I/O port from the Ports tab and drop it to the spreadsheet-like table to make the I/O assignment.
The multi-line comment shows the locations where you can legally place the I/O port. Green indicates
legal placements, and red indicates illegal placements. Illegal assignments are not allowed.

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IOD View

8.2 DRC Rules

The I/O Editor enforces DRC rules. More DRC rules will be implemented in future releases. The following
is a list of the more common DRC rules enforced by the I/O Editor.
1. All I/Os of the same logical lane must be placed within the same physical lane.
2. For any one physical lane, only one logical lane is allowed to be placed.
3. Non-logical lane I/Os can be placed in any physical lane.
4. For RGMII Interface, the *_RXC port must be placed on the DQS_P side of the physical lane.
5. When the CDR is placed in a physical lane, the DQS_N slot is reserved and is not available to the
user for I/O placement.
See UG0686: PolarFire FPGA User I/O User Guide for more DRC rules for IOD I/O placement.

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Floorplanner View

9 Floorplanner View

The Floorplanner View displays all design elements in one window. The selections you make in the views
are reflected in the window. The color scheme used in the canvas is dependent on the layers and colors
you have selected in the Display Options window.
The following figure shows the Floorplanner View.
Figure 31 • Floorplanner View

9.1 Operation Modes

The Floorplanner View has two modes of operation. Click the Macro Manipulation Mode button to
switch between Macro Manipulation Mode and Region Manipulation modes:
• Macro Manipulation Mode
Use this mode to work
with macros, such as assigning macros to location or unassigning placed macros from locations.
You can also view properties of selected macros in the Floorplanner View from the properties win-
dow. You can select multiple macros by pressing the <CTRL> key and selecting required macros.
• Region Manipulation Mode
Use this mode to work on regions such as resizing, renaming, or deleting regions, or assigning and
unassigning macros or nets to regions.

9.1.1 Display Modes

The Display Options window configures the display of the Floorplanner View. Three display options are
available as follows:
• Fill Device Cells
• Use Cluster Mode
• Consolidate Globals
You can also see the colors for different component types (nets, modules, pins, etc.) in the Display
Options window.

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Floorplanner View

9.1.2 Floorplanner View Icons

The icons available across the top of the Floorplanner View window allows you to zoom in, zoom out,
assign I/O banks, runs DRC checks, create regions for placement.
Figure 32 • Floorplanner View Icons

The following table lists the functions of each icon.

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Floorplanner View

Table 1 • Floorplanner View Icons

Icon Name Function

Rubber Band Zoom Rubber Band Zoom - Drags out an area to

enlarge/zoom into.

Rubber Band Select Rubber Band Select an area to Zoom into. Click in
the Floorplanner View and drag the mouse to
delineate an area. Release the mouse and all
macros inside the delineated area are selected.
Works in the Macro Manipulation Mode.

Zoom In Zoom In to canvas.

Zoom Out Zoom Out of canvas.

Zoom to Fit Zoom to fit the canvas size.

Zoom to Location Zoom to a Location Specified by X-Y co-ordinates.

Zoom to fit Selection Zoom to fit selected macros and ports. When
enabled, the view attempts to center the view on
the selected and placed ports.

Check Design Rules Run the Prelayout Checker, a preliminary check of

the netlist for possible Place and Route issues.

Check DRC Rules for Selected Check the DRC Rules for selected interfaces.
Interfaces

I/O Bank Settings Set the I/O bank to specific I/O Technology.

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Floorplanner View

Icon Name Function

Auto Assign I/O Bank Run the Auto I/O Bank and Globals Assigner.
Assigns a voltage to every I/O Bank that does not
have a voltage assigned to it and if required, a
VREF pin.

Collapse Visible Views Collapse the visible views.

Expand Selected Items in Visible Expand selected Items in the visible views.
Views

Create Empty Create an empty user region.

Create Inclusive Create an inclusive user region.

Create Exclusive Create an Exclusive user region.

Delete Delete the selected user region.

Show Nets For Macros Show all nets connected to the macro. There are
often many nets attached to the macro, and it is off
by default.

An object or a collection of the objects in the Design View window can be selected and placed in any
location that is legal.
The following figure shows an example of a successful placement into the Floorplanner View.

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Floorplanner View

Figure 33 • Floorplanner View - Successful Placement

The following figure shows an example of an unsuccessful placement attempt into the Floorplanner View.
Figure 34 • Floorplanner View - Unsuccessful Placement Attempt

9.1.3 Region Assignments

When you right-click an item in one of the tabs in the Main Object Browser, you can choose from
available options, which can include placing an item to a location, unplacing an item from a location,
locking the placement, and assigning a region.
Multiple items can be selected and assigned to the same region at the same time. You can also select a
region assignment by right-clicking an item and choosing Region Assign. The dialog box shown below
opens. This option is not available for objects in the Region tab.

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Floorplanner View

Figure 35 • Select Region Dialog Box

.The progress of all Region Assign and Unassign commands is shown (see the example below).

Note: This dialog only shows the progress, and does not give the user the opportunity to cancel the operation.
Closing the dialog does not terminate the operation.

9.2 Netlist Views

Two windows are available for viewing the netlist (a schematic view of the design used to trace the nets
and debug) of the design.
• Post-Synthesis Hierarchical View (Netlist Viewer - Hier)
• Post-compile flattened Netlist View (Netlist Viewer - Flat)
Separate tabs for Hierarchical View and Flattened Netlist View make it easy to switch between the
different views.

9.2.1 Netlist Viewer - Hier

The Post-Synthesis Hierarchical View (Netlist Viewer - Hier) is a hierarchical view of the netlist after
synthesis and after technology mapping to the Microsemi FPGA technology. Click on the Canvas to load
the 'Hierarchical view' in Nelist Viewer - Hier. The Chip Planner loads the netlist into the system memory
and displays it in the window.
When the netlist is loaded for the first time into memory, a pop-up progress bar indicates the progress of
the loading process, which may incur some runtime penalty for a large netlist.

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Floorplanner View

Figure 36 • Netlist Viewer - Hier View

9.2.2 Netlist Viewer - Flat

This is the flattened (non-hierarchical) netlist generated after synthesis, technology mapping and further
optimization based on the DRC rules of the device family and/or die. Click on the Canvas to load the 'Flat'
view in the Netlist Viewer - Flat window. The Chip Planner loads the netlist into the system memory and
displays it in the window as shown in the following figure.
Figure 37 • Netlist Viewer - Flat View (Flattened Netlist)

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Floorplanner View

9.2.2.1 Display Across Multiple Pages

Hierarchical or flattened netlists can span multiple pages, in which case the first page is displayed when
it opens.
The current page number and the total number of pages are displayed in the status bar at the lower right
corner of the window.
Figure 38 • Status Bar

To go to different pages of the Netlist view, use the left-pointing arrow or right-pointing
arrow .

9.2.3 Netlist Viewer Features

See the Netlist Viewer Interface User Guide for details about Netlist Viewer features.

9.2.4 Chip Planner Features

See the Chip Planner User Guide for details about Chip Planner features.

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Other I/O Editor Windows

10 Other I/O Editor Windows

10.1 World View Window

The World View shows a red rectangle which reflects what is visible in the Floorplanner
View in the context of the die. Changing what is visible in the canvas also changes the red
rectangle. Changing the size or position of the red rectangle changes what is seen in the
Floorplanner View.
Figure 37 • World View Window

10.2 Log Window

The Log window displays all messages generated by I/O Editor. You can filter the
messages according to the type of message: Error, Warning, and Info. If you have made
and saved changes in I/O Editor, the Log window displays the name and location of the
PDC file(s) which have been edited/updated to reflect the changes.
Figure 38 • Log Window

10.3 Object Window

The Object window (Main Object Browser) includes the following tabs:
• Port

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Other I/O Editor Windows

• Logical
• Net
• Region
Press Ctrl-F to open a floating window for the active tab. See the following example.
Figure 39 • Floating Object Window Tab Example

The following table lists the Object window icons.

Table 11 • Object Window Icons

Icon Description

Collapse everything in the tree.

Expand selected.

Clear the filter and refresh the tree reflecting no filters.

Change sort order and allow additional filtering.

Dock. Present except when already docked. This command docks

the filter browser next to the Main Object Browser.

Float. Present when docked or maximized. Causes the window to

float.

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Other I/O Editor Windows

10.4 Display Options Window

The Display Options window configures the display of the selected viiew. Three display
options are available as follows:
• Fill Device Cells
• Use Cluster Mode
• Consolidate Globals

10.5 Properties Window

The Properties window displays the properties of the design elements. What is displayed in
the Properties window is dependent on what is selected in the design view. Properties
displayed may include the following, depending on the type of design elements:
• Macro/Component Name - Full Macro or component name based on selection.
• Cell Type - Resource type based on design element selection.
• Placed (Location) - X-Y coordinates where device element is placed.
• Resource Usage Table - A table showing resources based on component and macro
selection.
• Region Attached Table - A table showing region to which selected macro/component is
assigned.
• User region (if any) it is attached to.
• Nets Table - A table showing pins and nets which is associated with the selected
macro along with fanout value.
• Locked/Unlocked (Placement) - The selected port is locked or unlocked.
• Port - Port name to which the I/O macro is assigned (only shown for I/O port macros).
• I/O Technology Standard - I/O Technology which is associated with the selected I/O
macro (only shown for I/O port macros).
• I/O Bank- I/O bank to which the selected I/O macro is assigned (only shown for I/O
port macros).
• Pin (Package Pin) - Pin to which the macro is assigned (only shown for I/O port
macros).
Not all properties in the list are displayed. The list of displayed properties varies with the
type of design element selected.

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Export Physical Constraints (PDC)

11 Export Physical Constraints (PDC)

The I/O Editor allows you to export the physical constraints ( I/O Constraints and Floorplan
Constraints) of the design in a PDC file to any file location on your disk. You can export the
User constraints or the Full constraints of the design. The IO PDC files can be exported
(File > Export Physical Constraint (PDC) > I/O Constraint) as shown below.
Figure 1 • Export I/O Constraints PDC File Dialog Box

The fp.pdc file can be exported (File > Export Physical Constraint (PDC) > Floorplan
Constraint) as shown below.

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Export Physical Constraints (PDC)

Figure 2 • Export Floorplanner Constraints PDC File Dialog Box

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