Nlx-Atx Sspa
Nlx-Atx Sspa
Nlx-Atx Sspa
CONTENTS
Chapter 25.4
TROUBLESHOOTING...................................................................... 25.4-5
LEDs 1 to 9 ....................................................................................... 25.4-5
STATE OF HEALTH LED (D10) ................................................... 25.4-5
PEARL ASIC LED (D15) ................................................................ 25.4-5
SPAM ASIC LED (D14) .................................................................. 25.4-6
COMMS LED................................................................................... 25.4-6
CONTENTS
Chapter 25.4
INTRODUCTION
This chapter describes the Self-Service Personality Adapter (SSPA)
board used in the NLX and ATX PC Cores of NCR ATMs.
GENERAL DESCRIPTION
PC COMMUNICATIONS MODULE
The integrated PCCM logic provides the following features:
PEARL ASIC providing embedded V20 processor:
DMA
Interrupt Controller
Timer/Counter
64 KB ROM.
Zilog compatible Z8530 Serial Communications Controller, with
only Channel B connected
Up to 256 KB of SRAM memory for the downloaded communica-
tions driver and buffers (default is 128 KB with additional 128
KB)
RS-232 High Order Communications interface
Dundee low level compatible hardware interface between the
ISA bus and the V20 microprocessor
Switch selectable enable/disable
PEARL ASIC level 0 diagnostic LED.
POWER REQUIREMENTS
The NLX and ATX SSPA board has the following voltage and
current requirements:
Lithium Battery
The lithium battery for the NVRAM is rated as follows:
Voltage = +3.67 V, -0.7 V +0.23 V
Current = 15 µ A max.
Capacity = 1 Ah
Life (@ 15 µ A) = 7.5 years.
TEST TOOLS
None.
STRAPPING
SWITCHPACK U1
SSPA Board
8 SER
7 RESERVED
6 RESERVED
5 SER/PAR EN
4 PCCM EN
3 NVRAM CLEAR
2 SDC 200/210H
1 PCCM 380/3A0H
SW PACK - U1
8 7 6 5 4 3 2 1 D8 D7 D6 D5 D4 D3 D2 D1 D9
SW1 LED8
SW8 LED1
LED9
Switch
Position Function
No.
1 OPEN PCCM base I/O address set to 3A0H (default)
CLOSED PCCM base I/O address set to 380H
6 Not used
7 Not used
Switch
Position Function
No.
8 OPEN Ser 4 port base address config. 2E8 (default)
CLOSED Ser 4 port base address config. 278
ADJUSTMENTS
None.
TROUBLESHOOTING
LEDs 1 to 9
LEDs 1 to 8 on the SSPA display level 0 error codes from the
motherboard BIOS and from the NCR Extended ROM BIOS. LED 9
is lit when the code is from the NCR Extended ROM BIOS and is off
when the LEDs are being written to by the motherboard main
BIOS.
The error codes are listed in Chapter 4.2.25 “Level 0 Diagnos-
tics - NLX/ATX PC Core”.
COMMS LED
The COMMS LED, on the operator panel, flashes to indicate comms
activity. It is driven from an output of the PEARL ASIC and is
routed via connector J4 to the Std PC Miscellaneous I/F Board.
CABLE INFORMATION
Schematic diagrams of the cables between modules inside the NLX/
ATX PC Core are in chapter 6.2.25. This section shows pinouts of
the connectors on the SSPA board.
MISC CONNECTOR J1
Connector J1 is a 10-way header connector that carries the
following signals:
Beeper
Tamper switch
Power Good
Front panel reset.
AMP_BEEP_A 1 2 AMP_BEEP_B
TAMP_SW_A 3 4 TAMP_SW_B
GND 5 6 FP_RSTb
GND 7 8 PWOK
GND 9 10 N/C
SERIAL3_CDb 1 2 SELECT
SERIAL3_DSRb 3 4 PE
SERIAL3_RXD 5 6 BUSY
SERIAL3_RTSb 7 8 ACKb
SIGNAL_GND 9 10 GND
SERIAL3_TXD 11 12 PDATA7
SERIAL3_CTSb 13 14 PDATA6
SERIAL3_DTRb 15 16 PDATA5
SERIAL3_RIb 17 18 PDATA4
SERIAL4_DSRb 19 20 SELECT_INb
SERIAL4_CDb 21 22 PDATA3
SERIAL4_RXD 23 24 PDATA2
SERIAL3_RTSb 25 26 INITb
PDATA1 27 28 GND
GND 29 30 GND
SERIAL4_TXD 31 32 ERRORb
SERIAL4_CTSb 33 34 PDATA0
SERIAL4_DTRb 35 36 AUTOFDXTb
SERIAL4_RIb 37 38 STROBEb
SIGNAL_GND 39 40 GND
LED_INb 1
N/C 2
N/C 3
6 SDC_DATA_P
1 TAMP_SW_B 7 SDC_RESET_P 11 SDC_DATA_N
2 TAMP_SW_B 8 EXT_RESET_b 12 SDC_RESET_N
3 GND 9 SUPERVISOR 13 RESET_GND
4 AMP_BEEP_A 10 COMMS_LEDb 14 SUP_GND
5 AMP_BEEP_B 15 COMMS_5 V
N/C 1 14 NEWSYNC
TDb 2 15 TSET
RDb 3 16 N/C
RTS 4 17 RSET
CTS 5 18 WCA
DSR 6 19 N/C
GND 7 20 DTR
DCD 8 21 N/C
N/C 9 22 CI
N/C 10 23 DSRS
N/C 11 24 EXTSET
N/C 12 25 WIN
N/C 13