STM32 Timers Tutorial
STM32 Timers Tutorial
STM32 Timers Tutorial
The main block of the programmable timer is a 16-bit up-counter with its related auto-reload register.
The counter clock can be divided by a Prescaler. The counter, the auto-reload register, and the Prescaler
register can be written or read by software. This is true even when the counter is running. The time-base
unit includes:
The auto-reload register is preloaded. The preload register is accessed each time an attempt is made to
write or read the auto-reload register. The contents of the preload register are transferred into the
shadow register permanently or at each update event UEV, depending on the auto-reload preload
enable bit (ARPE).
In counter mode, the counter counts from 0 to the auto-reload value (contents of the TIMx_ARR
register), then restarts from 0 and generates a counter overflow event. An update event can be
generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by
using the slave mode controller).
Also, the LPTIM capability to wake up the system from low-power modes makes it suitable to realize
“Timeout functions” with extremely low power consumption. The LPTIM introduces a flexible clock
scheme that provides the needed functionalities and performance while minimizing power
consumption.
The Low-Power Timers (LPTIM) Main Features:
16-bit up-counter
3-bit Prescaler with 8 possible dividing factors (1,2,4,8,16,32,64,128)
Selectable clock
– Internal clock sources: LSE, LSI, HSI16 or APB clock
– External clock source over LPTIM input (working with no LP oscillator running, used by
Pulse Counter application)
16 bit ARR auto-reload register
16 bit compare register
Continuous/One-shot mode
Selectable software/hardware input trigger
Programmable Digital Glitch filter
Configurable output: Pulse, PWM
Configurable I/O polarity
Encoder mode
Repetition counter
For control and monitoring purposes, the timer has also timing measure capabilities and links to built-in
ADC and DAC converters. Last, it features a light-load management mode and is able to handle various
fault schemes for safe shut-down purposes.
This mode of operation is usually used to get a specific operation done each specific time interval. And
to achieve timing & sync between various tasks and events in the system. It can also replace delays in
various situations for better system response.
Counter Mode
In counter mode, the timer module gets clocked from an external source (timer input pin). So the timer
counts up or down on each rising or falling edge of the external input. This mode is really helpful in
numerous situations when you need to implement a digital counter without polling input pins or
periodically reading a GPIO or continuously interrupt the CPU if you’ve chosen to hook it up to an EXTI
pin.
You can actually monitor the counter value difference each time interval to tell how many pulses did
occur or what was the frequency of it. Such a mode can be advantageous in many situations like this.
PWM Mode
In PWM mode, the timer module is clocked from an internal clock source and produces a digital
waveform on the output channel pin called the PWM signal. By using output compare registers (OCR),
the incrementing timer’s register value is constantly compared against this OCR register. When a match
occurs the output pin state is flipped until the end of the period and the whole process is repeated.
The timer in PWM mode will produce a PWM signal at the specified frequency the user chose. The duty
cycle is also programmatically controlled by its register. The PWM resolution is affected by the desired
FPWM and other factors as we’ll see in the dedicated tutorials for PWM generation.
The ability to produce a complementary PWM signal that is typically the same as the PWM on
the main channel but logically inverted (high portion becomes low and vice versa).
The ability to inject dead-time band in the PWM signal for motor driving applications to prevent
shoot-through currents that result from PWM signals overlapping.
The ability to perform auto-shutdown for the PWM signal, it’s also called “auto brake” which an
important feature for safety-critical applications.
And the ability to phase-adjust the PWM signal, and much more! All of this is referred to as
advanced-PWM control.
The output compare pin can be driven high, low, toggles its sate, or stay unchanged. This is determined
by the programmer as per the application requirements. This mode of operation can be extremely
advantageous for generating timing signals and output driving in many applications as we’ll see in future
tutorials.
One-Pulse Mode
One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in
response to a stimulus and to generate a pulse with a programmable length after a programmable
delay. Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode.
A pulse can be correctly generated only if the compare value is different from the counter initial value.
Before starting (when the timer is waiting for the trigger), the configuration must be CNT<CCRx ≤ ARR (in
particular, 0<CCRx). For example, you may want to generate a positive pulse on OC1 with a length of
tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.