OPERATIONAL AMPLIFIER

1 Introduction:
An Operational Amplifier (op amp.) is characterised by the following
1. Very High Input Impedance
2. Very High Bandwidth.
3. Very High Gain
4. Differential Input
5. High Common Mode Rejection Ratio and
6. Signal Integrity at the output.
Of the above, Common Mode Rejection Ratio is a measure of the goodness of an
amplifier with differential input. As will be seen later this is a measure of the
rejection of the average of the two inputs in comparison to the difference of the
two input signals. We have seen in the discussion of single ended amplifier, say a
Common Source Amplifier, the variations across the gate and source terminal about
the DC bias leads to a variation in the drain source current and hence the potential
across drain and source. In a single ended common source amplifier, the source is
grounded and the ac input is applied to the gate as shown in Fig. 1(a). If one needed
an amplifier with differential input, we may apply one input terminal to the source
and the other to the gate as shown in Fig. 1(b). The major issue with the

Fig. 1 Development of a differential amplifier. (a) A normal

Common Source Amplifier with a bypassed source resistance.
(b) The input voltage vgs given as a difference between two
signals, retaining the dc condition (c) Circuit in (b) modified
to obtain the same dc condition and high load impedance for
the source vs2.
Configuration in Fig. 1(b) is that the source vs1 sees a load of large impedance while
the source vs2 sees a load of input impedance of a common gate amplifier of 1/gm,
this would be untenable to obtain an output proportional to vs1 – vs2. It is best when
both the sources see the same impedance. This has been achieved in Fig. 1(c) by
connecting the source through a source follower to the source of M1. For the
source follower using M2, the source and drain resistances are taken identical to
the common source amplifier to ensure proper dc bias matching. The amplifier in
Fig. 1(c) has been redrawn in Fig. 2 with an additional output taken at the drain of
M2 and the resistance R2 ||l R2 by a current source ISS.

Fig. 2. (a) The emitter resistance in Fig. 1(c) replaced by a current

source ISS (b) The circuit redrawn to look its familiar self.

2. Analysis of a basic Differential Amplifier: It is evident from the circuit in

Fig. 5.2 that when we consider the output vo2 at the drain of transistor M2, we are
looking at a cascode of CD amplifier (source follower) followed by CG amplifier
from vs1 to vo2 and CS amplifier from vs2 to v02. Similarly, considering the output at
transistor M1, vo1, we are looking at a cascade of CD amplifier followed by CG
amplifier from vs2 to vo1 and CS amplifier from vs1 to v01. Assuming a total
symmetrical circuit, it is sufficient to analyse the effect of any one signal input to
analyse the total circuit. In analysing the circuit we will use superposition theorem.
 Fig. 3 Equivalent Circuit of the differential amplifier.

Let us now look at the equivalent circuit and its analysis. We represent the current
source ISS by its output impedance 1/go in the equivalent circuit. In the equivalent
circuit, solving for vo1/vs1 from the above three equations we get
⎧ g ⎫ ⎧ gm1 ⎫
⎪ 1 + m1 ⎪ ⎪ g ⎪
vo1 ⎪ go ⎪ vo2 ⎪ o ⎪
= − (gm1 RL ) ⎨ ⎬ and = − (g R )
m1 L ⎨ ⎬ (1)
vs1 ⎪1 + 2 gm1 ⎪ v s1 ⎪1 + 2 gm1 ⎪
⎪⎩ go ⎪⎭ ⎪⎩ go ⎪⎭
Let us define the following:
vo1 vo2 vo1 vo2
= A11 ; = A21 and = A12 ; = A22 (2)
vs1 vs1 vs2 v s2
We can then write
vo1 = A11 vs1 + A12 vs2 and vo2 = A21 vs1 + A22 vs2 (3)
We can now recast the equations as
(v + v )
vo1 = Ad (vs1 − vs2 ) + ACM s1 s2
2

(vs1 + vs2 )
vo2 = − Ad (vs1 − vs2 ) + ACM
2
(4)
(A11 − A12 ) ⎛ gm1 RL ⎞ ⎛g R ⎞
where Ad = = − ⎜⎜ ⎟ ≈ − ⎜ m1 L ⎟
2 ⎝ (1 + 2gm go ) ⎠
⎟
⎝ 2 ⎠
⎛g R ⎞
and ACM = (A11 + A12 ) = − ⎜ o L ⎟
⎝ 2 ⎠
The signal (vs1 – vs2) is called the differential signal and the signal (vs1 + vs2)/2 is
called the Common Mode signal. This leads us to define a very important parameter
defining a differential Amplifier, the Common Mode Rejection Ratio, CMRR. CMRR
is defined as
A (1 + 2gm1 go ) ⎛⎜ gm1 ⎞⎟
CMRR = d = ≈⎜ (5)
ACM 2 g
⎝ o ⎠
⎟

Having evaluated the gains of differential and common mode gain an interesting fall
out is what is popularly known as half circuit equivalent. Based on the results for
Differential and common mode gains we can represent the behaviour of the
differential amplifier in to two half circuits for evaluating the two gains as shown
in Fig. 4.

(a) (b)
Fig. 4 (a) Differential Half Circuit. (b) Common Mode Half Circuit.

3. Differential Amplifier with an Active Load:

3.1 Amplifier gain and Common Mode Rejection Ration (CMRR):
In our analysis above we see that to increase the gain of the amplifier we would
need to increase the load resistance RL. An increase in RL would necessarily mean an
increase in the supply voltage to maintain the same VDSQ for the given quiescent DC
drain current IDSQ. To alleviate this problem we can replace the load Resistance
used in a differential amplifier with an active load. An active load is a DC current
source that will provide large impedance to time varying current and can thus give a
larger gain than a simple resistance. The simplest active loads could be each a
PMOS transistor in saturation with a constant Gate to Source Voltage or Gate tied
to Drain. In Fig. 5(a) we will have RL = rds = 1/gd and in Fig. 5(b) RL = 1/gm.
 (a) (b)
Fig. 5 Two possible configurations of differential amplifier with active
load.

Let us now consider a non-symmetric load on M1 and M2 and look at the outputs vo1
and vo2. For this circuit we will have, with gm1 = gm2, gm3 = gm4, gd1 = gd2 and gd3 = gd4.
Drawing its equivalent circuit and carrying out node analysis we have

Fig. 6 An asymmetric load Differential Amplifier.

 ⎛ g ⎞ ⎛ 1 + gm go ⎞ ⎛ g ⎞ ⎛ gm go ⎞
A11 = − ⎜⎜ m1 ⎟⎟ ⎜⎜ ⎟ ; A12 = ⎜ m1 ⎟ ⎜ ⎟
⎝ gm3 ⎠ ⎝ 1 + 2 gm go
⎟ ⎜ g ⎟⎜ 1+ 2g g ⎟
⎠ ⎝ m3 ⎠ ⎝ m o ⎠
(6)
⎛ g ⎞ ⎛ 1 + gm go ⎞ ⎛ g ⎞ ⎛ gm go ⎞
A22 = ⎜⎜ m1 ⎟⎟ ⎜⎜ ⎟ ; A21 = ⎜ m1 ⎟ ⎜ ⎟
⎝ gds3 ⎠ ⎝ 1 + 2 gm go
⎟ ⎜ g ⎟⎜ 1+ 2g g ⎟
⎠ ⎝ ds3 ⎠ ⎝ m o ⎠

This will give us the outputs vo1 and vo2 as

(v +v )
vo 1 = Ad 1 (v s 1 − v s 2 ) + ACM 1 s 1 s 2
2
(v s 1 +v s 2 )
vo 2 = − Ad 2 (v s 1 − v s 2 ) + ACM 2
2 (7)
(A11 − A12 ) (A − A )
where Ad 1 = ; Ad 2 = 22 21
2 2
and ACM 1 = (A11 + A12 ) ; ACM 2 = (A22 + A21 )

Assuming that gm1 >> go, the values of Ad1, Ad2, ACM1 and ACM2 reduce to
⎛ g ⎞ ⎛ g ⎞ ⎛ g ⎞ ⎛ g ⎞
Ad 1 = − ⎜⎜ m1 ⎟⎟ ; Ad 2 = − ⎜⎜ m1 ⎟⎟ ; ACM 1 = − ⎜⎜ o ⎟⎟ ; ACM 2 = − ⎜⎜ o ⎟⎟ (8)
⎝ 2 g m3 ⎠ ⎝ 2g d 3 ⎠ ⎝ 2 g m3 ⎠ ⎝ 2g d 3 ⎠
Now since we are interested only in single ended output (say) vo2, we will device a
useful method to use the other output to our advantage. What we would like to do
is to connect the output vo1 to the gate of M4. We will then get the most commonly
used single ended differential amplifier structure given in Fig. 7(a).

Fig. 7 (a) A differential amplifier giving a single ended output (b) its
equivalent circuit.

Solving for the circuit assuming gm1 , gm3 >> go, gd1, gd3 we obtain the differential
and common mode gain from the equivalent circuit given in Fig. 7(b) as
 g m1 ⎛ g o g d1 ⎞
Ad = and ACM = − ⎜⎜ ⎟⎟
(g d 1 + g d 3 ) ⎝ 2 g m 3 (g d 1 + g d 3 ) ⎠
(9)
⎛g g ⎞
Giving us CMRR = 2 ⎜⎜ m1 m3 ⎟⎟
⎝ g o g d1 ⎠

(a) (b)

(c) (d)
Fig. 8 (a) Differential Amplifier with NMOS input pair
(b) The corresponding vout vs. v+ plot for different v-.
(c) Differential Amplifier with PMOS input pair.
(d) The corresponding vout vs. v+ plot for different v-.

In our discussions so far we had considered NMOS input devices with PMOS load
devices. It is equally likely that we may use PMOS input transistors and NMOS
load transistors. In Fig. 8(a), we present a NMOS input Differential amplifier with
a plot of the output voltage as a function of the positive input voltage v+ with
varying negative input voltage v- shown in Fig. 8(b). It is seen that for negative
input voltage at v+, the transistor M2 gets in to pre-saturation region earlier for
larger values of v- and the gain is adversely affected. A similar amplifier circuit
and plot for a PMOS input pair is given in Fig. (c) and (d). In this case also the
transistor M2 gets in to pre-saturation region earlier for larger values of v- and the
gain is adversely affected.

3.2 Common Mode Input Range

One of the important metric of a differential amplifier is the Common Mode Input
Range normally referred to as Common Mode Range or CMR. CMR defines the range
of voltages at the input that would ensure that all the transistors in the amplifier
circuit operate in saturation. We obtain the two extremes VG1(min) and VG1(max)
for a PMOS input Differential Amplifier (given in Fig. 9).

Fig. 9 A differential amplifier with PMOS input pair.

The lowest common mode input voltage at gate of M1(M2) for the input transistors
to be in saturation is given by
V G1(min) = V SS + V GS3 + V SD1 - V SG1 (10)
with the minimum value of V SD1 for the transistor M1 in saturation, V SD1 = V SG1 -
|V T1 |. This gives us
ISS
VG1 min = V SS +V GS3 -| V T1 | = VSS + + VTO3 −| VTO1 | (11)
β
Similarly we can obtain the maximum possible voltage at the gate to be
 ISS
VG1 (max) = VDD − VSD5 − VSG1 = VDD − VSD5 − −| VTO1 | (12)
β
Assume that V DD = 3V and that V SS = -3V. Using K’N = 2K’P 18 A/V2, 0.8V <VTO3 , VT1<
1.2V, let us find the common mode range for worst case conditions. Assume that
ISS = 100mA, W1/L1 = W2/L2 = 5, W3/L3 = W4/L4 = 1, and vSD5 = 0.2V.
ISS
VG1 min = VSS + + VTO3 −| VTO1 |
β
100
= − 3+ + 1.2 − 0.8 = − 0.25V
18
I
VG1 max = VDD − VSD5 − SS −| VTO1 |
β
100
= 3 − 0.2 − − 1.2 = 0.6V
5 x9
The input common mode range is -0.25V to 0.6V.

3.3 Slew Rate:

Fig. 5.10 A differential amplifier with a load capacitance CL with an output plot
for a sinusoidal in the presence of slew rate limitation.

This defines the rate at which the load capacitor charged. In other words it
defines the rate dv/dt at the output. Slew rate is a measure of the ability of the
output to follow the input signal. This is normally associated with large signal
property. For a large signal input, the output would swing from VDD to VSS when the
input goes from positive to negative at the input. Under large signal, only one of M1
or M2 will be ON and the charging current will be I5. This gives a slew rate CL(VDD-
VSS)/I5.
3.4 Parasitic elements in a differential amplifier:

The various parasitic capacitors associated with a

differential amplifier are shown in Fig. 11. The
various parasitic elements are
CT = tail capacitor (common mode only)
CM = mirror capacitor = Cdg1 + Cdb1 + Cgs3 + Cgs4 + Cdb3,
COUT = output capacitor » Cbd4 + Cbd2 + Cgd2 + CL
These parasitic capacitors will come in to play when
we consider the frequency characteristics of the
amplifier.

3.5 Noise sources in a differential amplifier:

Fig. 12 The differential amplifier with the noise source due to each
transistor marked in the figure.
Noise can be normally modelled as a current source in parallel to iD. This current
source represents two sources of noise, thermal noise and flicker noise. The mean
square current noise source is defined as
⎡ 8kT gm (1 + η) (KF) ID ⎤
in2 = ⎢ + ⎥ Δf (13)
⎣⎢ 3 f Cox L2 ⎦⎥
where Δf is the bandwidth at frequency f, η = gmbs/gm, and KF is the flicker noise
coefficient. We now define mean square noise reflected to the gate giving mean
square voltage noise at the gate and is given by

2 in2 ⎡ 8kT (1 + η) (KF) ⎤

veq = = ⎢ + ⎥ Δf (14)
gm2 ⎢⎣ 3gm f Cox WLK ' ⎥⎦

The total output noise current is obtained by summing each of the noise current
contributions.
2
ito = gm21 veq
2 2 2 2 2 2 2 2 2
1 + gm1 veq2 + gm3 veq3 + gm3 veq4 = gm1 veq (15)
⎛ gm2 3 ⎞ 2
where 2
veq
= (2
veq
+ 1
2
veq ) (
+ ⎜⎜ 2 ⎟⎟ veq3 + veq
2
2
)
4
⎝ gm1 ⎠
Assuming identical N and P transistors
⎛ gm2 3 ⎞
2 2
veq = 2 veq1 + ⎜ 2 ⎟ 2veq
⎜g ⎟
(
2
3 ) (16)
⎝ m1 ⎠
The total 1/f and thermal noise contributions can be written as
2
2 ⎛ 2 Bp ⎞ ⎛⎜ ⎛ KN' BN ⎞ ⎛ L1 ⎞ ⎞⎟
veq (1 / f) = ⎜⎜ ⎟ 1+ ⎜ ⎟ ⎜ ⎟ (17)
⎝ f W1 L1 ⎠ ⎝
⎟⎜ ⎜ K' B ⎟ ⎜ L ⎟ ⎟
⎝ P P ⎠⎝ 3⎠ ⎠
1
⎛ ⎞⎛ '
⎞
2
⎜ 16 k T ⎟ ⎜ ⎛ K (W
⎜ N 3 3 ⎟ ⎟L ) ⎞ 2 ⎟
veq (th) = ⎜ 1 ⎟ ⎜ 1 +
⎜ K' (W L ) ⎟ ⎟
⎝ (
⎜ 3 2 K' I (W L ) 2 ⎟ ⎜⎜
P 1 1 1 ⎠⎝ ) ⎝ P 1 1 ⎠ ⎟
⎠ (18)
KF
where BN, P =
2 Cox KN' , P
To get the input noise for NMOS input stages interchange BP for BN, KN’ for KP’ and
vice versa. Since BN = 5BP it is preferable to use PMOS input stage to reduce 1/f
2
⎛ K' B ⎞ ⎛ L ⎞
noise with large area for M1 and M2 and ⎜ N' N ⎟ ⎜⎜ 1 ⎟⎟ << 1 .
⎜K B ⎟ L
⎝ P P ⎠⎝ 3⎠

⎛ KN' (W3 L3 ) ⎞
To reduce thermal noise we choose, ⎜ ' ⎟ << 1 and large value of gm1.
⎜ K (W L ) ⎟
⎝ P 1 1 ⎠
We have so far seen the structure of a differential amplifier, the input stage of an
operational amplifier. The second stage of the simplest possible operational
amplifier could be 1. Class A amplifier, 2. Source follower, and 5. Push-Pull amplifier
(inverting and follower).

(a) (b) (c)

(d) (e)
Fig. 13 Various configurations used as second and subsequent stages of an
operational amplifier. (a) A class A common source amplifier. (b) A simple
source follower (c) A push pull inverting amplifier (d) Push pull common
source amplifier (e) Push Pull inverting amplifier including the circuit to
realize the required bias.
4 Characterization of Operational Amplifiers:

Fig. 14 A simple CMOS Operational Amplifier

The basic characteristics that characterise an operational amplifier are (1) Gain,
(2) Common Mode Rejection Ratio, CMRR (3) Common Mode Range CMR, (4) Gain
Bandwidth product, (5) Power Supply Rejection Ratio, PSRR, (6) Output Swing, (7)
Input Offset, (8) Noise, and (9) Slew Rate. We will take a simple two stage
Operational Amplifier as an example to evaluate these characteristics; this can
easily be extended to the various operational amplifier structures. It should be
mentioned here that the Common Mode Rejection Ration and the Common Mode
Range of the Operational Amplifier is the same as that of the input Differential
Amplifier.

4.1 DC gain and frequency response

Fig. 15 Small Signal equivalent circuit of the amplifier given in Fig. 5.19.
Fig. 15 presents the small signal equivalent circuit of Fig. 14 with gm1 = gm2, gds1 =
gds2, gm3 = gm4 and gd3 = gd4. At the source of M1, we see that the current branches
between the source current of M2(an impedance of 1/gm1) and the impedance gd5.
We can safely assume that since gm1 >> gd5, very little current will flow through gd5.
Here gd5 is the same as go that we used in our discussions on Differential
Amplifier. We have also assumed v- = 0 and v+ = vin. Solving for the gain as a
function of frequency we have the over all gain as a function of frequency as
gm1 gm6 1
Av (ω) = (19)
(gd1 + gd3 )(gd6 + gd7 ) (1 + jωC1 (gd1 + gd3 )) (1 + jωCL (gd6 + gd7 ))
gm1 gm6
From 19 we see that the DC gain is given by Av = with poles at
(gd1 + gd3 )(gd6 + gd7 )
p1 = (gd1 + gd3 ) C1 and p2 = (gd6 + gd7 ) CL .

In most operational amplifier application they are used in a feedback mode. For the
stability of the amplifier configuration we desire that the loop gain be less than
unity when the phase shift nears 180º (normally) at 135º.

Fig. 16 (a) An operational Amplifier Connected in a Feedback Mode

(b) A plot of gain vs. frequency for Aβ
(c) A plot of phase vs. frequency for Aβ

Depending on the relative values of ω1 and ω2 will determine whether the loop gain
will reach unity before the phase shift reaches 0º. The closer the two frequencies
ω1 and ω2 the less stable will the circuit be. We define two quantities here namely
Gain Margin and Phase Margin. Gain margin is the loop gain when the phase is 0º and
Phase Margin is the difference of the phase from 0º, when the loop gain is unity. If
the phase reaches 0° at a frequency before the loop gain drops to 0dB, the phase
margin will be negative and the feedback system can get to be oscillatory. Similarly
if the gain is less than 0dB at the frequency when the phase is 0° the system will
be oscillatory. In other words for a stable circuit we require that the Phase Margin
(ΦM) should be positive and the Gain Margin (GM) should be negative. For the
system shown in Fig. 16 we see that ΦM is zero and GM is positive, a situation
unacceptable for stability. It can also be seen that if ω1 and ω2 are torn farther
apart ΦM can be made positive and the GM negative. The process of circuit
correction to separate the two corner frequencies further is called compensation.
In Fig. 17 (a) and (b) we present a plot of step response of an amplifier as a
function of the ratio of ω1 and ω2 and as a function of phase margin respectively.

(a) (b)

Fig. 17 (a) Step Response of an Amplifier for various ω2/ω1 ratios

(b) Step Response of an Amplifier for various ΦM.

4.1.1 Miller Compensation of a Two Stage Op. Amp. One of the most commonly
used and popular compensation techniques is the Miller Compensation. In here we
connect an external capacitance CC between the final output and the output of the
differential stage. In Fig. 18(a) we present an op. amp. With Miller Compensation
and its equivalent circuit in Fig. 18(b).
 (a)

(b)
Fig. 18 (a) Miller Compensated Op. Amp.
(b) Small Signal Equivalent Circuit of Miller Compensated Op. Amp.

From the equivalent circuit given in Fig. 18(b), we can obtain the gain Vout(s)/Vin(s)
as

Vout (s) (gm1 gm6 R1 R2 ) (1 − s(CL gm6 ))

=
Vin (s) 1 + s[R1 (C1 + CL ) + R2 (CC + CL ) + gm6R1R2CC ] + s2R1R2 [C1CL + Cc CL + C1CC ]
(20)
Av (0) (1 − s z1 )
=
(1 − s p1 ) (1 − s p2 )
where we have used R1 = (gd1 + gd3)-1 and R2 = (gd6 + gd7)-1 and have neglected the
effect of CM on the gain unction. From eqn. 20, using dominant pole approximation
and using the inequality R1(C1 + CL) + R2(CC + CL) << gm6R1R2CC we obtain the poles (p1
and p2) and zero (z1) as

− (gd1 + gd3 ) (gd6 + gd7 ) − gm6CC − gm6 g

p1 = ; p2 ≈ ≈ , and z1 = m6 (21)
gm6 Cc [C1CL + CC CL + C1CC ] CL CC
Comparing the expression for p1 and p2, we can see that p1 < p2, and the 3dB cut off
can be equated to p1. We the obtain the Gain Bandwidth Product GBW, the product
of dc gain Av(0) and the bandwidth ω1 as GB = gm1/CC.
In Fig. 19 we present a gain and phase plot of a compensated op. amp. before and
after compensation.

Fig. 19. Gain and Phase plot of a compensated op. amp.

In a good compensated op. amp., the phase margin should be at least 60º. This
means that
⎛ ω ⎞ ⎛ ω ⎞ ⎛ ω ⎞
Φ M = ± 180! − tan −1 ⎜⎜ ⎟ − tan −1 ⎜ ⎟ − tan −1 ⎜
⎜ | z | ⎟ = 60 at ω = GBW
⎟ !
(22)
| p
⎝ 1 ⎠ | ⎟ ⎜ | p
⎝ 2 ⎠ | ⎟
⎝ 1 ⎠
This gives us for large gain, |p2| ≥ 2.2 GB. Demanding z1 >> p1, along with p2| ≥ 2.2
GBW gives us the condition gm6 > 10gm2 and CC > 0.22CL. A question that rises in ones
mind is how far should the zero be to be identified as much greater than p1. The
best answer to it is “if we can remove the zero, it is an happy situation”. There are
several ways of eliminating the zero. We will discuss one such method in the next
section.
4.1.2 Nulling Resistor in Compensation Path:

One of the most prevalent methods used for eliminating the zero is the use of a
nulling resistor, RZ in series with the compensation capacitor CC. We present the
compensation circuit with nulling resistor and its equivalent circuit in Fig. 20.

(a)

(b)
Fig. 20(a) Compensated Op Amp with nulling resistor (b) its small signal
equivalent circuit.
From the equivalent circuit we obtain the gain as
 Vout (s) Av (0) (1 − s z1 )
== (23)
Vin (s) (1 − s p1 ) (1 − s p2 ) (1 − s p2 )
where p1 and p2 are same as in eqn. (5.21) and p3 and z1 are given by
−1 ⎛ 1 1 1 ⎞ 1 1
p3 ≈ ⎜ + + ⎟≈ and z 1 = (24)
RZ ⎜⎝ CC CL C1 ⎟⎠ RZ C1 ⎛ 1 ⎞
⎜ RZ − ⎟
⎜
⎝ gm6 ⎟⎠
In order to remove the zero z1, we can either (1) choose to push z1 to ∞ or (2) push
the zero on the RHP to LHP to the same location as p2, consequently canceling the
pole p2. The latter approach is also called pole zero cancellation.
In case 1, we will need to choose RZ = 1/gm6.
In case 2, putting z1 = p2 we have,
1 g ⎛ (C + CL ) ⎞ ⎛ 1 ⎞
= m6 giving us RZ = ⎜⎜ C ⎟⎜ ⎟ (25)
CC (1 gm6 − RZ ) CL ⎝ CC
⎟⎜ g ⎟
⎠ ⎝ m6 ⎠
and the condition
−1 ⎛ 1 1 1 ⎞ 1 g
p3 = ⎜ + + ⎟≈ ≥ GBW = m1 (26)
RZ ⎝ CC CL C1 ⎠ RZ C1
⎜ ⎟ CC

4.2 Power Supply Rejection Ratio:

Power supply rejection ratio (PSRR) is a measure of the reflection of variations in
VDD and VSS at the output. This becomes an important factor when in a system
there is a considerable load variation on the power supply leading to the power
supplies VDD and VSS appearing as VDD + vdd and VSS + vss as shown in Fig. 21. We
define two metrics on PSRR, PSRR+ and PSRR-as defined below.

Fig. 21 A block representation of an op amp with power supply

variations.
 vout vout
(vdd = 0) (vss = 0)
vin vin
PSRR =
+
; PSRR =
−
(27)
vout vout
(vin = 0) (v = 0)
vdd vss in

4.2.1 PSRR to variations in VDD (PSRR+)

(a) (b)
Fig. 22 (a) The op. amp circuit showing the signal flow to evaluate PSRR+
(b) Small signal equivalent circuit to evaluate PSRR+

Fig. 22 gives the op amp circuit showing the signal flow due to VDD fluctuations and
the equivalent circuit. From the equivalent circuit shown in Fig. 22(b), we obtain
the PSRR+ = vout/vdd as

⎡ ⎛ s Cc ⎞ ⎛ s (Cc C1 + Cc CL + CL C1 ) ⎞⎤
⎢ ⎜⎜ + 1 ⎟⎟ ⎜⎜ + 1 ⎟⎟ ⎥
gm1 gm6 ⎢ ⎝ gm1 ⎠⎝ gm6 Cc ⎠⎥
PSRR + =
(gds1 + gds3 ) gds6 ⎢ ⎛ s gm6 Cc ⎞ ⎥
⎢ ⎜
⎜ (g + g ) g + 1 ⎟
⎟
⎥
⎢⎣ ⎝ ds1 ds3 ds6 ⎠ ⎥⎦
(28)
⎡ ⎛ s Cc ⎞ ⎛sC ⎞⎤
⎢ ⎜⎜ + 1 ⎟⎟ ⎜⎜ L + 1 ⎟⎟ ⎥
gm1 gm6 ⎢ ⎝ gm1 ⎠ ⎝ gm6 ⎠ ⎥ = vdd
=
(gds1 + gds3 ) gds6 ⎢⎛ s gm6 Cc ⎞⎥ vout
⎢⎜ + 1 ⎟⎥
⎢⎣ ⎜⎝ (gds1 + gds3 ) gds6 ⎟⎥
⎠⎦
4.2.1.1 PSRR to variations in VSS (PSRR-)

(a) (b)
Fig. 23 (a) The op. amp circuit showing the signal flow to evaluate PSRR-
(b) Small signal equivalent circuit to evaluate PSRR-

Fig. 23 gives the op amp circuit showing the signal flow due to VSS fluctuations and
the equivalent circuit. From the equivalent circuit shown in Fig. 23(b), we obtain
the PSRR+ = vout/vdd as
⎡ ⎛ s Cc ⎞ ⎛sC ⎞⎤
⎢ ⎜⎜ + 1 ⎟⎟ ⎜⎜ L + 1 ⎟⎟ ⎥
⎛ gm1 gm6 ⎞ ⎢ ⎝ gm1 ⎠ ⎝ gm6 ⎠⎥
PSRR − = ⎜⎜ ⎟ (29)
( g + g ) g ⎟ ⎢ s C c
⎥
⎝ ds1 ds3 ds6 ⎠
⎢ +1 ⎥
⎢⎣ (gds1 + gds3 ) ⎥⎦

4.2.2 Slew Rate:

Let us consider the response of an operational amplifier used in inverting unity gain
mode. Assuming that the amplifier is compensated and the dominant pole is located
at p1, we can write the output vout(t) to a step input vin(t) = V1u(t) as
A(0) ⎛ ⎛ A(0) ⎫ ⎞ ⎞
vout (t) = − V1 u(t) ⎜1 − exp⎜⎜ ⎧⎨ ⎬ + 1 ⎟
⎟ p1 t ⎟ (30)
(A(0) + 2) ⎜⎝ ⎝⎩ 2 ⎭ ⎠
⎟
⎠
This gives at the output an exponential rise before it settles down to the maximum
value. A similar behaviour can be obtained for a negative step as shown in Fig.
24(b). This is true when the input step is small, of the order of 1V for a ±5V supply
operation. However, for large steps, say 5V, the output shows a near linear rise and
fall. This is called slewing and the slope of the linear region is called the Slew rate.
Slewing is a large signal phenomenon.

Fig. 24 Response of a CMOS op. amp. Connected in the inverting

unity gain mode, showing slewing effect: (a) op. amp. In the
inverting unity gain mode (b) input waveform, (c) output
waveform for small input step (d) output waveform for
large input step.
To analyze the response of the op amp in Fig. 24 and thus evaluate the slew rate,
let us look in to the op amp with the differential stage drawn in detail and the gain
stage and the compensation capacitance as an amplifier with a capacitive feedback
as shown in Fig. 25.

Fig. 25 A model for calculating the slew rate for a CMOS op

amp as an inverting unity gain amplifier.
For a large signal at the gate of M1, M2 will be turned completely OFF and the
current 2IBIAS will flow through M1 and M3. This current will be mirrored in M4 and
will charge the compensation capacitance CC. The slew rate under this condition will
be given by
dv 2I
Sr = out = BIAS (31)
dt CC

Fig. 26 (a) A model for calculating the slew rate for a CMOS op amp
as a non-inverting unity gain amplifier (b) input and
corresponding output response for a large signal step input.

The step response of an op amp under voltage follower mode to a large positive
step input, V1u(t), shows an interesting jump followed by a linear increase, as shown
in Fig. 26(b). When a positive step input is applied to M2, Transistors M1, M3 and M4
are turned off. The current in M2 includes the current, iw drawn by CW, the
capacitance across the current source. Assuming that vin ≈ vw, where vw is the
voltage across CW, we have
dv (t ) dv (t )
iw (t ) = CW w ≈ CW in (32)
dt dt
The output voltage vout(t) is then given by
1 2I C
vout (t) = ∫ (2IBIAS + iw ) dt = BIAS + W V1 u(t) (33)
CC CC CC
The first term is the linear rise at the output while the second term is the step
seen at the output.
For a negative step input at M2, M2 will be turned OFF and all other transistors in
the diff. Amp will be turned ON. Under this condition we can say that vw ≈ vout
giving us
dvout 2I −i dv i 2IBIAS
= − BIAS w ≈ w = − w = − (34)
dt CC dt CW (CC + CW )
From eqn. 5.34 we see that the negative slew rate is decreased by the presence of
CW by a factor ( 1 + CW/CC).

5 Design example for a two stage compensated Op. Amp.:

In designing an opamp the following specifications are to be met:
Amplifier has VDD = 5.0V and VSS = 0V, Amplifier output should swing form
close to 5V to close to 0V with a minimum gain of 6000. The required gain
bandwidth product and slew rate are 2.5MHz. and 8V/µsec respectively.
The required CMR is 1.3V to 4.6V, the minimum acceptable phase margin is
60°
a. Draw the schematic circuit diagram including the bias arrangement.
b. Draw the equivalent circuit of the amplifier.
c. If the amplifier should be driving a capacitive load of 5pF, what should be
the operating DC current of the amplifier?
d. What should be the gm of the input transistor pair?
e. Obtain the W/L ratio of all the transistors used. Also obtain the power
dissipation and the over all voltage gain.

Given K ' = 50µA /V 2 ; K ' = 100 µA /V 2 ; λ = 0.05; λ = 0.04; 0.60V < V , V < 0.80V , VDD=5V, VSS =
P N N P T1 T 03

0V

a)
b)

c) The required slew rate is 8V/µsec and the capacitive load is 5pF. To
obtain a phase margin of at least 60°, we require CC ≥ 0.22CL. Let us
consider CC > 0.22CL = 1.5pF.
Slew rate = 8V/μsec = 2IBIAS/CC, giving us 2IBIAS = 8 * 1.5μA = 12μA or
IBIAS = 6μA.

d) We are given that the required gain bandwidth product is 2.5MHz. We

know that the gain bandwidth product is given by 𝐺𝐵𝑊 = 𝑔!! 𝐶! , where
gm1 is the gm of the input transistors and the gain bandwidth product is
!
expressed in rad/sec. We therefore have, !!! = 2 𝜋 ∗ 2.5 ∗ 10! wherefrom
!
we obtain the required gm1 = 2π(2.5 * 10 * 1.5 * 10-12 ) = 23.56 * 10-6S.
6

The gm of the input transistor should be 23.56µS.

e) W/L ratio for M3 and M4: Using the condition for VG1(max)
⎛W ⎞ 2I BIAS
⎜ ⎟ =
⎜ ⎟
⎝ L ⎠3 K ' ⎡V − V max − V
2
⎤
P ⎢
⎣ DD G1 ( ) T 03
max( )
+ V T1 ( )
min ⎥⎦
12 x 10−6 ⎛W ⎞
= = 6 = ⎜⎜ ⎟
⎟
⎝L
2
50 x 10−6 ⎡5 − 4.6 − 0.80 + 0.60⎤
( ) ⎠4
⎣ ⎦
(2)
W/L ratio for M1 and M2: Knowing the value of gm1 we can write,
 2
⎛W
⎜
⎞ ⎛W
⎟ =⎜
⎞
⎟ =
g 2m 1
=
23.56 (
≈ 0.5
)
⎜ ⎟ ⎜ ⎟
⎝L ⎠1 ⎝ L ⎠2 2K N I 1 (2)(100)(6)
'

(2)
W/L ratio for M5:
2I BIAS
V DS 5 = V G 1 min − V SS −
K1
( )
− VT 1 max

12
= 1.3 − 0 − − 0.8 = 0.02V
50
With VDS5 = 0.31V = VGS5 – VT1(max) gives us VGS5 = 1.11V = VGG5

⎛W
⎜
⎞
⎟ =
2I 5
=
(
2 12 x 10−6 ) ≈ 600
⎜ ⎟
⎝L
2 2
⎠5 K ' V
5 ( ) (100 x 10 ) (0.02)
DS 5
−6

(2)
W/L ratio for M6: We take gm6 = 10 gm1 = 1571µS
Since IDS3 = IBias = 10µA, 𝐾!! = 50µA/V2 and (W/L)3 is 6, we get

!
!!! !"∗! !.!
! !
𝑔!! = 𝑔!! ! !
= 23.56 !""∗!.!
= 57.71
!!
! !
Since VGS3 = VGS6,

⎛W ⎞ ⎛W ⎞ ⎛g ⎞ ⎛ ⎞
⎜ ⎟ =⎜ ⎟ ⎜ m 6 ⎟ = 6 ⎜ 235.6 ⎟ ≈ 24.5
⎜ ⎟ ⎜ ⎟ ⎜ ⎟
⎝L ⎠6 ⎝ L ⎠4 ⎜g ⎟
⎝ m3 ⎠ ⎝ 57.71 ⎠
(2)
From the expression for gm6 we have,
2

I6 =
g 2m 6 ( =
) = 22.65µA
235.6 x 10−6

2K 6
'
(W 6) (2) (50 x 10 ) (24.5)
6
−6

⎛W ⎞ ⎛W ⎞ ⎛ I ⎞ ⎛ 22.65 x 10−6 ⎞
and ⎜⎜ ⎟ = ⎜ ⎟ ⎜ 6 ⎟ = 600 ⎜
⎟ ⎜ ⎟ ⎜ ⎟ ⎜
⎟ = 1132
⎟
⎝L L I 12 x 10 −6
⎠7 ⎝ ⎠5 ⎝ 5 ⎠ ⎝ ⎠
(2)
The total Power dissipation is Pdiss = 5V(16µA + 22.65µA) = 0.193mW and
the over all gain is
 (23.56 x 10−6 ) (2356x 10−6 )
AV = = 1890
16 x 10−6 (0.04 + 0.05)22.65x 10−6 (0.04 + 0.05)
(2)

Since the gain is far too lower than 6000, let us increase W/L ratio of M1 by a
⎛W ⎞ ⎛W ⎞
factor of 10 i.e let ⎜⎜ ⎟⎟ = ⎜⎜ ⎟⎟ = 5 giving us gm1 = 74.56 µS. Let us recalculate
⎝ L ⎠1 ⎝ L ⎠2
all other values.

2I BIAS
V DS 5 = V G 1 min − V SS −
K1
− VT 1 max ( )
12
= 1.3 − 0 − − 0.8 = 0.345V
500

giving us
⎛W
⎜
⎞
⎟ =
2I 5
=
(
2 12 x 10−6 ) ≈ 2.1
⎜ ⎟
⎝L
2 2
⎠5 K ' V
5 DS 5( ) (100 x 10 ) (0.345) −6

W/L ratio for M6: We take gm6 = 10 gm1 = 745.6µS

Since IDS3 = IBias = 10µA, 𝐾!! = 50µA/V2 and (W/L)3 is 6, we get

! !.!
!!! !"∗! !.!
! !
𝑔!! = 𝑔!! ! !
= 74.56 !""∗!
= 57.75
!!
! !
Since VGS3 = VGS6,

⎛W ⎞ ⎛W ⎞ ⎛g ⎞ ⎛ ⎞
⎜ ⎟ =⎜ ⎟ ⎜ m 6 ⎟ = 6 ⎜ 745.6 ⎟ ≈ 77.46
⎜ ⎟ ⎜ ⎟ ⎜ ⎟
⎝L ⎠6 ⎝ L ⎠4 ⎜g ⎟
⎝ m3 ⎠ ⎝ 57.75 ⎠
From the expression for gm6 we have,
2

I6 =
g m6
2
( =
) = 71.76µA
745.6 x 10−6

2K '6 (W L) (2) (50 x 10 ) (77.46)

6
−6

⎛W ⎞ ⎛W ⎞ ⎛I ⎞ ⎛ 71.76 x 10−6 ⎞
and ⎜⎜ ⎟ =⎜
⎟ ⎜
⎟ ⎜ 6 ⎟ = 2.1 ⎜
⎟ ⎜ ⎟ ⎜
⎟ = 12.6
⎟
⎝L ⎠7 ⎝ L ⎠5 ⎝ I 5 ⎠ ⎝ 12 x 10
−6
⎠
The total Power dissipation is Pdiss = 5V(16µA + 71.76µA) = 0.438mW and the
over all gain is
 (74.56 x 10−6 ) (745.6x 10−6 )
AV = = 5977
16 x 10−6 (0.04 + 0.05) 71.76x 10−6 (0.04 + 0.05)

This is acceptable and the design is through.