CDX-600/606/626

SERVICE MANUAL US Model

CDX-600/606

Canadian Model
AEP Model
UK Model
CDX-600

E Model
CDX-626

Photo: CDX-600

Model Name Using Similar Mechanism CDX-505RF

CD Drive Mechanism Type MG-250C-137
Optical Pick-up Name KSS-521A/J2N

SPECIFICATIONS

COMPACT DISC CHANGER

MICROFILM
 CDX-600/606/626

7-3. SCHEMATIC DIAGRAM – RF Section – • See page 18 for Waveforms. • See page 31 for IC Block Diagrams.

(Page 27)

The components identified by mark ! or dotted Les composants identifiés par une marque ! sont
line with mark ! are critical for safety. critiques pour la sécurité. Ne les remplacer que
Replace only with part number specified. par une piéce portant le numéro spécifié.

– 21 – – 22 –
CDX-600/606/626

7-6. SCHEMATIC DIAGRAM – MAIN Section (1/2) – • See page 18 for Waveforms. • See page 33 for IC Block Diagrams.

(Page 22)

– 27 – – 28 –
 CDX-600/606/626

7-7. SCHEMATIC DIAGRAM – MAIN Section (2/2) – • See page 18 for Waveforms. • See page 33 for IC Block Diagrams.

– 29 – – 30 –
• IC Block Diagrams IC52 BA6287F
– RF Board –
OUT1 1 8 GND
IC11 CXA1992BR

RF M
RFTC

RF O
PD1

CC1

FOK
PD2

RF I

CC2
PD

LD

CP
CB
39 38 37 36 35 34 33 32 31 30 29 28 27
VM 2 7 OUT2

PD 2 PD 1 PD LD
I-V AMP I-V AMP AMP AMP RF SUMMING DRIVER DRIVER
AMP FOCUS OK TSD
COMPARATOR

VCC 3 6 VREF
VCC CONTROL LOGIC
LASER
POWER
CONTROL
IFB1 – IFB6 POWER
PEAK/BOTTOM MIRR SAVE
HOLD COMPARATOR IIL
↓ FIN 4 5 RIN
FE PEAK/BOTTOM DEFECT TTL
40
BIAS HOLD AMP

FOCUS BIAS
FOCUS ERROR
WINDOW
VEE AMP
COMPARATOR

DFCT1
LDON

MIRR
LPCL

TGFL
LPC
FOH
FOL

CC1
F I-V
F 41
AMP
IIL 26 SENS2
E I-V TRACKING GAIN
TGH ↓ 25 SENS1
E 42 TGFL TTL
AMP WINDOW TGL 24 C. OUT
COMPARATOR – MAIN Board –
EI 43 BALH IIC DATA REGISTER, INPUT SHIFT REGISTER,
ADDRESS DECODER, SENSE SELECTOR,
VEE 44 VEE BALL 23 XRST
OUTPUT DECODER IC101 CXD2530Q
TEO 45 TTL 22 DATA
ATSC
TOG1 – TOG4
BAL1 – BAL4

↓ 21 XLT

PCMD
EMPH
WFCK

MNT0
MNT1
MNT3
SCOR

DOUT
SBSO

GTOP
XROF
C2PO

XPCK
XUGF
EXCK

RFCK
IIL

XTSL
TES6

TES5

TES4

TES3

TES9
FSTT
C4M
CLK

VDD

VDD
20

VSS

VSS

BCK
GFS
19 LOCK
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
TZC

FZC

E-F BALANCE
LPFI 46 WINDOW
TG1 – TG2

PS1 – PS4
FS1 – FS4
DFCTO

IFB1 – IFB6
BAL1 – BAL4
TOG1 – TOG4

TM1 – TM7

COMPARATOR VCC 18 VCC

TEI 47 VCC 50 LRCK
NC 81 49 WDCK
ATSC
ATSC 48 WINDOW ISET 17 ISET VSS 82
TM6 VDD 48 ASYE
COMPARATOR 83
NC 47 ASYO
84 ERROR ASYMMETRY
TZC 16 SL O 46 ASYI
TZC 49 TES7 85 CORRECTOR CORRECTOR
COMPARATOR D/A 45 BIAS
NC 86 EFM INTERFACE 44 RF
TM1 15 SL M VSS 87 DEMODULATOR
43 AVDD
XVDD 88
DFCT TRACKING PHASE 42 CLTV
– XTAI 89 DIGITAL
COMPENSATION XTAO 16K RAM DIGITAL OUT 41 AVSS
14 SL P 90 PLL
TDFCT 50 TG1 TM5
+
40 FILI
VCC XVSS 91
TM2 VSS 92 39 FILO
NC 93 38 PCO
CENTER VEE SUB CODE
VCC TES8 94 37 VCTL
VC 51 VOLTAGE PROCESSOR OSC
TM7 NC 95 36 V16M
GENERATOR
VDD 96
FZC 35 VCKI
FZC 52 VCC TM4 VSS 97 CLOCK
COMPARATOR 34 VPCO1
VEE NC 98 GENERATOR
33 VPCO2
NC 99
FOCUS PHASE FS1 TIMING 32 TES1
CHARGE UP XRST 100 SERVO
COMPENSATION LOGIC CPU 31 TES0
AUTO
INTERFACE DIGITAL CLV
SEQUENCER
–
+

FS4 FS2
DFCT
FSET
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
TG2 TM3
VDD
VSS
LMUT
RMUT
TES2
CKOUT
SQCK
SQSO
SENS
DATA
XLAT
CLOK
SEIN
CNIN
DATO
XLTO
CLKO
SPOA
SPOB
SPOC
SPOD
XLON
FOK
VDD
VSS
MON
MDP
MDS
LOCK
PWMI
VEE VEE
1 2 3 4 5 6 7 8 9 10 11 12 13
FSET
FEO

TA O
SRCH
FLB
FE O
FDFCT

TA M
TGU

TG2
FE M
FEI

FGD

– 31 – – 32 –
IC204 BA8272F-E2 IC301 BA6287F

DATA OUT
LINK OFF

CLK OUT

DATA IN
BUS ON

RESET
OUT1 1 8 GND
VCC

14 13 12 11 10 9 8

RESET VM 2 7 OUT2
SWITCH

DRIVER DRIVER
TSD
1 2 3 4 5 6 7
BUS CLK
VREF
BUS ON OUT

BUS ON IN

GND

BUS DATA

BUS RESET
VCC 3 6 VREF
CONTROL LOGIC

POWER
SAVE

FIN 4 5 RIN

IC401 TC9464FN-EL
(EMP)

GNDX
LRCK

DATA

MCK
(SM)

SH

VDX
(BS)
BCK

ATT

LA
HS

XO

XI

24 23 22 21 20 19 18 17 16 15 14 13

INTERFACE MICROCOMPUTER
INTERFACE OSC
CIRCUIT
CIRCUIT

DIGITAL FILTER CIRCUIT TIMING

ATTENUATOR OPERATIONAL CIRCUIT GENERATOR

DEEMPHASIS FILTER CIRCUIT

D-∆ MODULATION CIRCUIT

TEST OUTPUT OUTPUT

CIRCUIT CIRCUIT CIRCUIT

ANALOG ANALOG
FILTER FILTER

1 2 3 4 5 6 7 8 9 10 11 12
VDD

T1

P/S
VDA

RO

GNDA

VR

GNDA

LO

VDA
ZD
GNDD

– 33 –
7-8. IC PIN FUNCTION DESCRIPTION
• MAIN BOARD IC302 CXP84124-080Q (SYSTEM CONTROLLER)
Pin No. Pin Name I/O Function
Sled limit in detect switch (SW1) input terminal
1 LIM.SW I
“L”: When the optical pick-up is inner position
2 BUSON I Bus on/off control signal input from the SONY bus interface (IC204) “H”: bus on
3 EJECT I Eject switch (SW303) input terminal “H” active
Save end detect switch (SW12) input terminal
4 LOAD1 I
“L”: When completion of the disc chucking operation
Chucking end detect switch (SW11) input terminal
5 LOAD2 I
“L”: When completion of the disc chucking operation
6 A.MUTE O Audio line muting on/off control signal output terminal “H”: muting on
7 EMPH O Emphasis mode output to the D/A converter (IC401) “L”: emphasis on
Motor drive signal (save direction) output to the chucking motor drive (IC52)
8 CH.R O
“H” active *1
Motor drive signal (load chucking direction) output to the chucking motor drive (IC52)
9 CH.F O
“H” active *1
10 — O Not used (open)
Motor drive signal (elevator down direction) output to the elevator motor drive (IC301)
11 ELV.R O
“L” active *2
12 ELV.ON O Mechanism deck section power supply on/off control signal output “H”: power on
13 CD RST O System reset signal output to the CXA1992BR (IC11) and CXD2530Q (IC101) “L”: reset
14 CDON O D/A converter and servo section power supply on/off control signal output “H”: power on
15 to 23 — O Not used (open)
Setting terminal for the automatic adjustment
24 AUTO ON/OFF I
“L”: automatic adjustment, “H”: manual adjustment (fixed at “L” in this set)
25 to 29 — O Not used (open)
System reset signal input from the reset signal generator (IC202) and SONY bus interface (IC204)
30 RESET I “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
31 EXTAL I Main system clock input terminal (8 MHz)
32 XTAL O Main system clock output terminal (8 MHz)
33 VSS — Ground terminal
34 TX O Sub system clock output terminal Not used (open)
35 TEX I Sub system clock input terminal Not used (fixed at “L”)
36 AVSS — Ground terminal (for A/D converter)
37 AVREF I Reference voltage (+5V) input terminal (for A/D converter)
38 ATRIBT I Selection input of the custom file, D-BASS, etc.
Input of signal for the fine adjustment (linear position sensor adjustment; RV301) of elevator
39 MCK I
position (A/D input)
40 EHS I Elevator height position detect input from the RV302 (elevator height sensor) (A/D input)
41 to 47 — O Not used (open)
48 SCK I Serial data transfer clock signal input from the SONY bus interface (IC204)
49 SI I Serial data input from the SONY bus interface (IC204)
50 SO O Serial data output to the SONY bus interface (IC204)
51 SQCLK O Subcode Q data reading clock signal output to the CXD2530Q (IC101)
52 SUBQ I Subcode Q data input from the CXD2530Q (IC101)
53 — O Not used (open)
54 — I Not used (fixed at “H”)
Magazine eject operation completion detect switch (SW301) input terminal
55 MGLK I
“L”: eject completed

– 34 –
 Pin No. Pin Name I/O Function
56 SCOR I Subcode sync (S0+S1) detection signal input from the CXD2530Q (IC101)
57 SENS2 I Internal status signal (sense signal) input from the CXA1992BR (IC11)
Motor drive signal (elevator up direction) output to the elevator motor drive (IC301)
58 PWM O
“L” active *2
59 — O Not used (open)
60 MAG.SW I Magazine in/out detect switch (SW302) input terminal “L”: magazine detected
61 BUCHECK I Battery detection signal input terminal “H”: battery on
62 W.UP I Bus on or eject switch (SW303) input terminal “H”: bus on or eject switch pushing
63 C.OUT I Track number count signal input from the CXA1992BR (IC11)
64 EEDATA I/O Two-way data bus with the EEPROM Not used (open)
65 EECLK O Serial clock signal output to the EEPROM Not used (open)
66 EEINIT I Initialize signal input for the EEPROM “H”: format Fixed at “L” in this set
67 — O Not used (open)
Setting terminal for the single disc/multiple discs mode
68 SINGLE I
“L”: single mode, “H”: multiple discs mode (fixed at “H”)
69 FOK I Focus OK signal input from the CXA1992BR (IC11) “L”: NG, “H”: OK
70 GFS I Guard frame sync signal input from the CXD2530Q (IC101) “L”: NG, “H”: OK
71 SENS1 I Internal status signal (sense signal) input from the CXD2530Q (IC101)
72 VDD — Power supply terminal (+5V)
73 NC (VDD) — Connected to the power supply (+5V)
74 CDCLK O Serial data transfer clock signal output to the CXD2530Q (IC101)
75 CDXLT O Serial data latch pulse signal output to the CXD2530Q (IC101)
76 CDDATA O Serial data output to the CXD2530Q (IC101)
77 to 80 — O Not used (open)

*1 chucking motor (M103) control

Mode LOAD
STOP SAVE BRAKE
Terminal CHUCKING
CH.F (pin 9) “L” “H” “L” “H”
CH.R (pin 8) “L” “L” “H” “H”

*2 elevator motor (M104) control

Mode ELEVATOR ELEVATOR
STOP BRAKE
Terminal UP DOWN
PWM (pin %•) “H” “L” “H” “L”
ELV.R (pin !¡) “H” “H” “L” “L”

– 35 –