STAR Memory System Top Level

Interface Handling

Application Note - 0316

STAR Memory System 6.x

November 2018
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Revision History

Version Date Note

1.0 November, 2018 Initial revision

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Table of Contents
1 Introduction ............................................................................................................................................................. 5
2 General Information ................................................................................................................................................5
3 TAP interface signals ..............................................................................................................................................6
4 Clock and reset signals ...........................................................................................................................................7
5 SMART interface control signals ........................................................................................................................... 14
6 DFT related signals ............................................................................................................................................... 18
7 SMS status signals ............................................................................................................................................... 19
8 UDR signals .......................................................................................................................................................... 21
9 Power down signals .............................................................................................................................................. 21
10 Other control signals ............................................................................................................................................. 23

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1 Introduction
This document is intended to provide the top level overview of the SMS Network signals and give an idea on how to
organize power up and smart sequencing of the SMS. It provides information about SMS Network all clock and reset
signals as well as other control signals that need specific handling for BIST test. It is assumed that the reader is familiar
with SMS Network components such as SMS Wrapper, SMS Processor and SMS Server (SFP and JPC) and knows
the architecture of the system.
Please note, that the document describes the mentioned flow for one level server architecture. A separate document
on two-level server approach is under development. Meanwhile please check server compiler User Manual for the
details on two level server.

2 General Information
Before going deep into the document, it is useful to understand the difference between SoC usage in production
and on the field.
During production, the goal is to comprehensively test the memories under all corners and all available March test
algorithms to identify all potential failures. This will help to generate the so called golden repair signature taking into
account all the faults that can happen in the memories during normal usage (on the field). Then the signature will be
burned into e-fuse non volatile container. In production phase, JTAG TAP will be used as it gives full access to the
SMS data and instruction registers. Specifying the proper instructions sequence users will be able to run the desired
test on the memories scheduling them in a specific way depending on the design specification. For example, to
consume less power, users need to disable some SMS-es and run the test only on the specific set of memories.
Similarly, the diagnostic data can be shifted out using JTAG TAP interface for debug purposes. For example, memory
faults bitmapping.
Smart mode is to be used on the field (application mode). It is assumed that the chip is tested and all failures are
identified and repaired. E-fuse is programmed with the golden repair signature. This is a chip normal usage. After power
up to use the memories functionally, these need to be repaired. Toggling just one pin (smart interface) the SMS will
initiate a predefined sequence of actions which will load the repair data from e-fuse into memories and perform other
checks to make sure the repair has been successful. JTAG TAP can also be used on the field, but usually to save the
area designers do not put the JTAG controllers into the SoC giving the precedence to smart control interface.

The top interface of the SMS network can be divided into the following subparts:
o TAP interface signals
o Clock and reset signals
o SMART interface control signals
o DFT related signals
o SMS status signals
o UDR signals
o Power down signals
o Other control signals

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3 TAP interface signals

Figure 1
JTAG TAP interface is intended to access the SMS instruction and data registers during production mode. SMS
Network consists of two JTAG TAP controllers: master and spare. Master TAP is highlighted with green color in Figure
1. Though we provide RTL for the master TAP controller, usually customers replace our TAP controller with their TAP
controller having more instructions to have an access to the functional logic registers. To do this, it is mandatory to
specify SMS related TAP instructions to be able to control SMS-es through the custom TAP controller. The detailed
description of the “JTAG TAP Controller and STAR Memory System Network Integration” can be found in apnt0300.pdf
application note. The red TAP controller is so called spare TAP controller. This is inactive by default and in reset state.
While in reset state the master TAP is selected. SP_TAP can be activated only if customer working with functional logic
wants to access purely to SMS registers and wants to perform specific operations on the memories or SMS
components. This is the light version of the TAP controller supporting only SMS logic. The RTL for SP_TAP controller
needs to be taken from compout directory. The RTL files for both TAP controllers can be found under
./compout/views/<server_name>/ directory. The interface signal names that will be visible from top level module are
shown on the left side of Figure 1 above.

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Please note slow clock multiplexer in Figure 1 is switching off the TCK clock and enabling func_slow_clk signal
that will be sourced to SMS System slow clocks (TCK for SFP_JPC Server and WRCK for SMS). The diagram above
is just the representation of the clocks and the TAP control. It shows how it is done in the SMS system standalone files.
The RTL for the above circuit can be found in the compout directory in the <server_name>_top.v file. Please note that
the file will not be inserted automatically to the user design with the STAR Builder tool. This is up to the designer to
select the desired way to control the system and the clocks during production (testing through ATE) and smart (on the
field usage) modes. We do not request to have two TAP controllers in the system as shown below. Based on the SoC
usage scenarios only one TAP controller can be sufficient removing the need to have SP_TAP in the system.

4 Clock and reset signals

SMS Network clock signals

Signal name Designation SMS top level handling

WRCK SMS IEEE1500 serial interface clock One per SMS. All SMS-es WRCK
signal. signals must be connected to each
other and be driven from the same
source. At the top level this will be
connected to JTAG TCK for
production mode and slow clock in
the field.

clk_sms SMS fast running clock One per SMS. All SMS-es clk_sms
signals can be connected to each
other and be driven from the same
source. Also these can be
propagated to the top level and be
driven completely independently
from different sources. This is fully
up to the user and based on design
specification.

TCK TAP, JPC, SFP/JPC clock JTAG TAP TCK clock. Goes down to
JPC and SFP modules.

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SMS System reset signals

Signal name Designation SMS top level handling

TRSTN TAP controller asynchronous active low TAP reset signal. Does not drive
signal(optional) directly the SMS Network signals.

WRSTN IEEE1500 serial interface asynchronous One per SMS processor. All SMS-es
active low signal WRSTN signals must be connected
to each other and be driven from the
same source. At the top level this
will be connected to single reset
source (sys_rst).

rst_sms SMS Processor/Wrapper registers reset One per SMS processor. All SMS-es
signal rst_sms signals can be connected to
each other and be driven from the
same source. Also, these can be
propagated to the top level and be
driven completely independently
from different sources. This is fully
up to the user and based on design
specification.

rst_sfbp Shared Fuse Processor registers reset Single signal going to SFP only. Has
signal the same polarity as rst_sms. Can
be controlled from the same source
as rst_sms.

Figure 2 shows the interconnectivity in the SMS Network in terms of clock and reset signals.

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WRCK
IEEE1500 Wrap 1
Mem 1
WRSTN

Wrap 2 Mem 2
SMS
Server Processor
SFP/JPC 1
Mem 3
clk_sms_1 Wrap 3
rst_sfbp clk_sms
p tclk_sms

rst_sms_1 TCLK
resetn

TCK
Tck ; WRCK
clk_sfbp WRSTN
IEEE1500
Wrap 1 Mem 1

Wrap 2 Mem 2
SMS
Processor
2
func_mode Wrap 3
clk_sms_2 Mem 3
clk_sms tclk_sms
1 0
rst_sms_2
TCLK
spif_mode
MUX
slow_func_clock

TRSTN TAP APB

controller driver
TCK

JTAG APB
control control
–
signals signals

Figure 2

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Presented below is a list of things to keep in mind while handling SMS Network Clock and Reset signals
Clock related:

a. There are two clocks used in SMS Processor/SMS Wrapper – slow (WRCK) and fast (clk_sms)
b. Basically WRCK is IEEE1500 clock and clk_sms is controlling SMS logic flip flops
c. WRCK is also used to control repair data loading mechanism. (See item “i” for more details).
d. The memory controlled by SMS system will be run at clk_sms clock applied to SMS Processor.
e. Each SMS Processor can have separate clk_sms clocks having different frequency and be driven from
different sources
f. clk_sms clocks of different SMS Processors can be connected together and driven from the same source.
g. The same clock should be applied to all the SMS Processors/SMS Wrappers WRCK signal and be driven
from the same source
h. During BIST flow all the clk_sms and WRCK clocks need to be applied and running for powered on SMS-es.
This is important to note when different SMS-es are sourced from different clk_sms clocks.
i. During BIST flow clk_sms and WRCK clocks can be gated for the powered off SMS-es. This is safe since the
powered down SMS is out of the SMS-es global chain and does not block any other SMS placed in powered
on domain.
j. SMS System designed the way clk_sms is not needed during Hard Repair flow. So, the process of loading e-
fuse repair data into memory reconfiguration register does not require fast clk_sms clock in most of cases.
The only exception is the case when the memory having the internal reconfiguration register does not have
dedicated clock for its control and sharing the same functional clock to shift in/out the repair data. During Hard
Repair Flow clk_sms should be either gated or running. It cannot toggle randomly.
k. SMS Server (SFP/JPC) does not have fast clock and the only controlling clock is slow TCK clock.
l. On the system SMS Processor, SMS Wrapper WRCK slow clocks and SMS Server TCK clock needs to be
driven from the same source.
m. During BIST production mode when controlling the system through JTAG, SMS Processor, SMS Wrapper
WRCK slow clocks and SMS Server TCK clock need to be driven from JTAG TAP TCK clock.
n. On the field, the SMS Processor, SMS Wrapper WRCK slow clocks, and SMS Server TCK clock should be
sourced from the same clock. The source is not JTAG TCK clock, since in most of the cases users do not use
JTAG controller on the field. See func_slow_clock in Figure 1.

Reset related:
a. There are two reset signals used in SMS Processor: rst_sms and WRSTN
b. Each SMS Processor has WRSTN signal and each SMS Processor and SMS Wrapper have rst_sms signal
c. WRSTN is used to reset IEEE1500 interface flip flops
d. rst_sms is used to reset the rest of the SMS logic
e. WRSTN is always asynchronous active low and does not depend on SMS configuration
f. There is a reset synchronization logic put on WRSTN signal to synchronize it with WRCK.
g. rst_sms can be configured with reset_type SMS Wrapper custom parameter and have 2 options:

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reset_type = 1 Asynchronous with Active low Must remain active for at least 3
synchronizers (three) WRCK periods. This is the
safe reset scenario that has been
tested on our side.

reset_type = 2 Asynchronous without Active low Must remain active for at least 3
synchronizers (three) WRCK periods. This is the
safe reset scenario that has been
tested on our side.

For more information on reset synchronizers please refer to SMS Processors User’s Manual provided together
with SMS Processor and SMS Wrapper compilers in the same directory.
h. SMS System does not support different reset_type parameters for different SMS Processors/SMS Wrappers.
reset_type parameter should be the same across all the SMS Wrappers/Processors/Server.
i. reset_type parameter is applied from SMS Wrapper configuration and effective for the SMS Processor and
upper hierarchy SMS modules.
j. Basically rst_sms, WRSTN signals from different SMS-es can be tied together and controlled from the same
reset tree. This scenario may become not viable in case some set of initially powered down SMS-s will be
reset at the time the other set of SMS-s is running either in test or functional mode. Reset gating needs to be
considered in such a power up scenario.
k. There are two reset signals for SMS Server: wrstn and rst_sfbp.
l. Server level wrstn signal is resetting the SFP IEEE1500 registers and JPC control logic registers.
m. rst_sfbp is resetting SFP control logic registers.
n. Server JPC wrstn is synchronized and asynchronous active low signal and does not depend on SMS
configuration.
o. rst_sfbp is dependent on reset_type parameter specified in SMS Wrapper. Please refer to item “g” for more
details.
p. All resets in the SMS system can be connected to each other and driven from the same reset tree. The most
conservative reset signal requirements should be considered in this case.
q. It is not mandatory to control the reset signals from the same source. The requirement is to have all the SMS
System flip flops initialized prior to BIST flow activation.
r. In case the resets are driven from different sources, it is mandatory to apply the reset pulse to all the signals
and only activate any of the SMS test sequences. The resets can be applied in any order with no specific
recommendation on which one to start first.
s. Refer to chapter “Wrapper Compiler for SRAM Clocking” of the Wrapper User’s Manual for details on clock
and reset sequence.

The waveforms shown in Figure 3 are provided for the project having three SMS-es. SMS_2 is running at 1.25ns
clock, another at SMS_1 is running at 5ns and SMS_3 at 2.5ns. Based on the design considerations the rst_sms signals
for SMS_1 and SMS_2 and SMS_3 were combined and done through the same source. Also note that IEEE1500 serial
interface WRSTN reset signals were connected to the same source as SMS_1 and SMS_2 and SMS_3 rst_sms reset
signal. Right at the reset time the ready_sms status bit goes to low, but after reset de-assertion it goes to high indicating
the specific SMS or SFP_JPC Server is ready for new instructions. In this project all WRSTN resets are tied to the
same reset source, which is not mandatory. WRCK clocks are driven from TAP TCK clock during production mode and
this is very important to run them from the same source. In the field, the slow clock can be driven from a different source
as it is mentioned in Figure 3. When the system is reset it is important to have the stable clocks running. In this example,
the clocks are being run normally as they were expected after 251ns. The purple marker shows the timeline when the

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clocks are stable. Though the system is in idle condition it can be dangerous having glitches on the clock since it may
damage the FF cell initial content depending on the specific cell physical design. This type of issues should be captured
during gate-netlist SDF simulation.

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5 SMART interface control signals
Smart interface signals are:
Signal Name Designation When available Component parameter
name(Can be set from
compiler *_custom.glb or
component configuration
*.cfg file) affecting the signal
or bus presence in the top
interface
Smart Activates SMART Mostly available. The exceptions user_total_num_of_fuses
flow. A pulse is are the below 3 cases:
needed. enable_smart_sch
a. At least one memory in
Enable SMART BIST the project contains redundancy_enable
Mode should be set redundancy and
from the processor enable_smart_sch =
level false. UDR is disabled.
b. The memories are
without redundancies
and neither of SMPR and
PMPR have parallel
access. UDR is disabled.
c. The ROM-s wrappers are
configured to have
external anti-signature.
UDR is disabled.
smart_bist_srv When asserted Available when more than one
includes BIST test to SMS integrated into the
SMART flow. Server/Sub-Server have such a
functionality, “Enable Hard Repair”
option is set to "true".
bist_algo_sel_srv The index of Test Available when more than one
[n-1:0] algorithm to be used SMS integrated into the
during SMS SMART Server/Sub-Server have such a
BIST sequence. functionality, “Enable Hard Repair”
option is set to "true".
bist_fail_srv SFP fail bit. High level Available when more than one
on this bit indicates SMS integrated into the
that an error occurred Server/Sub-Server have such a
in at least one SMS functionality, “Enable Hard Repair”
during SMS SMART option is set to "true".
BIST sequence.
bist_ready_srv SFP readiness pin. Available when more than one
High level indicates SMS integrated into the
that SMS SMART Server/Sub-Server have such a
BIST sequence is functionality, “Enable Hard Repair”
completed. option is set to "true”.
bihr_run When asserted the Available when at least one enable_smart_sch = true and
SMART sequence will memory in the project contains
contain the hard redundancy and redundancy_enable = true
repair. enable_smart_sch = true.
udr_load For both parallel and Available when user_total_num_of_fuses
serial UDR interfaces user_total_num_of_fuses SMS
loads UDR data from

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e-fuse to UDR register Server parameter is specified (for

in the SMS Server. example “6”).
udr_si1 Serial Input for UDR Available when UDR register type user_total_num_of_fuses = 6
register. is specified as serial. and
user_reg_type = "serial"
udr_en1 Serial Scan Enable for Available when UDR register type user_total_num_of_fuses = 6
UDR register. is specified as serial. and
user_reg_type = "serial"
udr_rdy Ready signal Available when user_total_num_of_fuses = 6
indicating UDR user_total_num_of_fuses SMS
register is loaded from Server parameter is specified (for
e-fuse. Logic high by example “6”).
default.
udr_so1 Serial Scan Output for Available when UDR register type user_total_num_of_fuses = 6
UDR register. is specified as serial. and
user_reg_type = "serial"
udr_in1 UDR register size bus. Available when UDR register type user_total_num_of_fuses = 6
Parallel input to the is specified as parallel. and
UDR register.
user_reg_type = "parallel"
udr_out1 UDR register size bus. Available when UDR register type user_total_num_of_fuses = 6
Parallel output to the is specified as parallel. and
UDR register.
user_reg_type = "parallel"
udr_wr1 Write signal. When Available when UDR register type user_total_num_of_fuses = 6
active with the TCK is specified as parallel. and
clock posedge write
the udr_in data to user_reg_type = "parallel"
UDR register.
sfp_fail Fail status bit Always available.
indicating failure
during any instruction
running on SMS
Server.
sfp_ready Ready status bit Always available.
indicating the SMS
Server instruction run
status.
ring_bypass Bus. Equals to total Always available.
[ring_num-1:0] number of Rings in the
project. Logic high
removes the
respective SMS from
SMS-es global chain.

1. These are not actual smart control signals and can be used also out of smart flow. These are brought to the list since can be used during smart mode to control UDR
register.

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Figure 4 below depicts the smart flow block diagram showing the smart flow depending on the smart control signals..

Assert smart control signals before smart pulse activation.

Generate smart pulse (negedge on the smart pulse will initiate the sequence)

Loads UDR part of the e-fuse to the UDR register for

further access through UDR pins (serial or parallel).
Once udr_load is complete, the user can shift out the YES
UDR content with available UDR interface (serial or udr_load = 1
parallel). WRCK clock is mandatory. clk_sms is not
required for this procedure.1

NO

Loads repair signature from e-fuse to SFP Buffer Data

register and shift into powered on(power_off bus
dedicated bit is low) SMS-es. WRCK clock is YES
mandatory. clk_sms is not required for this procedure.
bihr_run = 1

NO

YES
Runs BIST test on the memory’s full address space and bisr_run = 1
loads the updated repair signature into powered on
(power_off bus dedicated bit is low) SMS memories
reconfiguration registers. WRCK and clk_sms clock are NO
mandatory.

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Runs BIST test on the powered on SMS (power_off

bus dedicated bit is low) memory’s full address YES
space. WRCK and clk_sms clock are mandatory. bist_run = 1

NO

Loads BYPASS instruction into the powered

on SMS-es (power_off bus dedicated bit is
low). End of SMART sequence.

The complete flow shown above can be

started again from the very first step. For
example, this is needed to run the sequence
on the previously powered off SMS-es by
changing power_off bus value before smart
pulse generation.

Figure 4

1. Synopsys memories can be generated in two ways: with internal and external repair register. reconfig_reg is the memory parameter to control this. When the memory
is generated with external repair register it will be placed inside SMS Wrapper and controlled with WRCK. clk_sms clock will not be needed for repair register shift
in/out. When the repair register is inside the memory the memory will have a dedicated interface to shift in/out the value of the repair register. If the interface has the
dedicated clock for shifting purposes, SMS will control it with WRCK and there will be no need for clk_sms clock for BIHR flow. The clk_sms will be needed only in
case the memory internal reconfiguration register interface does not have a dedicated clock signal and repair data will be shifted in/out using memory operational
clock. This is the only case when BIHR flow will require the clk_sms running.

Depending on the predefined smart sequence the smart run time will differ. The total smart run time can be represented
as a sum of all smart sub-sequences run times. The total run time will be Tudr_load + Tbihr_run + Tbisr_run + Tbist_run. Each
and every SFP_JPC Server instruction cycle numbers can be found in the SFP_JPC Server data-sheet. For example,
the cycles required to complete UDR_LOAD instruction will be described as “Nudr_load” and will be stated under
UDR_LOAD instruction description chapter.

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Smart control waveforms are shown in Figure 5

6 DFT related signals

Signal Name Designation Component Name Signal handling from
controlled by the SMS level
signal
sfp_dft_mode Server DFT signal. Gates the reset signals SMS Server Single signal.
of the Server (when reset_type = 1) and
ties e-fuse signals to safe values.
dm0 SMS Processor/Wrapper signal. Gates the SMS Processor and One per SMS. While
reset signals (when reset_type = 1) of SMS Wrapper inserting the SMS-es into
Processor and Wrapper and puts the functional design all the
memory into DFT mode activating dm0 signals can be tied
periphery logic. together and controlled
through a single signal.
dm1 SMS Processor/Wrapper signal. Gates the SMS Processor and One per SMS. While
reset signals (when reset_type = 1) of SMS Wrapper inserting the SMS-es into
Processor and Wrapper and puts the functional design all the
memory into DFT mode activating dm1 signals can be tied
periphery logic. together and controlled
through a single signal.
dm2 SMS Processor/Wrapper signal. Gates the SMS Processor and One per SMS. While
reset signals (when reset_type = 1) of SMS Wrapper inserting the SMS-es into
Processor and Wrapper and puts the functional design all the
memory into DFT mode activating dm2 signals can be tied
periphery logic. together and controlled
through a single signal.

During functional usage all DFT related signals mentioned above have to be tied to low. This will let the memory and
e-fuse corresponding interface signals to get the control from SMS and SFP logic and toggle based on the specific
SMS/SFP processor instruction. During DFT mode the signals have to be applied to non-zero value. Sfp_dft_mode
signal has to be tied to high and dm0/dm1/dm2 signals need to be controlled based on the predefined dft operations
tcl file. The file is sourced to the wrapper using “dft_ops_file” wrapper custom GLB parameter during project generation.
For more information on DFT modes please look into SMS_Synthesis_and_DFT.pdf application note available in
sn6xx000vpnnsmref000s* part number.
During non DFT mode, the signals must be inactive. This will release the memory and e-fuse control signals
and grant the control to the SMS or functional logic. In this case the design can be used functionally. During DFT mode
sfp_dft_mode should be tied to logic high and dm* signals values should be different from 3’b000. As you will see from
SMS_Synthesis_and_DFT.pdf application note the specific dm* signals combination corresponds to the specific DFT
mode. Sometimes customers ask whether it is allowed to put the DFT signals into boundary register. The rule is that
during the predefined mode functional, SMS or DFT/ATPG the signals have to be static. These can be controlled from
boundary register if the User makes sure these are not being shifted or changed during specific SoC usage scenario.

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7 SMS status signals

Signal Name Designation Component Name Signal handling from
controlled by the SMS level
signal
fail_sms SMS Processor fail status bit. Output from SMS Processor One per SMS processor.
SMS processor. The signal needs to be
sourced to functional logic for failure
monitoring.
ready_sms SMS Processor ready status bit. Output SMS Processor One per SMS processor.
from SMS processor. The signal needs to
be sourced to functional logic for SMS run
operation completion monitoring.
sfp_fail SMS Server fail status bit. Output from SMS Server One per Server. Single
SMS Server. The signal needs to be signal since there is just
sourced to functional logic for SFP run one Server in the project.
operation failure monitoring.
sfp_ready SMS Server ready status bit. Indicates the SMS Server One per Server. Single
Server instruction run status. Output from signal since there is just
SMS Server. The signal needs to be one Server in the project.
sourced to functional logic for SFP run
operations completion monitoring.
udr_rdy SMS Server UDR ready status bit. SMS Server One per Server. Single
Indicates UDR register loading progress signal since there is just
from e-fuse into user data register inside one Server in the project.
SMS Server. Output from SMS Server.
The signal needs to be sourced to
functional logic for SFP run operations
completion monitoring.

Usually status bits are used to notify the functional logic about the SMS test run completion. After completion
the memories are available for functional logic.
Please look into the waveforms below in Figure 5.

The below waveforms show smart sequence split into two phases on different SMS-es. It is assumed that the
test is run on SMS_1 and SMS_3 at the first run and the second smart run will repair the SMS_2. Please notice
power_down signal value before smart pulse activation. Once power_down signal is asserted on the next TCK cycle
the smart signal can be activated. Please keep the smart at least 3 TCK cycles and the SFP_JPC Server state machine
will move from its IDLE condition with the falling edge of the smart signal. It is important to note that falling edge on the
smart signal is important to start smart sequence. As long as udr_load signal has been asserted prior to smart pulse
the SFP will first load the UDR data from e-fuse container into user data register. The process can be monitored with
udr_rdy signal. When goes low it means the UDR loading is processing. Once udr_rdy transitions to high, the user data
register is preloaded and ready to be shifted out. Smart sequence will continue the next steps based on the block

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diagram shown in Figure 5. At the same (in parallel) time the user data register can be scanned out using UDR parallel
signals. On the second smart pulse udr_load is specified as “low” since the UDR data is scanned out already. It will
just process the BIHR>BISR>BIST flow on the SMS_2. Please also note the SMS-es relevant ready_sms signals based
on smart pulses and power_down value. Note the powered down SMS-es ready signals. Depending on the
power_down value it does not change, meaning the SMS is not operating and has been disconnected from SMS-es
chain. Since we are performing BIHR and will be loading repair register from e-fuse it is important to make sure safe_rr
is kept low (see “Other control signals” section). DFT related signals and vddq are also inactive. The memory is put into
operational mode, so SMS can perform read and operations on the memory. As long as we have BISR and BIST
sequences in our smart flow we are mandated to supply both WRCK(TCK) and clk_sms clocks.

Figure 5

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8 UDR signals
UDR signals are dedicated to access UDR register using SMS Server parallel signals. The signal names are
udr_load, udr_si, udr_en, udr_rdy, udr_so, udr_in, udr_out, udr_wr and blk_jtag2udr. Please look into SMART interface
control signals chapter for signals full description.
The signal that needs additional description is blk_jtag2udr signal. When blk_jtag2udr pin is active (high), the
access to UDR register through JTAG interface during UDR_SEL instruction is denied. The UDR register can be
accessed only using parallel pins mentioned above.
Sometimes user needs to program the memories read margin information into e-fuse UDR part. This is needed
when they want to run the functional operations on the memories with custom RM values. The control over it can be
done using Server UDR parallel signals. To be able to achieve the task it is mandatory to have a dedicated access to
RM pins. In SMS 4.x the RM pins should be configured using one of the methods shown below:

1. RM and RME are controlled by SMPR or PMPR, but have parallel access enabled
(pa_pmpr_enable = true and pmpr_list = {RM RME} or
pa_smpr_enable = true and smpr_list = {RM RME})

2. RM and RME are not controlled by SMS and considered as functional signals
(pmpr_list = {does not contain RM and RME})

During smart flow execution user needs to assert udr_load control signal to preload SMS Server user data register from
e-fuse. The rest of the flow will slightly differ depending on UDR type specified during SFP_JPC Server configuration.
It is assumed that the e-fuse UDR part has been programmed already with the proper RM values.

1. If user_reg_type = "parallel" (SFP_JPC Server custom GLB parameter)

As soon as udr_load is accomplished (udr_rdy low to high transition), the UDR data will appear on UDR
output pins (udr_out). The output data can be sourced to the SMS input RM signals directly to control the
RM values. This is the recommended way.

2. If user_reg_type = "serial" (SFP_JPC Server custom GLB parameter)

As soon as UDR data is preloaded, it needs to be shifted out into the functional register. In this case udr_si,
udr_se and udr_so signals will be used for shifting purposes. The functional register will be driving the RM
signals. This method requires additional register in functional logic, hence is not recommended. Being more
difficult scenario this is represented in Figure 5
Figure 5

Please look into “Memory RM Repair Recommended Flow” chapter of SMS Server User’s Manual for additional
information.

9 Power down signals

SMS Network may consist of many SMS-es that will be split around in the SoC and belong to different power
domains. Accessing to the SMS Network either through TAP controller or smart interface the SMS-es will be serially
connected to each other through their WSI and WSOR serial signals. Having one of the SMS-es switched off will
break the chain and make it impossible to load the required instruction to the SMS standing next to the switched off
SMS in the SMS-es queue. Ring Bypass Register is dedicated to remove the selected SMS from the queue. Ring
Bypass register can be accessed using ring_bypass[num_of_sms:0] parallel bus or SMS Server RBYPASS_SEL
instruction. The format of the register is shown in Figure 6 below.

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Figure 6
The register width is defined by the number of SMSs. The SMS-es numbering is specific per SMS project and
will be shown in Server datasheet file. This will look as it is shown in Figure 7.

Figure 7
pwdn[0] bit will correspond to the “1” processor in the datasheet and so on.
Each bit of the register is assigned for a particular SMS and the code loaded into the register defines whether
a corresponding SMS is powered off (“1” if power-down, “0” if power-up). Power down register is assigned to bypass a
corresponding SMS using JPC_SFP internal circuitry (1-bit bypass register per each SMS) to be independent of
whether SMS is powered-up because the user may be required to isolate the SMS regardless it is powered or not. This
allows to keep the serial data path viable when JPC_SFP operates with daisy chained SMSs.
Figure 8 below shows the SMS-es interconnectivity to Server based on power down register value.

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Powered
SMS 1
off SMS 2 SMS 3
domain
SMS is
connected to the
Fuse Box JPC/SFP chain
SMS is NOT
Power down
1 register
1 0 0 1 1 0 0
connected to the
SMS 8 SMS 4 chain
1 2 3 4 5 6 7 8
sms sms sms sms sms sms sms sms

Powered
SMS 7 SMS 6 off SMS 5
domain
Figure 8
It is assumed that SMS Server is on always on power domain.
During the test you can specify the SMS-es that are powered off (or you want to exclude them from the test
flow) and activate BIST_RUN instruction. This can be done either through JTAG interface or smart parallel
pins. After test run completion the power down register can be selected again enabling the disabled
memories and disabling the enabled ones and re-run the test again. The test-flow will be very similar to the
one described on the block-diagram and waveforms shown in Figure 4 and Figure 5.

10 Other control signals

The only remaining signals are safe_rr and SMPR parallel pins.
The SMPR pins are being defined during wrapper configuration using
“smpr_list = { "memory input signal name" " memory input signal name " " memory input signal name " }” and
pa_smpr_enable parameters. You can find the detailed information on these signals and their initialization flow from
MPR access through JTAG for SMS 5.x and 6.x apnt-0253.pdf.
safe_rr signal is indented to block the memory reconfiguration register (if memory is configured with
reconfig_reg = 1 and redundancy_enable = 1 parameters) or wrapper reconfiguration register (when reconfig_reg = 0
and redundancy_enable = 1) reset and input pins. With this signal the reset and shift operations along with the
reconfiguration register are disabled not to affect the reconfiguration information. This is done based on Figure 9 below.
safe_rr signal will be the input to each SMS processor controlling at least on repairable memory. During repair
data operation (BIRA_RUN, MRR2INBR, FLOAD_RUN, BIHR_RUN, BISR_RUN) the safe_rr must be tied to low to
give an access to the reconfiguration register to be loaded in/out.

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dm0
dm1
dm2

Reconfiguration
safe_rr Register
0 SE
T rscout
rscin D Q
1
rscen 0
1'b0
1
CL
R
RST Q
WRCK

rst_sms
0
1'b0 (inactive level)
1

Figure 9

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