Von Neumann Architecture

The Von Neumann Architecture

The first computers had fixed programs and changing a computer program required physically rewiring or
redesigning the machine. This meant that re-repurposing a computer was a difficult, expensive and time-
consuming process.
The Mathematician John Von-Neuman designed the specification for the first programmable computer in
1954, where the programs themselves could be stored in memory, not just data.
Instructions are stored in memory and are retrieved and processed by the Central Processing Unit one by
one. This blueprint is known as the Von-Neumann Architecture.
The Von-Neuman Architecture is based on the principle of:

 Fetch an Instruction
 Decode the Instruction
 Execute the Instruction
The process above is repeated indefinitely, and is known as the fetch, decode, and execute cycle.

Registers
The registers form part of the CPU Cache, temporarily storing data ready for processing or send to the
RAM.

PC – Program Control Register

The program control register stores the address of the current instruction. Once the current instruction has
been fetched and decoded, the program control register changes to the address of the next instruction.
IR – Instruction Register
The instruction register contains the current instruction itself, retrieved from it’s stored address.

MAR – Memory Address Register

The memory address register contains the memory location of either the next instruction to be fetched or
the location of where the results of the current process are to be stored.

MDR – Memory Data Register

The memory data register contains either the data retrieved from memory (either an instruction or an
operand) during the current fetch cycle at the address stipulated in the MAR, or the data the is due to be
written to memory.

ACC – Accumulator
The accumulator receives the results of the current process from the ALU and stores it for the use in the
next Fetch-Decode-Execute cycle.

IX – Index Register
This register is used when performing operations involving index addressing.

Buses
Buses are the physical wires along which data is passed, both within the CPU itself and across the
motherboard.

CPU Bus
The CPU bus is used to pass data around the CPU between the CU, ALU and registers.

Control Bus
The Control bus sends signals to the RAM, indicating whether to initiate a read or write on the address
received along the address bus

Address Bus
The address bus is the wire along which the address of the memory location in RAM required for the
read/write is sent.

Data Bus
The data bus is the wire along which the data is sent either to or from the RAM (depending whether a
read or write has been initiated.

CPU Performance
CPU performance is affected by a number of key characteristics:
Clock Speed
The clock speed is the number of instructions per second that the a CPU can process, and is currently
usually measured in GigaHertz GHz. A 3.2 Ghz processor can process 3,200,000,000 processes per
second, in theory. This is dependent of course on the processor receiving all the instructions it needs from
the main memory.

Cache Size
In order to ensure that the next instruction is loaded and ready to be processed by the CPU, commonly
executed instructions are stored in the Cache memory area of the CPU. The larger the cache memory, the
more commonly used instructions can stored and therefore it is less likely that the CPU will have to stop
and wait for instructions to be loaded. Modern CPUs have a cache size up to 1 or 2 Megabytes.

Number of cores
Many modern computers contain dual, quad or even 8 core processors (effectively 8 separate CPUs on
one chip). Most computers are used used for multitasking applications, for example you might be
listening to music playing on YouTube at the same time as playing a computer game. The most efficient
way to handle multitasking is to assign one core of the processor to one particular application. This means
that if one core has to wait from data to load from the hard disk, the other cores are not affected.
The overall theoretical speed of a processor can be calculated by multiplying the number of cores by the
processor speed. e.g.

 4.2 Ghz Dual Core processor = 4.2 x 2 = 8.4Ghz

 2.2 Ghz Quad Core processor = 2.2 x 4 = 8.8Ghz
Although the 4.2 Ghz processor has a higher base speed, the quad core processor has a higher effective
speed.
Quad core processors only run faster than single core processors if the operating system and software
being used is able to take advantage of multi-threading, otherwise the extra cores will merely sit idle.

Assembly Language and two pass assembler

Computer Instruction Set
Computer instruction consists of an op-code and one or more operands
Symbolic Addressing vs Absolute Addressing
When we write computer programs in a high level language we use Symbolic Addressing, where we refer
to memory locations using identifier names for variables, functions, data structures etc.
Example program to calculate profit

 LDD REVENUE
 SUB COST
 STR PROFIT
This program is easy for humans to read. If we used absolute addressing instead it would be very difficult
to understand the purpose of the code.
This has two key advantages in assembly language programming:

 First it makes the programs easier to read as we are using words that mean something to us.
 Second it means that if the memory location where that data is stored changes we only have to
change it once in our program.
 The computer cannot process these symbolic addresses so when the program is assembled all
symbolic addresses are replaced with the memory address assigned to that symbol. The assembler
builds a symbol table or symbolic names and the corresponding addresses in memory.
Profit program after the symbolic addresses have been swapped out

 LDD #4454
 SUB #3326
 STR #4410

Grouping Instruction Sets

Show understanding that a set of instructions are grouped

Including the following groups:

 Data movement
 Input and output of data
 Arithmetic operations
 Unconditional and conditional instructions
 Compare instructions
Addressing Mode
Immediate Addressing
The operand is actual value to be used.
So if the instruction LDM 4 – the number 4 would be sent to the accumulator.

Direct Addressing
The operand is the address of the value to be used.
If the instruction is LDD 1 then the value stored at address 1 will sent to the accumulator.
Indirect Addressing
The operand is the address of the address to be used. This is similar to direct, but with one more hop in
the process.

Indexed Addressing
The operand plus the contents of the Index Register is the address of the value to be used.
Relative Addressing
The operand is the offset from the current address of the value to be used.
Logical Left Shift

In a left shift each bit is simply moved to the left with the empty space on the right replaced with zero.

Example

000110
<< 2
011000

Logical Right Shift

In a logical right shift the bits are shifted to the right and the most significant bit(empty bit to the left ) is
replace with zero. The least significant bit(Any bit falling off the right) is discarded

Example
0011001
>>1
0001100

Arithmetic Left Shift

Arithmetic left shifts work the same as logical left shifts. The bit is shifted to the left (the sign bit is
discarded) with zeroes add at the right hand end.
Example
000110
<< 2
011000

Arithmetic Right Shift

In an arithmetic right shift the bit is shifted to the right but the most significant bit is copied to the
next most significant bit position on the left.
This is used when the most significant bit is the sign bit (1s/2s Compliment) indicating + / – value. The
least significant bit is discarded.
Example 1

1011
>>1
1101

Example 2

10110100
>>3
11110110

Cyclic Shift

These shifts can be performed either left or right. No data is discarded as the bit that falls off one end is
added to the other end.

Example
10110011
Shift 3 Right
01110110
Bit Manipulation Instruction Table
Here is the table given by the exam board in the syllabus.

Instruction
Label Explanation
Opcode Operand

AND #n Bitwise AND operation of the contents of ACC with the operand

Bitwise AND operation of the contents of ACC with the contents

AND <address>
of <address>

XOR #n Bitwise XOR operation of the contents of ACC with the operand

Bitwise XOR operation of the contents of ACC with the contents

XOR <address>
of <address>

OR #n Bitwise OR operation of the contents of ACC with the operand

Bitwise OR operation of the contents of ACC with the contents of

OR <address>
<address> (can be an absolute address or a symbolic address)

Bits in ACC are shifted logically n places to the left. Zeros are
LSL #n
introduced on the right hand end

Bits in ACC are shifted logically n places to the right. Zeros are
LSR #n
introduced on the left hand end

<label>: <opcode> <operand> Labels an instruction

Gives a symbolic address to the memory location with contents

<label>: <data>
<data>

Bit Masking Operations

When computers were first invented processing power was very limited so any tricks that could be used to
speed up processing were incredibly useful and as such bit masking was introduced.
Bit Masking allows the checking, setting and resetting individual bits within a binary without having to
loop through or involve complicate logic. It could all be achieved at the logic circuit level which meant that
the operations were incredibly efficient.
Computers are far more powerful today, however the amount of data our programs process has also
increased exponentially, and so in certain circumstances these ‘binary tricks’ can still come in credibly
handy. They are also useful in low level control applications where simple systems use individual bits as
flags. These systems are often battery/solar power systems so it is also useful to reduce processing as much
as possible. Bit masking is also still widely used in networking when using subnet masks.
Register Transfer Notation
The following table is an example of an instruction set:

Instruction Explanation

Opcode Operand

LDM #n Immediate addressing. Load the number n to ACC

LDD <address> Direct addressing. Load the contents of the location at the given address
to ACC

LDI <address> Indirect addressing. The address to be used is at the given address. Load
the contents of this second address to ACC

LDX <address> Indexed addressing. Form the address from <address> + the contents of
the index register. Copy the contents of this calculated address to ACC

LDR #n Immediate addressing. Load the number n to IX

MOV <register> Move the contents of the accumulator to the given register (IX)

STO <address> Store the contents of ACC at the given address

ADD <address> Add the contents of the given address to the ACC

ADD #n/Bn/&n Add the number n to the ACC

SUB <address> Subtract the contents of the given address from the ACC

SUB #n/Bn/&n Subtract the number n from the ACC

INC <register> Add 1 to the contents of the register (ACC or IX)

DEC <register> Subtract 1 from the contents of the register (ACC or IX)

JMP <address> Jump to the given address

CMP <address> Compare the contents of ACC with the contents of <address>

CMP #n Compare the contents of ACC with number n

CMI <address> Indirect addressing. The address to be used is at the given address. Compare the
contents of ACC with the contents of this second address

JPE <address> Following a compare instruction, jump to <address> if the compare was
True

JPN <address> Following a compare instruction, jump to <address> if the compare was
False

IN Key in a character and store its ASCII value in ACC

OUT Output to the screen the character whose ASCII value is stored in ACC

END Return control to the operating system

All questions will assume there is only one general purpose register available (Accumulator) ACC denotes
Accumulator
IX denotes Index Register
<address> can be an absolute or symbolic address # denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001010 & denotes a hexadecimal number, e.g. &4A