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Correction TP

The document contains VHDL code for 4 different circuits: 1. A movie ticket machine that changes states based on coin inputs to eventually output a ticket and coins. 2. An elevator that changes between up, down, and stopped states based on button inputs. 3. A testbench that simulates the ticket machine and elevator circuits. 4. A counter circuit that sequences through states to output a quarter signal every 10 counts.

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Hichem Guedri
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55 views4 pages

Correction TP

The document contains VHDL code for 4 different circuits: 1. A movie ticket machine that changes states based on coin inputs to eventually output a ticket and coins. 2. An elevator that changes between up, down, and stopped states based on button inputs. 3. A testbench that simulates the ticket machine and elevator circuits. 4. A counter circuit that sequences through states to output a quarter signal every 10 counts.

Uploaded by

Hichem Guedri
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Correction TP :

Exercice 2 : machine Film (programme Programme test


principale)
LIBRARY IEEE; Library ieee;
USE IEEE.STD_LOGIC_1164.ALL; Use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity test_machine is
ENTITY machine IS PORT ( End test_machine;
clk : IN STD_LOGIC; Architecture test_Arc_machine OF
un_dollar : IN STD_LOGIC; deux_dollars : test_machine is
IN STD_LOGIC; film : OUT component machine
STD_LOGIC; PORT (
monnaie : OUT STD_LOGIC clk : IN STD_LOGIC;
); un_dollar : IN STD_LOGIC;
END machine; deux_dollars : IN STD_LOGIC;
film : OUT STD_LOGIC;
ARCHITECTURE rtl OF machine IS monnaie : OUT STD_LOGIC);
TYPE etats IS (zero, un , deux, trois, quatre, end component;
cinq, six); SIGNAL etat_present : etats; signal clk,un_dollar,deux_dollars, film ,
SIGNAL etat_prochain : etats; monnaie: std_logic:='0';
begin
BEGIN u1: machine port map
(clk,un_dollar,deux_dollars, film , monnaie);
PROCESS (etat_present, un_dollar, process
deux_dollars) BEGIN begin
CASE etat_present IS WHEN zero => clk<='0'; wait for 10 ns;
clk<='1'; wait for 10 ns;
film <= '0'; end process;
monnaie <= '0'; un_dollar<='1','0' after 20 ns, '1' after 40 ns,
IF un_dollar = '1' THEN '0' after 60 ns;
etat_prochain <= un; deux_dollars<='0','1' after 20 ns, '0' after 40
ELSIF deux_dollars = '1' THEN ns, '1' after 60 ns;
etat_prochain <= deux; ELSE end test_Arc_machine;
etat_prochain <= zero; END IF;
WHEN un =>
film <= '0';
monnaie <= '0';
IF un_dollar = '1' THEN etat_prochain <=
deux;
ELSIF deux_dollars = '1' THEN
etat_prochain <= trois;
ELSE
etat_prochain <= un; END IF;
WHEN deux =>
film <= '0';
monnaie <= '0';
IF un_dollar = '1' THEN
etat_prochain <= trois;
ELSIF deux_dollars = '1' THEN
etat_prochain <= quatre;
ELSE
etat_prochain <= deux;
END IF;
WHEN trois =>
film <= '0';
monnaie <= '0';
IF un_dollar = '1' THEN etat_prochain <=
quatre;
ELSIF deux_dollars = '1' THEN
etat_prochain <= cinq; ELSE
etat_prochain <= trois; END IF;
WHEN quatre => film <= '0';
monnaie <= '0';
IF un_dollar = '1' THEN etat_prochain <=
cinq;
ELSIF deux_dollars = '1' THEN
etat_prochain <= six;
ELSE

etat_prochain <= quatre; END IF;


WHEN cinq =>
film <= '1';
monnaie <= '0';
etat_prochain <= zero; WHEN six =>
film <= '1';
monnaie <= '1'; etat_prochain <= zero;
END CASE; END PROCESS;

PROCESS (clk) BEGIN


IF clk'EVENT AND clk = '1' THEN
etat_present <= etat_prochain; END IF;
END PROCESS;

END rtl;
Exercice 3 monte charge (programme Programme test
principale)
LIBRARY IEEE; Library ieee;
USE IEEE.STD_LOGIC_1164.ALL; Use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity test_montecharge is
ENTITY montecharge IS End test_montecharge;
PORT ( Architecture test_Arc_montecharge OF
B, p0, p1 : IN STD_LOGIC; test_montecharge is
M, D : OUT STD_LOGIC component montecharge
); PORT (B, p0, p1 : IN STD_LOGIC;
END montecharge; M, D : OUT STD_LOGIC
);
ARCHITECTURE rtl_montecharge OF end component;
montecharge IS signal B, p0,p1, M, D: std_logic:='0';
TYPE etats IS (ar, mon, desc); begin
SIGNAL etat_present : etats; u1: montecharge port map (B, p0,p1, M, D);
B<='0', '1' after 10 ns, '0' after 20 ns, '1' after
BEGIN 30 ns, '0' after 40 ns ;
p0<= '0', '1' after 10 ns, '0' after 20 ns, '1'
PROCESS (etat_present, p0,p1, B) BEGIN after 40 ns ;
CASE etat_present IS p1<= '0' , '1' after 20 ns, '1' after 30 ns, '0'
WHEN ar => M<='0'; after 40 ns;
D<='0'; end test_Arc_montecharge;
if (B='1' and p1='1') then
etat_present<= desc;
elsif (B='1' and p0='1') then
etat_present<= mon;
else
etat_present<= ar;
end if;
WHEN desc => M<='0';
D<='1';
if (B='0' and p0='1') then
etat_present<= ar;
else
etat_present<= desc;
end if;
WHEN mon => M<='1';
D<='0';
if (B='0' and p0='0') then
etat_present<= ar;
else
etat_present<= mon;
end if;
END CASE;
END PROCESS;
end;
Exercice 4 compteur(programme principale) Programme test
LIBRARY IEEE; Library ieee;
USE IEEE.STD_LOGIC_1164.ALL; Use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity test_compteur is
ENTITY compteur IS End test_compteur;
PORT ( Architecture test_Arc_compteur OF
clk : IN STD_LOGIC; test_compteur is
qrt : OUT STD_LOGIC component compteur
); PORT (
END compteur; clk : IN STD_LOGIC;
qrt : OUT STD_LOGIC
ARCHITECTURE rtl_compteur OF );
compteur IS end component;
TYPE etats IS (zero, un , deux, trois, quatre, signal clk,qrt: std_logic:='0';
cinq, six, sept, huit, neuf); begin
SIGNAL etat_present : etats; u1: compteur port map (clk,qrt);
process
BEGIN begin
clk<='0'; wait for 10 ns;
PROCESS (etat_present, clk) clk<='1'; wait for 10 ns;
BEGIN end process;
if clk'event and clk='1' then end test_Arc_compteur;
CASE etat_present IS
WHEN zero => etat_present<=un;
qrt<='0';
WHEN un => etat_present<=deux;
qrt<='0';
WHEN deux => etat_present<=trois;
qrt<='0';
WHEN trois => etat_present<=quatre;
qrt<='0';
WHEN quatre => etat_present<=cinq;
qrt<='0';
WHEN cinq => etat_present<=six;
qrt<='0';
WHEN six => etat_present<=sept;
qrt<='0';
WHEN sept => etat_present<=huit;
qrt<='0';
WHEN huit => etat_present<=neuf;
qrt<='1';
WHEN neuf=> etat_present<=zero;
qrt<='0';
END CASE;
end if;
END PROCESS;
end;

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