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Counter V

This document describes a 4-bit up/down counter module and its testbench. The counter module uses a clock input and reset signal to increment or decrement the count. It can count up from 0 to 15 or down from 15 to 0 depending on the state of the UpOrDown input. The testbench applies different conditions to the inputs over time to test the up/down counting functionality.

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Samy
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30 views2 pages

Counter V

This document describes a 4-bit up/down counter module and its testbench. The counter module uses a clock input and reset signal to increment or decrement the count. It can count up from 0 to 15 or down from 15 to 0 depending on the state of the UpOrDown input. The testbench applies different conditions to the inputs over time to test the up/down counting functionality.

Uploaded by

Samy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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module upordown_counter(

Clk,
reset,
UpOrDown, //high for UP counter and low for Down counter
Count
);

//input ports and their sizes


input Clk,reset,UpOrDown;
//output ports and their size
output [3 : 0] Count;
//Internal variables
reg [3 : 0] Count = 0;

always @(posedge(Clk) or posedge(reset))


begin
if(reset == 1)
Count <= 0;
else
if(UpOrDown == 1) //Up mode selected
if(Count == 15)
Count <= 0;
else
Count <= Count + 1; //Incremend Counter
else //Down mode selected
if(Count == 0)
Count <= 15;
else
Count <= Count - 1; //Decrement counter
end

endmodule

Testbench for counter:

module tb_counter;

// Inputs
reg Clk;
reg reset;
reg UpOrDown;

// Outputs
wire [3:0] Count;

// Instantiate the Unit Under Test (UUT)


upordown_counter uut (
.Clk(Clk),
.reset(reset),
.UpOrDown(UpOrDown),
.Count(Count)
);

//Generate clock with 10 ns clk period.


initial Clk = 0;
always #5 Clk = ~Clk;
initial begin
// Apply Inputs
reset = 0;
UpOrDown = 0;
#300;
UpOrDown = 1;
#300;
reset = 1;
UpOrDown = 0;
#100;
reset = 0;
end

endmodule

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