University M’Hamed Bougara, Boumerdes

Institute of Electrical and Electronics Engineering

Digital Systems I with VHDL

Lab Work # 7
Design, Simulation and Implementation of Basic
Digital Circuits using VHDL Design Entry

Done by
- BAY Seif-El-Islam
- MELAH Raid Chems Eddine

L03, G06

Fall-2022
Sun, 20 Nov, 2022

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Introduction:
Complex digital electronic circuits can now be captured using VHDL (VHSIC
Hardware Description Language), which is becoming more and more popular for
both simulation and synthesis. VHDL-based digital circuit capture makes it simple
to simulate captured circuits, increases their likelihood of being synthesized into
numerous target technologies, and allows them to be archived for future
modification and reuse.
Objectives:
The objective of this laboratory experiment is to get hands-on experience
with VHDL design entry (We will create basic digital circuits using the dataflow
design style by writing VHDL codes. We will download your design onto the
EP2C35F672C6 device and map your circuit signals to the FPGA pins. Then, we will
run the RTL Viewer).
Equipment and components:
- A computer with QURATUS II installed in it.

- The DE2 board - DE2 Pins Assignements Preferences

Getting Started:
1. Launch Quartus II.
2. Start a new project.
3. Choose Cyclone II, and from Available devices, choose EP2C35F672C6.
4. To create a VHDL source code file
From Quartus II window select: File  New  VHD file and click OK.

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Problem 1: Majority
Three inputs and one output make up a circuit. Whenever we have a
majority of 1s in the three inputs, the output should be true (1). In all other
circumstances, the result should be false.
- Write the VHDL code for this circuit using
i- Direct signal assignment statement:

The VHDL code for Prob1

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iii- Assign input and output pins, then download your design onto the FPGA of the
DE2 board to test its functionality.

iv- It is possible to see the circuit synthesized by the synthesizer. To see this circuit,
proceed as follows:
• In TASK window (left), Expand Analysis & Synthesis sub-list.
• Expand Netlist Viewer folder.
• Double click on RTL Viewer

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Problem 2: Bar-Graph LED
WE must enter a value in a bar graph where an increasing number of LEDs
come on as the input number increases. Red LEDs (LEDR7–LEDR0) can be used to
mimic your bar-graph LED. To verify your design's functionality, compile it, assign
pins to it, and download it onto the FPGA.

Bar-Graph LED

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Problem 3:
There are six inputs and six outputs in a combinational circuit. Wi (i = 0, 1, 2,... 5)
represents the six inputs, while Yi (i = 0, 1, 2,... 5) represents the six outputs.
- If and only if Wk is "1" and each Wi is "0" for all i > k, then Yk is 1.
a- Write an optimal VHDL code for this circuit.

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 b- Assign logic switches to the inputs and LEDs to the outputs. Download your
code onto the FPGA of the DE2 board to verify its functionality.

Problem 4: Hexadecimal to 7-Segment Display Converter

Problem 5:

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Conclusion:
In lab 7, We were introduced to VHDL in order to build circuits an easier and
more efficient method than Schematic Capture. Throughout the lab, we had to
write different VHDL codes, which were then tested. I learned basic knowledge of
VHDL such a show to set up a VHDL code, its syntax, and how to test and run it.
These skills would help us through future labs with VHDL by building upon this
basic knowledge in order to write more complicated codes and test them more
efficiently.

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