INTRODUCTION TO COMPUTER SYSTEM

ASSEMBLY LANGUAGE: (LOW –LEVEL LANGUAGE):

To make programming easier, many programmers write programs in assembly language. They then
translate it to m/c language so that it can be loaded into memory and run. Assembly language used
two, three or four letter mnemonics to rep. each instruction type. A mnemonic is just a device to help
you remember something
Ex: for subtraction, the mnemonic is SUB
To copy data from one location to other, MOV

High Level languages: Ex: C, Pascal

An interpreter program or a compiler program is used to translate higher level language Statements
tom/c codes which are loaded into memory and then executed. These programs can be written faster.
However, programs written in HLL execute more slowly and require more memory than the programs
written in assembly language.
Compiler: Compiler is used to translate the high-level language program into machine code at a time.
It doesn’t require special instruction to store in a memory, it stores automatically. The Execution time
is less compared to Interpreter.

ASSEMBLY LANGUAGE PROGRAM STATEMENT FORMAT:

1. Label: It is a symbol or group of symbols used to rep. an address which is not specifically
known at the time the statement is written. Labels are followed by a colon. They are optional
2. OP code field: It contains mnemonic for the instruction to be performed. Instruction
mnemonics are also called operation codes.
3. Operand field: It contains the data, the memory address, the port address, other name of the
register on which the instruction is to be performed. It is just another name for the data items
acted on the instruction. In the previous example, there are two operands AL and 07H.
4. Comment field: (optional)They start with a semicolon. There are two ways for translating an
assembly language tom/c language. One way is to work out the binary code for each
instruction a bit at a time using the templates given in the manufacturer‟s data books. The
second method of doing the translation is with an assembler.

ASSEMBLY LANGUAGE DEVELOPMENT TOOLS:

To develop an assembly language program we need certain program development tools. The various
development tools required for 8086 programming are explained below.
1. Editor: An Editor is a program which allows us to create a file containing the assembly
language statements for the program. Examples of some editors are PC write (Wordstar). As
we type the program the editor stores the ACSII codes for the letters and numbers in
successive. RAM locations. If any typing mistake is done editor will alert us to correct it. If
we leave out a program statement an editor will let you move everything down and insert a
line. After typing all the program we have to save the program for a hard disk. This we call it
as source file. The next step is to process the source file with an assembler. While using
TASM or MASM we should give a file name and extension .ASM.
Ex: Sample. asm
2. Assembler: An Assembler is used to translate the assembly language mnemonics into
machine language( i.e binary codes). When you run the assembler it reads the source file of
your program from where you have saved it. The assembler generates two files . The first file
is the Object file with the extension .OBJ. The object file consists of the binary codes for the
instructions and information about the addresses of the instructions. After further processing,
the contents of the file will be loaded in to memory and run. The second file is the assembler
list file with the extension .LST.
 3. Linker: A linker is a program used to connect several object files into one large object file.
While writing large programs it is better to divide the large program into smaller modules.
Each module can be individually written, tested and debugged. Then all the object modules
are linked together to form one, functioning program. These object modules can also be kept
in library file and linked into other programs as needed. A linker produces a link file which
contains the binary codes for all the combined modules. The linker also produces a link map
file which contains the address information about the linked files. The linkers which come
with TASM or MASM assemblers produce link files with the .EXE extension.
4. Locator: A locator is a program used to assign the specific addresses of where the segments
of object code are to be loaded into memory. A locator program called EXE2BIN comes with
the IBM PC Disk Operating System (DOS). EXE2BIN converts a .EXE file to a .BIN file
which has physical addresses.
5. Debugger: A debugger is a program which allows loading object code program into system
memory, executing the program, and troubleshooting or debugging it. The debugger allows
looking into the contents of registers and memory locations after the program runs. We can
also change the contents of registers and memory locations and rerun the program. Some
debuggers allows to stop the program after each instruction so that you can check or alter
memory and register contents. This is called single step debug. A debugger also allows to set
a breakpoint at any point in the program. If we insert a break point , the debugger will run the
program up to the instruction where the breakpoint is put and then stop the execution.
6. Emulator: An emulator is a mixture of hard ware and software. It is usually used to test and
debug the hardware and software of an external system such as the prototype of a
microprocessor based instrument.

INTRODUCTION TO PROCESSOR
A processor is the logic circuitry that responds to and processes the basic instructions that drive a
computer. The term processor has generally replaced the term central processing unit (CPU). The
processor in a personal computer or embedded in small devices is often called a microprocessor. The
processor (CPU, for Central Processing Unit) is the computer's brain. It allows the processing of
numeric data, meaning information entered in binary form, and the execution of instructions stored in
memory.

Evolution of Microprocessor:
A microprocessor is used as the CPU in a microcomputer. There are now many different
microprocessors available. Microprocessor is a program-controlled device, which fetches the
instructions from memory, decodes and executes the instructions. Most Micro Processor are single
chip devices. Microprocessor is a backbone of computer system which is called CPU. Microprocessor
speed depends on the processing speed depends on DATA BUS WIDTH.
 A common way of categorizing microprocessors is by the no. of bits that their ALU can work
with at a time
 The address bus is unidirectional because the address information is always given by the
microprocessor to address a memory location of an input / output devices.
 The data bus is Bi-directional because the same bus is used for transfer of data between
microprocessor and memory or input / output devices in both the direction.
 It has limitations on the size of data. Most Microprocessor does not support floating point
operations.
 Microprocessor contain ROM chip because it contain instructions to execute data.

What is the primary & secondary storage device?

 a) In primary storage device the storage capacity is limited. It has a volatile memory. Primary
devices are: RAM (Read / Write memory, High Speed, Volatile Memory) / ROM (Read only
memory, Low Speed, Non Voliate Memory)
b) In secondary storage device the storage capacity is larger. It is a non-volatile memory.
Secondary devices are: Floppy disc / Hard disk

Types of Microprocessor
1. 4-bit Microprocessor:
The first microprocessor (Intel 4004) was invented in 1971. It was a 4-bit calculation device
with a speed of 108 kHz. Since then, microprocessor power has grown exponentially. So what
exactly are these little pieces of silicone that run our computers (" Common Operating Machine
Particularly Used For Trade Education And Research ")
 It has 3200 PMOS transistors.
 It is a 4-bit device used in calculator.

2. 8-Bit microprocessor:
In 1972, Intel came out with the 8008 which is 8-bit.
In 1974, Intel announced the 8080 followed by 8085 is a 8-bit processor Because 8085 processor has
8 bit ALU (Arithmetic Logic Review). Similarly 8086 processor has 16 bit ALU. This had a larger
instruction set then 8080. used NMOS transistors, so it operated much faster than the 8008. The 8080
is referred to as a “Second generation Microprocessor”

Limitations of 8 Bit microprocessor:

 Low speed of execution
 Low memory addressing capability
 Limited number of general purpose registers
 Less power full instruction set
Examples for 4/ 8 / 16 / 32 bit Microprocessors:
a) 4-Bit processor – 4004/4040
b) 8-bit Processor - 8085 / Z80 / 6800
c) 16-bit Processor - 8086 / 68000 / Z8000
d) 32-bit Processor - 80386 / 80486

What are 1st / 2nd / 3rd / 4th generation processor?

i. The processor made of PMOS technology is called 1st generation processor, and it is made up
of 4 bits
ii. The processor made of NMOS technology is called 2nd generation processor, and it is made
up of 8 bits
iii. The processor made of CMOS technology is called 3rd generation processor, and it is made
up of 16 bits
iv. The processor made of HCMOS technology is called 4th generation processor, and it is made
up of 32 bits (HCMOS : High-density n- type Complementary Metal Oxide Silicon field
effect transistor)
 BUSES

Buses are the means by which data is transmitted from one part of a computer to another,
connecting all major internal components to the CPU and memory. A standard CPU system bus is
comprised of aa control bus, data bus and address bus.

Table 3: The Buses

Address Bus Carries the addresses of data (but not the data) between
the processor and memory
Data Bus Carries data between the processor, the memory unit
and the input/output devices

Control Bus Carries control signals/commands from the CPU (and

status signals from other devices) in order to control
and coordinate all the activities within the computer

Data Lines/Data Bus:

The no .of data lines, like add. Lines vary with the specific CPU .The set of data lines is database like
the address bus unlike add. Bus, the data bus is bidirectional because while the information on the
address Bus always flows out of the CPU; the data can flow both out of the CPU as well as into the
CPU.
Control lines/ Control Bus: The no. of control lines also depends on the specific CPU one is using.
Ex: Read; Write lines are examples of control lines.
Address bus is unidirectional because the address information is always given by the Micro
Processor to address a memory location of an input / output devices

The Central Processing Unit (CPU):

This device coordinates all operations of a micro computer. It fetches programs stored in ROM‟s or
RAMs and executes the instructions depending one a specific Instructions set, which is characteristic
of each type of CPU, and which is recognized by the CPU.
The Random Access Memory (RAM): Temporary or trail programs are written.
Besides the ROM area, every computer has some memory space for temporary storage of data as well
as for programs under development. These memory devices are RAMs or Read – write memory. The
contents of it are not permanent and are altered when power is turned off. So the RAM memory is
considered to be volatile memory.
The Read Only Memory (ROM): Permanent programs are stored.
The permanent memory device/area is called ROM, because whatever be the memory contents of
ROMs, they cannot be over written with some other information. For a blank ROM, the manufacturer
supplies the device without any inf. In it, information can be entered electrically into the memory
space. This is called burning a ROM or PROM.

ASSEMBLER DIRECTIVES
Assembler directives are the directions to the assembler which indicate how an operand or section of
the program is to be processed. These are also called pseudo operations which are not executable by
the microprocessor. The various directives are explained below.
i. ASSUME: The ASSUME directive is used to inform the assembler the name of the logical
segment it should use for a specified segment.
Ex: ASSUME DS: DATA tells the assembler that for any program instruction which refers to
the data segment ,it should use the logical segment called DATA.
ii. DB -Define byte. It is used to declare a byte variable or set aside one or more storage
locations of type byte in memory.
For example, CURRENT_VALUE DB 36H tells the assembler to reserve 1 byte of memory
for a variable named CURRENT_ VALUE and to put the value 36 H in that memory location
when the program is loaded into RAM .
iii. DW -Define word. It tells the assembler to define a variable of type word or to reserve
storage locations of type word in memory.
iv. DD(define double word) :This directive is used to declare a variable of type double word or
restore memory locations which can be accessed as type double word.
v. DQ (define quadword) :This directive is used to tell the assembler to declare a variable 4
words in length or to reserve 4 words of storage in memory .
vi. DT (define ten bytes):It is used to inform the assembler to define a variable which is 10
bytes in length or to reserve 10 bytes of storage in memory.
vii. EQU –Equate It is used to give a name to some value or symbol. Every time the assembler
finds the given name in the program, it will replace the name with the value or symbol we
have equated with that name
viii. ORG -Originate : The ORG statement changes the starting offset address of the data. It
allows to set the location counter to a desired value at any point in the program.
For example the statement ORG 3000H tells the assembler to set the location counter to
3000H.
ix. PROC- Procedure: It is used to identify the start of a procedure. Or subroutine.
x. END- End program .This directive indicates the assembler that this is the end of the program
module. The assembler ignores any statements after an END directive.
xi. ENDP- End procedure: It indicates the end of the procedure (subroutine) to the assembler.
xii. ENDS-End Segment: This directive is used with the name of the segment to indicate the end
of that logical segment.
Ex: CODE SEGMENT: Start of logical segment containing code CODE ENDS : End of the
segment named CODE.

ARCHITECTURE OF 8086:

The 8086 has two blocks BIU (BUS INTERFACE UNIT) and EU (EXECUTION UNIT)
• The BIU performs all bus operations such as instruction fetching, reading and writing operands
for memory and calculating the addresses of the memory operands. The instruction bytes are
transferred to the instruction queue.
• EU executes instructions from the instruction system byte queue.
• Both units operate asynchronously to give the 8086 an overlapping instruction fetch and
execution mechanism which is called as Pipelining. This results in efficient use of the system
bus and system performance.
• BIU contains Instruction queue, Segment registers, Instruction pointer, and Address adder.
 • EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag
register.
•
1. BUS INTERFACR UNIT:
 It provides a full 16 bit bidirectional data bus and 20 bit address bus.
 The bus interface unit is responsible for performing all external bus operations
 Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus
control.
 The BIU uses a mechanism known as an instruction stream queue to implement a pipeline
architecture.
 This queue permits pre-fetch of up to six bytes of instruction code. Whenever the queue of the
BIU is not full, it has room for at least two more bytes and at the same time the EU is not
requesting it to read or write operands from memory, the BIU is free to look ahead in the
program by prefetching the next sequential instruction.
 These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU
fetches two instruction bytes in a single memory cycle
 The BIU is also responsible for generating bus control signals such as those for memory read
or write and I/O read or write

2. EXECUTION UNIT
 The Execution unit is responsible for decoding and executing all instructions.
 The EU extracts instructions from the top of the queue in the BIU, decodes them, generates
operands if necessary, passes them to the BIU and requests it to perform the read or write bys
cycles to memory or I/O and perform the operation specified by the instruction on the
operands.
 During the execution of the instruction, the EU tests the status and control flags and
 updates them based on the results of executing the instruction.
 If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to
top of the queue.
 When the EU executes a branch or jump instruction, it transfers control to a location
corresponding to another set of sequential instructions.
 Whenever this happens, the BIU automatically resets the queue and then begins to fetch
instructions from this new location to refill the queue.

INSTRUCTION FORMATS
The number of address fields in the instruction format of a computer depends on the internal
organization of its registers. Most computers fall into one of three types of CPU organizations:
1 Single accumulator organization.
2 General register organization.
3 Stack organization.
The instruction format in this type of computer needs three register address fields. Thus the
instruction for an arithmetic addition may be written in an assembly language as
ADD R1, R2, R3 denote the operation R1 ← R2 + R3.
The number of address fields in the instruction can be reduced from three to two if the destination
register is the same as one of the source registers.
ADD R1, R2 denote the operation R1 ← R1 + R2.
Only register addresses for R1 and R2 need be specified in this instruction.
Computers with multiple processor registers use the move instruction with a mnemonic MOV to
symbolize a transfer instruction.
MOV R1, R2 denotes the transfer R1 ← R2 (or R2 ← R1,
Depending on the particular computer). Thus transfer-type instructions need two address fields to
specify the source and the destination.
General register-type computers employ two or three address fields in their instruction format. Each
address field may specify a processor register or a memory word. An instruction symbolized by
ADD R1, X R1 ← R + M [X]. It has two address fields, one for register R1 and the other
for the memory address X.
Computers with stack organization would have PUSH and POP instructions which require an address
field.
PUSH X will push the word at address X to the top of the stack. The stack pointer is
updated automatically. Operation-type instructions do not need an address field in stack-organized
computers. This is because the operation is performed on the two items that are on top of the stack.

THREE-ADDRESS INSTRUCTIONS
Computers with three-address instruction formats can use each address field to specify either a
processor register or a memory operand. The program in assembly language that evaluates X = (A +
B) ∗ (C + D) is shown below, together with comments that explain the register transfer operation of
each instruction.
ADD R1, A, B R1 ← M [A] + M [B]
ADD R2, C, D R2 ← M [C] + M [D]
MUL X, R1, R2 M [X] ← R1 ∗ R2
It is assumed that the computer has two processor registers, R1 and R2. The symbol M [A] denotes
the operand at memory address symbolized by A.
The advantage of the three-address format is that it results in short programs when evaluating
arithmetic expressions. The disadvantage is that the binary-coded instructions require too many
bits to specify three addresses. An example of a commercial computer that uses three -address
instructions is the Cyber 170. The instruction formats in the Cyber computer are restricted to
either three register address fields or two register address fields and one memory address field.

TWO-ADDRESS INSTRUCTIONS
Two address instructions are the most common in commercial computers. Here again each a ddress
field can specify either a processor register or a memory word. The program to evaluate X = (A + B) ∗
(C + D) is as follows:
MOV R1, A R1 ← M [A]
ADD R1, B R1 ← R1 + M [B]
MOV R2, C R2 ← M [C]
ADD R2, D R2 ← R2 + M [D]
MUL R1, R2 R1 ← R1∗R2
MOV X, R1 M [X] ← R1
The MOV instruction moves or transfers the operands to and from memory and processor registers.
The first symbol listed in an instruction is assumed to be both a source and the destination where the
result of the operation is transferred.

ONE-ADDRESS INSTRUCTIONS
One-address instructions use an implied accumulator (AC) register for all data manipulation. For
multiplication and division there is a need for a second register. However, here we will neglect the
second and assume that the AC contains the result of tall operations. The program to evaluate X = (A
+ B) ∗ (C + D) is
LOAD A AC ← M [A]
 ADD B AC ← A [C] + M [B]
STORE T M [T] ← AC
LOAD C AC ← M [C]
ADD D AC ← AC + M [D]
MUL T AC ← AC ∗ M [T]
STORE X M [X] ← AC
All operations are done between the AC register and a memory operand. T is the address of a
temporary memory location required for storing the intermediate result.

ZERO-ADDRESS INSTRUCTIONS
A stack-organized computer does not use an address field for the instructions ADD and MUL. The
PUSH and POP instructions, however, need an address field to specify the operand that communicates
with the stack. The following program shows how X = (A + B) ∗ (C + D) will be written for a stack
organized computer. (TOS stands for top of stack)
PUSH A TOS ← A
PUSH B TOS ← B
ADD TOS ← (A + B)
PUSH C TOS ← C
PUSH D TOS ← D
ADD TOS ← (C + D)
MUL TOS ← (C + D) ∗ (A + B)
POP X M [X] ← TOS

OVERVIEW OF 8086
In1978, Intel came out with the 8086 processor. The Intel 8086 is a 16-bit microprocessor, the term
16-bit means that its ALU, its internal registers, and most of its instructions are designed to work with
16-bit binary words. The instruction set as 8086.(8086: 16-bit add.bus and 8-bit data bus).
Implemented in N–channel, depletion load, silicon gate technology (HMOS) and packaged it in a 40
pin dual in line package.

Features of 8086 Microprocessor are:

 It is a 16-bit μp.
 8086 has a 20 bit address bus can access up to 220 memory locations (1 MB).
 It can support up to 64K I/O ports.
 It provides 14, 16 -bit registers.
 It has multiplexed address and data bus AD 0 - AD15 and A16 – A19 .
 It requires single phase clock with 33% duty cycle to provide internal timing.
 8086 is designed to operate in two modes, Minimum and Maximum.
 It can pre-fetches up to 6 instruction bytes from memory and queues them in order to speed
up instruction execution.
 It requires +5V power supply.
 A 40 pin dual in line package

Register Organization of 8086:

8086 has two types of registers. All the registers of 8086 are 16-bit registers
i. General purpose register (GPR)
ii. Special purpose register (SPR)

1. General purpose registers (GPR):

GPR register can be used as 8-bit or 16-bit.These registers are generally used for holding data,
variables and intermediate results temporarily. They can also used as a counters or used for sorting
offset address for some particular addressing mode

8086 CPU has 8 general purpose registers; each register has its own name:
i. AX - the Accumulator Register (divided into AH / AL): Accumulator register consists of 2-
8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX.
AL in this case contains the low-order byte of the word, and AH contains the high-order byte.
Accumulator can be used for I/O operations and string manipulation.
a. Generates shortest machine code
b. Arithmetic, logic and data transfer
c. One number must be in AL or AX
d. Multiplication & Division
e. Input & Output

ii. BX - the Base Address Register (divided into BH / BL): Base register consists of 2 8-bit
registers BL and BH, which can be combined together and used as a 16-bit register BX. BL in
this case contains the low-order byte of the word, and BH contains the high-order byte. BX
register usually contains a data pointer used for based, based indexed or register indirect
addressing.

iii. CX - the Count Register (divided into CH / CL): Count Register consists of 2 8-bit registers
CL and CH, which can be combined together and used as a 16-bit register CX. When
combined, CL register contains the low-order byte of the word, and CH contains the high
order byte. Count register can be used as a counter in string manipulation and shift/rotate
instructions
a. Iterative code segments using the LOOP instruction
b. Repetitive operations on strings with the REP command
c. Count (in CL) of bits to shift and rotate

iv. DX - the Data Register (divided into DH / DL): Data register consists of 2 8-bit registers DL
and DH, which can be combined together and used as a 16-bit register DX. When combined,
DL register contains the low-order byte of the word, and DH contains the high-order byte.
Data register can be used as a port number in I/O operations. In integer 32-bit multiply and
divide instruction the DX register contains high-order word of the initial or resulting number.
a. DX: AX concatenated into 32-bit register for some MUL and DIV operations
b. Specifying ports in some IN and OUT operations

2. SPECIAL PURPOSE REGISTERS (SPR):

SPR are used as segment registers, pointers, index registers or as offset storage registers for
addressing modes
We categories the registers are
i. Segment registers:
ii. Pointers and index registers
iii. Flag registers

i. Segment registers: Is a 16-bit address to form a 20-bit address. The physical address of the
8086 is 20 bit wide to access 1 Mbyte memory locations. 1 Mbyte of memory is divided into
segments, with a maximum size of segment as 64 Kbytes The 8086 allows only four active
segments at a time, as shown the below figure, these four registers are:
a. Code segment (CS) is a 16-bit register containing address of 64 KB segment with
processor instructions.
b. Stack segment (SS) is a 16-bit register containing address of 64KB segment with program
stack
 c. Data segment (DS) is a 16-bit register containing address of 64KB segment with program
data.
d. Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with
program data.

Memory organization:
The total memory of 1MB is divided into 16 segments and each segment can store 64kb of data and
the segments available are CS, DS, ES, and SS
Physical address calculation:
Physical address calculation = segment address+offset address. In segment we use always four
registers i.e. CS, DS, ES, and SS. Offset register are BP, SP, SI, DI, IP
Move the code segment address to left side and add zero
Eg: let 4000
40000 8000-offset
4000-segment address
Physical address represented as 4000:8000
For CS we use IP, for DS we use SI, DI, for Es we use SI, DI, for SS we use SP

Functions of segment registers:

 The CS register holds the upper 16-bits of the starting address of the segment from which the
BIU is currently fetching the instruction code byte.
 The SS registers is used for the upper 16-bit of the starting address for the program stack
 ES registers and DS registers are used to hold the upper 16 bit of the starting address of the
two memory segments which are used for data
ii. Pointers and index registers:
SI - source index register:
1. Can be used for pointer addressing of data
2. Used as source in some string processing instructions
3. Offset address relative to DS
DI - destination index register:
1. Can be used for pointer addressing of data
2. Used as destination in some string processing instructions
3. Offset address relative to ES
BP - base pointer:
1. Primarily used to access parameters passed via the stack
2. Offset address relative to SS
SP - stack pointer:
1. Always points to top item on the stack
2. Offset address relative to SS
3. Always points to word (byte at even address)
4. An empty stack will had SP = FFFEh

iii. FLAG REGISTER:

There are nine types of flag registers in 8086 these are divided into two.
1. Conditional flag
2. Control flag
Flag registers is used to indicate the results of arithmetic operations
i. Carry Flag (CF): - this flag is set to 1 when there is an unsigned overflow. For example when
you add bytes 255 + 1 (result is not in range 0...255). When there is no overflow this flag is set
to 0. (OR) If this bit is one it indicates it as carry And zero means no carry
ii. Parity Flag (PF): this flag is set to 1 when there is even number of one bits in result, and to 0
when there is odd number of one bits.
iii. Auxiliary Flag (AF): set to 1 when there is an unsigned overflow for low nibble (4bits).
iv. Zero Flag (ZF): set to 1 when result is zero. For non-zero result this flag is set to 0.
 v. Sign Flag (SF): set to 1 when result is negative. When result is positive it is set to 0.. (This
flag takes the value of the most significant bit.)
vi. Overflow Flag (OF): set to 1 when there is a signed overflow. For example, when you add
bytes 100 + 50 (result is not in range -128...127).The above six flags are called as conditional
flags.
vii. Direction Flag (DF): this flag is used by some instructions to process data chains, when this
flag is set to 0 - the processing is done forward, when this flag is set to 1the processing is done
backward.
viii. Trap Flag (TF) - Used for on-chip debugging.
ix. Interrupt enable Flag (IF) - when this flag is set to 1 CPU reacts to interrupts from External
devices.

INSTRUCTION SET OF 8086

The 8086 microprocessor supports 6 types of Instructions. They are
1. Data transfer instructions
2. Arithmetic instructions
3. Bit manipulation instructions
4. String instructions
5. Program Execution Transfer instructions
6. Iteration Control Instructions
7. And Others

1. Data Transfer instructions: These instructions are used to transfer the data from source operand
to destination operand. All the store, move, load, exchange, input and output instructions belong to
this group.
i. General purpose byte or word transfer instructions :
MOV: Copy byte or word from specified source to specified destination
PUSH: Push the specified word to top of the stack
POP: Pop the word from top of the stack to the specified location
PUSHA: Push all registers to the stack
POPA: Pop the words from stack to all registers
XCHG: Exchange the contents of the specified source and destination operands one of which
may be a register or memory location.
XLAT: Translate a byte in AL using a table in memory
ii. Simple input and output port transfer instructions
IN: Reads a byte or word from specified port to the accumulator
OUT: Sends out a byte or word from accumulator to a specified port
iii. Special address transfer instructions
LEA : Load effective address of operand into specified register
LDS : Load DS register and other specified register from memory
LES : Load ES register and other specified register from memory.
iv. Flag transfer registers
LAHF : Load AH with the low byte of the flag register
SAHF : Store AH register to low byte of flag register
PUSHF : Copy flag register to top of the stack
POPF : Copy word at top of the stack to flag register

2. Arithmetic instructions : These instructions are used to perform various mathematical operations
like addition, subtraction, multiplication and division etc….
i. Addition instructions
ADD : Add specified byte to byte or word to word
ADC : Add with carry
INC : Increment specified byte or specified word by 1
AAA : ASCII adjust after addition
DAA : Decimal (BCD) adjust after addition
 ii. Subtraction instructions
SUB : Subtract byte from byte or word from word
SBB : Subtract with borrow
DEC : Decrement specified byte or word by 1
NEG : Negate or invert each bit of a specified byte or word and add 1(2’s complement)
CMP : Compare two specified byte or two specified words
AAS : ASCII adjust after subtraction
DAS : Decimal adjust after subtraction
iii. Multiplication instructions
MUL : Multiply unsigned byte by byte or unsigned word or word.
IMUL : Multiply signed bye by byte or signed word by word
AAM : ASCII adjust after multiplication
iv. Division instructions
DIV : Divide unsigned word by byte or unsigned double word by word
IDIV : Divide signed word by byte or signed double word by word
AAD : ASCII adjust after division
CBW : Fill upper byte of word with copies of sign bit of lower byte
CWD : Fill upper word of double word with sign bit of lower word.

3. Bit Manipulation instructions : These instructions include logical , shift and rotate instructions in
which a bit of the data is involved.
i. Logical instructions
NOT : Invert each bit of a byte or word.
AND : ANDing each bit in a byte or word with the corresponding bit in another byte or word.
OR : ORing each bit in a byte or word with the corresponding bit in another byte or word.
XOR : Exclusive OR each bit in a byte or word with the corresponding bit in another byte or
word.
TEST :AND operands to update flags, but don’t change operands.
ii. Shift instructions
SHL/SAL : Shift bits of a word or byte left, put zero(S) in LSBs.
SHR : Shift bits of a word or byte right, put zero(S) in MSBs.
SAR : Shift bits of a word or byte right, copy old MSB into new MSB.
iii. Rotate instructions
ROL : Rotate bits of byte or word left, MSB to LSB and to Carry Flag [CF]
ROR : Rotate bits of byte or word right, LSB to MSB and to Carry Flag [CF]
RCR :Rotate bits of byte or word right, LSB TO CF and CF to MSB
RCL :Rotate bits of byte or word left, MSB TO CF and CF to LSB

4. String instructions
A string is a series of bytes or a series of words in sequential memory locations. A string often
consists of ASCII character codes.
REP : An instruction prefix. Repeat following instruction until CX=0
REPE/REPZ : Repeat following instruction until CX=0 or zero flag ZF=1
REPNE/REPNZ : Repeat following instruction until CX=0 or zero flag ZF=1
MOVS/MOVSB/MOVSW: Move byte or word from one string to another
COMS/COMPSB/COMPSW: Compare two string bytes or two string words
INS/INSB/INSW: Input string byte or word from port
OUTS/OUTSB/OUTSW : Output string byte or word to port
SCAS/SCASB/SCASW: Scan a string. Compare a string byte with a byte in AL or a string
word with a word in AX
LODS/LODSB/LODSW: Load string byte in to AL or string word into AX

5. Program Execution Transfer instructions

These instructions are similar to branching or looping instructions. These instructions include
conditional & unconditional jump or loop instructions.
 i. Unconditional transfer instructions
CALL : Call a procedure, save return address on stack
RET : Return from procedure to the main program.
JMP : Goto specified address to get next instruction
ii. Conditional transfer instructions
JA/JNBE : Jump if above / jump if not below or equal
JAE/JNB : Jump if above /jump if not below
JBE/JNA : Jump if below or equal/ Jump if not above
JC : jump if carry flag CF=1
JE/JZ : jump if equal/jump if zero flag ZF=1
JG/JNLE : Jump if greater/ jump if not less than or equal
JGE/JNL : jump if greater than or equal/ jump if not less than
JL/JNGE : jump if less than/ jump if not greater than or equal
JLE/JNG : jump if less than or equal/ jump if not greater than
JNC : jump if no carry (CF=0)
JNE/JNZ : jump if not equal/ jump if not zero(ZF=0)
JNO : jump if no overflow(OF=0)
JNP/JPO : jump if not parity/ jump if parity odd(PF=0)
JNS : jump if not sign(SF=0)
JO : jump if overflow flag(OF=1)
JP/JPE : jump if parity/jump if parity even(PF=1)
JS : jump if sign(SF=1)

6. Iteration Control Instructions

These instructions are used to execute a series of instructions for certain number of times.LOOP
Loop through a sequence of instructions until CX=0
LOOPE/LOOPZ : Loop through a sequence of instructions while ZF=1 and CX = 0
LOOPNE/LOOPNZ : Loop through a sequence of instructions while ZF=0 and CX =0
JCXZ : jump to specified address if CX=0

7. Interrupt instructions
INT : Interrupt program execution, call service procedure
INTO : Interrupt program execution if OF=1
IRET : Return from interrupt service procedure to main program

8.High level language interface instructions

ENTER : enter procedure
LEAVE :Leave procedure
BOUND : Check if effective address within specified array bounds

9.Processor control instructions

Flag set/clear instructions
STC : Set carry flag CF to 1
CLC : Clear carry flag CF to 0
CMC : Complement the state of the carry flag CF
STD : Set direction flag DF to 1 (decrement string pointers)
CLD : Clear direction flag DF to 0
STI : Set interrupt enable flag to 1(enable INTR input)
CLI : Clear interrupt enable Flag to 0 (disable INTR input)

10. External Hardware synchronization instructions

HLT : Halt (do nothing) until interrupt or reset
WAIT : Wait (Do nothing) until signal on the test pin is low
ESC : Escape to external coprocessor such as 8087 or 8089
 LOCK : An instruction prefix. Prevents another processor from taking the bus while the
adjacent instruction executes.

11. No operation instruction

NOP : No action except fetch and decode

ADDRESSING MODES:
The operation field of an instruction specifies the operation to be performed. This operation must be
executed on some data stored in computer registers or memory words. The way the operands are
chosen during program execution in dependent on the addressing mode of the instruction. The
addressing mode specifies a rule for interpreting or modifying the address field of the instruction
before the operand is actually referenced.
Computers use addressing mode techniques for the purpose of accommodating one or both of the
following provisions:
1 To give programming versatility to the user by providing such facilities as pointers to Memory,
counters for loop control, indexing of data, and program relocation
2 To reduce the number of bits in the addressing field of the instruction.
3 The availability of the addressing modes gives the experienced assembly language programmer
flexibility for writing programs that are more efficient with respect to the number of instructions
and execution time.
The different ways in which a source operand is denoted in an instruction are known as the addressing
modes. There are 8 different addressing modes in 8086 programming. They are
1. Immediate addressing mode
2. Register addressing mode
3. Direct addressing mode
4. Register indirect addressing mode
5. Based addressing mode
6. Indexed addressing mode.
7. Based indexed addressing mode
8. Based Indexed with displacement.
 Immediate addressing mode: The addressing mode in which the data operand is a part of the
instruction itself is called Immediate addressing mode.
For Ex: MOV CX, 4847 H
ADD AX, 2456 H
MOV AL, FFH
 Register addressing mode : Register addressing mode means, a register is the source of an
operand for an instruction.
For Ex : MOV AX, BX copies the contents of the 16-bit BX register into the 16-bit AX
register.
EX : ADD CX,DX

Advantages of this mode:

• Shorter instructions and faster instruction fetch.
 • Faster memory access to the operand(s)

Disadvantages of this mode:

 Very limited address space
 Using multiple registers helps performance but it complicates the instructions.

 Direct addressing mode: The addressing mode in which the effective address of the memory
location at which the data operand is stored is given in the instruction.i.e the effective address
is just a 16-bit number is written directly in the instruction.
For Ex: MOV BX, [1354H]
MOV BL,[0400H]
The square brackets around the 1354 H denotes the contents of the memory location. When
executed, this instruction will copy the contents of the memory location into BX register. This
addressing mode is called direct because the displacement of the operand from the segment
base is specified directly in the instruction.

 Register indirect addressing mode : Register indirect addressing allows data to be addressed
at any memory location through an offset address held in any of the following registers: BP,
BX, DI and SI.
Ex: MOV AX, [BX]. Suppose the register BX contains 4675H ,the contents of the 4675 H are
moved to AX.
ADD CX, {BX}

 Based addressing mode: The offset address of the operand is given by the sum of contents of
the BX or BP registers and an 8-bit or 16-bit displacement.
Ex: MOV DX, [BX+04]
ADD CL,[BX+08]
 Indexed Addressing mode : The operands offset address is found by adding the contents of
SI or DI register and 8-bit or 16-bit displacements.
Ex: MOV BX,[SI+06]
ADD AL,[DI+08]
 Based -index addressing mode : The offset address of the operand is computed by summing
the base register to the contents of an Index register.
Ex: ADD CX,[BX+SI]
MOV AX,[BX+DI]
  Based Indexed with displacement mode: The operands offset is computed by adding the
base register contents, an Index registers contents and 8 or 16-bit displacement.
Ex : MOV AX,[BX+DI+08]
ADD CX,[BX+SI+16]

 Stack Addressing Mode

In this mode, operand is at the top of the stack. For example: ADD, this instruction will POP top two
items from the stack, add them, and will then PUSH the result to the top of the stack.
 Register Mode
In this mode the operand is stored in the register and this register is present in CPU. The instruction
has the address of the Register where the operand is stored.
 Auto Increment/Decrement Mode
In this the register is incremented or decremented after or before its value is used.

Table 4: Summary of the Addressing Mode

The most common names for addressing modes (names may differ among architectures)
Addressing Example Meaning When used
modes Instruction
Register Add R4,R3 R4 <- R4 + R3 When a value is in a register
Immediate Add R4, #3 R4 <- R4 + 3 For constants
Displacement Add R4, R4 <- R4 + M[100+R1] Accessing local variables
100(R1)
Register Add R4,(R1) R4 <- R4 + M[R1] Accessing using a pointer or a computed
Indexed address
Indexed Add R3, (R1 + R3 <- R3 + M[R1+R2] Useful in array addressing:
R2) R1 - base of array
R2 - index amount
Direct Add R1, (1001) R1 <- R1 + M[1001] Useful in accessing static data
Memory Add R1, @(R3) R1 <- R1 + M[M[R3]] If R3 is the address of a pointer p, then
deferred mode yields *p
Auto- Add R1, (R2)+ R1 <- R1 +M[R2] Useful for stepping through arrays in a
increment R2 <- R2 + d loop.
R2 - start of array
d - size of an element
Auto- Add R1,-(R2) R2 <-R2-d Same as autoincrement.
decrement R1 <- R1 + M[R2] Both can also be used to implement a
stack as push and pop
Scaled Add R1, R1<- Used to index arrays. May be applied to
100(R2)[R3] R1+M[100+R2+R3*d] any base addressing mode in some
machines.