AT28C256

Features
• Fast Read Access Time - 150 ns
• Automatic Page Write Operation
Internal Address and Data Latches for 64-Bytes
Internal Control Timer
• Fast Write Cycle Times
Page Write Cycle Time: 3 ms or 10 ms Maximum
1 to 64-Byte Page Write Operation
• Low Power Dissipation
50 mA Active Current
200 µA CMOS Standby Current 256K (32K x 8)
• Hardware and Software Data Protection
• DATA Polling for End of Write Detection Paged
• High Reliability CMOS Technology
Endurance: 104 or 105 Cycles CMOS
Data Retention: 10 Years
• Single 5V ± 10% Supply
E2PROM
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC Approved Byte-Wide Pinout
• Full Military, Commercial, and Industrial Temperature Ranges

Description
The AT28C256 is a high-performance Electrically Erasable and Programmable Read
Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-
tured with Atmel’s advanced nonvolatile CMOS technology, the device offers access
times to 150 ns with power dissipation of just 440 mW. When the device is deselected,
the CMOS standby current is less than 200 µA.
(continued)

Pin Configurations
TSOP
Pin Name Function Top View AT28C256
A0 - A14 Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Don’t Connect

CERDIP, PDIP,
PGA LCC, PLCC FLATPACK, SOIC
Top View Top View Top View

Note: PLCC package pins 1 and

17 are DON’T CONNECT. 0006F

2-217
Description (Continued)
The AT28C256 is accessed like a Static RAM for the read Atmel’s 28C256 has additional features to ensure high
or write cycle without the need for external components. quality and manufacturability. The device utilizes internal
The device contains a 64-byte page register to allow writ- error correction for extended endurance and improved
ing of up to 64-bytes simultaneously. During a write cycle, data retention characteristics. An optional software data
the addresses and 1 to 64-bytes of data are internally protection mechanism is available to guard against inad-
latched, freeing the address and data bus for other opera- vertent writes. The device also includes an extra 64-bytes
tions. Following the initiation of a write cycle, the device of E2PROM for device identification or tracking.
will automatically write the latched data using an internal
control timer. The end of a write cycle can be detected by
DATA POLLING of I/O7. Once the end of a write cycle has
been detected a new access for a read or write can begin.

Block Diagram

Absolute Maximum Ratings*

*NOTICE: Stresses beyond those listed under “Absolute Maxi-
Temperature Under Bias................. -55°C to +125°C mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
Storage Temperature...................... -65°C to +150°C device at these or any other conditions beyond those indi-
All Input Voltages cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
(including NC Pins)
for extended periods may affect device reliability.
with Respect to Ground ................... -0.6V to +6.25V

All Output Voltages

with Respect to Ground .............-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground ................... -0.6V to +13.5V

2-218 AT28C256
 AT28C256

Device Operation
READ: The AT28C256 is accessed like a Static RAM. DATA PROTECTION: If precautions are not taken, inad-
When CE and OE are low and WE is high, the data stored vertent writes may occur during transitions of the host sys-
at the memory location determined by the address pins is tem power supply. Atmel has incorporated both hardware
asserted on the outputs. The outputs are put in the high and software features that will protect the memory against
impedance state when either CE or OE is high. This dual- inadvertent writes.
line control gives designers flexibility in preventing bus HARDWARE PROTECTION: Hardware features protect
contention in their system. against inadvertent writes to the AT28C256 in the follow-
BYTE WRITE: A low pulse on the WE or CE input with CE ing ways: (a) VCC sense - if VCC is below 3.8V (typical) the
or WE low (respectively) and OE high initiates a write cy- write function is inhibited; (b) VCC power-on delay - once
cle. The address is latched on the falling edge of CE or VCC has reached 3.8V the device will automatically time
WE, whichever occurs last. The data is latched by the first out 5 ms (typical) before allowing a write: (c) write inhibit -
rising edge of CE or WE. Once a byte write has been holding any one of OE low, CE high or WE high inhibits
started it will automatically time itself to completion. Once write cycles; (d) noise filter - pulses of less than 15 ns (typi-
a programming operation has been initiated and for the cal) on the WE or CE inputs will not initiate a write cycle.
duration of tWC, a read operation will effectively be a poll- SOFTWARE DATA PROTECTION: A software controlled
ing operation. data protection feature has been implemented on the
PAGE WRITE: The page write operation of the AT28C256 AT28C256. When enabled, the software data protection
allows 1 to 64-bytes of data to be written into the device (SDP), will prevent inadvertent writes. The SDP feature
during a single internal programming period. A page write may be enabled or disabled by the user; the AT28C256 is
operation is initiated in the same manner as a byte write; shipped from Atmel with SDP disabled.
the first byte written can then be followed by 1 to 63 addi- SDP is enabled by the host system issuing a series of
tional bytes. Each successive byte must be written within three write commands; three specific bytes of data are
150 µs (tBLC) of the previous byte. If the tBLC limit is ex- written to three specific addresses (refer to Software Data
ceeded the AT28C256 will cease accepting data and com- Protection Algorithm). After writing the 3-byte command
mence the internal programming operation. All bytes dur- sequence and after tWC the entire AT28C256 will be pro-
ing a page write operation must reside on the same page tected against inadvertent write operations. It should be
as defined by the state of the A6 - A14 inputs. For each noted, that once protected the host may still perform a
WE high to low transition during the page write operation, byte or page write to the AT28C256. This is done by pre-
A6 - A14 must be the same. ceding the data to be written by the same 3-byte command
The A0 to A5 inputs are used to specify which bytes within sequence used to enable SDP.
the page are to be written. The bytes may be loaded in any Once set, SDP will remain active unless the disable com-
order and may be altered within the same load period. mand sequence is issued. Power transitions do not dis-
Only bytes which are specified for writing will be written; able SDP and SDP will protect the AT28C256 during
unnecessary cycling of other bytes within the page does power-up and power-down conditions. All command se-
not occur. quences must conform to the page write timing specifica-
DATA POLLING: The AT28C256 features DATA Polling tions. The data in the enable and disable command se-
to indicate the end of a write cycle. During a byte or page quences is not written to the device and the memory ad-
write cycle an attempted read of the last byte written will dresses used in the sequence may be written with data in
result in the complement of the written data to be pre- either a byte or page write operation.
sented on I/O7. Once the write cycle has been completed, After setting SDP, any attempt to write to the device with-
true data is valid on all outputs, and the next write cycle out the 3-byte command sequence will start the internal
may begin. DATA Polling may begin at anytime during the write timers. No data will be written to the device; however,
write cycle. for the duration of tWC, read operations will effectively be
TOGGLE BIT: In addition to DATA Polling the AT28C256 polling operations.
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to (continued)
read data from the device will result in I/O6 toggling be-
tween one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.

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Device Operation (Continued)
DEVICE IDENTIFICATION: A n e x t r a 6 4 - b y t e s o f OPTIONAL CHIP ERASE MODE: The entire device can
E2PROM memory are available to the user for device be erased using a 6-byte software code. Please see Soft-
identification. By raising A9 to 12V ± 0.5V and using ad- ware Chip Erase application note for details.
dress locations 7FC0H to 7FFFH the additional bytes may
be written to or read from in the same manner as the regu-
lar memory array.

DC and AC Operating Range

AT28C256-15 AT28C256-20 AT28C256-25 AT28C256-35
Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C
Operating
Temperature (Case) Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C
Mil. -55°C - 125°C -55°C - 125°C -55°C - 125°C -55°C - 125°C
VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%

Operating Modes
Mode CE OE WE I/O
Read VIL VIL VIH DOUT
Write (2) VIL VIH VIL DIN
(1)
Standby/Write Inhibit VIH X X High Z
Write Inhibit X X VIH
Write Inhibit X VIL X
Output Disable X VIH X High Z
(3)
Chip Erase VIL VH VIL High Z
Notes: 1. X can be VIL or VIH. 3. VH = 12.0V ± 0.5V.
2. Refer to AC Programming Waveforms.

DC Characteristics
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC + 1V 10 µA
ILO Output Leakage Current VI/O = 0V to VCC 10 µA
Com., Ind. 200 µA
ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC + 1V
Mil. 300 µA
ISB2 VCC Standby Current TTL CE = 2.0V to VCC + 1V 3 mA
ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 50 mA
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage IOL = 2.1 mA .45 V
VOH Output High Voltage IOH = -400 µA 2.4 V

2-220 AT28C256
 AT28C256

AC Read Characteristics
AT28C256-15 AT28C256-20 AT28C256-25 AT28C256-35
Symbol Parameter Min Max Min Max Min Max Min Max Units
tACC Address to Output Delay 150 200 250 350 ns
(1)
tCE CE to Output Delay 150 200 250 350 ns
(2)
tOE OE to Output Delay 0 70 0 80 0 100 0 100 ns
(3, 4)
tDF CE or OE to Output Float 0 50 0 55 0 60 0 70 ns
Output Hold from OE, CE or
tOH Address, whichever 0 0 0 0 ns
occurred first

AC Read Waveforms (1, 2, 3, 4)

Notes: 1. CE may be delayed up to tACC - tCE after the address 3. tDF is specified from OE or CE whichever occurs first
transition without impact on tACC. (CL = 5 pF).
2. OE may be delayed up to tCE - tOE after the falling 4. This parameter is characterized and is not 100% tested.
edge of CE without impact on tCE or by tACC - tOE
after an address change without impact on tACC.

Input Test Waveforms and Output Test Load

Measurement Level

tR, tF < 5ns

Pin Capacitance (f = 1 MHz, T = 25°C) (1)

Typ Max Units Conditions
CIN 4 6 pF VIN = 0V
COUT 8 12 pF VOUT = 0V
Note: 1. This parameter is characterized and is not 100% tested.

2-221
AC Write Characteristics
Symbol Parameter Min Max Units
tAS, tOES Address, OE Set-up Time 0 ns
tAH Address Hold Time 50 ns
tCS Chip Select Set-up Time 0 ns
tCH Chip Select Hold Time 0 ns
tWP Write Pulse Width (WE or CE) 100 ns
tDS Data Set-up Time 50 ns
tDH, tOEH Data, OE Hold Time 0 ns
(1)
tDV Time to Data Valid NR
Note: 1. NR = No Restriction

AC Write Waveforms
WE Controlled

CE Controlled

2-222 AT28C256
 AT28C256

Page Mode Characteristics

Symbol Parameter Min Max Units
AT28C256 10 ms
tWC Write Cycle Time
AT28C256F 3.0 ms
tAS Address Set-up Time 0 ns
tAH Address Hold Time 50 ns
tDS Data Set-up Time 50 ns
tDH Data Hold Time 0 ns
tWP Write Pulse Width 100 ns
tBLC Byte Load Cycle Time 150 µs
tWPH Write Pulse Width High 50 ns

Page Mode Write Waveforms (1, 2)

Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.

Chip Erase Waveforms

tS = tH = 5 µsec (min.)
tW = 10 msec (min.)
VH = 12.0V ± 0.5V

2-223
Software Data Software Data
Protection Enable Algorithm (1) Protection Disable Algorithm (1)
LOAD DATA AA LOAD DATA AA
TO TO
ADDRESS 5555 ADDRESS 5555

LOAD DATA 55 LOAD DATA 55

TO TO
ADDRESS 2AAA ADDRESS 2AAA

LOAD DATA A0 LOAD DATA 80

TO TO
ADDRESS 5555 WRITES ENABLED (2) ADDRESS 5555

LOAD DATA XX LOAD DATA AA

TO TO
ANY ADDRESS (4) ADDRESS 5555

LOAD LAST BYTE LOAD DATA 55

TO TO
LAST ADDRESS ADDRESS 2AAA
ENTER DATA
PROTECT STATE
LOAD DATA 20
TO
ADDRESS 5555 EXIT DATA
Notes for software program code: PROTECT STATE (3)
1. Data Format: I/O7 - I/O0 (Hex); LOAD DATA XX
Address Format: A14 - A0 (Hex). TO
2. Write Protect state will be activated at end of write even if no ANY ADDRESS (4)
other data is loaded.
3. Write Protect state will be deactivated at end of write period LOAD LAST BYTE
even if no other data is loaded. TO
LAST ADDRESS
4. 1 to 64-bytes of data are loaded.

Software Protected Write Cycle Waveforms (1, 2)

Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after
the software code has been entered.
2. OE must be high only when WE and CE are both low.

2-224 AT28C256
 AT28C256

Data Polling Characteristics (1)

Symbol Parameter Min Typ Max Units
tDH Data Hold Time 0 ns
tOEH OE Hold Time 0 ns
tOE OE to Output Delay (2) ns
tWR Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics.

Data Polling Waveforms

Toggle Bit Characteristics (1)

Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Delay (2) ns
tOEHP OE High Pulse 150 ns
tWR Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics.

Toggle Bit Waveforms (1, 2, 3)

Notes: 1. Toggling either OE or CE or both OE and CE will 3. Any address location may be used but the address
operate toggle bit. should not vary.
2. Beginning and ending state of I/O6 will vary.

2-225
2-226 AT28C256
 AT28C256

Ordering Information (2)

tACC ICC (mA)
Ordering Code Package Operation Range
(ns) Active Standby
150 50 0.2 AT28C256(E,F)-15JC 32J Commercial
AT28C256(E,F)-15PC 28P6 (0°C to 70°C)
AT28C256(E,F)-15SC 28S
AT28C256(E,F)-15TC 28T
AT28C256(E,F)-15JI 32J Industrial
AT28C256(E,F)-15PI 28P6 (-40°C to 85°C)
AT28C256(E,F)-15SI 28S
AT28C256(E,F)-15TI 28T
50 0.3 AT28C256(E,F)-15DM/883 28D6 Military/883C
AT28C256(E,F)-15FM/883 28F Class B, Fully Compliant
AT28C256(E,F)-15LM/883 32L (-55°C to 125°C)
AT28C256(E,F)-15UM/883 28U
200 50 0.2 AT28C256(E,F)-20JC 32J Commercial
AT28C256(E,F)-20PC 28P6 (0°C to 70°C)
AT28C256(E,F)-20SC 28S
AT28C256(E,F)-20TC 28T
AT28C256(E,F)-20JI 32J Industrial
AT28C256(E,F)-20PI 28P6 (-40°C to 85°C)
AT28C256(E,F)-20SI 28S
AT28C256(E,F)-20TI 28T
50 0.3 AT28C256(E,F)-20DM/883 28D6 Military/883C
AT28C256(E,F)-20FM/883 28F Class B, Fully Compliant
AT28C256(E,F)-20LM/883 32L (-55°C to 125°C)
AT28C256(E,F)-20UM/883 28U
250 50 0.2 AT28C256(E,F)-25JC 32J Commercial
AT28C256(E,F)-25PC 28P6 (0°C to 70°C)
AT28C256-W DIE
AT28C256(E,F)-25JI 32J Industrial
AT28C256(E,F)-25PI 28P6 (-40°C to 85°C)
50 0.3 AT28C256(E,F)-25DM/883 28D6 Military/883C
AT28C256(E,F)-25FM/883 28F Class B, Fully Compliant
AT28C256(E,F)-25LM/883 32L (-55°C to 125°C)
AT28C256(E,F)-25UM/883 28U
AT28C256(E,F)-35UM/883 28U
50 0.2 AT28C256-W DIE Commercial
(0°C to 70°C)

(continued)

2-227
Ordering Information (Continued)
tACC ICC (mA)
Ordering Code Package Operation Range
(ns) Active Standby
150 (3) 50 0.35 5962-88525 16 UX 28U Military/883C
5962-88525 16 XX 28D6 Class B, Fully Compliant
5962-88525 16 YX 32L (-55°C to 125°C)
5962-88525 16 ZX 28F
5962-88525 15 UX 28U Military/883C
5962-88525 15 XX 28D6 Class B, Fully Compliant
5962-88525 15 YX 32L (-55°C to 125°C)
5962-88525 15 ZX 28F
5962-88525 14 UX 28U Military/883C
5962-88525 14 XX 28D6 Class B, Fully Compliant
5962-88525 14 YX 32L (-55°C to 125°C)
5962-88525 14 ZX 28F
50 0.35 5962-88525 08 UX 28U Military/883C
5962-88525 08 XX 28D6 Class B, Fully Compliant
5962-88525 08 YX 32L (-55°C to 125°C)
5962-88525 08 ZX 28F
5962-88525 07 UX 28U Military/883C
5962-88525 07 XX 28D6 Class B, Fully Compliant
5962-88525 07 YX 32L (-55°C to 125°C)
5962-88525 07 ZX 28F
5962-88525 06 UX 28U Military/883C
5962-88525 06 XX 28D6 Class B, Fully Compliant
5962-88525 06 YX 32L (-55°C to 125°C)
5962-88525 06 ZX 28F
200 (3) 50 0.35 5962-88525 12 UX 28U Military/883C
5962-88525 12 XX 28D6 Class B, Fully Compliant
5962-88525 12 YX 32L (-55°C to 125°C)
5962-88525 12 ZX 28F
50 0.35 5962-88525 04 UX 28U Military/883C
5962-88525 04 XX 28D6 Class B, Fully Compliant
5962-88525 04 YX 32L (-55°C to 125°C)
5962-88525 04 ZX 28F
250 (3) 50 0.35 5962-88525 13 UX 28U Military/883C
5962-88525 13 XX 28D6 Class B, Fully Compliant
5962-88525 13 YX 32L (-55°C to 125°C)
5962-88525 13 ZX 28F
5962-88525 11 UX 28U Military/883C
5962-88525 11 XX 28D6 Class B, Fully Compliant
5962-88525 11 YX 32L (-55°C to 125°C)
5962-88525 11 ZX 28F
(continued)

2-228 AT28C256
 AT28C256

Ordering Information (Continued)

tACC ICC (mA)
Ordering Code Package Operation Range
(ns) Active Standby
250 50 0.35 5962-88525 05 UX 28U Military/883C
5962-88525 05 XX 28D6 Class B, Fully Compliant
5962-88525 05 YX 32L (-55°C to 125°C)
5962-88525 05 ZX 28F
5962-88525 03 UX 28U Military/883C
5962-88525 03 XX 28D6 Class B, Fully Compliant
5962-88525 03 YX 32L (-55°C to 125°C)
5962-88525 03 ZX 28F
300 50 0.35 5962-88525 10 UX 28U Military/883C
5962-88525 10 XX 28D6 Class B, Fully Compliant
5962-88525 10 YX 32L (-55°C to 125°C)
5962-88525 10 ZX 28F
50 0.35 5962-88525 02 UX 28U Military/883C
5962-88525 02 XX 28D6 Class B, Fully Compliant
5962-88525 02 YX 32L (-55°C to 125°C)
5962-88525 02 ZX 28F
350 50 0.35 5962-88525 09 UX 28U Military/883C
5962-88525 09 XX 28D6 Class B, Fully Compliant
5962-88525 09 YX 32L (-55°C to 125°C)
5962-88525 09 ZX 28F
50 0.35 5962-88525 01 UX 28U Military/883C
5962-88525 01 XX 28D6 Class B, Fully Compliant
5962-88525 01 YX 32L (-55°C to 125°C)
5962-88525 01 ZX 28F
Notes: 1. Electrical specifications for these speeds are defined by Standard Microcircuit Drawing 5962-88525.
2. See Valid Part Number table below.
3. SMD specifies Software Data Protection feature for device type, although Atmel product supplied to every device type
in the SMD is 100% tested for this feature.

Valid Part Numbers

The following table lists standard Atmel products that can be ordered.
Device Numbers Speed Package and Temperature Combinations
AT28C256 15 JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883
AT28C256E 15 JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883
AT28C256F 15 JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883
AT28C256 20 JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883
AT28C256E 20 JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883
AT28C256F 20 JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883
AT28C256 25 JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883
AT28C256E 25 JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883
AT28C256F 25 JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883
AT28C256 - W

2-229
 Package Type
28D6 28 Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline Package (Cerdip)
28F 28 Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack)
32J 32 Lead, Plastic J-Leaded Chip Carrier (PLCC)
32L 32 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)
28P6 28 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28S 28 Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
28T 28 Lead, Plastic Thin Small Outline Package (TSOP)
28U 28 Pin, Ceramic Pin Grid Array (PGA)
W Die
Options
Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
E High Endurance Option: Endurance = 100K Write Cycles
F Fast Write Option: Write Time = 3 ms

2-230 AT28C256