Department of Electrical Engineering and

Computer Science

Faculty Member: Dr. Rehan Ahmed Dated: 12/04/2023

Semester:          6          
th
Section: BEE 12C

EE-421: Digital System Design

Lab 8: Finite State Machines

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Name Reg. No Viva / Quiz / Analysis of data in Modern Ethics Individual

Lab Lab Report Tool and and
Performance Usage Safety      Teamwork

5 Marks 5 Marks 5 5 Marks 5 Marks

Marks

Hassan Rizwan 335753

Syeda Fatima
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EE – 421: DIGITAL SYSTEM DESIGN LAB

 CONTENTS

LAB 8: FINITE STATE MACHINES.......................................................................................3

Objectives...............................................................................................................................3
Introduction............................................................................................................................3
LAB EXERCISES.................................................................................................................4
Exercise 1...........................................................................................................................4
Exercise 2...........................................................................................................................9
Exercise 3.........................................................................................................................12
Exercise 4.........................................................................................................................15
Conclusion:..........................................................................................................................21

EE – 421: DIGITAL SYSTEM DESIGN LAB

 LAB 8: FINITE STATE MACHINES

Objectives
The purpose of this lab was as follows:

 Learning how to use FSM

 Completing lab tasks using FSMs

Introduction
Finite state machines (FSMs) are conceptual representations of systems that can only exist in
a limited number of states and can transition between these states based on specific inputs
and outputs.

FSMs are commonly utilized in various fields such as computer science, engineering, and
mathematics to design and analyze algorithms, circuits, protocols, and languages. The
primary purpose of this lab report is to showcase our comprehension and proficiency in
utilizing FSMs as a potent tool for modeling and resolving computational problems.

Software
Quartus Prime is a design software developed by Intel for the design of digital circuits using
Field Programmable Gate Arrays (FPGAs). It supports various programming language
including Verilog and VHDL.

LAB EXERCISES

EE – 421: DIGITAL SYSTEM DESIGN LAB

Exercise 1

1. Create a new Quartus project for the FSM circuit.

2. Write a Verilog file that instantiates the nine flip-flops in the circuit and which specifies
the logic expressions that drive the flip-flop input ports. Use only simple assign statements in
your Verilog code to specify the logic feeding the flip-flops. Note that the one-hot code
enables you to derive these expressions by inspection. Use the toggle switch SW0 as an
active-low synchronous reset input for the FSM, use SW1 as the w input, and the pushbutton
KEY0 as the clock input which is applied manually. Use the red light LEDR9 as the output z,
and assign the state flip-flop outputs to the red lights LEDR8 to LEDR0.

3. Include the Verilog file in your project, and assign the pins on the FPGA to connect to the
switches and the LEDs.

4. Simulate the behavior of your circuit.

EE – 421: DIGITAL SYSTEM DESIGN LAB

5. Once you are confident that the circuit works properly as a result of your simulation,
download the circuit into the FPGA chip. Test the functionality of your design by applying
the input sequences and observing the output LEDs. Make sure that the FSM properly
transitions between states as displayed on the red LEDs, and that it produces the correct
output values on LEDR9.

6. Finally, consider a modification of the one-hot code given in Table 1. It is often desirable
to set all flip-flop outputs to the value 0 in the reset state. Table 2 shows a modified one-hot
state assignment in which the reset state, A, uses all 0s. This is accomplished by inverting the
state variable y0. Create a modified version of your Verilog code that implements this state
assignment. (Hint: you should need to make very few changes to the logic expressions in
your circuit to implement the modified state assignment.)

7. Compile your new circuit and test it.

Code:
module lab8 (
input [3:0] KEY,
input [9:0] SW,
output [9:0] LEDR
);

wire clk = ~KEY[0]; // Inverted clock signal

wire w = SW[1]; // Input signal from SW[1]
wire z; // Output signal for z
wire reset = SW[0]; // Input signal from SW[0] for reset

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 //ONE HOT COMMANDS
parameter A = 9'b000000001,
B = 9'b000000010,
C = 9'b000000100,
D = 9'b000001000,
E = 9'b000010000,
F = 9'b000100000,
G = 9'b001000000,
H = 9'b010000000,
I = 9'b100000000;

reg [9:0] p_state; // Register for storing

current state
wire [9:0] n_state; // Wire for computing next state

// Assign statement to determine next state based on current

state and input signal w
assign n_state = (p_state == A) ? ((w) ? F : B) :
(p_state == B) ? ((w) ? F : C) :
(p_state == C) ? ((w) ? F : D) :
(p_state == D) ? ((w) ? F : E) :
(p_state == E) ? ((w) ? F : E) :
(p_state == F) ? ((w) ? G : B) :
(p_state == G) ? ((w) ? H : B) :
(p_state == H) ? ((w) ? I : B) :
(p_state == I) ? ((w) ? I : B) : A;

always @(posedge clk) begin

if (!reset) p_state <= A; // Reset state to A if reset
signal is active
else p_state <= n_state; // Update state with next state
end

// Using assign statements to determine values for z and LEDR

assign z = (p_state == E | p_state == I); // z is true if
current state is E or I
assign LEDR[8:0] = p_state; // LEDR[8:0] takes value of current
state
assign LEDR[9] = z; // LEDR[9] takes value of z

endmodule
RTL Viewer:

EE – 421: DIGITAL SYSTEM DESIGN LAB

State Machine Viewer:

Hardware Implementation:

EE – 421: DIGITAL SYSTEM DESIGN LAB

Exercise 2
1. Create a new project for the FSM.

2. Include in the project your Verilog file that uses the style of code in Figure 3. Use the same
switches, pushbuttons, and lights that were used in Part I.

3. Before compiling your code it is necessary to explicitly tell the Synthesis tool in Quartus
that you wish to have the finite state machine implemented using the state assignment
specified in your Verilog code. If you do not explicitly give this setting to Quartus, the
Synthesis tool will automatically use a state assignment of its own choosing, and it will
ignore the state codes specified in your Verilog code. To make this setting, choose
Assignments > Settings in Quartus, and click on the Compiler Settings item on the left side of
the window, then click on the Advanced Settings (Synthesis) button. As indicated in Figure 4,
change the parameter State Machine Processing to the setting User-Encoded.

4. Compile your project. To examine the circuit produced by Quartus open the RTL Viewer
tool. Double-click on the box shown in the circuit that represents the finite state machine, and
determine whether the state diagram that it shows properly corresponds to the one in Figure2.
To see the state codes used for your FSM, open the Compilation Report, select the Analysis
and Synthesis section of the report, and click on State Machines.

5. Download the circuit into the FPGA chip and test its functionality.

Code:
module lab8(KEY,SW,LEDR);

input [3:0] KEY;

input [3:0] SW;
output [9:0] LEDR;

FSM f1(KEY[0],SW[0],KEY[1],LEDR[0]);
endmodule

module FSM
( input clk, w, reset,
output reg z
);
// DECLARE STATE REGISTER
reg [3:0]state;
// DEFINED PARAMETERS
parameter A = 0, B = 1, C= 2, D = 3,E = 4, F = 5, G = 6, H =
7, I=8;

EE – 421: DIGITAL SYSTEM DESIGN LAB

 // Output depends only on the state
always @ (state) begin
case (state)
A:z=0;
B:z=0;
C:z=0;
D:z=0;
E:z=1;
F:z=0;
G:z=0;
H:z=0;
I:z=1;
default:
z=1'bx;
endcase
end

// NEXT STATE BLOCK

always @ (posedge clk, negedge reset) begin
if (~reset)
state <= A;
else
case (state)
A:
if(w)
state <= F;
else
state<=B;
B:
if(w)
state <= F;
else
state<=C;
C:
if(w)
state <= F;
else
state<=D;
D:
if(w)
state <= F;
else
state<=E;
E:
if(w)
state <= F;
else
state<=E;

EE – 421: DIGITAL SYSTEM DESIGN LAB

 F:
if(w)
state <= G;
else
state<=B;
G:
if(w)
state <= H;
else
state<=B;
H:
if(w)
state <= I;
else
state<=B;
I:
if(w)
state <= I;
else
state<=B;
endcase
end
endmodule

RTL Viewer:

Hardware Implementation:

EE – 421: DIGITAL SYSTEM DESIGN LAB

Exercise 3
The sequence detector can be implemented in a straightforward manner using shift registers,
instead of using the more formal approach described above. Create Verilog code that
instantiates two 4-bit shift registers; one is for recognizing a sequence of four 0s, and the
other for four 1s. Include the appropriate logic expressions in your design to produce the
output z. Make a Quartus project for your design and implement the circuit on your DEseries
board. Use the switches and LEDs on the board in a similar way as you did for Parts I and II
and observe the behavior of your shift registers and the output z. Answer the following
question: could you use just one 4-bit shift register, rather than two? Explain your answer.

Code:
module lab8(KEY,SW,LEDR,out0,out1);

input [9:0]SW;
input[3:0] KEY;
output reg [9:0] LEDR;
output [3:0] out0,out1;
wire [3:0] w0,w1;

assign out0=w0;
assign out1=w1;

//INSTANTIATING SHIFT REGISTER MODULES

SHIFT_REGISTER0 ZEROS(KEY[0],SW[0],w0,SW[0]);

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SHIFT_REGISTER1 ONES(KEY[0],SW[0],w1,SW[0]);

always @(*)
begin
if(w0==4'b0000 || w1==4'b1111)
LEDR[0]=1;
else
LEDR[0]=0;
end
endmodule

module SHIFT_REGISTER0(clk,in,out,en);

input in,clk,en;
output reg [3:0] out;

always@(posedge clk)
begin
if(~en)
begin
out[0]<=in;
out[1]<=out[0];
out[2]<=out[1];
out[3]<=out[2];
end
else
out=4'bxxxx;
end
endmodule

module SHIFT_REGISTER1(clk,in,out,en);
input in,clk,en;
output reg [3:0] out;

always@(posedge clk)
begin
if(en)
begin
out[0]<=in;
out[1]<=out[0];
out[2]<=out[1];
out[3]<=out[2];
end
else
out=4'bxxxx;
end

endmodule

EE – 421: DIGITAL SYSTEM DESIGN LAB

RTL Viewer:

Hardware Implementation:

Exercise 4
Design and implement a Morse-code encoder circuit using an FSM. Your circuit should take
as input one of the first eight letters of the alphabet and display the Morse code for it on a red
LED. Use switches SW2−0 and pushbuttons KEY1−0 as inputs. When a user presses KEY1,
the circuit should display the Morse code for a letter specified by SW2−0 (000 for A, 001 for

EE – 421: DIGITAL SYSTEM DESIGN LAB

B, etc.), using 0.5-second pulses to represent dots, and 1.5-second pulses to represent dashes.
Pushbutton KEY0 should function as an asynchronous reset.

Code:
module lab8
(
input clk,reset,input [2:0] sw,input[1:0] key,output
ledr,output reg [15:0] out
);
// STATE REGISTERS DECLARED
reg[3:0]state;
wire [15:0]w2;

// DEFINING STATES
parameter A = 0, B = 1, C = 2, D = 3,E= 4, F = 5, G = 6, H
=7,I=8;

shift_register s1(clk,reset,out,ledr,w2);
always @ (*) begin
case (state)
A:out=16'b0000000000000000;
B:out=16'b1011100000000000;
C:out=16'b1110001010100000;
D:out=16'b1110001011100010;
E:out=16'b1110001010000000;
F:out=16'b100000000000000;
G:out=16'b1010111000100000;
H:out=16'b0011100011100010;
I:out=16'b101010100000;
default:out=16'bxxxxxxxxxxxxxxxx;
endcase
end

always @ (posedge clk or negedge key[0]) begin

if (~key[0])
state <= A;
else
case (state)

EE – 421: DIGITAL SYSTEM DESIGN LAB

 A:
begin
if(sw[2:0]==000&& ~key[1])
state <= B;
else if(sw[2:0]==001&& ~key[1])
state <= C;
else if(sw[2:0]==010&& ~key[1])
state <= D;
else if(sw[2:0]==011&& ~key[1])
state <= E;
else if(sw[2:0]==100&& ~key[1])
state <= F;
else if(sw[2:0]==101&& ~key[1])
state <= G;
else if(sw[2:0]==110&& ~key[1])
state <= H;
else
state <=I;
end

B:
begin
if(sw[2:0]==000&& ~key[1])
state <= B;
else if(sw[2:0]==001&& ~key[1])
state <= C;
else if(sw[2:0]==010&& ~key[1])
state <= D;
else if(sw[2:0]==011&& ~key[1])
state <= E;
else if(sw[2:0]==100&& ~key[1])
state <= F;
else if(sw[2:0]==101&& ~key[1])
state <= G;
else if(sw[2:0]==110&& ~key[1])
state <= H;
else
state <=I;
end

C:
begin
if(sw[2:0]==000&& ~key[1])
state <= B;
else if(sw[2:0]==001&& ~key[1])
state <= C;
else if(sw[2:0]==010&& ~key[1])
state <= D;
else if(sw[2:0]==011&& ~key[1])

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 state <= E;
else if(sw[2:0]==100&& ~key[1])
state <= F;
else if(sw[2:0]==101&& ~key[1])
state <= G;
else if(sw[2:0]==110&& ~key[1])
state <= H;
else
state <=I;
end

D:
begin
if(sw[2:0]==000&& ~key[1])
state <= B;
else if(sw[2:0]==001&& ~key[1])
state <= C;
else if(sw[2:0]==010&& ~key[1])
state <= D;
else if(sw[2:0]==011&& ~key[1])
state <= E;
else if(sw[2:0]==100&& ~key[1])
state <= F;
else if(sw[2:0]==101&& ~key[1])
state <= G;
else if(sw[2:0]==110&& ~key[1])
state <= H;
else
state <=I;
end

E:
begin
if(sw[2:0]==000&& ~key[1])
state <= B;
else if(sw[2:0]==001&& ~key[1])
state <= C;
else if(sw[2:0]==010&& ~key[1])
state <= D;
else if(sw[2:0]==011&& ~key[1])
state <= E;
else if(sw[2:0]==100&& ~key[1])
state <= F;
else if(sw[2:0]==101&& ~key[1])
state <= G;
else if(sw[2:0]==110&& ~key[1])
state <= H;
else
state <=I;

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 end

F:
begin
if(sw[2:0]==000&& ~key[1])
state <= B;
else if(sw[2:0]==001&& ~key[1])
state <= C;
else if(sw[2:0]==010&& ~key[1])
state <= D;
else if(sw[2:0]==011&& ~key[1])
state <= E;
else if(sw[2:0]==100&& ~key[1])
state <= F;
else if(sw[2:0]==101&& ~key[1])
state <= G;
else if(sw[2:0]==110&& ~key[1])
state <= H;
else
state <=I;
end

G:
begin
if(sw[2:0]==000&& ~key[1])
state <= B;
else if(sw[2:0]==001&& ~key[1])
state <= C;
else if(sw[2:0]==010&& ~key[1])
state <= D;
else if(sw[2:0]==011&& ~key[1])
state <= E;
else if(sw[2:0]==100&& ~key[1])
state <= F;
else if(sw[2:0]==101&& ~key[1])
state <= G;
else if(sw[2:0]==110&& ~key[1])
state <= H;
else
state <=I;
end

H:
begin
if(sw[2:0]==000&& ~key[1])
state <= B;
else if(sw[2:0]==001&& ~key[1])
state <= C;
else if(sw[2:0]==010&& ~key[1])

EE – 421: DIGITAL SYSTEM DESIGN LAB

 state <= D;
else if(sw[2:0]==011&& ~key[1])
state <= E;
else if(sw[2:0]==100&& ~key[1])
state <= F;
else if(sw[2:0]==101&& ~key[1])
state <= G;
else if(sw[2:0]==110&& ~key[1])
state <= H;
else
state <=I;
end

I:
begin
if(sw[2:0]==000&& ~key[1])
state <= B;
else if(sw[2:0]==001&& ~key[1])
state <= C;
else if(sw[2:0]==010&& ~key[1])
state <= D;
else if(sw[2:0]==011&& ~key[1])
state <= E;
else if(sw[2:0]==100&& ~key[1])
state <= F;
else if(sw[2:0]==101&& ~key[1])
state <= G;
else if(sw[2:0]==110&& ~key[1])
state <= H;
else
state <=I;
end
endcase
end
endmodule

module shift_register(clk,reset,in2,LEDR,out2);

input clk,reset;
input [15:0] in2;
output reg [15:0] out2;

initial

begin
out2=in2;
end
output reg LEDR;
integer i;

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always @(posedge clk,negedge reset)
if(~reset)
out2<=0;
else
begin
for(i=0;i<15;i=i+1)
begin
out2[i+1]<=out2[i];
out2[15]<=out2[0];
LEDR<=out2[0];
end
end

endmodule

RTL Viewer:

Hardware Implementation:

EE – 421: DIGITAL SYSTEM DESIGN LAB

Conclusion:
In this lab, we explored the design and analysis of Finite State Machines (FSMs) for solving
diverse problems in fields such as computer science, engineering, and mathematics. We
learned how FSMs serve as effective models for algorithms, circuits, protocols, and
languages. By implementing FSMs using Verilog HDL and simulating them using tools like
Quartus, we gained a deeper understanding of the fundamental principles of FSMs and their
practical applications in real-world problem-solving.

EE – 421: DIGITAL SYSTEM DESIGN LAB