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This document contains a problem set on logic circuits for an introduction to logic course. It includes 40 problems involving logic gates, Boolean algebra, Karnaugh maps, and the implementation of logic circuits using gates. The problems cover topics such as drawing timing diagrams, evaluating logic gate outputs, simplifying Boolean expressions, developing truth tables, and designing logic circuits from expressions.

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Mohamed Tag Eldeen
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43 views5 pages

Sheet 3

This document contains a problem set on logic circuits for an introduction to logic course. It includes 40 problems involving logic gates, Boolean algebra, Karnaugh maps, and the implementation of logic circuits using gates. The problems cover topics such as drawing timing diagrams, evaluating logic gate outputs, simplifying Boolean expressions, developing truth tables, and designing logic circuits from expressions.

Uploaded by

Mohamed Tag Eldeen
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Alexandria University Introduction to logic circuits

Faculty of Engineering Course Code: EEE 141


EEE and EEP programs Lecturer: Karim Banawan
First Year Problem Set: 3
Academic Year: 2020-2021

Problem Set (3)


Logic Gates and Combinational Logic
1. The input waveform shown in figure is applied to an inverter. Draw the timing diagram
of the output waveform in proper relation to the input.

2. For the two input waveforms shown in figure, Determine the output for a 2-input AND gate and
the output for 2-input OR gate. Draw the timing diagram.

3. For the three input waveforms shown in figure, Determine the output for a 3-input AND gate
and the output for 3-input OR gate. Draw the timing diagram.

4. For the two input waveforms shown in figure, Determine the output for a 2-input NAND gate,
the output for 2-input NOR gate, the output for 2-input XOR gate and the output for 2-input
XNOR gate. Draw the timing diagram.

5. For the four input waveforms shown in figure, Determine the output for a 4-input NAND gate
and the output for 4-input NOR gate. Draw the timing diagram.
6. Evaluate the following operations:
a) 100 b) 111 c) 11 + 011

7. Find the values of the variables that make each product term 1 and each sum term 0.
a) 𝐴̅ + 𝐵 + 𝐶̅ b) 𝐴̅ + 𝐵 c) 𝐴𝐵 𝐶̅

8. Find the value of X for all possible values of the variables.


a) 𝑋 = (𝐴 + 𝐵)𝐶 b) 𝑋 = 𝐴𝐵 𝐶 + 𝐴𝐵 c) 𝑋 = (𝐴 + 𝐵)(𝐴̅ + 𝐵)

9. Identify the Boolean rule(s) on which each of the following equalities is based:
a) 𝐴(𝐵𝐶 + 𝐵𝐶) + 𝐴𝐶 = 𝐴(𝐵𝐶) + 𝐴𝐶 b) 𝐴𝐵(𝐶 + 𝐶̅ ) + 𝐴𝐶 = 𝐴𝐵 + 𝐴𝐶
C) 𝐴𝐵 + 𝐴𝐵 𝐶 = 𝐴𝐵 d) 𝐴𝐵𝐶 + 𝐴𝐵 + 𝐴𝐵𝐶 𝐷 = 𝐴𝐵𝐶 + 𝐴𝐵 + 𝐷

10. Apply DeMorgan’s theorems to each expression:


a) 𝐴𝐵 + 𝐶𝐷 b) (𝐴 + 𝐵 )(𝐶̅ + 𝐷)
c) (𝐴̅ + 𝐵 + 𝐶 + 𝐷 )(𝐴𝐵𝐶̅ 𝐷) d) 𝐴𝐵(𝐶𝐷 + 𝐸 𝐹)(𝐴𝐵 + 𝐶𝐷)
e) 𝐴 + 𝐵𝐶̅ + 𝐶𝐷 + 𝐵𝐶 f) (𝐴 + 𝐵 )(𝐶 + 𝐷 )(𝐸 + 𝐹 )(𝐺 + 𝐻 )

11. Write the Boolean expression for each of the logic circuits in figure.

12. Draw the logic circuit represented by each of the following expressions:
a) 𝐴𝐵 + 𝐶𝐷 b) 𝐴𝐵(𝐶 + 𝐷) c) 𝐴 + 𝐵[𝐶 + 𝐷(𝐵 + 𝐶̅ )]

13. Construct the truth table for each of the following Boolean expressions:
a) (𝐴 + 𝐵)𝐶 b) 𝐴𝐵 + 𝐵𝐶 c) (𝐴 + 𝐵)(𝐵 + 𝐶)

14. Use AND gates, OR gates, or combinations of both to implement the following logic expressions
as stated:
a) 𝑋 = 𝐴(𝐶𝐷 + 𝐵) b) 𝑋 = 𝐴𝐵(𝐶 + 𝐷𝐸𝐹) + 𝐶𝐸(𝐴 + 𝐵 + 𝐹)
c) 𝑋 = 𝐴[𝐵𝐶(𝐴 + 𝐵 + 𝐶 + 𝐷)] d) 𝑋 = 𝐵(𝐶𝐷 𝐸 + 𝐸 𝐹𝐺)(𝐴𝐵 + 𝐶)

15. Use NAND gates, NOR gates, or combinations of both to implement the following logic
expressions as stated:
a) 𝑋 = 𝐴𝐵𝐶̅ 𝐷 + 𝐷𝐸 𝐹 + 𝐴𝐹 b) 𝑋 = 𝐴̅[𝐵 + 𝐶̅ (𝐷 + 𝐸)]

16. Using Boolean algebra, simplify the following expressions:


a) 𝐴(𝐴 + 𝐴̅𝐵) b) 𝐴𝐵𝐶 + 𝐴̅𝐵𝐶 + 𝐴̅𝐵 𝐶
c) 𝐴𝐵 + 𝐴𝐵𝐶 + 𝐴 d) (𝐴 + 𝐴̅)(𝐴𝐵 + 𝐴𝐵𝐶̅ )
e) 𝐴𝐵 + (𝐴̅ + 𝐵 )𝐶 + 𝐴𝐵 f) (𝐵 + 𝐵𝐶)(𝐵 + 𝐵𝐶)(𝐵 + 𝐷)
g) 𝐴𝐵𝐶𝐷 + 𝐴𝐵(𝐶𝐷 ) + (𝐴𝐵)𝐶𝐷 h) 𝐴𝐵𝐶[𝐴𝐵 + 𝐶̅ (𝐵𝐶 + 𝐴𝐶)]
17. Determine which of the logic circuits in figure are equivalent.

18. Convert the following expressions to sum-of-product (SOP) forms:


a) 𝐴𝐵 + 𝐶𝐷(𝐴𝐵 + 𝐶𝐷) b) 𝐴𝐵(𝐵 𝐶̅ + 𝐵𝐷) c) 𝐴 + 𝐵[𝐴𝐶 + (𝐵 + 𝐶̅ )𝐷]

19. Covert each SOP expression in problem 18 to standard SOP form.

20. Determine the binary value of each term in the standard SOP expressions from problem 19.

21. Covert each standard SOP expression in problem 19 to standard POS form.

22. Develop a truth table for each of the following standard SOP expressions.
a) 𝐴̅𝐵 𝐶̅ 𝐷 + 𝐴̅𝐵𝐶𝐷 + 𝐴𝐵𝐶̅ 𝐷 + 𝐴̅𝐵𝐶̅ 𝐷
b) 𝑊𝑋𝑌𝑍 + 𝑊𝑋𝑌𝑍̅ + 𝑊 𝑋𝑌𝑍 + 𝑊𝑋𝑌𝑍 + 𝑊𝑋𝑌𝑍
c) 𝐴̅𝐵 + 𝐴𝐵𝐶̅ + 𝐴̅𝐶̅ + 𝐴𝐵 𝐶

23. Develop a truth table for each of the following standard POS expressions.
a) (𝐴 + 𝐵)(𝐴 + 𝐶)(𝐴 + 𝐵 + 𝐶)
b) (𝐴 + 𝐵 )(𝐴 + 𝐵 + 𝐶̅ )(𝐵 + 𝐶 + 𝐷 )(𝐴̅ + 𝐵 + 𝐶̅ + 𝐷)
24. Implement a logic circuit for the truth table:
25. For each truth table in figure, drive standard SOP and standard POS expressions.

26. Minimize the gates required to implement the functions in part(c, d) of problem 14.
27. Minimize the gates required to implement the functions in each part of problem 15.
28. Use Karnaugh map to simplify each expression to a minimum SOP form:
a) 𝐴̅𝐵 𝐶̅ + 𝐴𝐵 𝐶 + 𝐴̅𝐵𝐶 + 𝐴𝐵𝐶̅ b) 𝐴𝐶[𝐵 + 𝐵(𝐵 + 𝐶̅ )] c) 𝐷𝐸𝐹 + 𝐷 𝐸𝐹 + 𝐷 𝐸 𝐹
29. Use Karnaugh map to reduce each expression to a minimum SOP form:
a) 𝐴̅𝐵 (𝐶̅ 𝐷 + 𝐶̅ 𝐷 ) + 𝐴𝐵(𝐶̅ 𝐷 + 𝐶̅ 𝐷 ) + 𝐴𝐵𝐶̅ 𝐷
b) (𝐴̅𝐵 + 𝐴𝐵)(𝐶𝐷 + 𝐶𝐷 )
c) 𝐴̅𝐵 + 𝐴𝐵 + 𝐶̅ 𝐷 + 𝐶𝐷

30. Use Karnaugh map to simplify each expression to a minimum POS form:
a) (𝐴 + 𝐵 + 𝐶 + 𝐷 )(𝐴̅ + 𝐵 + 𝐶̅ + 𝐷)(𝐴̅ + 𝐵 + 𝐶̅ + 𝐷 )
b) (𝑋 + 𝑌)(𝑊 + 𝑍̅)(𝑋 + 𝑌 + 𝑍̅)(𝑊 + 𝑋 + 𝑌 + 𝑍)

31. Reduce the function specified in the truth table in figure to its minimum SOP form and to its
minimum POS form by using a Karnaugh map.

32. Convert each of the following POS expression to minimum SOP expression using a Karnaugh
map.
a) (𝐴 + 𝐵 )(𝐴 + 𝐶̅ )(𝐴̅ + 𝐵 + 𝐶) b) (𝐴̅ + 𝐵)(𝐴̅ + 𝐵 + 𝐶̅ )(𝐵 + 𝐶̅ + 𝐷) (𝐴 + 𝐵 + 𝐶 + 𝐷 )
33. Write the output expression for each circuit in figure.

34. Develop truth table for each circuit in problem 33.


35. Write the output expression for each circuit in figure, and then change each circuit to an
equivalent AND-OR configuration.

36. Develop truth table for each circuit in problem 35.


37. Implement the logic circuits in figure using only NAND gates.

38. Repeat problem 37 using only NOR gates.


39. Show how the following expressions can be implemented as stated using only NOR gates:
a) 𝑋 = 𝐴𝐵 + 𝐶𝐷 b) 𝑋 = (𝐴 + 𝐵)(𝐶 + 𝐷) c) 𝑋 = 𝐴𝐵[𝐶(𝐷𝐸 + 𝐴𝐵) + 𝐵𝐶𝐸 ]
40. Repeat problem 39 using only NAND gates.

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