1

भारत सरकार – रे ऱ मंत्राऱय

GOVERNMENT OF INDIA – MINISTRY OF RAILWAYS

Guidelines on
Interface Design of
Electronic Interlocking Installation
CAMTECH/S&T/2022-23/ID-EI/ 1.0
December 2022
End Users : Signal Engineers of Indian Railways

Indian Railways
Centre for Advanced Maintenance Technology Maharajpur,
Gwalior (M P) 474005
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Guidelines on
Interface Design of
Electronic Interlocking Installation
CAMTECH/S&T/2022-23/ID-EI/ 1.0
December 2022
End Users : Signal Engineers of Indian Railways

Prepared by : Praveer Kumar Wakankar, SSE/Signal, IRCAMTECH GWL

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Foreword
The relay based Signal Interlocking installations use Electro-magnetic relays which
require complex wiring, interconnections, hundreds of sheets of wiring diagrams
and occupy a large space for installation. These systems pose some drawbacks due
to the tremendous growth in freight and passenger traffic in Indian Railways, such
as long duration traffic blocks during commissioning and alterations for yard
remodeling works. To overcome the limitations of relay based interlocking
systems, microprocessor based Electronic Interlocking (EI) systems have been
introduced. They are more reliable, with less number of relays, less power
consumption and ease of installation and maintenance. Although the interlocking
functions are catered through application logic (software), some relays and external
equipments are still required to be interfaced with EI system. The Interface Design
is a very important stage which involves interfacing of various signalling functions
and associated equipments with the EI system for their proper functioning.
CAMTECH has prepared this handbook which explains the concept of Interface
Design of Electronic Interlocking and provides information on preparation and
documentation for the same during pre-commissioning stage.
I hope that this handbook will be useful for Signal Engineers of Indian Railways
concerned with EI installation to get familiar with the basic concepts of Interface
Design and help them in implementing the same in their respective installations. I
wish them all the success.

CAMTECH Gwalior Jitendra Singh

Principal Executive Director
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Preface
In Indian Railways, Electronic Interlocking (EI) installations are progressively
being commissioned replacing the existing relay based Signal Interlocking
installations. Unlike PI/RRI the interlocking among various signalling gears like
signals, points, track circuits etc. is achieved through software. However some
relays and other equipments are still required for interfacing with the EI for
detection and control of various field functions. During the planning stage of EI
installation, assessment of Input & Output bits, number of Relays, Relay Racks and
Cable Termination (CT) Racks, Number of Sub Racks/ Housings, System
Configuration and Communication arrangement, Interconnection of various racks
and interlocking equipment etc. has to be done.
This handbook covers basic concepts of Interface Design, procedure for
preparation of bit chart, assessment of relays, relay racks, subracks/housings for
Electronic Interlocking installation and their documentation with reference to
already commissioned stations.
We are sincerely thankful to S&T Directorate RDSO, IRISET Secunderabad, M/s
Siemens Rail Automation Pvt. Ltd., Bangalore and M/s TVM Signalling &
Transportation Systems Pvt. Ltd. (KYOSAN), Bangalore, who have provided
valuable inputs for preparing this handbook. Since technological upgradation and
learning is a continuous process, you may feel the need for some
addition/modification in this handbook. If so, please give your comments on email
address [email protected] or write to us at Indian Railways Centre for
Advanced Maintenance Technology, In front of Adityaz Hotel, Airport Road, Near
DD Nagar, Maharajpur, Gwalior (M.P.) 474005.
CAMTECH Gwalior Avadhesh Kumar Yadav
Director (S&T)
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Table of Contents

Section I 1
Electronic Interlocking Interface Design 1
1.1 Introduction 1
1.2 Some important terms related to Interface Design 3
1.3 Objective of Interface design 8
1.4 Inputs required for preparation of Interface Design 9
1.5 Stages involved in interface design 10
1.6 Input & Output modules of different make EIs 11
1.7 Inputs/Output bits & Relays for various outdoor signalling gears 18
1.8 RDSO Report on Standardization of Typical Circuits for EI 20
1.9 Interface Design Documentation 21
Section II 27
Interface Design for 27
Siemens WESTRACE VLM6 EI 27
2.1 Introduction 27
2.2 Details of Signalling assets 27
2.3 Assessment of Vital Input /Output bits & Relays 29
2.4 Assessment of Non-Vital Input/Output bits 32
2.5 Calculation of Vital Input & Output Modules 35
2.6 Assessment of Housings for accommodation of Vital Input & Output Modules 35
2.7 Preparation of Bit Chart 36
2.8 Calculation of Non-Vital Input & Output Modules 39
2.9 Calculation of Relay Racks 41
Section III 43
Interface Design for 43
Siemens WESTRACE Mark II EI 43
3.1 Introduction 43
3.2 Details of Signalling Assets 43
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3.3 Assessment of Vital Input/Output bits & Relays 45

3.4 Calculation of Vital Input & Output Modules 48
3.5 Assessment of Housings for accommodation of Vital Input & Output Modules 49
3.6 Preparation of Bit Chart 49
3.7 Calculation of Relay Racks 51
ANNEXURE I 53
Interface Circuits documentation of stations commissioned with Electronic Interlocking 53
References 51
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Amendments & Revisions

The amendments/revisions to be issued in future for this report will be numbered as
follows:

CAMTECH/S&T/2022-23/ID-EI/1.0 # XX date .......

Where “XX” is the serial number of the concerned amendment/revision (starting from 01
onwards).

Sr. No. Date of Amendment/Revision Remarks

issue
1.00 28.12.2022 First Release --
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Disclaimer & Objective

Disclaimer
It is clarified that the information given in this handbook does not
supersede any existing provisions laid down in the Signal Engineering
Manual, Railway Board and RDSO publications. This document is not
statuary and instructions given are for the purpose of guidance only.
If at any point contradiction is observed, then Signal Engineering
Manual, Telecom Engineering Manual, Railway Board/RDSO
guidelines may be referred or prevalent Zonal Railways instructions
may be followed.

Our Objective
To upgrade Maintenance Technologies and Methodologies and
achieve improvement in Productivity and Performance of all Railway
assets and manpower which inter-alia would cover Reliability,
Availability and Utilisation.

If you have any suggestion & any specific comments, please write to us:
Contact person : Director (Signal & Telecommunication)
Postal Address : Centre for Advanced Maintenance Technology, Opposite
Hotel Adityaz, Near DD Nagar, Maharajpur, Gwalior
(M.P.) Pin Code – 474 005

Phone : 0751 - 2470185

Fax : 0751 – 2470841
Email : [email protected]
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CAMTECH Publications
CAMTECH is continuing its efforts in the documentation and up-gradation of information on
maintenance practices of Signalling & Telecom assets. Over the years a large number of
publications on Signalling & Telecom subjects have been prepared in the form of handbooks,
pocket books, pamphlets and video films. These publications have been uploaded on the internet
as well as railnet. For viewing/downloading these publications

On Internet:
Visit www.indianrailways.gov.in
Go to About Indian Railways → Railway Board Directorates →Efficiency &
Research→CAMTECH, Gwalior → Other Important links → Publications for download →S&T
Engineering (Yearwise/ Subjectwise).

On Railnet:
Visit Railway Board website at 10.1.2.21
Go to Railway Board Directorates → →Efficiency & Research→CAMTECH, Gwalior → Other
Important links → Publications for download →S&T Engineering (Yearwise/ Subjectwise).

Alternatively the CAMTECH publications can be viewd/downloaded through following link on

Internet/Railnet:

https://indianrailways.gov.in/railwayboard/view_section.jsp?lang=0&id=0,1,304,366,538,2713,2
718,2722,2731

A limited number of publications in hard copy are also available in CAMTECH library which
can be got issued by deputing staff with official letter from controllong officer. The letter should
be addressed to Director (S&T), CAMTECH, Gwalior.
For any further information regarding publications please contact:

Director (S&T) – 0751-2470185 (O)(BSNL)

SSE/Signal - 7024141046 (CUG)
Or
Email at [email protected]
Or
FAX to 0751-2470841 (BSNL)
Or
Write at
Director (S&T)
Indian Railways Centre for Advanced Maintenance Technology,
In front of Hotel Adityaz, Airport Road, Maharajpur,
Gwalior (M.P.) 474005
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List of Figures
Figure 1 : Block Diagram of Electronic Interlocking - Centralized Architecture ........................................ 2
Figure 2 : Block Diagram of Electronic Interlocking - Distributed Architecture ........................................ 3
Figure 3 : Block diagram of Input & Output Interface of EI ........................................................................ 5
Figure 4 : Parallel Input Module (PIM50) Input Circuit ........................................................................... 12
Figure 5 : Relay Output Module (ROM) Output Circuit ............................................................................ 12
Figure 6 : A typical Input Board Circuit of Kyosan K5BMC EI ................................................................ 13
Figure 7 : A typical Output Board Circuit of Kyosan K5BMC EI .............................................................. 14
Figure 8 : Typical System Configuration of an EI Installation .................................................................. 24
Figure 9: Signalling Plan of SINGRA Station (North East Frontier Railway) ........................................... 28
Figure 10 : Indications of Point 111/112 on CCIP..................................................................................... 34
Figure 11 : Indications of Point 101/102 on CCIP..................................................................................... 34
Figure 12 : Arrangement of Modules in SNGA WESTRACE VLM6 Housings .......................................... 36
Figure 13 : Front Panel Indications of DIP/DOP Card ............................................................................. 39
Figure 14 : Front view of WESTRONICS S2 Panel Processor .................................................................. 39
Figure 15 : Signalling Plan of HAYAGHAT Station (East Central Railway) ............................................. 44
Figure 16 : Arrangement of Modules in HYT WESTRACE Mark II Housings ........................................... 49
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List of Tables
Table 1 : Comparative of Executive & Application Software ...................................................................... 8
Table 2 : Comparative of different make EIs .............................................................................................. 17
Table 3 : I/O Bits & Relays for Signalling Gears ....................................................................................... 18
Table 4 : Vital Input/Output bits & Relays of SNGA station with WESTRACE VLM6 EI ...................... 29
Table 5 : Additional Relays required for SNGA station ............................................................................. 32
Table 6 : Non-Vital Input/Output bits for SNGA station with WESTRACE VLM6 EI............................. 32
Table 7 : Summary of Input/Output bits & Relays (SNGA) ....................................................................... 34
Table 8 : Bit Chart for SNGA WESTRACE VLM6 Housing 1 ................................................................. 37
Table 9 : Bit Chart for SNGA WESTRACE VLM6 Housing 2 ................................................................. 37
Table 10 : Bit Chart for SNGA WESTRACE VLM6 Housing 3 ............................................................... 38
Table 11: Vital Input/Output bits & Relays of HYT station with WESTRACE Mark II EI ...................... 45
Table 12 : Additional Relays required for HYT station .............................................................................. 47
Table 13 : Summary of Input/Output bits & Relays ................................................................................... 48
Table 14 : Bit Chart for HYT WESTRACE Mark II Housing 1................................................................. 50
Table 15 : Bit Chart for HYT WESTRACE Mark II Housing 2................................................................. 50
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Abbreviations
ABS Automatic Block Signalling
BPAC Block Proving by Axle Counter
CCIP Control Cum Indication Panel
CD Compact Disc
CHLR Crank Handle Lock Relay
CHPR Crank Handle Proving Relay
CIU Central Interlocking Unit
CPU Central Processing Unit
CT Cable Termination
DC Direct Current
DIP Digital Input
DOP Digital Output
ECR Lamp Proving Relay
EI Electronic Interlocking
EKT Electric Key Transmitter
EPROM Erasable Programmable Read Only Memory
FCOR False Feed Cut Off Relay
FTB Fiber termination Box
IB Intermediate Block
I/O Input/Output
IPS Integrated Power Supply
LED Light Emitting Diode
LX Level Crossing
LXPR Interlocked Level Crossing Gate Proving Relay
MT Maintainer‟s Terminal
NCDM Network Communication & Diagnostic Module
OC Object Controller
OCM Object Controller Module
OEM Original Equipment Manufacturer
OFC Optical Fiber Communication
OPC Output Power Control
PCB Printed Circuit Board
PI Panel Interlocking
PIM Parallel Input Module
PM Processor Module
PP Panel Processor
PSU Power Supply Unit
RAM Random Access Memory
RI Relay Input
RO Relay Output
ROM Read Only memory/ Relay Output Module
RRI Route Relay Interlocking
SIP Signal Interlocking Plan
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SM Station Manager
SYSON System On
TPR Track Proving Relay
VDU Visual Display Unit
VLC Vital Interlocking Card
VLM Vital Logic Module
VPIM (i) Vital Parallel Input Module
VR Vital Relay
VROM Vital Relay Output Module
WNCDM WESTRACE Network Communication & Diagnostic Module
WFM Wayside Function Module

Note: Relay nomenclatures have not been covered in the above list.
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Section I
Electronic Interlocking Interface Design

1.1 Introduction
Electronic Interlocking (EI) system is a microprocessor based interlocking equipment to read the
inputs from the signalling gears in the yard and process commands from the operational console
in a fail-safe manner as per selection table and generate required output for controlling field
gears. This system is the alternative to the conventional Relay Interlocking system (PI & RRI).
Unlike PI/RRI the interlocking among various signalling gears like signals, points, track circuits
etc. is achieved through application software. Hence significant numbers of relays are reduced
and the human interference with interlocking functions is avoided. However in the Indian
Railways, relays are continued to be used with associated field equipment for interfacing the
feedback (through input) and control (through output) of various field functions with the EI as
given below.
The contacts of following relays are taken as inputs from field:
 Track Proving Relays (TPRs),
 Signal Lamp Proving Relays (ECRs),
 Point position proving Relays (NWKR/RWKR) etc.
The following relays are picked up through the output voltage given by EI which in turn drive
the field gears through their contacts:
 Signal Control Relays (HRs, DRs, HHRs)
 Point Control Relays (WNR, WRR)
 Crank Handle Relay (CHLR) etc.
The EI system also requires button inputs from the operator‟s panel. It also gives output voltage
for indications on CCIP.
The software associated with EI system are of two types (i) Executive Software or System
Software governing system working & (ii) Application Software designed and loaded as per the
signal interlocking requirements. The Executive software pertains to „Principles of Interlocking‟
and is universal for all stations. The application software pertains to „Table of Control‟ of yard
and it is station specific.

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What is Interface Design?

The EI system consists primarly
 Processor
 Input Modules
 Output Modules
 Communication Interface – to communicate with operator console (CCIP/Panel/VDU) ,
monitoring hardware(Maintenance/Diagnostic Terminal, Datalogger etc.) and other
processors and object controllers if any
The Signalling functions as mentioned above are classified as Input and Output functions. These
functions are required to be interfaced with the EI system for its operation. Total number of
inputs and outputs depend on yard layout. Hence for preparation of interface design of EI, all the
details related to yard layout such as Approved Signalling Plan, Panel diagrams and cabin wise
gear segregation in case of distributed interlocking etc. are required.

Figure 1 : Block Diagram of Electronic Interlocking - Centralized Architecture

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In other words, Interface design consists of organizing EI Hardware, allocation of field Inputs &
Outputs, floor plan to accommodate other peripherals like Relay Rack, Datalogger equipment
and cable termination rack etc. and associated physical wiring. Interface design also consists of
communication network design with associated configuration to connect peripherals like
Maintenance/Diagnostic Terminal , VDU and other Processor and Object Controller if any

Figure 2 : Block Diagram of Electronic Interlocking - Distributed Architecture

1.2 Some important terms related to Interface Design

Some important terms related to interface circuit design of Electronic Interlocking are explained
below:
(i) Input Functions
The inputs from field such as Track detection (TPRs, VRs), Point position detection (WKRs),
Signal aspect proving (ECRs), Interlocked gate, Siding and Crank handle position proving, and

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Block line clear position are considered as Vital input functions. Panel button/ knob/ key
controls or VDU commands are considered as Non-vital input functions.
(ii) Output Functions
Signal controls (HRs, DRs, UHR/UGR), Point controls (WNRs/ WRRs), Slot controls (YRs/
CHYRs/LXYRs/KLYRs) are considered as Vital output functions. All panel/ VDU indications,
alarms, counters are considered as Non-vital output functions.

(iii) Read back inputs

Apart from above input and output functions, the vital output functions are read back as inputs to
the system for the purpose of ensuring integrity of the vital output commands generated by CPU.
These depend on the type of EI and Zonal Railway requirements. Examples are HRs, DRs,
WNRs, WRRs.

(iv) Input Cards

These are printed circuit Boards (PCBs). Status of all the field functions, through concerned
relay contacts, is connected to input cards via terminals or tag blocks. These cards read the
conditions of inputs from field and pass the information to EI system. These input cards are
named as Vital Input Card / Relay Input Card / Read Interface Card (RI card). Panel
controls are connected to Input cards via terminals or tag blocks. These input cards are named as
Non-vital Input Cards. The number of inputs per Input Card will vary from make to make
(Please refer para 1.6). The total number of inputs will depend on the yard layout.

(v) Output Cards

These are also printed circuit Boards (PCB). Output card receives the output of CPU Card as
input and gives output voltage to pick up relevant output relays to drive field functions. Output
cards are generally named as Vital Output Card / Relay Output Card (RO Card)/ Relay
Driver Card. Panel indications, alarms and counters are driven by output cards via terminals or
tag blocks. These output cards are named as Non-vital Output Cards. The number of outputs
per output card will vary from make to make (Please refer para 1.6). The total number of outputs
will depend on the yard layout.

(vi) CPU Card

Central Processing Unit (CPU) serves as Logic processor. It consists of
microprocessor/microcontroller, RAM – Random Access Memory, ROM – Read Only Memory

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and EPROM – Erasable Programmable read only Memory. There will be separate EPROM for
Application software and Executive software. The CPU receives commands from Panel /VDU
and processes them as per the Application data stored in the EPROMs. It drives output field
functions if the interlocking conditions are satisfied. It also drives requisite indications on the
panel/ VDU.

Figure 3 : Block diagram of Input & Output Interface of EI

(v) Operator Console

I. VDU
VDU, Visual Display Unit is used as operator console to digitally communicate between
operator and EI hardware. VDU consists of a monitor, standard PC, network switches for
connectivity. In general VDU is arranged with a dual redundancy so as either one of the VDU
will be able to communicate to EI hardware. The operational commands (inputs), the
indications (outputs) on the VDU are mapped and configured as I/O in the network session
defined in the application software. These I/Os doesn‟t require any physical wiring or
connectivity. In the Interface design VDU connectivity in general is shown in the schematic
architectural diagram.

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II. Control Cum Indication Panel (Operator’s panel)

CCIP is provided with push buttons/control switches for individual operation of points, clearing
of signals, releasing of crank handle interlocking/ground lever frame/gate controls, cancellation
of routes and other functions including block signalling, auto signal, IB signal, adjacent yard
layout, to facilitate indication or operation cum indication as per requirement.

Note: A control terminal with VDU in lieu of or in addition to conventional CCIP is provided as
per requirement.

(vii) Panel processor

A microprocessor based electronic device used as interface between control/indication panel and
the EI hardware. This is also called as non-vital processor or panel processor. The Panel
processor is used to convert analog to digital or vice versa between CCIP and EI hardware. The
physical wiring and interconnectivity between CCIP and Panel Processor are generally provided
in the Interface circuits. The network connectivity between Panel Processor and EI hardware is
shown in the schematic architectural diagram.

(viii) Maintenance Terminal

Maintenance Terminal consists of a standard PC with printer. It performs the following
operations:
 Display of the current status of points, signals controls etc. of the yard.
 Display/replay of recorded events
 Data transfer to floppy, CD, flash memory or any other storage media.
 Transfer of recorded events to external data logger.
 Result of the failure of any card/module in the system.
 Control operation of yard functions is not possible from the maintenance terminal.
 In case of any module /card becoming faulty, this fact is displayed on MT with diagnostic
facility to identify faulty module/card.
 Maintenance terminal connectivity through network is generally shown in the architectural
diagram.

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(ix) Object Controller

 Object Controller is a processor-based system having similar architecture as of CIU. It works
as a slave unit of Central Interlocking Unit (CIU) through duplicated serial communication.
 The OC drives the field gears (Points, Signals & Relays) and take feedback (Inputs) from
various field gears. OC is normally placed in field locations.
 The medium of communication between CIU and OC is OFC provided on a ring basis. In
case of communication failure between CIU and OC, all the outputs are brought to safe state
whenever two consecutive telegrams are not received in stipulated time period.
 Occurrence of any error in any OC or hardware fault leading to unsafe condition immediately
withdraws all output commands and removes the source supply to outputs.

(x) RAM
Random Access Memory (Used for vital data processing and event/error logs).

(xi) EPROM
Erasable Programmable Read Only Memory (Used for storing Executive and Application
software).

(xii) Software
The software of the system has two layers:
 Executive Software or System Software
 Application Software

Executive Software or System Software

The Executive Software is programmed in system EPROMs. This Software defines what the
system can do and how the various parts of the system operate together. It includes all start up
and operational safety tests (including checking the Executive software itself) that are the parts
of the processor for continual assurance of safety operation. Executive software pertains to
„Principles of Interlocking‟.

Application Software
The application software is programmed in Data EPROMs. It contains the logic that defines how
the inputs and outputs for a particular station are related. It pertains to „Table of Control‟ of yard.
This shall be station specific.

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The Executive Software and Application Software are programmed into Read Only Memories
(ROMs) by the manufacturer. Both the ROMs shall be separated and isolated from each other. A
comparative study is shown in the following table:

Table 1 : Comparative of Executive & Application Software

Sr. Executive software Application software

No.
1. Common to all EIs for the Yard specific. Different for different
same manufacturer. station.
2. Factory installed Can be installed at site by signal
engineers.
3. Performs all operations. Performs operations as per table of control
of specific station.
4. It is not possible to modify Application engineers have the facility to
Executive Software. modify application software as and when
required

At the time of yard alteration work, Data EPROMs are to be replaced with new Data EPROMs
programmed with software pertaining to revised table of control as per altered yard data.
Compiler software is used for yard alteration.

1.3 Objective of Interface design

The objective of interface design is to assess following for planning of an Electronic Interlocking
installation :

 Vital and Non-vital I/O bits.

 Vital and Non-vital I/O boards.
 Number of Card files/ Housings.
 System Configuration and Communication arrangement.
 No. of Relays, Relay Racks and Cable Termination (CT) Racks.
 No. of PCB Connector Assemblies and Terminals.
 Interconnection of sub-systems and interlocking equipment.
This may vary for different make Electronic Interlocking systems.

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1.4 Inputs required for preparation of Interface Design

Following inputs in the form of documents are required for preparation of Interface Design of an
Electronic Interlocking installation:
 Approved Signal Interlocking Plan.
 Approved Panel Diagram
 Approved Route Control Chart/Selection Table
 Communication diagram between systems and other consoles.
 Relay and SM Room building layout.
 Power Supply scheme for EI systems and Interlocking equipment
 Cabin-wise signalling gear segregation in case of distributed interlocking architecture.
 Details of any additional Interlocking equipment to be interfaced with EI system.

Why required?
The significance of the items listed above is given below:

Approved Signal Interlocking Plan

Signal Interlocking Plan (SIP) is required to know the details of the outdoor gears like signals,
points, tracks circuits, crank handles, Level crossing gates etc. Details like aspects of signals,
type of point (single ended or double ended) & its operation, type of track circuit/axle counter.
This helps in the assessment of Vital Inputs/Output bits for interface design.

Approved Panel Front Plate Diagram

The Front Plate Diagram of Control cum Indication Panel if provided helps in the assessment of
controls and indications for calculation of Non-Vital Input/output bits.

Approved Route Control Chart/Selection Table

Route Control Chart (RCC) along with Signal Interlocking Plan (SIP) help to prepare external
signalling circuits which are required to operate the functions such as Signal Lighting Circuits,
Level crossing gate control, Block circuits and other miscellaneous circuits. It also helps in the
preparation of wiring diagram of Interlocking equipments such as Signals, Points, Crank handles,
LX, Siding, Slot, Block, Axle Counters etc.

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Power Supply scheme

Power supply scheme or IPS scheme is required to calculate the power supply requirement and
distribution to EI system and other signalling gears or equipments.

Communication arrangements
This helps in preparation of System Configuration of EI. The system configuration is designed
specific to the station depending upon the requirements.

Approved Floor Plan

Before commissioning of EI installation, the approved floor plans for Relay Room, EI Room,
SM Room, IPS Room, Battery Room, OFC Room etc. as applicable are required. This helps in
planning for installation of various systems and equipments such as EI Rack, Relay Rack, Cable
Termination Rack, Block Instruments, Axle Counter equipment, VDU/CCIP, Data Logger,
Diagnostic Terminal etc.

Details of any additional Interlocking equipment to be interfaced with EI system

This helps in making the provision of input/output bits, relays associated with additional
interlocking equipments in the interface circuits. For example Block Proving By Axle Counter
(BPAC), Automatic Block Signalling (ABS), Siding control etc.

1.5 Stages involved in interface design

Following stages are involved in the process of Interface Design:
 Vital I/O Bit calculation
 Non-Vital I/O Bit calculation
 Calculation of no. of relays
 Preparation of Bit Chart.
 Calculation of boards & Relays
 Calculation of Sub racks
 System Configuration
 Communication between various boards

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1.6 Input & Output modules of different make EIs

A brief description of various input and output modules of different make EIs is given below for
comparison:

(A) Siemens WESTRACE VLM6

(ii) Vital Parallel Input Module (VPIM)
Each module accepts 12 inputs
VPIMs receive 50 V DC inputs from the contacts of relays proving the status of outdoor gears
such as:
Track Proving Relays (TPRs, VRs), Point Detection Relays (WKRs), Signal Aspect Proving
Relays (ECRs), Interlocked Level Crossing Gate Proving Relay (LXPR), Crank Handle Proving
Relay (CHPR) etc.
VPIMs in turn provide an equivalent logic state to the Vital Logic Module (VLM).

(iii) Vital Relay Output Module (VROM)

Each module has 8 individual outputs that provide to the relays.
VROM receive logic states as 50 V DC input from the Vital Logic Module (VLM) and applies
50 V DC voltage to its isolated output terminals to pick up controlling relays for outdoor
signalling gears such as Signal Control Relays HR, DR & HHR, Point Control Relays WNR &
WRR, Crank Handle Lock Relay CHLR etc.

(iv) Power Supply Card

Normally one PSU card caters power supply requirements for two housings. However for better
system availability, one PSU card per housing is desirable.
(v) Processor Card
There will be Output Power Control (OPC) card in second slot, Vital Logic Module (VLM) in
third slot and Network Communication & Diagnostic Module (NCDM) in fourth slot. VLM and
OPC together form VLM6

(B) Siemens WESTRACE Mark II

(i) Parallel Input Module (PIM)
PIM50 have 12 inputs. Two PIMs of the same type may be connected in hot-standby for
improved availability.

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Figure 4 : Parallel Input Module (PIM50) Input Circuit

(ii) Relay Output Module (ROM)

ROM50 have 8 outputs. Outputs of Hot-Standby modules are paralleled.

Figure 5 : Relay Output Module (ROM) Output Circuit

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(iii) Power Supply

Typically two 24 DC supplies are used, derived from separate sources to give high availability.
Each housing requires its own power connection. WESTRACE Mark II systems also require 50
V DC signalling supply to power ROM50 modules and provide input to PIM50 modules from
external relay contacts.

(iv) Processor Module

A PM is normally placed in slot 1 of housing 1.
Hot-standby PMs are normally placed in slots 1 and 2 of housing 1 or slot 1 in each of two co-
located housings.

(C) Kyosan K5BMC

(i) ETPIO2 Board
ETPIO2 Board of EP5/ET sub-rack is a Vital I/O PCB. Each ETPIO2 I/O Board is having 32
input and 32 output ports. Input voltage is 24 V DC for each board.

Figure 6 : A typical Input Board Circuit of Kyosan K5BMC EI

(ii) MMIF2 Board
Each MMIF2 Board of EM6 sub-rack is a Non Vital I/O PCB. Each MMIF2 Board is having 32
Non-vital input and 64 output ports. Input voltage is 24 V DC for each board.

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(iii) Power Supply

Power supply to each card of the Logic Module is catered by IPU6C card. The first two Slots of
Logic Sub rack are used to accommodate IPU6C.
The Input Voltage is DC 24V + 10%
The Output Voltages are DC 24V + 10% and DC 5V +5%, -0%
It provides the isolated power supply to the each card of the Logic Module through built in DC-
DC converter.

Figure 7 : A typical Output Board Circuit of Kyosan K5BMC EI

(iv) Processor Card

F486-4I is a Fail safe 32 bit Intel processor CPU PCB with 2 out of 2 Architecture. It processes
main tasks of the EI System (setting system cycle time, Processing of interlocking connections

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and input/output with various apparatus, etc.). In addition, it also processes interlocking
connections by reading station-based data and driver data for inputs and outputs of each card
from IC cards. The Interlocking Logic Module of K5BMC EI uses two identical interlocking
logic modules (LK7-C) for redundancy.

(D) Hitachi Microlok II

(i) Vital Input PCB
Each Vital Input PCB is having 16 inputs.

(ii) Vital Output PCB

Each Vital Output PCB is having 16 independent 24 V outputs.

(iii) Non-Vital I/O Board

The Non-Vital I/O board is designed to receive non-vital inputs (controls) and generate non-vital
outputs (indications).
Each PCB provides 32 inputs and 32 outputs through its rear 96 pin connector.
Available in 12 V and 24 V DC applications.
(iv) Power Supply & Processor Boards
Slot No. 1 to 15 & 20 of MICROLOK II card file accommodate Non-Vital Input/Output or Vital
Input or Vital Output boards. (Slot No. 20 is used to accommodate Coded System Interface Card
or CSI Card for CTC.
Slot No. 16 & 17 accommodates Power Supply Board.
Slot 18 & 19 accommodate CPU board.

(E) Medha MEI633

(i) Wayside Function Module
The Wayside Function Module (WFM) is the Vital I/O Board of Object Controller Module
(OCM).
Each Input WFM can read at most 8 wayside function inputs and each Output WFM can drive at
most 8 wayside function outputs.

(ii) PP Input card

The input card of Panel Processor (PP) scans the state of the inputs on CCIP (Panel button/ knob/
key controls or VDU commands etc.). It is an interface card for scanning the CCIP buttons and
acts like Non-Vital Input Card. A Non-Vital Input Card can handle 64 inputs.

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(iii) PP Output card

Similarly output card of Panel Processor drives the indication information received from Vital
Interlocking Computer (VLC) to Control Cum Indication Panel (CCIP). It is an interface card for
driving the CCIP indication outputs and acts like Non-Vital Output Card. A Non-Vital output
Card can handle 64 outputs.
(iv) Power Supply
MEI633 uses three types of Power Supply modules viz, Type A, Type B and Type C Power
supplies. These power supplies are designed specifically to meet the requirements of various
cards in the CIU, OC and PP modules. All the three types take +24V as input.
(v) Processor
Central Interlocking Unit (CIU) Performs the Vital Interlocking functions and Communicates
with the other Sub-Systems. It consists of VIC, COMP, CIF and VHM cards, which are enclosed
in a single box.

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Table 2 : Comparative of different make EIs

Sr. EI make I/O Card Inputs/Outputs Remarks

No. that can be
handled per card
1 Siemens Vital Parallel Input 12 Vital Inputs The Vital Parallel Input Module (VPIM)
WESTRACE Module (VPIM) is used to accept signalling inputs into the
VLM6 WESTRACE system.
Vital Relay Output 8 Vital Outputs The Vital Relay Output Module (VROM)
Module (VROM) is used to directly drive 50 V DC
signalling relay and similar loads.
2 Siemens Parallel Input 12 Vital Inputs PIM receives 50 V DC inputs from the
WESTRACE Module (PIM) contacts of relays proving the status of
Mark II outdoor gears.
Relay Output 8 Vital Outputs ROM receives logic states as 50 V DC
Module (ROM) input from the Processor Module (PM)
and drives controlling relays for outdoor
signalling gears.
3 Kyosan ETPIO2 Board 32 Vital Inputs & ETPIO2 Board is housed in EP5/ET sub-
K5BMC 32 Vital Outputs rack. ET-PIO2 gets conditional input and
output of DC 24V.
MMIF2 Board 32 Non-Vital MMIF2 Board is housed in EM6 sub-
Inputs & 64 Non- rack.
Vital Outputs
4 Hitachi Vital Input PCB 16 Vital Inputs Each vital input is assigned to the
Microlok II detection of outdoor gear status.
Vital Output PCB 16 Vital Outputs Output is assigned to the final relay which
is driving the outdoor signalling gears.
Non-Vital I/O 32 Non-Vital Receives non-vital inputs (controls) and
Board Inputs & 32 Non- generate non-vital outputs (indications).
Vital Outputs
5 Medha Wayside Function 8 Vital Outputs & WFM is the Vital I/O Board of Object
MEI633 Module (WFM) 8 Vital Inputs Controller Module (OCM).
PP Input card 64 Non-Vital It is an interface card for scanning the
Inputs CCIP buttons.
PP Output card 64 Non-Vital It is an interface card for driving the CCIP
Outputs indication outputs.

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1.7 Inputs/Output bits & Relays for various outdoor signalling gears
Inputs/output bits & relays for various outdoor signalling gears are tabulated as below:

Table 3 : I/O Bits & Relays for Signalling Gears

Outdoor Vital Output Vital Input Non-Vital Non-Vital Relays

Gear Input Output
4 Aspect DR, HHR, DECR, DR_F 4GN 4DGKE, QN1 - 3
Signal HR HHECR, 4HHGKE, QECX61 – 4
HHR_F 4HGKE,
HECR, HR_F 4RGKE.
RECR.
3 Aspect DR, HR DECR, DR_F 3GN DGKE, QN1 - 2
Signal HECR, HR_F HGKE, QECX61 – 3
RECR. RGKE.
2 Aspect HR HECR, HR_F 2GN HGKE, QN1 - 1
Signal RECR. RGKE QECX61 – 2
1 Way Route UGR1 UECR. -- UGKE1. QN1 - 1
Indicator UGR1_F QECX61 – 1
2 way Route UGR1, UGR2 UGR1_F, -- UGKE1, QN1 - 2
Indicator UGR2_F, UGKE2. QECX61 – 1
UECR.
Calling On COHR COHECR, GN CO_HGKE QN1 - 1
Signal COHR_F QECX61 – 1
Semi-Auto AHR AECR, -- AGKE QN1 - 1
Signal AHR_F QECX61 – 1
Fixed ON -- RECR -- RGKE QECX61 – 1
Aspect
Independent HR OFFECR, GN OFFKE, QN1 - 1
Shunt Signal ONECR, ONKE QECX61 – 2
HR_F
Dependent HR OFFECR, GN OFFKE. QN1 - 1
Shunt Signal HR_F. QECX61 – 1
below Main
Signal
Point WNR, WRR NWKR, WN NWKE, QN1 – 2,
RWKR RWKE. QNA1 – 2
Crank Handle CHYR. CHCR CHYN KEYINKE, QN1 - 1
OUTKE. QNA1-1
Level LXYR LXCR LC.N CLOSKE, QN1 - 1
Crossing OPENKE QNA1 – 1
Siding YR CR N KEYINKE, QN1 – 1,
KEYOUTKE QNA1 –1
Slot YR OVYR, YN YKE, QN1 - 1
YR_F. OVYKE QNA1-1
Track circuit -- TPR -- TKE, TKRE QNA1 – 1

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Note:
 In addition to above, some other relays are also required for additional interlocking
equipments (if provided) to be interfaced with EI. For example, relays associated with Block
instrument, BPAC, Timer, SM‟s Key, Crank Handle, EKT, Point operation, IPS Health
Monitoring, Relay Room Door Lock, Repeater relays (for point, signal, track circuit), System
related Input & Output etc.
 The quantity of various relays is calculated as above.
 Number of relay racks required is calculated as below:
Total no. of Relay Racks = (Total no. of Relays + 15% Spare) divided by (Capacity of
Standard relay Rack)
 After finding out final quantity of Vital and Non-vital I/O bits, quantity of various
Input/Output modules is derived as given below:
(i) Total No. of Vital Output Modules = (Total no. of Vital Outputs + 15% spare) divided
by (Capacity of Vital Output Module)
(ii) Total No. of Vital Input Modules = (Total no. of Vital Inputs + 15% spare) divided by
(Capacity of Vital Input Module)
(iii) Total No. of Non-Vital Output Modules = (Total no. of Non-Vital Outputs + 15%
spare) divided by (Capacity of Non-Vital Output Module)
(iv) Total No. of Non-Vital Input Modules = (Total no. of Non-Vital Inputs + 15% spare)
divided by (Capacity of Non-Vital Input Module)

The requirement of Vital & Non-Vital Input/Output Modules will depend upon the make of EI.
In case of VDU, Non-Vital Inputs & Outputs cards are not required as requirements of
indications and controls of VDU are catered internally through direct communication with EI
system. The digital signals between VDU and EI system are configured to the processor module
through network sessions or network modules (like NCDM in WESTRACE VLM6). VDU or
Operator PC can communicate directly with EI System but for communication between CCIP
and EI System an interface with separate set of cards or hardware called Panel Processor is
required. In case of CCIP, the communication between EI system and CCIP is in the form of
analog signals. Hence for converting these signals into digital signals, a Panel Processor is
required. When CCIP is not used, there is no need to calculate Non-Vital Inputs & Outputs.

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As per RDSO Report on Standardization of Typical Circuits for EI Ver.2.0 dated 29.03.2022, in
all future installations, EI shall be provided with Dual VDU and therefore no provision in
standardized logic has been kept for CCIP working.

1.8 RDSO Report on Standardization of Typical Circuits for EI

In connection with the standardization of the typical design for Electronic Interlocking, a Sub
Working Group was formed as per Railway Board Letter No. 2010/Sig/WG/IP Dt. 02.05.2012 to
bring uniformity over Indian Railways. The Sub Working Group had finalized Typical Designs
of the Application Logics/Circuits required for Electronic Interlocking. This was submitted in the
form of report vide No. SS/137/2013. Observations of various zonal railways have been
examined by the committee through multiple rounds of video conference including discussions
with zonal railway design representatives and individual discussions among members. The
comments were also received from all approved EI vendors and Zonal Railways. Based on
above, the committee issued a Report on Standardization of Typical Circuits for EI (Report No.
SS/155/2019/2022) Ver.2.0 dated 29.03.2022.

The typical EI circuits under this report are available at the following link:
http://10.100.2.19/signal/policy/uniform_circuit_diagram.htm
(A hyperlink is also provided in Annexure I)
The salient feature of this report are given below which may be useful in the Interface design of
all future EI installations.

Salient Features of the report

In a meeting held at Mumbai on 30th October 2018, certain decisions were taken and circulated
by Railway Board vide letter No. 2018/Sig/36-SD/1 dated 14.11.2018. Accordingly, considering
the decisions taken, following are salient feature of this standardization report:

(i) All EI shall be provided with Dual VDU and therefore no provision in standardized logic
has been kept for CCIP working.
(ii) All EI shall be having route setting feature, but point chain group feature is not considered
essential as maximum of 2 to 3 points may be required to be operated at any time.

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(iii) Currently recommended standardized logics are proposed to be used for way side station
with maximum of 100 routes. This will cover more than 95% of stations on Indian
railways.
(iv) These stations of less than 100 routes shall not be having Sectional route release feature.
(v) All operation through VDU shall be by drop down menu.
(vi) A drop down menu can generate multiple command bits which is equivalent to press of
multiple buttons simultaneously.
(vii) For emergency operations, it is recommended that an additional physical key shall be
provided which shall be configured as redundant Vital input to Electronic Interlocking like
vital field inputs.
(viii) For each independent route with each independent overlap, there shall be one controlling
relay (LR). Thus LR shall be equal to number of routes in Route control table. This will
not require provision of swinging locking/conditional locking. Direct locking of all
conflicting movement shall be provided in LR circuit.
(ix) Logic for FCOR relay/bit is not prepared as there are no such directives in codes and
manuals and there are differences of opinion regarding its requirement among the OEM.
Hence FCOR logic is not recommended here.
(x) Circuits for automatic signalling, IB signalling, operation of Interlock LC gates, axle
counter resetting are not included as they are external to EI. These shall be catered in next
Phase.
(xi) Siding control through Ground frame are also excluded as now most of them are
converted to motor operation.
(xii) The recommended circuits are valid only for EI installation with Metal to Carbon interface
relays. However, in case of Proved type Signalling relays (Metal to Metal), the
requirement of circuit design is different where opening of front contact of relay is proved
by closing of back contact. Hence, the present recommended circuits shall not be used for
EI installation with Metal to Metal interface relays.

1.9 Interface Design Documentation

The Interface Design contains complete drawings and wiring details of the signalling gears,
signalling circuits other than interlocking logic circuits, power supplies to the system,
Communication arrangement among various modules, Relay Rack arrangement, EI Housings

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details, Fuse details, Relay Contact Analysis etc. Generally following details are covered in
Interface Design documentation:
(a) Index
The index contains list of all the drawings with description, drawing number and sheet number
on which it is available.
(b) Symbols
The various symbols used in the interface design along with description are listed under this
head.
(c) Material Reference List
This list contains details of material (like EI modules, Racks & Fittings, Computer accessories,
Connectors & Accessories etc.) used in the installation including description, material part
number or type, manufacturer and quantity.
(d) Approved Floor Plan
This contains the details of various rooms such as EI Room, SM Room Axle Counter Room, IPS
Room as applicable. All the details like spacing between various racks/equipments and spacing
from the wall, location of windows and doors, location of building with respect to track etc. are
marked in the floor plan.

(e) Input/Output Bit Chart

This chart contains distribution of Input and Output bits in EI housing along with processor
module and power supply module depending upon configuration of the particular make EI. The
following guidelines for preparation of bit chart may help in designing an efficient EI system
which can eliminate the possibilities of heavy traffic disruptions during failure of a single
module:
The bits may be arranged in such a way that on failure of any module/PCB associated with a line
the other circuits of that line are not affected. For example if bits associated with Home Signal
control circuit are accommodated in a module, the bits related to Calling On Signal shall be
assigned in another module. On failure of module containing Home signal bits, the Calling On
can be cleared to minimize the delay in traffic.
The bits can also be accommodated line wise in different modules so that failure of
signal/signalling gear pertaining to one line does not affect signals/signaling gears of other lines.
For example UP and DN Block circuits shall be accommodated in separate modules.

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(f) EI Rack Layout

This layout contains drawing of front, rear and side views of EI Rack showing locations of DC-
DC Converters (Main & Standby), fuses, terminals, Fan trays, deflector arrangements, Vital &
Non-Vital Input/Output modules, Processor & Power Supply modules and spare slots. Terminal
details for connections of housings with converters and to the external equipments are also
shown in this layout. Fuse details are shown in the layout to help the user in navigating them
easily.

(g) Relay Rack Layout

This layout shows the front view of Relay Rack with distribution of various relays, fuses,
terminals and spares. Termination details of rely rack to EI rack and CT rack are provided.

(h) Wiring diagrams

This will cover:
 Power Distribution SM Room (VDU, CCIP, Ethernet Switch, Block)
 Power Distribution Relay Room (EI Housing, Ethernet Switch, Data Logger, Diagnostic
Terminal)
 EI Housing Power Supply Arrangement
 Data cable wiring
 Other wiring details specific to the EI installation.

(i) Circuit drawings

The external circuits like signal lighting, Point control & detection, Level crossing Gate
operation, siding control, block circuits etc. will be as per practice of zonal railways.
The detailed drawings for following circuits are covered in the interface design:
 Vital output Board Circuits (HR, DR, HHR, NWR, RWR, TPR, CHYR, SYSON etc.)
 Vital Input Board Circuits (HECR, DECR, RECR, UECR, NWKR, RWKR, CHKLNR,
SM_KEY etc.)
 Non-Vital Output Circuits (if required)
 Non-Vital Input Circuits (if required)
 Signal Lighting & Repeater Circuits
 Point Control Circuits
 Crank Handle Control Circuits

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 Emergency Crank Handle Circuits

 Level Crossing Gate Control Circuits
 Block Instrument/BPAC Circuits
 DC-DC Converter Monitoring Circuits
 Track Proving/Axle Counter Relay Circuits
 Data Logger Digital Input Circuits
 Data Logger Analog Input Circuits
 Any other circuits for equipments interfaced with EI

(j) System configuration

The system configuration is designed specific to the station depending upon the requirements. A
sample diagram for system configuration of EI is given in Error! Reference source not found..
egends are provided for type of communication in different colours.

Figure 8 : Typical System Configuration of an EI Installation

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The VDU is kept in SM Room as an operator console. In Relay Room the EI hardware is
installed along with other equipments such as Diagnostic module (Maintainer Terminal) and
Data logger. In the EI system shown above there are two processor modules in hot standby
mode. The Processor communicates with the diagnostic module, data logger and VDU through
manageable Ethernet switch connections. Relay Room to SM Room communication is done
through Optic Fibre Communucation cable which is connected through Fibre Termination Box
(FTB).

(k) Fuse & Terminal details

This covers details and location of bus bars, terminals, fuses of Relay Rack and EI Housing Sub
Racks and their functions.

(l) Relay Contact Analysis

This contains details of contacts of relays used along with mention of circuit where these are
used along with circuit sheet number.

(m) Relay Configuration

This contains details of types of relays used along with contact configuration for example type
QN1 Relay with contact configuration 8F/8B.

In the following sections assessment of Vital and Non-Vital Inputs /Outputs, Relays, Relay
Racks and Module requirements of already commissioned stations with EI are explained along
with hyperlink to detailed Interface circuits of concerned vendor.

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Section II
Interface Design for
Siemens WESTRACE VLM6 EI
2.1 Introduction
In this section the assessment of Vital & Non-Vital Input/Output bits, Relays, Relay Racks, Vital
Input/Output modules and housings for SINGRA station of North East Frontier Railway
commissioned with Siemens WESTRACE VLM6 EI is explained. In this station both VDU and
CCIP are provided for operation. The mini Signalling plan layout given in Fig. is for the purpose
of understanding which is based on approved SIP.

2.2 Details of Signalling assets

List of Signalling Gears

A. Signals

UD UP Distant
S2 DN Advance Starter -2 Aspect
S3 UP Home -3 Aspect with Route Indicator
C3 UP Calling On
SH7 UP Shunt (to L1 & L2)
S35 UP Line 2 Starter – 2 Aspect
SH35 UP Line 2 Shunt (to S47)
S37 UP Line 1 Starter – 2Aspect
SH37 UP Line 1 Shunt (to S47)
S12 DN Line 2 Starter -2 Aspect
SH12 DN Shunt (to S2)
S14 DN Line 1 Starter – 2 Aspect
SH14 DN Line 1 Shunt (to S2)
S47 UP Advance Starter – 2 Aspect
S46 DN Home – 3 Aspect with Route Indicator
C46 DN Calling On
SH44 DN Shunt (to L1 & L2)
DD DN Distant

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Figure 9: Signalling Plan of SINGRA Station (North East Frontier Railway)
(Based on Approved SIP)
DN UP
DPRA
BOKO
UD C3 S3 SH35 S35 S47
A SH7

B
C 111T
C3T 3T 101T 0A1T 0A2T 47AT 46T C46T
2AT
101 111
B

A
S2 SH44 C DD
S12 SH12 SH37 S37 S46 C46

102
0C1T 0C2T 112
102T
112T

S14 SH14
Note: Block Proving by Axle Counter (BPAC) in SNGA –DPRA and SNGA-BOKO sections with Single Line tokenless Block
instruments

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B. Points

101/102 Motor operated

111/112 Motor operated

C. Track Circuits
C3T, 3T, 2AT, 101T, 0A1T, 0A2T, 111T, 47AT, 46T, C46T, 102T, 0C1T, 0C2T, 112T

D. Crank handle groups

CH Zone 1 for points 101/102
CH Zone 2 for points 111/112

2.3 Assessment of Vital Input /Output bits & Relays

Based on the list of Signaling assets, the assessment of Vital Inputs /Outputs and requirement of
various types of relays is tabulated below:
Table 4 : Vital Input/Output bits & Relays of SNGA station with WESTRACE VLM6 EI

Gear Vital Vital Input Vital Relays

Output Output QN1 QEC QNA1 QNN QSPA1
Read back (50 V) X61 (24 V) A1 (24 V)
Signals
UD UD DR, UD DECR, 2 3
UD HHR UD HHECR,
UD HECR
S2 S2 DR S2 DECR 1 2
S2 RECR
S3 S3 DR, S3 DECR, 3 4
S3 HR, S3 HECR,
S3C UHR S3 RECR,
S3 UECR
C3 C3 HR C3 HECR 1 1

SH7 SH7 HR SH7 COM 1 1

ECR*
S35 S35 DR S35 DECR, 1 2
S35 RECR
SH35 SH35 HR SH35 1 1
COMECR*,
S37 S37 HR S37 HECR, 1 2
S37 RECR
SH37 SH37 HR SH37 COM 1 1
ECR*
S12 S12 DR S12 DECR, 1 2

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Gear Vital Vital Input Vital Relays

Output Output QN1 QEC QNA1 QNN QSPA1
Read back (50 V) X61 (24 V) A1 (24 V)
S12 RECR
SH12 SH12 HR SH12 COM 1 1
ECR
S14 S14 HR S14 HECR, 1 2
S14 RECR
SH14 SH14 HR SH14 COM 1 1
ECR*
S47 S47 DR S47 DECR, 1 2
S47 RECR
S46 S46 DR, S46 DECR, 3 4
S46 HR, S46 HECR,
S46 UHR S46 RECR,
S46 UECR
C46 C46 HR C46 HECR 1 1
SH44 SH44 HR SH44 1 1
COMECR*
DD DD DR, DD DECR, 2 3
DD HHR DD HHECR,
DD HECR
Points
Point 101/102 101/102 101/102 3 1
NWR, NWKR,
101/102 101/102
RWR RWKR
101/102
WL1R
Point 111/112 111/112 111/112 3 1
NWR, NWKR,
111/112 111/112
RWR RWKR
111/112
WL1R
Track Circuits
C3T C3TPR 1
3T 3TPR 1
2AT 2ATPR 1
101T 101TPR 1
0A1T 0A1TPR 1
0A2T 0A2TPR 1
111T 111TPR 1
47AT 47ATPR 1
46T 46TPR 1
C46T C46TPR 1
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Gear Vital Vital Input Vital Relays

Output Output QN1 QEC QNA1 QNN QSPA1
Read back (50 V) X61 (24 V) A1 (24 V)
102T 102TPR 1
0C1T 0C1TPR 1
0C2T 0C2TPR 1
112T 112TPR 1
Crank Handle
CH1 CH1YR CH1 INPR CH1 YR_F, 1 1
CH2 YR_F
CH2 CH2 YR CH2 INPR 1 1
Emergency ECHRKEY 1
Crank Handle CR
Block Instrument
DN Block DN TAR SNGA- DN TAR_F, 3 2 (S2
DPRA side UP SAR DPRA VPR DN SNR_F, GR
(SL Tokenless DN ASR SNGA- DN ASR paired
type) TPR DPRA PPR TPR_F with
S2 GR CH1
INPR)
UP Block UP TAR, SNGA- UP TAR_F, 3 2
BOKO side DN SAR BOKO VPR UP SNR_F, (S47
(SL Tokenless UP ASR SNGA- UP ASR GR
type) TPR BOKO PPR TPR_F paired
S47 GR with
CH2
INPR)
EI System
System SYSAON
SYSBON
SM Key SM_KEY 1
RRBU Key RRBU_KEY
Total 38 65 38 34 -- 6 14

* As per latest RDSO Report on Standardization Typical Circuits for EI Ver.2.0 dated
29.03.2022:

In case of Independent Shunt Signal, a common GECR is to be picked up means that Pilot Lamp
along with „OFF‟ or „ON‟ is litting at site. However two Inputs ( ‘ON’ ECR & ‘OFF’ ECR) are
to be considered for Interface.

For Dependent Shunt Signal, only one Input (‘OFF’ ECR) is to be considered.

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Table 5 : Additional Relays required for SNGA station

Gear Relay Nomenclature Type Total

Crank Handle ECHR_CR, ECHR_CPR QN1 (50 V) QN1 (50 V) - 7
ECH_JR, ECH_JSLR QNNA1 QNNA1 – 1
ECHTIMER Electronic Timer Electronic Timer -1
System W(A)-OPCR QN1 (50 V)
W(B)-OPCR QN1 (50 V)
W(A)-OPCR1 QN1 (50 V)
W(B)-OPCR1 QN1 (50 V)
W(A)-OPCR2 QN1 (50 V)
W(B)-OPCR2 QN1 (50 V)

2.4 Assessment of Non-Vital Input/Output bits

As CCIP along with VDU is also provided in this EI installation, assessment of Non-Vital Input
& Output bits is required.

Table 6 : Non-Vital Input/Output bits for SNGA station with WESTRACE VLM6 EI

Gear Non –Vital Input Non-Vital Output

UD UD DGKE,UD HHGKE,UD HGKE
C3 C3 COHGKE
S3 S1 GN S3 DGKE,S3 HGKE, S3 RGKE,
S3 UGKE
SH7 SH7 GN SH7 ONKE, SH7 OFFKE
SH35 SH35 GN SH35 OFFKE
S35 S35 GN S35 DGKE, S35 RGKE
SH37 SH37 GN SH37 OFFKE
S37 S37 GN S37 HGKE, S37 RGKE
S47 S47 GN S47 DGKE, S47 RGKE
DD DD DGKE, DD HHGKE,
DD HGKE
C46 C46 COHGKE
S46 S46 GN S46 DGKE, S46 HGKE, S46 RGKE, S46 UGKE
SH44 SH44 GN SH44 ONKE, SH44 OFFKE
SH12 SH12 GN SH12 OFFKE
S12 S12 GN S12 DGKE, S12 RGKE
SH14 SH14 GN SH14 OFFKE
S14 S14 GN S14 HGKE, S14 RGKE
S2 S2 GN S2 DGKE, S2 RGKE
Point 101/102 101/102WN (1)101 NWKE
(2)101 NWKRE
(3)101 RWKE
(4)101 RWKRE
(5)102 NWKE
(6)102 NWKRE

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Gear Non –Vital Input Non-Vital Output

(7)102 RWKE
(8)102 RWKRE
(9)101 WLKE
(10)102 WLKE (Refer Figure 11)
Point 111 111/112WN (1)111 NWKE
(2)111 NWKRE
(3)111 RWKE
(4)111 RWKRE
(5)112 NWKE
(6)112 NWKRE
(7)112 RWKE
(8)112 RWKRE
(9)111 WLKE
(10)112 WLKE (Refer Figure 10)
CH1 CH1 YN CH1FKE,CH1_INKE, CH1_OUTKE
CH2 CH2 YN CH2FKE,CH2_INKE, CH2_OUTKE
C3T C3TKE, C3TKRE
3T 3TKE, 3TKRE
2AT 2ATKE, 2ATKRE
101T 101TKE, 101TKRE
0A1T 0A1TKE, 0A1TKRE
0A2T 0A2TKE, 0A2TKRE
111T 111TKE, 111TKRE
47AT 47ATKE, 47ATKRE
46T 46TKE, 46TKRE
46AT C46ATKE, C46ATKRE
112T 112TKE, 112TKRE
0C1T 0C1TKE, 0C1TKRE
0C2T 0C2TKE, 0C2TKRE
102T 102TKE, 102TKRE
Emergency Crank ECHRKEY_KLN ECHRE
Handle
Route Buttons DM,OA,OC1,OC2,
NN,PP,UM
Common Points GBP
Button
Signal Cancel Button ERRB
Route Cancel Buttons EGBS, RRBU,
Group Calling On COGGN, COCAN. COGGKE,COCANKE
Buttons
Slot Buttons GSBN, GSRBN
Other Buttons GXYN,WXYN,NN GNCKE,WNCKE,UNCKE,
CYN,POWER, PWRFLKE
ACK,

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Gear Non –Vital Input Non-Vital Output

SM Key SMKEY_INKE
.
Panel –PC Key PANEL_PCKEY. PANELKE, PCKE
Counters EMCH1CNT, EMCH2CNT, COGGNCNT,
RRBUCNT, ERRBCNT,EBPUCNT
Overlap Indication OV3AKE, OV3BKE, OV3CKE, OV46AKE,
OV46BKE, OV46CKE
System Indication SYSA_H, SYSA_F,
SYSB_H, SYSB_F,
SYSFAILBUZ.
Flasher FLASH_KE
Timer AJ_KE
Total 40 117

Figure 11 : Indications of Point 101/102 on Figure 10 : Indications of Point 111/112 on CCIP

CCIP

Table 7 : Summary of Input/Output bits & Relays (SNGA)

(i) Total No. of Vital Outputs 38

(ii) Total No. of Vital Inputs 65
(iii) Total No. of Non-Vital Outputs 117
(iv) Total No. of Non-Vital Inputs 40
(v) Total No. of Relays =101 QN1 (50 V) - 45
QCEX61 - 34
QNNA1 -7
QSPA1 - 14
Electronic Timer -1

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2.5 Calculation of Vital Input & Output Modules

Capacity of Vital Output Module (VROM) in WESTRACE VLM6 – 8 Vital Outputs per module

Capacity of Vital Input Module (VPIM) in WESTRACE VLM6 – 12 Vital Inputs per module

No. of VROMs required = (Total no. of Vital Output bits + 15% spare bits) divided by (capacity
of one VROM)

= (38+8) /8

= 46/8

= 5.75

~ 6

No. of VPIMs required = (Total no. of Vital Input bits + 15% spare bits) divided by (capacity of
one VPIM)

= (65 + 10) /12

= 75 /12

= 6.25

~ 7

2.6 Assessment of Housings for accommodation of Vital Input & Output Modules
Various modules are installed in one or more WESTRACE housings as per the following
guidelines:
(1) There are four housings in a WESTRACE rack.
(2) Each housing has 16 slots.
(3) Numbering of slots is from Right to Left.
(4) Numbering of housings is from Top to Bottom.
(5) First slot in first housing should be blank. A Blanker card is provided for continuity.
(6) There will be Output Power Control (OPC) card in second slot, Vital Logic Module
(VLM) in third slot and Network Communication & Diagnostic Module (NCDM) in
fourth slot. VLM and OPC together form VLM6.

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(7) Slot 5 to 15 in the first housing can be Vital Parallel Input Module (VPIM) or Vital Relay
Output Module (VROM).
(8) Each VPIM and VROM occupies two slots.
(9) There will be no NCDM, VLM or OPC in second, third and fourth housings.
(10) Each housing has a slot reserved for PSU card.
(11) Normally one PSU card caters power supply requirements for two housings. However for
better system availability, one PSU card per housing is desirable.
Based on the above guidelines the arrangement of various modules in WESTRACE VLM6
housing can be as given below:

Slot 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
number
Blanker Card

Blanker Card
NCDM Card
Housing 1

VLM6 Card

OPC Card
PSU Card

VROM5 VROM4 VROM3 VROM2 VROM1

Blanker Card

Blanker Card

Blanker Card

Blanker Card
Housing 2

VPIM6 VPIM5 VPIM4 VPIM3 VPIM2 VPIM1

Blanker Card

Blanker Card

Blanker Card

Blanker Card

Blanker Card

Blanker Card

Blanker Card

Blanker Card

Blanker Card

Blanker Card

Blanker Card
Housing 3

PSU Card

VPIM VROM
7 6

Figure 12 : Arrangement of Modules in SNGA WESTRACE VLM6 Housings

Thus 6 Vital Output Modules (VROMs), 7 Vital Input Modules (VPIMs), 2 PSU Cards, NCDM
Card, VLM6 Card and OPC Card are accommodated in 3 housings as above.

2.7 Preparation of Bit Chart

The Bit Chart for each housing based upon the calculations done as above is given in following
pages:

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Table 8 : Bit Chart for SNGA WESTRACE VLM6 Housing 1

WESTRACE HOUSING 1
VROM5 VROM4 VROM3 VROM2 VROM1
Slot No. 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Bit 1 SH44_HR 111.112_WL1R DNTAR SH7_HR 101.102_WL1R
Bit 2 Blanker Card S37_HR DD_DR DNASR_TPR S12_DR UD_DR

Blanker Card
NCDM Card

VLM6 Card
Bit 3 SH37_HR DD_HHR DNSAR SH12_HR UD_HHR

OPC Card
PSU Card

Bit 4 S35_DR S46_DR CH1_YR S14_HR S3_DR

Bit 5 SH35_HR S46_HR SPARE SH14_HR S3_HR
Bit 6 111.112_NWR S46C_UHR SPARE 101.102_NWR C3_HR
Bit 7 111.112_RWR C46_HR SPARE 101.102_RWR S3C_UHR
Bit 8 CH2_YR S47_DR SPARE SPARE S2_DR

Table 9 : Bit Chart for SNGA WESTRACE VLM6 Housing 2

WESTRACE HOUSING 2
VPIM6 VPIM5 VPIM4 VPIM3 VPIM2 VPIM1
Slot No. 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Bit 1 C46_TPR S47_GR 111.112_NWK1R C3_TPR S2_GR 101.102_NWK1R
Bit 2 46_TPR SH44_COMECR 111.112_RWK1R 3_TPR SH7_COMECR 101.102_RWK1R
Bit 3 47A_TPR S37_HECR DD_DECR 2A_TPR S12_DECR UD_DECR
Bit 4 111_TPR S37_RECR DD_HHECR 101_TPR S12_RECR UD_HHECR
Blanker Card

Blanker Card

Blanker Card

Bit 5 112_TPR SH37_COMECR DD_HECR 102_TPR SH12_COMECR UD_HECCR

Bit 6 OA1_TPR S35_DECR S46_DECR DPRA_SNGA_VPR S14_HECR S3-DECR
Bit 7 OC1_TPR S35_RECR S46_HECR DPRA_SNGA_PPR S14_RECR S3_HECR
Bit 8 OA2_TPR SH35_COMECR S46_RECR CH1_F SH14_COMECR S3_RECR
Blanker Card

Bit 9 OC2_TPR CH2_INPR S46_UECR DNTAR_F CH1_INPR S3_UECR

Bit 10 SPARE SPARE C46_HECR DNASR_TPR_F SYSA_ON C3_HECR
Bit 11 SPARE SPARE S47_DECR DNSNR_F SYSB_ON S2-DECR
Bit 12 SPARE SPARE S47_RECR SPARE SPARE S2_RECR

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Table 10 : Bit Chart for SNGA WESTRACE VLM6 Housing 3

WESTRACE HOUSING 3
VPIM 7 VROM 6
Slot No. 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Bit 1 SNGA_BOKO_VPR UPTAR
Bit 2 SNGA_BOKO_PPR UPASR_TPR

Bit 3 CH2_F UPSAR

Bit 4 UPTAR_F SPARE

Bit 5 UPASR_TPR_F SPARE
Blanker Card

Blanker Card

Blanker Card

Blanker Card

Blanker Card

Blanker Card

Blanker Card

Blanker Card

Blanker Card

Blanker Card
Blanker Card
PSU Card

Bit 6 UPSNR_F SPARE

Bit 7 ECHRKEY_CR SPARE
Bit 8 RRBUKEY SPARE
Bit 9 SMKEY
Bit 10 SPARE
Bit 11 SPARE
Bit 12 SPARE

For details please refer SINGRA WESTRACE Interface Circuits through Annexure I.

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2.8 Calculation of Non-Vital Input & Output Modules

The Non-Vital Input & Output Modules for WESTRACE VLM6 are housed in S2
WESTRONICS Panel Processor. The S2 WESTRONICS Panel Processor is the interface
between hard wired Control cum Indication Panel (CCIP) and the WESTRACE. It consists of
following modules:

Power Supply Unit

There are two Power Supply Unit (PSU) Cards provided in slot 1 of first housing and both are
connected in parallel. Each PSU Card consists of an ON/OFF switch. Input voltage to the PSU
i.e. 24 VDC is shown by LED Steady Green. It gives 12 V DC also shown by Green LED on the
front plate for working of various cards – scanners, DIP and DOP cards

Scanner A and Scanner B

Two scanners named Scanner A and Scanner B are fitted in the first housing which has a
motherboard MBD45. Scanner A is online while Scanner B is standby. There is an alphanumeric
indicator on the front plate which gives transmitter receiver condition and Telemetry indications
which are normally flashing on both scanners indicting that the bits are being transmitted and
received between WESTRACE and S2 and the system is healthy.

Figure 14 : Front view of Figure 13 : Front Panel

WESTRONICS S2 Panel Processor Indications of DIP/DOP Card

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DIP Card
DIP stands for Digital Input Card. Each DIP card caters for 32 inputs and numbers of cards are
provided depending upon the requirement. A DIP Card takes input from panel and connects to
the scanner which in turn sends it to WESTRACE. Thus the output bit of any button pressed on
the operating panel will go through DIP Card. Two indicators ACK A and ACK B are provided
on the front plate. Flashing Red shows healthy communication with the scanner. 32 LEDs (Red)
are provided on the DIP card in which each LED when lit indicates receiving bit from the panel.

DOP Card
DOP stands for Digital Output Card. Each DOP card caters for 32 outputs and numbers of cards
are provided depending upon the requirement. Indication received from WESTRACE in the
scanner is given to DOP card which in turn delivers the 24 V DC output to the LEDs in the
panel. ACK A and ACK B LED indications flashing indicate healthy communication with the
scanners. 32 LEDs (Red) are also provided in which each LED when lit indicates received bits
from WESTRACE.
Capacity of Digital Input (DIP) Card in WESTRACE VLM6 – 32 Non-Vital Inputs per card

Capacity of Digital Output (DOP) Card in WESTRACE VLM6 – 32 Non-Vital Outputs per card
No. of DIP Cards required = (Total no. of Non-Vital Input bits + 15% spare bits) divided by
(capacity of one DIP Card)

= (40+6) /32

= 46/32

= 1.43

~ 2

No. of DOP Cards required = (Total no. of Non-Vital Output bits + 15% spare bits) divided by
(capacity of one DOP Card)

= (117+18) /32

= 46/32

= 4.21

~ 5

Bit chart for Non-Vital Inputs & Outputs can be prepared similar to given in para 2.7.

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2.9 Calculation of Relay Racks

Capacity of one Standard Relay Rack = 90 relays

Total no. of relays = 101

No. of Relay racks required = (Total no. of Relays + 15% spare) divided by (Capacity of one
Relay Rack)

= (101+16)/90

= 117/90

= 1.3

~ 2

Hence relays can be accommodated in 2 Relay Racks.

The detailed Interface Circuits (as built) may be seen through the link provided in Annexure I.

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Section III
Interface Design for
Siemens WESTRACE Mark II EI
3.1 Introduction
In this section the assessment of Vital Input/Output bits, Relays, Relay Racks, Vital Input/Output
modules and housings for HAYAGHAT station of East Central Railway commissioned with
Siemens WESTRACE Mark II EI are explained. Non-Vital Inputs/Outputs are not considered as
only VDU is used as control panel (no CCIP is used) for which the bits are catered internally in
Mark II system. The mini Signalling plan layout is given for the purpose of understanding which
is based on approved SIP.

3.2 Details of Signalling Assets

HAYAGHAT Station (East Central Railway)
List of Signalling Gears

E. Signals

DD DN Distant
S1 DN Home -3 Aspect
S2 UP Advance Starter -2 Aspect
C3 DN Calling On
S4 UP Line 1 Starter -2 Aspect
S5 DN Line 1 Starter – 2 Aspect
S6 UP Line 2 Starter – 2 Aspect
S7 DN Line 2 Starter – 2Aspect
C10 UP Calling On
S11 DN Advance Starter – 2 Aspect
S12 UP Home – 3 Aspect
UD UP Distant

F. Points

21a/21b Motor operated

22a/22b Motor operated

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Figure 15 : Signalling Plan of HAYAGHAT Station (East Central Railway)

(Based on Approved SIP)
DN UP
RBZ L-Xing No. TLWA
11 B
UD C10 S12 S4 S2
A

B
B A1T A2T
A10T 12T 22T AT 1T A3T
A11T
22a 21a
B

A
S11 S5 B DD
S6 S1 C3

22b
B1T BT 21b
21bT
22bT

S7

L-Xing No.
11 B

NOTE
 Proving of clearance of berthing portion of Line no. 2 through HASSDAC in addition to
berthing track circuit no. B1T & BT.
 UFSBI Block Panel with HASSDAC single line type working between HYT-RBZ stations.
 Single line block working with Diado type tokenless Block instrument between HYT-
TLWA stations.
 Sliding boom barrier provided in addition to existing Lifting Barrier at LC Gate No. 11B.
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G. Track Circuits
A10T, 12T, A11T, 22T, A1T, AT, 21T, A2T, 1T, A3T, 22bT, B1T, BT, 21bT

H. Crank handle groups

Zone 1 CH for points 21a & 21b
Zone 2 CH for points 22a & 22b

I. Level Crossing Gate

LC Gate no. 11 B Electro-Mechanical

3.3 Assessment of Vital Input/Output bits & Relays

Based on the list of signalling assets, the assessment of Vital Inputs /Outputs and requirement of
various types of relays is tabulated below:
Table 11: Vital Input/Output bits & Relays of HYT station with WESTRACE Mark II EI

Gear Vital Vital Input Vital Relays

Output Output QN1 QECX61 QNA1 QL1 QSPA1
Read (50 V) (24 V) (24 V) (24 V)
back
Signals
DD DD DR, DD DECR, 2 3
DD HHR DD HHECR,
DD HECR
C3 C3 HR C3 ECR 1 1
S1 S1 DR, S1 DECR, 3 4
S1 HR, S1 HECR,
S1B UHR S1 RECR,
S1 UECR
S2 S2 DR S2 DECR, 1 2
S2 RECR
S4 S4 DR S4 DECR, 1 2
S4 RECR
S5 S5 DR S5 DECR, 1 2
S5 RECR
S6 S6 HR S6 HECR, 1 2
S6 RECR
S7 S7 HR S7 HECR, 1 2
S7 RECR
C10 C10 HR C10 ECR 1 1
S11 S11 DR S11 DECR, 1 2
S11 RECR
S12 S12 DR, S12 DECR, 3 4
S12 HR, S12 HECR,
S12B S12 RECR,
UHR S12 UECR

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Gear Vital Vital Input Vital Relays

Output Output QN1 QECX61 QNA1 QL1 QSPA1
Read (50 V) (24 V) (24 V) (24 V)
back
UD UD DR, UD DECR, 2 3
UD HHR UD HHECR,
UD HECR
Points
Point 21 21 NWR, 21 NWKR, 21W_F 2 2
21 RWR 21 RWKR
Point 22 22 NWR, 22 NWKR, 22W_F 2 2
22 RWR 22 RWKR
Track Circuits
A10T A10TPR 1
12T 12TPR 1
A11T A11TPR 1
22T 22TPR 1
A1T A1TPR 1
AT ATPR 1
21T 21TPR 1
A2T A2TPR 1
1T 1TPR 1
A3T A3TPR 1
22BT 22BTPR 1
B1T B1TPR 1
BT BTPR 1
21BT 21BTPR 1
Line 2 L2 AXCPR 1
HASSDAC
Level Crossing Gate
LC Gate 11 11 XRPR 11 KLNR 11 1 1
XRPR_F
Crank Handle
CH1 CH1YR CH1 KNLR CH1 1 1
YR_F,
CH2
YR_F
CH2 CH2 YR CH2 KNLR 1 1
Emergency ECH_PR, 2
Crank Handle ECHRBPR
Block Instrument
DN Block S11 LR, 11 ASDR S11 2 2
RBZ side 12.C10ZR HYT-RBZ LR_F,
(UFSBI Block VPR 12.C10Z
Panel) ZR_F

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Gear Vital Vital Input Vital Relays

Output Output QN1 QECX61 QNA1 QL1 QSPA1
Read (50 V) (24 V) (24 V) (24 V)
back
UP Block 1 TAR, 2ASR , 1TAR_F, 2 2
TLWA side 2 SNR HYT-TLWA 2SNR_F
(Diado type) VPR
EI System
System SYSON, 2
VDU_FAI
LKE
SM Key SM_KEY1, 2
SM_KEY2
Relay Room RRCLOSE 1
Door Switch
DC DC Converter Monitoring Circuits
Ethernet SW_A_OK 2
Switch SW_B_OK
50 V DC 50V_DC_OK 1
24 V DC 24V_DC_OK 1
SMR A SMR_A_OK 1
SMR B SMR_B_OK 1
IPS Main IPSMAINOK 1
Supply
Total 31 66 27 28 23 4 15

Table 12 : Additional Relays required for HYT station

Gear Relay Nomenclature Type

Signal 1_OFFECPR, DECPR, 12_OFFECPR, 12DECPR, QNA1 (24 V) – 6 Nos.
12RECPR, 11RECPR
Point 21NWP1R, 21RWP1R,22NWP1R,22RWP1R QN1 (50 V) - 4 Nos.
21ANWPR, 21BNWPR, 21ARWPR, 21BRWPR, QBCA1 – 8 Nos.
22ANWPR, 22BNWPR,22ARWPR,22BRWPR
21WJR,21ANWKR,21BNWKR,21ARWKR,21BRWKR,22 QNA1 (24 V) – 10 Nos.
WJR,22ANWKR,22BNWKR,22ARWKR,22BRWKR
Track Circuit 12TPR1, A10TPR1 QNA1 (24 V) – 2 Nos.
Crank Handle ECHR_CR, ECHGR, ECH_JR, ECH_JSLR, QNA1 (24 V) – 10 Nos.
ECH_SMKEY, EKTPR, ECH_CPR, ECH_CPR1, FR1,
FR2
ECHTIMER Electronic Timer – 1 No.
Block HYT_TLWA_VPR1, HYT_TLWA_PPR1, QNA1 (24 V) – 8 Nos.
HYT_TLWA_VPR2, HYT_TLWA_PPR2,
HYT_RBZ_VPR1, HYT_RBZ_PPR1, HYT_RBZ_VPR2,
HYT_RBZ_PPR2

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Table 13 : Summary of Input/Output bits & Relays

(vi) Total No. of Vital Outputs 31
(vii) Total No. of Vital Inputs 66
(viii) Total No. of Relays =146 QN1 (50 V) - 31
QNA1 (24 V) - 59
QCEX61 - 28
QL1(24 V) - 4
QBCA1 - 8
QSPA1 - 15
Electronic Timer -1

3.4 Calculation of Vital Input & Output Modules

Capacity of Vital Output Module (ROM) in WESTRACE Mark II – 8 Vital Outputs per module

Capacity of Vital Input Module (PIM) in WESTRACE Mark II – 12 Vital Inputs per module

No. of ROMs required = (Total no. of Vital Output bits + 15% spare bits) divided by (capacity of
one ROM)

= (31+5) /8

= 36/8

= 4.5

~ 5

No. of PIMs required = (Total no. of Vital Input bits + 15% spare bits) divided by (capacity of
one PIM)

= (66 + 10) /12

= 76 /12

= 6.34

~ 7

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3.5 Assessment of Housings for accommodation of Vital Input & Output Modules
WESTRACE Mark II housings are available in following configurations:
5-slot (a half 19" width) housing that holds 5 modules maximum - Processor Module, I/O
Modules & Hot standby Modules (if provided)
10-slot (a full 19" width) housing that holds 10 modules maximum - Processor Module (PM),
I/O Modules & Hot standby Modules (if provided)
A PM is normally placed in slot 1 of housing 1.
Hot-standby PMs are normally placed in slots 1 and 2 of housing 1 or slot 1 in each of two co-
located housings.
The other modules are Parallel Input Module (PIM) and Relay Output Module (ROM). Both
PIM and ROM can be duplicated for Hot Standby operation.
The arrangement of various modules in a 10 slot housing based on the assessment of Vital Input
and Output modules is given below:
Slot
10 9 8 7 6 5 4 3 2 1
No.
Housing 1

SPARE

SPARE
ROM ROM ROM ROM ROM ROM PM PM
7 6 5 4 2 1 2 1
Housing 2

SPARE

SPARE

SPARE

PIM PIM PIM PIM PIM PIM PIM

7 6 5 4 3 2 1

Figure 16 : Arrangement of Modules in HYT WESTRACE Mark II Housings

Thus 2 PMs in Hot Standby mode, 5 ROMs and 7 PIMs are accommodated in 2 Nos. 10 slot
housings.

3.6 Preparation of Bit Chart

The bit chart prepared on the basis of Vital Input and Output bits is given on following pages

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Table 14 : Bit Chart for HYT WESTRACE Mark II Housing 1

WESTRACE Mark II HOUSING 1
ROM5 ROM4 ROM3 ROM2 ROM1
Slot No. 10 9 8 7 6 5 4 3 2 1
Bit 1 12_HR 1B_UHR C3_HR DD_HHR DD_DR
Bit 2 UD_HHR 11_DR 6_HR 1_HR 1_DR
Bit 3 11_LR 12_DR 7_HR 5_DR 2_DR
Bit 4 12.C10_ZR UD_DR 12B_UHR C10_HR 4_DR
SPARE SPARE SPARE PM2 PM1
Bit 5 SPARE SYSON CH1_ZYR 11_LXRPR 1_TAR
Bit 6 SPARE VDU_FAILKE CH2_ZYR 21_RWP1R 2_SNR
Bit 7 SPARE SPARE SPARE 22_RWP1R 21_NWP1R
Bit 8 SPARE SPARE SPARE SPARE 22_NWP1R

Table 15 : Bit Chart for HYT WESTRACE Mark II Housing 2

WESTRACE Mark II HOUSING 2
PIM7 PIM6 PIM5 PIM4 PIM3 PIM2 PIM1
Slot 10 9 8 7 6 5 4 3 2 1
No.
Bit 1 1_UHECR 12_DECR 11_DECR 12_UHECR 2_DECR 1_DECR DD_DECR
Bit 2 UD_DECR 12_HECR 11_RECR 6_HECR 2_RECR 1_HECR DD_HHECR
Bit 3 UD_HHECR 12_RECR 11_ASDR 6_RECR 4_DECR 1_RECR DD_HECR
Bit 4 UD_HECR SW_A_OK HYT_RBZ_VPR 7_HECR 4_RECR 2_ASR C10_ECR
Bit 5 SW_B_OK IPSMAINOK ECHRBPR 7_RECR 5_DECR 21_RWK1R 21_NWK1R
Bit 6 50V_DC_OK RRCLOSE ECH_PR 21B_TPR 5_RECR 22_RWK1R 22_NWK1R
SPARE SPARE SPARE
Bit 7 SMR_B_OK 24V_DC_OK A1_TPR A_TPR C3_ECR CH1_KNLR 11_KNLR
Bit 8 A10_TPR SMR_A_OK B1_TPR B_TPR HYT_TLWA_VPR CH2_KNLR A3_TPR
Bit 9 12_TPR L2_AXCPR 22_TPR SPARE A2_TPR 1TAR_F 1_TPR
Bit 10 SPARE 22B_TPR 11_LR_F SPARE 21_TPR 11_LXRPR_F CH1_F
Bit 11 SPARE A11_TPR 12.C10ZR_F SPARE 2_SNR_F 22W_F 21W_F
Bit 12 SPARE SPARE SPARE SM_KEY1 CH2_F SPARE SPARE

Interface Design of Electronic Interlocking Installation December 2022

 CAMTECH/S&T/2022-23/ID-EI/1.0 51

3.7 Calculation of Relay Racks

Capacity of one Standard Relay Rack = 90 relays

Total no. of relays = 146

No. of Relay racks required = (Total no. of Relays + 15% spare) divided by (Capacity of one
Relay Rack)

= (146+22)/90

= 168/90

= 1.87

~ 2

Hence relays can be accommodated in 2 Relay Racks.

The detailed Interface Circuits (as built) may be seen through the link provided in Annexure I.



Interface Design of Electronic Interlocking Installation December 2022

CAMTECH/S&T/2022-23/ID-EI/1.0 52

 

Interface Design of Electronic Interlocking Installation December 2022

CAMTECH/S&T/2022-23/ID-EI/1.0 53

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ANNEXURE I
Interface Circuits documentation of stations
commissioned with Electronic Interlocking

Interface Design of Electronic Interlocking Installation December 2022

 CAMTECH/S&T/2022-23/ID-EI/1.0 54

Sr. Subject Hyperlink

No.
1 RDSO Report on Standardization of the https://drive.google.com/drive/folders/15xnXZ
Typical Circuits for Electronic Interlocking BkTqOsDuFGCgixKnlkTpqcDp1n7?usp=shar
Ver. 2.0 dated 29.03.2022. e_link

2 Interface Circuits for SINGRA Station https://drive.google.com/drive/folders/1J-

(North East Frontier Railway) commissioned PCS79jt-
with WESTRACE VLM6 EI wFn0Xnj0_0s06rJ2iDMozE?usp=share_link

3 Interface Circuits for MIRCHADHURI https://drive.google.com/drive/folders/1qJaqar

Station (East Central Railway) rtvxGCHTi0oZ6QRt__FXYFrAk-
commissioned with WESTRACE VLM6 EI ?usp=share_link

4 Interface Circuits for HAYAGHAT Station https://drive.google.com/drive/folders/1hbBSu

(East Central Railway) commissioned with FWOviaww5XuY4iIZVN3W1qtnRHd?usp=sh
WESTRACE Mark II EI are_link

5 Interface Circuits for BALLRPUR Station https://drive.google.com/drive/folders/18JjkvO

(Eastern Railway) commissioned with nBpU1Vtj2zP_d33NPpnAQ4ZYpu?usp=share
WESTRACE Mark II EI _link

6 Interface Circuits for SADANAPURA https://drive.google.com/drive/folders/1W9xPZ

Station (Western Railway) commissioned aOoAN545o9qbREUaJi5V7312IKT?usp=shar
with Ansaldo (Now Hitachi) Microlok II EI e_link

7 Interface Circuits for RANITAL Station https://drive.google.com/drive/folders/1OXKt1

(South Eastern Railway) commissioned with LhqB5K6kGcIAtILyaW1j9zHJ8gV?usp=shar
Ansaldo (Now Hitachi) Microlok II EI e_link

8 Presentation Slides on Interface Design for https://drive.google.com/drive/folders/1Rqw2

Kyosan K5BMC EI MWuJuVENn8SCsT3kAZ4z9cN9vR73?usp=s
hare_link





Interface Design of Electronic Interlocking Installation December 2022

References
 RDSO Report on Standardization of Typical Circuits for Electronic Interlocking (EI) Ver. 2.0
 IRISET Notes S18 on Electronic Interlocking
 Interface Circuits (as built) for SINGRA Station (North East Frontier Railway)
commissioned with WESTRACE VLM6 EI
 Interface Circuits (as built) for HAYAGHAT Station (East Central Railway) commissioned
with WESTRACE Mark II EI
 Presentation Slides on Interface Design for Kyosan K5BMC EI
 WESTRACE System Overview Manual –M/s Invensys Rail Systems India Pvt. Ltd. (now
Siemens Rail Automation Pvt. Ltd.)
 System Overview Manual Trackguard WESTRACE Mark II – M/s Siemens Rail Automation
 MICROLOK II Functional Description –M/s Union Switch & Signal India
 Maintenance Manual for K5BMC EI –M/s Kyosan India Pvt. Ltd.
 MEI633 System Manual – M/s Medha Servo Drives (P) Ltd.
 INDIAN RAILWAYS
Centre for Advanced Maintenance Technology
Maharajpur, Gwalior (M.P.) Pin Code – 474 005