IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 68, NO.

2, FEBRUARY 2021 545

Recent Advances and Trends in Noise

Shaping SAR ADCs
Gerardo Molina Salgado , Daniel O’Hare , Senior Member, IEEE,
and Ivan O’Connell , Senior Member, IEEE
(Invited Paper)

Abstract—This brief presents an overview of the recent

advances in noise shaping SAR ADCs. It discusses the funda-
mentals behind the noise shaping operation and the two main
implementation topologies. Error feedback and cascaded inte-
grators feedforward topologies are examined. Active and passive
circuit level implementations, with emphasis in deep nanometre
CMOS processes, are discussed along with the associated design
trade-offs. Trends in the area such as multi-stage and cascaded
implementations are also discussed.
Index Terms—Analysis, ADC, design, feedback, feedforward,
linearity, mismatch, noise-shaping, oversampling, thermal-noise,
SAR.

I. I NTRODUCTION
OISE Shaping (NS) Successive-Approximation-
N Register (SAR) Analog-to-Digital Converters (ADC)
combine the power efficiency and area advantages of the SAR
ADC architecture with noise shaping to extend the achievable
resolution beyond the number of bit trials. While the digital
nature of the SAR ADC has benefitted from CMOS scaling, Fig. 1. SAR ADC (a) schematic and (b) signal-flow diagram.
over-sampled Delta-Sigma () ADCs have struggled with
the reducing transistor gain associated with 65 nm CMOS have been published [9], [27]–[30]. These are just some of the
nodes and below [1]. The NS-SAR ADC leverages the best recent advancements in this area.
of both these architectures to realise a new hybrid ADC. This This brief discusses the main contributions made in this
enables its application in ultra-low-power sensor applications area up to the time of publication. It provides an overview of
including edge IoT devices. the recent advancements. This brief categorises the architec-
Since the first silicon implementation by Fredenburg and tures into feedback and feedforward and provides a detailed
Flynn in 2012 [2], the NS-SAR ADC has been gathering explanation of the main circuit limitations and trade-offs of
a lot of research interest with a growing number of publi- both, with an emphasis on deep nanometre CMOS realisations.
cations in recent years [4]–[11], [13]–[22], [27]–[34]. This is The rest of this brief is organised as follows, Section II
primarily driven by the fact that the residue voltage remain- provides fundamental background on the Qe error generation
ing on the Capacitive Digital-to-Analog Converter (CDAC) in SAR ADCs. Sections III and IV shown how the quantisation
within the SAR ADC at the end of conversion is the quanti- error can be used to realise noise shaping in the feedback
sation error, Qe , of the ADC. Simply adding Qe to the next and feedforward topologies, respectively. Section V discuss
input sample realises the long established error feedback mod- the impact of the SAR capacitor matching. Finally, Section VI
ulator with inherent noise shaping. Over the years a number concludes this brief by presenting some hybrid topologies and
of different implementations have been proposed from feed- the future trends.
forward to feedback based architectures, using both active and II. F UNDAMENTALS OF N OISE S HAPING SAR
passive gain stages. More recent cascaded based architectures
Fig. 1. shows the schematic of a binary-weighted, bottom-
Manuscript received November 2, 2020; revised December 9, 2020; plate sampling, SAR ADC. During the sampling phase, s , the
accepted December 16, 2020. Date of publication December 21, 2020; input signal Vin is sampled into the CDAC. In the conversion
date of current version January 29, 2021. This work was supported by phase, the comparator, comp , and SAR controller sequentially
Enterprise Ireland Technology Centers Programme, under Grant TC2015- generate the equivalent digital output Dout by following the
0019. This brief was recommended by Associate Editor E. Bonizzoni.
(Gerardo Molina Salgado and Daniel O’Hare equally contributed to this
successive approximation algorithm [3].
work.) (Corresponding author: Gerardo Molina Salgado.) One extra switching of the CDAC array based on the final
The authors are with the Microelectronic Circuits Centre Ireland, Tyndall comparator decision produces a residue voltage, Vres , at the
National Institute, Cork, T12R5CP Ireland (e-mail: [email protected]; top-plate node that is given by [2]:
[email protected]; [email protected]).
Color versions of one or more figures in this article are available at Vres = Qe + ncomp , (1)
https://doi.org/10.1109/TCSII.2020.3046170.
Digital Object Identifier 10.1109/TCSII.2020.3046170 where ncomp is the input referred noise of the comparator.
1549-7747 
c 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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546 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 68, NO. 2, FEBRUARY 2021

On the other hand, the Signal-Transfer-Function (STF) is

unitary.
From (2) it can be seen that by simply feeding-back the
quantisation error with a negative sign, a high-pass NTF of
the form 1-z−1 is realised. Similarly, L(z) = −2z−1 +z−2 leads
to an NTF = (1-z−1 )2 . Note that more complex NTFs, such
as band-pass [10], can be can realised with simple Finite-
Impulse-Response (FIR) filtering in L(z), as conceptually
depicted in Fig. 2(a).
The circuit implementation of L(z) and the additional sum-
mation point would dictate the effectiveness of the NTF. Early
designs, [4], [5], adopted a passive residue sampling with the
summation point implemented using high-gain closed loop
amplifiers, limiting its suitability for designs using deep nm
CMOS processes.
The first silicon implementation of an EF NS-SAR was
reported in [6]. Charge sharing is used to implement the sum-
mation point where the quantisation error is added to the
sampled input signal. Due to the attenuating nature of charge
sharing between two capacitors, the implemented EF NS-SAR
only achieved a mild NTF with a zero placed at z = 0.5.
More recently, the authors in [8] proposed the use of a low-
power dynamic amplifier to gain up the residue before charge
recombination, in order to compensate for the attenuation
introduced by the charge sharing process. This general idea of
gaining up the residue has set the basics of modern EF
Fig. 2. EF NS-SAR (a) conceptual schematic, and (b) signal-flow diagram. NS-SAR ADCs, and influenced more recent works such as
those in [9]–[11]. In the following a general discussion of the
impact of circuit errors in this topology is presented.
Assuming a white noise model, Fig. 1(b) shows the cor-
responding signal-flow diagram of a SAR ADC with this A. Circuit Imperfections Degrading the NTF
extra switching event.
This free and perfect quantisation error generation char- The implemented filter coefficients of L(z) are given by the
acteristic has been exploited, by the research community, to product of the amplifier gain, A, and the ratio of the feed-
introduce noise shaping to SAR ADCs. One of the primary back capacitor with the main CDAC. Since the amplifier is
benefits of this is that the noise shaping, not only shapes usually implemented by an open-loop dynamic amplifier, gain
the quantisation error but also shapes the comparator noise, calibration should be included [8].
which in a well-designed SAR contributes significantly to the In EF NS-SAR’s gain sensitivity degrades for a higher order
overall noise and power. When combined with oversampling, NTF as detailed in [9] and [12].
noise shaping leads to a highly reduced in-band quantisation
and comparator noise, which significantly increases the achiev- B. Additive Noise Sources
able Signal-to-Noise Ratio (SNR). Similarly, sampled in-band The introduction of the feedback path introduces other unde-
kT/C noise on the CDAC is reduced by the Over-Sampling sired noise sources to the overall ADC. These errors are related
Ratio (OSR). to the feedback filter implementation and include the ampli-
The two main topologies used to realise NS-SAR ADCs fier noise (thermal and flicker) and sampled kT/C noise from
are the Error-Feedback (EF) and the Cascade-Integrators- the feedback capacitors. The instantaneous random value of
Feed-Forward (CIFF), whose basic characteristics, design each one of this noise sources is sampled onto each one of
considerations and trade-offs are described in the next two the feedback capacitors at the end of the residue gain stage.
sections. During charge recombination this sampled noise is attenu-
ated by the passive charge sharing and added to the CDAC
III. E RROR -F EEDBACK N OISE S HAPING SAR input signal [8], [12]. Note that increasing the noise shaping
One of the first NS-SAR was described as an Error- order leads to additional noise contributions from the addi-
Feedback (EF) M using a SAR quantiser [4]. In this tional capacitors and switches added. In order to minimise
implementation the quantisation error is processed by a loop- the feedback filter noise contributions, increased power to
filter, L(z), whose output is directly added to the input signal as drive a larger CDAC and to obtain a high gain and low-noise
depicted in Fig. 2. Note that there is a unitary delay preceding amplifier are necessary.
L(z), which is due to the fact that the quantisation error can
be only used in the subsequent conversion cycle. IV. F EED -F ORWARD N OISE S HAPING SAR
For this NS-SAR, the digital output is given by:
The authors of [2] introduced an alternative NS-SAR topol-
Dout = Vin + NTF(Qe + ncomp ), (2) ogy, in which the quantisation error is integrated before being
fed forward to an additional comparator input. The additional
where NTF is the Noise-Transfer-Function that shapes the
comparator input enables the comparator to act as a summing
quantisation error, and is defined as [4]:
node, prior to making a decision. The conceptual schematic
NTF = 1 + LEF (z). (3) and signal-flow diagram of this topology are depicted in Fig. 3.

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SALGADO et al.: RECENT ADVANCES AND TRENDS IN NOISE SHAPING SAR ADCs 547

Fig. 4. Signal-flow diagram of the FF NS-SAR with added noise sources.

noise performance. A more conventional 3rd order cascade of

active integrators achieved an SNDR of 98dB in [34], albeit
with a signal bandwidth of 2kHz.

B. Passive Integrator Topologies

Using active integrators in a NS-SARs negates two of the
main benefits of SARs: that their power scales dynamically
with the clock frequency and that they are built of com-
ponents that readily scale to nm CMOS. To recover these
benefits FF NS-SARs which do not require active gain stages
have been proposed [6], [7], [15], [16], [17], [19]. However,
lossy-passive-integrators lead to NTFs with zeros not at DC
and parasitic poles, as it can be inferred from (4). These
Fig. 3. FF NS-SAR (a) conceptual schematic, and (b) signal-flow diagram. ADCs have implemented passive summing using different
weighted comparator inputs or more recently using a coupling
The loop filter, H(z), is made up of an FIR section cascaded capacitor [15], [16].
with an Infinite-Impulse-Response (IIR) section. Therefore, in
this case the NTF is given by [2]: C. Additive Noise Sources
1 B(z) In addition to quantisation noise, sampled kT/C, and com-
NTF = = . (4) parator noise, there are several other noise sources that limit
1 + H(z)z−1 B(z) + A(z)z−1 the achievable performance of CIFF NS-SARs. These noise
From (4) it can be seen that in order to obtain a high-pass sources are detailed in the modified signal flow diagram of
NTF of the form 1-z−1 , an integrator is necessary as a loop- the FF NS-SAR shown in Fig. 4. At the ADC input, sampling
filter H(z). Note that the poles of the loop filter become the clock jitter causes aperture errors njit . The SAR feedback DAC
NTF-zeros, and that NTF-poles are generated as a result of adds mismatch noise nM due to incorrect capacitor values and
the algebraic addition of A(z) and B(z). This topology resem- noise from the reference voltage generators nref . Oversampling
bles Cascade-Integrator-Feed-Forward (CIFF) seen in M, provides a benefit allowing the out of band noise from all
and therefore it is commonly referred to as CIFF NS-SAR or sources to be filtered and discarded. However, noise from these
simply FF NS-SAR. sources that falls in-band needs to be addressed. The disad-
Note that the STF is unitary due to the feedforward path. vantage of the noise shaping is that all loop filters introduce
additional thermal noise nlfilt , which is not shaped. This is the
trade-off of NS-SAR design balancing the benefit of the reduc-
A. Circuit Errors Degrading the NTF tion of comparator and quantisation noise versus the cost of
The loss-less integrators that would enable sharp nulls in loop filter thermal noise.
the NTF necessitate the use of high gain amplifier stages. The noise of loop filters implemented with active stages can
These amplifiers, which are challenging to build in scaled be reduced at the expense of increased power consumption.
nm CMOS, require time for settling and consume power. The noise bandwidth of these active gain stages is inversely
Amplifiers with reduced DC gain implement lossy integra- proportional to the amount of the SAR conversion time allo-
tors that cause NTF-zero displacements from close to z = 1 cated to the settling of the gain stages. This is particularly
in the z-plane. Similarly, the amplifier’s limited bandwidth a challenge for faster NS-SARs.
introduces gain errors in H(z) leading to NTF-poles. In gen- Techniques such as Dynamic amplifiers [8], [14], [20],
eral, NTF-poles are undesirable since they can reduce/cancel 2 step settling [9] and noise cancelling passive filters [16]
the attenuation provided by the NTF-zeros. However, for low have been used to reduce the loop filter thermal noise. The
OSRs the NTF-poles can be strategically placed on the right- flicker (1/f) noise of the loop filter is also not shaped and
hand side of the unit circle as a way to improve the in-band will not benefit from over-sampling. This can especially be
noise suppression [13]. In fact, the loop-filter used in [2] a problem at nm CMOS where large length devices are pro-
implements only one NTF-zero and a pair of complex conju- hibited. Techniques such as chopping and auto-zeroing can be
gate NTF-poles to achieve a similar performance than an ideal employed to reduce the effects of 1/f noise.
3rd order NTF with only zeros, considering an OSR equal In order to graphically illustrate the effect of some of this
to 4. In [14] a dynamic amplifier gain stage before a FIR- added noise sources in the overall ADC output, Fig. 5 shows
IIR cascade with passive integrator was used to achieve better the output spectrum of a 2nd order FF NS-SAR simulated

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548 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 68, NO. 2, FEBRUARY 2021

SAR switching so the DEM is usually only applied to the

MSBs [20].
A recently proposed novel shaping technique is Mismatch-
Error-Shaping (MES) [22], where the last SAR Least-
Significant-Bits conversion code is subtracted from the next
sampled signal to obtain shaped mismatch errors. This has
recently been expanded to 2nd order shaping in [16], [24], but
one of the drawbacks is that it can limit the input signal range.

VI. H YBRID T OPOLOGIES AND T RENDS

Most of the reported SNRs of published NS-SARs
have been limited to around 90dB performance or less.
Several efforts are continuously made to push the NS-
SAR SNR beyond 100dB. Recently, Multi-stgAge-noise-
Fig. 5. Illustration of the impact of some noise sources in the overall NS-SAR SHaping (MASH) with NS-SARs as constituent stages were
output (216 point FFT). presented [27]–[30]. These topologies are able to achieve
higher noise shaping orders with reduced coefficient-variation
sensitivities. Similarly, [9] presents a cascaded NS-SAR that
in MATLAB using the high-level models from the SIMSAR uses an inner and an outer 2nd order loops to realise a cascaded
toolbox [3], [25]. The core SAR ADC has 10-bit resolution 4th order NS-SAR without the need of a digital cancelation
with a CDAC equal to 4 pF, reference voltage of 1V, sampling logic. The cascaded nature of this architecture ensures that all
frequency of 50MS/s, and an OSR of 32 is considered. The two noise added by the inner loop is shaped by the outer loop.
amplifiers in the loop filter have a 100 kHz corner frequency In fact, the residue generation of SAR ADCs can be
for flicker and thermal noise, with an equivalent noise power exploited to create new and exciting hybrid topologies as the
equal to a quarter of kT/CDAC each. From Fig. 5 it can continuous time M in [31], which employs an EF NS-SAR
be seen that amplifier’s input referred thermal noise adds to boost the overall NTF order and to provide an amplifier-
to the sampled kT/CDAC noise and they both set the noise free summation point to compensate for excess loop delay.
floor within the signal-band. Similarly, amplifier flicker noise Other hybrid topologies include the recently described incre-
directly appears in the signal-band, which can highly reduce mental NS-SAR [27], [32], [33], which leverages the concepts
the maximum achievable SNR. of incremental M to produce an oversampled ADC that
behaves as a Nyquist rate ADC, i.e., a memoryless converter.
Despite all the efforts made to improve the SNR, this is still
V. C APACITOR M ISMATCH IN N OISE S HAPING SAR limited mainly due to the loop-filter noise sources and the sam-
Capacitor mismatch degrades the linearity of SAR pled kT/C noise. The authors of [35] have proposed a noise
ADCs [3]. In the frequency domain capacitor mismatch man- cancelation technique for Nyquist rate SAR ADCs that allows
ifests as distortion in the ADC’s output spectrum. In [12] it overcoming the fundamental kT/C limitation. This technique
has been demonstrated that the CDAC capacitor matching in uses an additional sampling capacitor, C2 , placed between the
NS-SAR has to meet the linearity requirements of the final comparator’s preamplifier and latch, such that with the proper
targeted resolution. For instance, for an SNDR = 90dB, the timing the series connection of CDAC and C2 allow the can-
capacitor matching in the CDAC has to meet the associated celation of the sampled noise in the CDAC. Although the
16-bit precision. Since the CDAC errors are not shaped in the sampling noise of C2 is not cancelled, it is greatly attenuated
EF NS-SAR nor in the FF NS-SAR, this statement holds for by the preamplifier’s gain when referred back to the com-
both topologies. As an illustration of this error mechanism, the parator input. A similar sampled noise cancelation technique
reader can refer to the illustration example of Fig. 5, where has been proposed for EF NS-SAR in [11]. This design also
a 0.5% capacitor mismatch is considered in a 10-bit SAR with uses an additional sampling capacitor, C2 , but in this case,
2nd order noise shaping. This mismatch manifests as distortion C2 is placed outside the comparator, specifically in the feed-
across the frequency spectrum. back network. With the proper timing, the feedback amplifier
The intrinsic matching of metal fringe capacitors in nm provides the necessary gain to implement the sampled noise
CMOS benefits from lithography improvements.√ Careful lay- cancellation of CDAC and the attenuation of the sampled noise
out can allow you to achieve 0.3% fF performance [21] of C2 . In both techniques, however, circuit limitations such as
which equates to around 14bit performance with a 1fF unit finite amplifier bandwidth, and input referred thermal noise
capacitor. Effects such a chemical metal polishing mean that can reduce the effectiveness of these noise cancellation tech-
it is often difficult to achieve this level of accuracy in practice. niques. Nevertheless, the resulting ADCs can benefit from
Background and foreground calibration techniques can be smaller CDACs and increased power efficiencies. We believe
used to recover the SAR linearity by means of on-chip that additional techniques to reduce sampled kT/C noise will
capacitor tuning and off-chip digital correction of capacitor be proposed.
weights [23]. As a final note, it should be remembered that a decimation
Other CDAC mismatch correction techniques include the filter is needed to filter out the out of band noise and reduce the
use Dynamic-Element-Matching (DEM), where the capaci- sampling rate. Although classical decimation filter structures
tor errors are averaged so that the in-band power density is for Ms can be used to decimate the output of NS-SAR,
reduced [14], [20]. To shuffle the DAC capacitors an element those filters are usually optimized for low number of bits in
selection mux is required. For moderate to high resolution the quantizer and for high OSR [36], [37]. On the other hand,
DACs this can be quite complex and cause delays in the NS-SAR mostly employ low OSR and large number of bits.

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SALGADO et al.: RECENT ADVANCES AND TRENDS IN NOISE SHAPING SAR ADCs 549

Therefore, this area will also provide additional interesting [16] J. Liu, X. Wang, Z. Gao, M. Zhan, X. Tang, and N. Sun, “9.3 A
research opportunities. 40kHz-BW 90dB-SNDR noise-shaping SAR with 4× passive gain
and 2nd-order mismatch error shaping,” in Proc. IEEE Int. Solid-State
Circuits Conf. (ISSCC), Feb. 2020, pp. 158–160.
VII. F UTURE D IRECTIONS /A PPLICATIONS [17] W. Guo and N. Sun, “A 12b-ENOB 61μW noise-shaping SAR ADC
The benefits of noise shaping SARs are their low area, with a passive integrator,” in Proc. ESSCIRC Conf. 42nd Eur. Solid-State
low power and that they improve with nm CMOS. These Circuits Conf., Sep. 2016, pp. 405–408.
[18] Y. Zhang, S. Liu, B. Tian, Y. Zhu, C.-H. Chan, and Z. Zhu, “A 2nd-
characteristics can be employed to solve two divergent chal- order noise-shaping SAR ADC with lossless dynamic amplifier assisted
lenges for ADCs. Firstly, as a replacement for Discrete-time integrator,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 67, no. 10,
Delta Sigma ADCs in nm CMOS. While the perfect linearity pp. 1819–1823, Oct. 2020.
of the 1bit DAC will be hard to replicate NS SARs can achieve [19] H. Zhuang et al., “A second-order noise-shaping SAR ADC with passive
greater than 100dB SNDR. The other application is as a low integrator and tri-level voting,” IEEE J. Solid-State Circuits, vol. 54,
no. 6, pp. 1636–1647, Jun. 2019.
area ADC for wireless communications receivers [15]. Despite
[20] M. Miyahara and A. Matsuzawa, “An 84 dB dynamic range
not having the filtering and input buffer benefits of CT  62.5–625 kHz bandwidth clock-scalable noise-shaping SAR ADC with
ADCs [26] the lower area is a good solution for MIMO radios open-loop integrator using dynamic amplifier,” in Proc. IEEE Custom
where many RX channels are required and the bandwidth scal- Integr. Circuits Conf. (CICC), Austin, TX, USA, 2017, pp. 1–4.
ing with clock frequency means they be dynamically adjusted [21] M. Pelgrom, H. Tuinhout, and M. Vertregt, “A designer’s view on mis-
for different signal bandwidths without requiring adjustable match,” in Nyquist AD Converters, Sensor Interfaces, and Robustness.
New York, NY, USA: Springer, 2013, pp. 245–267.
resistors or capacitors. [22] Y.-S. Shu, L.-T. Kuo, and T.-Y. Lo, “An oversampling SAR ADC with
DAC mismatch error shaping achieving 105 dB SFDR and 101 dB
R EFERENCES SNDR over 1 kHz BW in 55 nm CMOS,” IEEE J. Solid-State Circuits,
vol. 51, no. 12, pp. 2928–2940, Dec. 2016.
[1] B. Murmann. ADC Performance Survey 1997– [23] A. Salib, M. F. Flanagan, and B. Cardiff, “Blind SAR ADC capacitor
2020. Accessed: Oct. 10, 2020. [Online]. Available: mismatch calibration,” in Proc. IEEE 60th Int. Midwest Symp. Circuits
http://web.stanford.edu/∼murmann/adcsurvey.html Syst. (MWSCAS), 2017, pp. 587–590.
[2] J. Fredenburg and M. Flynn, “A 90MS/s 11MHz bandwidth 62dB SNDR
[24] J. Liu, C. Hsu, X. Tang, S. Li, G. Wen, and N. Sun, “Error-feedback
noise-shaping SAR ADC,” in Proc. IEEE Int. Solid-State Circuits Conf.,
mismatch error shaping for high-resolution data converters,” IEEE Trans.
San Francisco, CA, USA, 2012, pp. 468–470.
Circuits Syst. I, Reg. Papers, vol. 66, no. 4, pp. 1342–1354, Apr. 2019.
[3] G. M. Salgado, A. Dicataldo, D. O’Hare, I. O’Connell, and
[25] G. M. Salgado. SIMSAR Toolbox. Accessed: Oct. 10, 2020. [Online].
J. M. de la Rosa, “Behavioral modeling of SAR ADCs in Simulink,” in
Available: https://www.mcci.ie/simsar-toolbox/
Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 2018, pp. 1–5.
[26] S. Loeda, J. Harrison, F. Pourchet, and A. Adams, “A 10/20/30/40 MHz
[4] K. S. Kim, J. Kim, and S. H. Cho, “nth-order multi-bit  ADC
feedforward FIR DAC continuous-time  ADC with robust blocker
using SAR quantiser,” Electron. Lett., vol. 46, no. 19, pp. 1315–1316,
performance for radio receivers,” IEEE J. Solid-State Circuits, vol. 51,
Sep. 2010.
no. 4, pp. 860–870, Apr. 2016.
[5] Z. Chen et al., “Noise shaping implementation in two-step/SAR ADC
architectures based on delayed quantisation error,” in Proc. IEEE 54th [27] M. Akbari, M. Honarparvar, Y. Savaria, and M. Sawan, “OTA-free
Int. Midwest Symp. Circuits Syst. (MWSCAS), Seoul, South Korea, 2011, MASH two-step incremental ADC based on noise shaping SAR ADCs,”
pp. 1–4. in Proc. 18th IEEE Int. New Circuits Syst. Conf. (NEWCAS), Montreal,
[6] Z. Chen, M. Miyahara, and A. Matsuzawa, “A 9.35-ENOB, QC, Canada, 2020, pp. 138–141.
14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC,” in [28] Y.-S. Lin, S.-J. Chang, and C.-L. Wei, “A noise-shaping SAR assisted
Proc. Symp. VLSI Circuits (VLSI Circuits), Kyoto, Japan, 2015, MASH 2-1 sigma-delta modulator,” in Proc. Int. Symp. VLSI Design
pp. C64–C65. Autom. Test (VLSI-DAT), Hsinchu, Taiwan, 2020, pp. 1–4.
[7] Z. Chen, M. Miyahara, and A. Matsuzawa, “A 2nd order fully-passive [29] S. Oh et al., “A 80dB DR 6MHz bandwidth pipelined noise-shaping
noise-shaping SAR ADC with embedded passive gain,” in Proc. IEEE SAR ADC with 1–2 MASH Structure,” in Proc. IEEE Custom Integr.
Asian Solid-State Circuits Conf. (A-SSCC), 2016, pp. 309–312. Circuits Conf. (CICC), Boston, MA, USA, 2020, pp. 1–4.
[8] S. Li, B. Qiao, M. Gandara, and N. Sun, “A 13-ENOB 2nd -order [30] M. Akbari, M. Honarparvar, Y. Savaria, and M. Sawan, “OTA-free
noise-shaping SAR ADC realizing optimized NTF zeros using an MASH 2–2 noise shaping SAR ADC: System and design considera-
error-feedback structure,” in Proc. IEEE Int. Solid-State Circuits Conf. tions,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Sevilla, Spain,
(ISSCC), San Francisco, CA, USA, 2018, pp. 234–236. 2020, pp. 1–5.
[9] L. Jie, B. Zheng, H. Chen, R. Wang, and M. P. Flynn, “9.4 A 4th - [31] J. Liu, S. Li, W. Guo, G. Wen, and N. Sun, “A 0.029-mm2
order cascaded-noise-shaping SAR ADC with 88dB SNDR over 100kHz 17-fJ/conversion-step third-order CT  ADC with a single OTA
bandwidth,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), San and second-order noise-shaping SAR quantizer,” IEEE J. Solid-State
Francisco, CA, USA, 2020, pp. 160–162. Circuits, vol. 54, no. 2, pp. 428–440, Feb. 2019.
[10] Z. Jiao et al., “A configurable noise-shaping band-pass SAR ADC with [32] B. Gao, X. Li, C. Yan, and J. Wu, “Active noise shaping SAR ADC
two-stage clock-controlled amplifier,” IEEE Trans. Circuits Syst. I, Reg. based on ISDM with the 5MHz bandwidth,” in Proc. IEEE Int. Symp.
Papers, vol. 67, no. 11, pp. 3728–3739, Nov. 2020. Circuits Syst. (ISCAS), Sevilla, Spain, 2020, pp. 1–4.
[11] S. Li, “A kT/C-noise-cancelled noise-shaping SAR ADC with a duty- [33] V. Bajaj, A. Kannan, M. E. Paul, and N. Krishnapura, “Noise shaping
cycled amplifier,” in Proc. IEEE 63rd Int. Midwest Symp. Circuits techniques for SNR enhancement in SAR analog to digital converters,”
Syst. (MWSCAS), Springfield, MA, USA, 2020, pp. 758–761. in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Sevilla, Spain, 2020,
[12] G. M. Salgado, D. O’Hare, and I. O’Connell, “Modeling and analysis pp. 1–5.
of error feedback noise-shaping SAR ADCs,” in Proc. IEEE Int. Symp. [34] K. Obata, K. Matsukawa, T. Miki, Y. Tsukamoto, and K. Sushihara,
Circuits Syst. (ISCAS), Seville, Spain, 2020, pp. 1–5. “A 97.99 dB SNDR, 2 kHz BW, 37.1 μW noise-shaping SAR ADC with
[13] H. Garvik, C. Wulff, and T. Ytterdal, “Noise transfer functions dynamic element matching and modulation dither effect,” in Proc. IEEE
and loop filters especially suited for noise-shaping SAR ADCs,” in Symp. VLSI Circuits (VLSI-Circuits), 2016, pp. 1–2.
Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Montreal, QC, Canada, [35] J. Liu, X. Tang, W. Zhao, L. Shen, and N. Sun, “A 13b 0.005mm2
2016, pp. 1034–1037. 40MS/s SAR ADC with kT/C noise cancellation,” in Proc. IEEE ISSCC,
[14] C.-C. Liu and M.-C. Huang, “28.1 A 0.46mW 5MHz-BW 79.7dB-SNDR Feb. 2020, pp. 258–260.
noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter,” [36] F. J. Harris, “Reduce energy requirements by coupling a poly-phase
in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), San Francisco, pre-filter and cic filter in high-performance Sigma–Delta A/D convert-
CA, USA, 2017, pp. 466–467. ers,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Melbourne, VIC,
[15] Y. Lin, C. Lin, S. Tsou, C. Tsai, and C. Lu, “20.2 A 40MHz-BW Australia, 2014, pp. 1600–1603.
320MS/s passive noise-shaping SAR ADC with passive signal-residue [37] G. M. Salgado, G. J. Dolecek, and J. M. de la Rosa, “Low power two-
summation in 14nm FinFET,” in Proc. IEEE Int. Solid-State Circuits stage comb decimation structures for high decimation factors,” Analog
Conf. (ISSCC), Feb. 2019, pp. 330–332. Integr. Circuits Signal Process., vol. 88, no. 2, pp. 245–254, 2016.

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