National University – SUDAN

Electrical Engineering

8086 Microprocessor

Prepared by: Ahmed Saad

Introduced to: Dr. Alsaddig

The 8086] (also called iAPX 86) is a 16-bit microprocessor chip designed
by Intel between early 1976 and June 8, 1978, when it was released. The Intel 8088,
released July 1, 1979, is a slightly modified chip with an external 8-bit data bus (allowing
the use of cheaper and fewer supporting ICs) and is notable as the processor used in
the original IBM PC design.
The 8086 gave rise to the x86 architecture, which eventually became Intel's most
successful line of processors. On June 5, 2018, Intel released a limited-edition CPU
celebrating the 40th anniversary of the Intel 8086, called the Intel Core i7-8086K.
Buses and operation
All internal registers, as well as internal and external data buses, are
16 bits wide, which firmly established the "16-bit microprocessor" identity of
the 8086. A 20-bit external address bus provides a 1 MB physical address
space (220 = 1,048,576 x 1 byte). This address space is addressed by
means of internal memory "segmentation". The data bus is multiplexed with
the address bus in order to fit all of the control lines into a standard 40-
pin dual in-line package. It provides a 16-bit I/O address bus, supporting
64 KB of separate I/O space. The maximum linear address space is limited
to 64 KB, simply because internal address/index registers are only 16 bits
wide. Programming over 64 KB memory boundaries involves adjusting the
segment registers (see below); this difficulty existed until
the 80386 architecture introduced wider (32-bit) registers (the memory
management hardware in the 80286 did not help in this regard, as its
registers are still only 16 bits wide).
Hardware modes of 8086
Some of the control pins, which carry essential signals for all external
operations, have more than one function depending upon whether the
device is operated in min or max mode. The former mode is intended for
small single-processor systems, while the latter is for medium or large
systems using more than one processor (a kind of multiprocessor mode).
Maximum mode is required when using an 8087 or 8089 coprocessor. The
voltage on pin 33 (MN/MX) determines the mode. Changing the state of pin
33 changes the function of certain other pins, most of which have to do with
how the CPU handles the (local) bus. The mode is usually hardwired into
the circuit and therefore cannot be changed by software. The workings of
these modes are described in terms of timing diagrams in Intel datasheets
and manuals. In minimum mode, all control signals are generated by the
8086 itself.
Registers and instruction
 Intel 8086 registers The 8086 has eight
9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 (bit position)
1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 more or less
general 16-
Main registers bit registers (includi
  AH AL AX (primary ng the stack
accumulator) pointer but
0 0 0 0 BH BL BX (base, excluding the
accumulator) instruction pointer,
  CH CL CX (counter, flag register and
accumulator) segment registers).
  DH DL Four of them, AX,
DX (accumulator,
extended acc) BX, CX, DX, can
Index registers also be accessed
0 0 0 0 SI Source Index as twice as many
8-bit registers (see
0 0 0 0 DI Destination Index
figure) while the
0 0 0 0 BP Base Pointer other four, SI, DI,
0 0 0 0 SP Stack Pointer BP, SP, are 16-bit
Program counter only.
0 0 0 0 IP Instruction Pointe
Due to a compact
r
encoding inspired
Segment registers by 8-bit processors,
CS 0 0 0 0 Code Segment most instructions
DS 0 0 0 0 Data Segment are one-address or
ES 0 0 0 0 Extra Segment two-address
SS 0 0 0 0 Stack Segment operations, which
Status register means that the
  - - - - O D I T S Z - A - P - C Flags result is stored in
one of the
operands. At most one of the operands can be in memory, but this memory
operand can also be the destination, while the other operand, the source,
can be either register or immediate. A single memory location can also
often be used as both source and destination which, among other factors,
further contributes to a code density comparable to (and often better than)
most eight-bit machines at the time.
The degree of generality of most registers is much greater than in the 8080
or 8085. However, 8086 registers were more specialized than in most
contemporary minicomputers and are also used implicitly by some
instructions. While perfectly sensible for the assembly programmer, this
makes register allocation for compilers more complicated compared to
more orthogonal 16-bit and 32-bit processors of the time such as the PDP-
11, VAX, 68000, 32016, etc. On the other hand, being more regular than
the rather minimalistic but ubiquitous 8-bit microprocessors such as
the 6502, 6800, 6809, 8085, MCS-48, 8051, and other contemporary
accumulator-based machines, it is significantly easier to construct an
efficient code generator for the 8086 architecture.
Another factor for this is that the 8086 also introduced some new
instructions (not present in the 8080 and 8085) to better support stack-
based high-level programming languages such as Pascal and PL/M; some
of the more useful instructions are  push mem-op , and ret size, supporting
the "Pascal calling convention" directly. (Several others, such
as  push mimed  and  enter , were added in the subsequent 80186,
80286, and 80386 processors.)
A 64 KB (one segment) stack growing towards lower addresses is
supported in hardware; 16-bit words are pushed onto the stack, and the top
of the stack is pointed to by SS:SP. There are 256 interrupts, which can be
invoked by both hardware and software. The interrupts can cascade, using
the stack to store the return addresses.
The 8086 has 64 K of 8-bit (or alternatively 32 K of 16-bit word) I/O
port space.
Flags
The 8086 has a 16-bit flags register. Nine of these condition code flags are
active, and indicate the current state of the processor: Carry
flag (CF), Parity flag (PF), Auxiliary carry flag (AF), Zero flag (ZF), Sign
flag (SF), Trap flag (TF), Interrupt flag (IF), Direction flag (DF),
and Overflow flag (OF). Also referred to as the status word, the layout of
the flags register is as follows:

Bit 15-12 11 10 9 8 7 6 5 4 3 2 1 0

Fla
  OF DF IF TF SF ZF   AF   PF   CF
g

Performance
Simplified block diagram over Intel 8088 (a variant of 8086); 1=main &
index registers; 2=segment registers and IP; 3=address adder; 4=internal
address bus; 5=instruction queue; 6=control unit (very simplified!); 7=bus
interface; 8=internal data bus; 9=ALU; 10/11/12=external
address/data/control bus.
Although partly shadowed by other design choices in this particular chip,
the multiplexed address and data buses limit performance slightly; transfers
of 16-bit or 8-bit quantities are done in a four-clock memory access cycle,
which is faster on 16-bit, although slower on 8-bit quantities, compared to
many contemporary 8-bit based CPUs. As instructions vary from one to six
bytes, fetch and execution are made concurrent and decoupled into
separate units (as it remains in today's x86 processors): The bus interface
unit feeds the instruction stream to the execution unit through a 6-byte
prefect queue (a form of loosely coupled pipelining), speeding up
operations on registers and immediate, while memory operations became
slower (four years later, this performance problem was fixed with
the 80186 and 80286).