8 FREQUENCY SYNTHESIZERS ‘The oscillators used in RF transceivers are usually embedded in a synthesizer environment so as to achieve a precise definition of the output frequency. Syn- thesizer design still remains one of the challenging tasks in RF systems because it must meet very stringent requirements. In this chapter, we describe a number of approaches to frequency synthe- sis, emphasizing their merits and drawbacks with respect to low-power mono- lithic implementation. We first study the concept of phase locking and ana- lyze different types of phase-locked loops (PLLs).! Next, we present several synthesizer architectures, including integer- N,, fractional-N , and direct-digital synthesis techniques. Finally, we deal with the problem of frequency division. For a more extensive treatment of frequency synthesizers, the reader is referred to [1, 2, 3]- 8.1 GENERAL CONSIDERATIONS The frequency of oscillators in RF transceivers must be defined with very high absolute accuracy. Furthermore, in most cases the frequency must aiso be varied in small, precise steps. Recall from the wireless standards described in Chapter 4 that the channel spacing can be as small as 30 kHz while the center frequency is in the vicinity of 900 MHz or 1.9 GHz. In other words, to change the receive or transmit channel, the LO frequency may be required to vary by only 30 kHz. Also, the lower and upper edges of each channel are well defined and can tolerate an error of no more than a few hundred hertz. Thus, the error in the output frequency must remain below a few parts per million. The role of the synthesizer is illustrated in the generic transceiver of Fig. 8.1. 1 portions of Section 82 are reprinted, with permission, from Monolithic Phase-Locked Loops and Clock Recovery Circuits, B, Razavi, IEEE Press, Piscataway, NJ, pp. 4-32, ©1996 IEEE. 247248 Chap. 8 Frequency Synthesizers Channel Selection Figure 81 Generic transceiver architecture. In addition to accuracy and channel spacing, several other aspects of syn- thesizers influence the performance of a transceiver: phase noise, sidebands (“spurs”), and lock time. As explained in Chapter 7, the phase noise of the local oscillator impacts both the receive and transmit paths. While a free-running oscillator usually exhibits no sidebands, when it is embedded in a synthesizer, it may. Shown in Fig. 8.2, the effect of unwanted sidebands is particularly troublesome in the receive path. Suppose the syn- thesizer output consists of a carrier at zo and a sideband at «ws, while the received signal is accompanied by an interferer at ain. It can be seen that two important components appear after downconversion: the desired chan- nel convolved with the cartier and the interferer convolved with the sideband. If @int — @$ = @ — ©L0(= ejf), the downconverted interferer falls into the desired channel. For this reason, typical systems require that spurs be Interferer RF Input oO: Om o Lo Synthesizer Output Sideband ®o Os o IF Output 4, Or o Figure 82 Effect of synthesizer sidebands in a receiver.Sec. 8.2 Phase-Locked Loops 249 approximately 60 dB below the carrier, Nevertheless, if «; 9 — ws and hence (oo — iq: are large enough, the interferer appears out of the receive band and is therefore suppressed by the front-end duplexer or bandpass filter to some extent The lock time of synthesizers is also a critical parameter. As shown in Fig. 8.3, when the digital channel select input commands a change in the channel, the synthesizer requires a finite time to establish the new frequency. Defined more accurately in Section 83.1, the lock time is an indication of how fast the new frequency is stabilized, This parameter is especially important in fast frequency-hopped spread-spectrum systems, Lock times required in typical RF systems vary from a few tens of milliseconds to a few tens of microseconds. Lock Transi Figure 8.3. Synthesizer settling, 8.2 PHASE-LOCKED LOOPS 8.2.1 Bas Concepts VCO Dynamics Recall from Chapter 7 that an ideal VCO is charac- terized by wou = @PR + Kvcoveon and y(t) = Ac cosforrt + Kyco I’. Veont(?)d7]. In studying PLLs, we usually consider a VCO as a linear time- invariant system, with the control voltage as the system’s input and the excess phase (Chapter 3) of the carrier as the system’s output. Since the excess phase Pout) = Kyco f Yeomd?, the input-output transfer function is Pout Kye H(s) = =HCe, (8.1) Veont s The integration in VCOs leads to an interesting property: to change the out- put phase, we must first change the frequency and let the integration take place.* For example, suppose for f < fo, a VCO oscillates at the same fre- quency as a reference but with a finite phase error (Fig, 8.4). To reduce the error, the control voltage, cont, is stepped by +AV at f = fy, thereby increas- ing the VCO frequency and allowing the output to accumulate phase faster than the reference. Att = 1, when the phase error has decreased to zero, We assume the VCO has no other input to set its phase.250 Chap. 8 Frequency Synthesizers Reference et ae vco Output Figure 84 Phase alignment of a VCO with a reference Ucone TetUTnS tO its initial value. Now, the two signals have equal frequencies and zero phase difference. Note also that the same goal can be accomplished by lowering the VCO frequency during this interval. The above observation yields another interesting result as well: the output, phase of a VCO cannot be determined only from the present value of the control voltage, i.e., it depends on the history of veon:. For this reason, we treat the output phase of VCOs as an independent initial condition (or state variable) in the time-domain analysis of PLLs. Phase Detector An ideal phase detector (PD) produces an output signal whose de value is linearly proportional to the difference between the phases of two periodic inputs (Fig. 8.5), Tou KppAd, (8.2) where K pp isthe “gain” of the phase detector (specified in Virad) and Ag isthe input phase difference. In practice, the characteristic may not be linear or even monotonic for large Ag. Furthermore, K pp may depend on the amplitude or duty cycle of the inputs. These points are explained later. Phase Detector Vout se ao Figure 85 Characteristic of an ideal phase detector, Figure 8.6 illustrates a typical example, where the PD generates an output pulse whose width is equal to the time difference between consecutive zeroSec. 8.2 Phase-Locked Loops 251 x(t) xa(t) peat —LILILAT ALLL Output SSS es t Figure 86 Input and output waveforms of a PD. crossings of the two inputs. Since the two frequencies are not equal, the phase difference exhibits a “beat” behavior with an average value of zero. A commonly used type of phase detector is a multiplier (also called a mixer or a sinusoidal PD). For two signals x(t) = A; cost and x2(t) = Az cos(w2t + AG), a multiplier generates y(t) = wA; cosat + Az cos(at + Ap) (8.3) @A\Ar = cos [lor + on)t + Ad] @AiA2 cos [wi — @2)t — Ag]. (84) where a is a proportionality constant. Thus, for @; = wy, the phase/voltage characteristic is given by a= AYA: say = eA cos Ad. (85) Plotted in Fig. 8.7, this function exhibits a variable slope and nonmonotonicity, ut it resembles that in (8.2) if A¢ is in the vicinity of /2, — _ @AiAr x 8 ~ Ad), (8.6) yielding Kpp = —a@A,Az/2. Note that the average output is zero if w: # wr Figure 87 Characteristic of a sinusoidal PD.252 Chap. 8 Frequency Synthesizers An analog multiplier can be implemented as a Gilbert cell, operating as an exclusive-OR (XOR) gate if the input signals are relatively large. 8.2.2 Basic PLL Simple Loop A phase-locked loop is a feedback system that operates on the excess phase of nominally periodic signals. This is in contrast to familiar feedback circuits where voltage and current amplitudes and their rate of change are of interest. Shown in Fig. &.8is a simple PLL, consisting of a phase detector, a low-pass filter (LPF), and a VCO. The PD serves as an “error amplifier” in the feedback loop, thereby minimizing the phase difference, Ap, between x(F) and y(z). The loop is considered “locked” if Ad is constant with time, a result of which is that the input and output frequencies are equal. y(t) Figure 88 Basic phase-locked loop. In the locked condition, all the signals in the loop have reached a steady state and the PLL operates as follows, The phase detector produces an output whose de value is proportional to Ag. ‘The low-pass filter suppresses high- frequency components in the PD output, allowing the de value to control the VCO frequency. The VCO then oscillates at a frequency equal to the input frequency and with a phase difference equal to Ag. Thus, the LPF generates the proper control voltage for the VCO. Itis instructive to examine the signals at various points in a PLL. Figure 8.9 shows a typical example. The input and output have equal frequencies but a finite phase difference, and the PD generates pulses whose width is equal to the time difference between zero crossings of the input and output. These pulses are low-pass filtered to produce the DC voltage that sustains the VCO operation at the required frequency. As mentioned above, this voltage does not by itself determine the output phase. The VCO phase can be regarded as an initial condition of the system, independent of the initial conditions in the LPF. Let us now study, qualitatively, the response of a PLL that is locked for 1 < fy and experiences a smalll, positive frequency step at the input at f = t (Fig. 8.10). (For illustration purposes, the frequency step in this figure is only a few percent.) We note that since the input frequency, in, is momentar- ily greater than the output frequency, «aux, x (f) accumulates phase faster than does y(t), and the PD generates increasingly wider pulses. Each of these pulses creates an increasingly higher de voltage at the output of the LPF, thereby in-Sec. 8.2 Phase-Locked Loops 253 LPF Output Kent ee t Figure 89 Waveforms in a PLL. creasing the VCO frequency. As the difference between aq and dou dimin- ishes, the width of the phase comparison pulses decreases, eventually returning to slightly greater than its value before t = fp. The above analysis provides insight into the “tracking” capabi PLL. If the input frequency changes slowly, its variation can be viewed as a succession of small narrow steps, during each of which the PLL behaves as in Fig. 8.10. ies of a Figure8.10_ Response of a PLL toa small frequeney step, It is important to note that in the above example the loop locks only after two conditions are satisfied: (1) eau: has become equal to i,, and (2) the difference between gia and Go: has settled to its proper value [4]. If the two frequencies become equal at a point in time but Ad does not establish254 Chap.8 Frequency Synthesizers the required control voltage for the VCO, the loop must continue the tran- sient, temporarily making the frequencies unequal again. In other words, both “frequency acquisition” and “phase acquisition” must be completed. This is of course to be expected because for lock to occur again, all the initial conditions of the system, including the VCO output phase, must be updated. If the input to a PLL has a constant excess phase, i... is strictly periodic, but the input-output phase error, Ag, varies with time, we say the loop is “unlocked,” an undesirable state because the output does not track the input or the relationship between the input and output is too complex to be useful. For example, if win is sufficiently far from the VCO’s free-running frequency, the loop may never lock. While the behavior of a PLL in the unlocked state is not important per se, whether and how it enters the locked state are both critical issues. Before studying PLLs in more detail, we make three important observa- tions. First, since a PLL is a system with “memory,” its output requires a finite time to respond to a change at its input, mandating a good understanding of the loop dynamics. Second, in a PLL, unlike many other feedback systems, the variable of interest changes dimension around the loop: it is converted from phase to voltage (or current) by the phase detector, processed by the LPF as such, and converted back to phase by the VCO. Third, in the lock condition, the input and output frequencies are exactly equal, regardless of the magni- tude of the loop gain (although the phase error may not be zero). This is an extremely important property because many applications, including frequency synthesizers, are intolerant of even small (systematic) differences between the input and output frequencies. Note that if the phase detector is replaced with only a frequency detector, this property vanishes. While a PLL operates on phase, in many cases the parameter of interest is frequency. For example, we often need to know the response of the loop if (1) the input frequency is varied slowly, (2) the input frequency is varied rapidly, or (3) the input and output frequencies are not equal when the PLL is turned on. Therefore, the phase detector characteristic for unequal input frequencies plays an important role in the behavior of a phase-locked loop. Loop Dynamics in Locked State Transient response of phase-locked loops is generally a nonlinear phenomenon that cannot be formulated easily. Nevertheless, as with other feedback systems, a linear approximation can be used to gain intuition and understand trade-offs in PLL design, Figure 8.11 showsa linear model of the PLL in lock along with the transfer function of each block. The model is to provide the overall transfer function for the phase, ®our(s) /in(s); hence the PD is represented by a subtractor. The LPF is assumed to have a voltage transfer function Gzpr(s). The open-loop transfer function of the PLL is therefore equal to Kvco s Hols) = KppGrpr(s) (8.7)Sec. 8.2. Phase-Locked Loops 255 = Pin Pout Figure 811 Linear model of a PLL. yielding the following closed-loop transfer function: Dour HO) == 3 (88) _ _KpoKvcoGipr(s) (3) 5 KepKveoGurr@ " In its simplest form, a low-pass filter is implemented as in Fig. 8.12, with Gipr(s) = (8.10) OLPF where wy pr = 1/(RC). Equation (8.9) then reduces to Kook H(s) = ——ece (8.11) +s+KppKvyco OLPE indicating that the system is of second order, with one pole contributed by the VCO and another by the LPF. The quantity K = KppKyco iscalled the“loop gain” and expressed in rad/sec. In order to understand the dynamic behavior of the PLL, we convert the denominator of (8.11) toa familiar form used in control theory, 57++-2¢@5-+@2, R Vin i © Vout Figure 8.12 Simple low-pass filter.256 Chap. 8 Frequency Synthesizers where ¢ is the damping factor and , is the natural frequency of the system.) ‘Thus, H(s) = (8.12) where On (8.13) ‘ (8.14) Note that «, is the geometric mean of the —3-dB bandwidth of the LPF and the loop gain, in a sense an indication of the gain-bandwidth product of the loop. Also, the damping factor is inversely proportional to the loop gain, an important and often undesirable trade-off. Ina well-designed second-order system, ¢ is usually greater than 0.5 and preferably equal to 2/2 so as to provide an optimally flat frequency response. ‘Therefore, K and «1 pp cannot be chosen independently; for example, if ¢ = 2/2, then K = wp pr/2. ‘The transfer function in (8.12) is that of a low-pass filter, suggesting that if the input excess phase varies slowly, then the output excess phase follows, and conversely, if the input excess phase varies rapidly, the output excess phase variation will be small. In particular, if s > 0, we note that H(s) — 1; that is, a static phase shift at the input is transferred to the output unchanged, This is because for phase quantities, the presence of integration in the VCO makes the open-loop gain approach infinity as s > 0. To this end, we can examine the “phase error transfer function,” defined as He(s) = ©¢(s)/Pin(s) in Fig. 8.11, H.(s) = 1— His) (8.15) 2 + ons s? + ans + we (Sis) which drops to zero as s > 0. Since phase and frequency are related by a linear, time-invariant oper- ation, the transfer functions in (8.12) and (8.16) also apply to the input and output excess frequencies. For example, (8.12) indicates that if the input fre- quency varies rapidly, the instantaneous variation of the output frequency will be small. It is instructive to repeat our previous analysis of the loop step response (Fig. 8.10) with the aid of (8.12). Suppose the input excess frequency is equal to Awu(r), where u(t) is the unit step function (Fig. 8.13). The output excess na simple PLL, @, has no relation with the input and output frequencies.Sec.8.2 Phase-Locked Loops 257 frequency then exhibits the typical step response of a second-order system, eventually settling to Aw rad/sec higher than its initial value, The output excess phase, on the other hand, is given by Pours) = A(s)Pin(s) (8.17) wo Aw S$ Ways + oF 8? | 7 (8.18) which is the response of a second-order system to a ramp input. More impor- tantly, the phase error is Pe(s) = He(s)Pin(s) (8.19) _ 8 +2ans Aw ai ~ S$ 2o_s + az 5?! (6.20) whose final value is given by $e(t = 00) = lim soe(s) (8.21) 2 = Ao%~ (8.22) On = Ae 8.23) => (823) Therefore, static changes in the input frequency are suppressed by a factor of K when they manifest themselves in the static phase error (Fig. 8.13). This is of course to be expected because for the VCO frequency to change by Aw, the control voltage must change by Aw/Kyco and the input to the PD by Aw/(KycoK ep) Figure 813 Response of a PLL to s frequency step.258 Chap. 8 Frequency Synthesizers Itis also useful to have an approximate relation for the step response in the time domain. In a second-order system with £ < 1, the step response is given by = : 1 xp(—Zont) x sinomyl — 671 + w) | ule), (8.24) where y = sin Tracking and Acquisition Two aspects of the performance of PLLs prove essential in most applications. ‘The first is the “tracking” behavior, that is, the extent to which the loop can follow variations in the input frequency. ‘The second is the “acquisition” characteristics, i.c., how the loop goes from unlocked state to complete phase lock. A detailed analysis of these properties can be found in [4, 5, 6], but we should mention here that to ensure a sufficiently wide tracking and acquisition frequency range, most PLLs incorporate frequency comparison in addition to phase detection, The idea is that if the VCO and input frequencies are wide apart, a frequency detection mechanism governs the feedback loop, driving the VCO frequency closer to the input frequency. After the difference has dropped to sufficiently low values, the phase detection takes over, performing the final phase lock. 8.2.3 Charge-Pump PLLs Phase/Frequency Detectors A circuit that can detect both phase and frequency difference proves extremely useful because it significantly increases the acquisition range and lock speed of PLLs. Unlike multipliers and XORs, sequential phase/frequency detectors (PFDs) generate two outputs that are nof complementary. Illustrated in Fig. 8.14, the operation of a typical PFD is as follows. If the frequency of input A is greater than that of input B, then the PFD produces positive pulses at Qa, while Qy remains at zero. Conversely, if @4 < @g, then positive pulses appear at Og while O4 = 0. If wa = ep, then the circuit generates pulses at either Q.4 or Og with a width equal to the phase difference between the two inputs. (Note that, in principle, Q.4 and Qg are never high simultaneously.) ‘Thus, the average value of Q.4 — Qs is an indication of the frequency or phase difference between A and B. The outputs Q4 and Qg are usually called the “UP” and “DOWN” signals. ‘To arrive at a circuit with the above behavior, we postulate that at least three logical states are required: Q, = Qn = 0; Qu = 0,Qp = 1; and Qs =1,Qz = 0. Also, to avoid dependence of the output upon the dutySec. 8.2 Phase-Locked Loops 259 fa) (b) Figure 8:14 Phase/frequency detector response with (a) «4 > wn, (b) A lagging B. cycle of the inputs, the circuit should be implemented as an edge-triggered sequential machine. We assume the circuit can change state only on the rising transitions of A and B, and, for the sake of brevity, will omit the adjective “rising” hereafter. Fig. 8.15 shows a state diagram summarizing the operation. If the PFD is in the “ground” state, 04 = Q = 0, then a transition on A takes it to state I, where Q4 = 1, Qg = 0. The circuit remains in this state until a transition occurs on B, upon which the PFD returns to state 0. The switching sequence between states 0 and II is similar, Statell BA Stateo Ad State! af ah Bh Figure 8.15 PED state diagram. An important point in this state diagram is that if, for example, «04 > x. then there will be a time interval during which two transitions of A take place between two transitions of B. This ensures that, even if the PED begins in state 11, it will eventually leave that state and thereafter toggle between states 0 and 1{7]. A possible implementation of the above PED is shown in Fig. 8.16 [7] The circuit consists of two edge-triggered, resettable D flipflops with their D inputs connected to logical ONE. Signals A and B act as clock inputs of DF Fs and DF Fp, respectively. We note that if 04 = Qg = 0, a transition on A causes Q, to go high. Subsequent transitions on A have no effect on Q.4. and260 ONE ONE Chap. 8 Frequency Synthesizers DFF Figure 8.16 PED implementation, when B goes high, the AND gate activates the reset of both flipflops. Thus, Qx and Qz are simultaneously high for a duration given by the total delay through the AND gate and the reset path of the flipflops. Figure 8.17 shows the input-output characteristic of the PFD. Vout -2n +21 AG Figure 8.17 PFD characteristic. ‘The D flipflops in Fig. 8.16 may employ different topologies in bipolar and CMOS implementations. In bipolar technology, a standard master-slave configuration with an additional reset input can be used. In CMOS technology, a simple circuit such as that in Fig. 8.18 [8] proves adequate. Note that the D input is “hidden” here. Other implementations of PFDs are described in [9, 10}. ‘The output of a PED can be converted to DC in different manners. One approach is to sense the difference between the two outputs by means of a differential amplifier and apply the result to a low-pass filter. Alternatively, the outputs can drive a three-state “charge pump.”Sec. 8.2 Phase-Locked Loops 261 cK Reset Figure 8.18 Implementation of each DFF in Fig. 8.16, Charge Pumps _In the low-pass filters considered thus far (Fig, 8.12), the average value of the PD output is obtained by depositing charge onto a capacitor during each phase comparison and allowing the charge to decay afterwards. In a charge pump, on the other hand, there is negligible decay of charge between phase comparison instants, leading to interesting conse- quences A three-state charge pump can be best studied in conjunction with a three-state phase/frequency detector (Fig. 8.19), The pump itself consists of two switched current sources driving a capacitor. Note that for a pulse of width T on Qa, h deposits a charge equal to T on Cp. Thus, if #4 > wp, or 4 = Op but A leads B, then positive charge accumulates on Cp steadily, yielding an infinite DC gain for the PFD. Similarly, if pulses appear on Op. h; removes charge from Cp on every phase comparison, driving Voy. toward —oo. In the third state, with O, = Oz = 0, Vow remains constant. Since the steady-state gain is infinite, it is more meaningful to define the gain of the PFD/charge pump combination for one comparison instant, which is equal to IT/QxCp). An important conclusion to be drawn from the above observations is that, if offsets and mismatches are neglected, a PLL utilizing this arrangement locks such that the static phase difference between A and B is zero; even an infinitesimal phase error would result in an indefinite accumulation of charge on Cp. ‘The PFDicharge pump combination exhibits nonidealities such as the “dead zone,” charge sharing and injection, etc. These effects are described in 5.9].262 Chap. 8 Frequency Synthesizers Figure 8.19 PFD with charge pump. Charge-Pump PLLs —Charge-pump PLLs (CPPLLs) incorporate a PFD (or PD) and a charge pump instead of the combinational PD and the LPF in the generic architecture of Fig. 8.8. As mentioned before, the combination of a PFD and a charge pump offers two important advantages over the XOR/LPF approach: (1) the capture range is only limited by the VCO output frequency range, and (2) the static phase error is zero if mismatches and ofisets are neg- ligible. In this section, we study the characteristics of this type of PLLs and make comparisons with the conventional type. Charge pumps provide an infinite gain for a static phase difference at the input of the PFD. From another point of view, the response of a PFD/charge pump to a phase step is a linear ramp, indicating that the open-loop transfer function of the circuit contains a pole at the origin. With another such pole contributed by the VCO, a charge-pump PLL cannot remain stable. In fact, representing the transfer function of the PFD/charge pump with Kprp/s, we note that the closed-loop transfer function of the PLL isSec. 8.2 Phase-Locked Loops 263 Figure 820 Charge-pump PLL. Kprp Kvco H(s) = ——S—__5___ (8.25) Kerp Kve 14 Kero Kvco ss —Kreokveo 8? + KprpKyco’ revealing two imaginary poles at » = +j./KprpKyco- To avoid instability, a zero must be added to the open-loop transfer function. This is in contrast to the case of a sinusoidal PD and a simple low-pass filter, where the loop is, in principle, stable even with no zero. The stabilizing zero in a CPPLL can be realized by placing.a resistor in series with the charge pump capacitor (Fig. 8.21) (8.26) Yop | tn Figure 821 Addition of a zero to a charge pump. ‘To perform a small-signal analysis, we note that the switching operation of the charge pump and the lack of a discharge path between phase comparison instants make the PLL a discrete-time system. However, if the loop bandwidth264 Chap. 8 Frequency Synthesizers is much less than the input frequency, we can assume the state of the PLL changes by a small amount during each cycle of the input [11]. Using the “average” value of the discrete-time parameters, we can then study the loop as a continuous-time system (11). Suppose the loop begins with a phase error Gin — Pour = @e- Then, the average current charging the capacitor is given by I@-/(27r), and the average change in the control voltage of the VCO equals Veont(s) = @ G + as) (8.27) Noting that ®ou:(s) = Veoo(s)Kvco/s, We obtain the following closed-loop transfer function: ne, (RCps + I) Kvco Hs) = AO (8.28) Ki R: + on veoRs + inp ‘Thus, the system is characterized by a zero at @, = —1/(RCp) and I n= Rycos 8.29) @, Vince veo (8.29) R iC 5 (830) TV ag Kvco: Note that @, is independent of R. From Eq, (8.24), we note that the decay time constant of the system is equal to ({@,/2)—! = (RI Kyco/8)~', a quantity independent of Cp. In many applications, it is desirable to maximize the loop bandwidth, which is usually proportional to @,. While for a PLL with a sinusoidal PD, (oq and & cannot be maximized simultaneously, Eqs. (8.29) and (8.30) sug- gest that in a CPPLL, both w, and ¢ can be increased if J or Kyco is in- creased. However, as the loop bandwidth becomes comparable with the input frequency, the continuous-time approximation used above breaks down, ne- cessitating discrete-time analysis. Using such an analysis, Gardner has derived a stability limit [11] that can be reduced to Kvco mr Of < RG Ew)’ (831) implying an upper bound on w,, This equation also indicates that R cannot be increased indefinitely [10]. In typical designs, the loop bandwidth is roughly one-tenth of the input frequency to guarantee stability. In single-ended charge pumps, the resistor added in series with the ca- pacitor can introduce “ripple” in the control voltage [11] even when the loopSec. 8.2. Phase-Locked Loops 265 is locked. Since 5; and $2 turn on at every phase comparison instant, the mismatch between / and /; flows through R, causing a step at the output. Furthermore, mismatch between overlap capacitance of S; and Sp results in a net signal feedthrough to the output, Modulating the VCO frequency, this, effect is especially undesirable in frequency synthesizers. ‘To suppress the ripple, a second capacitor can be connected from the output of the charge pump to ground. This modification introduces a third pole in the PLL, requiring further study of stability issues. Gardner provides criteria for the stability of such systems [11]. 8.2.4 Type | and Type Il PLLs Our study of PLLs reveals that the combination of the PD and the loop filter plays an important role in the system dynamics. In particular, PLLs incorpo- rating sinusoidal PDs and RC filters exhibit distinctly different stability issues from those using three-state PFDs and charge pumps. The fundamental dif- ference between the two is that the open-loop transfer function of the former has only one pole at the origin whereas that of the latter has two poles at the origin. The two topologies are called “type I” and “type Il,” respectively. In order to understand the stability characteristics of the two PLL types, we analyze the root locus of each as the loop gain, K = KppKyco, varies ‘The open-loop transfer function of a type I PLL (with no zeros) is equal to K/[(1 + s/ozpp)s]. Thus, for K = 0, the closed-loop poles begin at s; = 0 and s> = —wzpr [Fig. 8.22(a)]. As K increases, s; and s) move toward each other on the real axis and meet for K = wypr/4. For higher K, the poles become imaginary and move toward oo. Since £ = cos, we note that increasing K’ makes the system less stable. @) ) Figure 822 Root loci for (a) type I and (b) type II PLL266 Chap. 8 Frequency Synthesizers For a type II charge-pump PLL, the open-loop transfer function is equal to Ip[R-+1/(Cps)]Kvco/ (225). As Ip Kyo increases from zero, both poles depart from the origin and move on a circle in the left half plane, eventually returning to the real axis for sufficiently high gain, that is, where I Kvco 8x/(R?Cp) and ¢ = 1. Thus, increasing the loop gain makes the PLL more stable. As mentioned above, type II PLLs are usually of third order because the capacitor placed in parallel with the series RC network contributes a third pole. The root locus and stability in such a case are described in [4, 11]. 8.2.5 Noise in PLLs Since PLLs operate on the phase of signals, they are susceptible to phase noise or jitter. Within the scope of this book, we consider phase noise as a random ‘component in the excess phase, as exemplified by $n (f) in x(t) = A cosferet + n(t)]. For the sake of brevity, we use the term noise to mean phase noise. If the input signal or the building blocks of a PLL exhibit noise, then the output signal will also suffer from noise. In general, all the loop components, including the phase detector, the LPF, the VCO, and the frequency divider may contribute noise [15]. The goal is to understand how the spectrum of a given noise source is shaped as it propagates to the output. We examine two important cases: (1) the input signal contains noise, and (2) the VCO introduces noise. In each case, we find the transfer function from the noise source of interest to the PLL output. In monolithic implementations, the phase noise of the VCO is typically much more significant than that of other loop components. 8.2.6 Phase Noise at Input Consider the PLL in Fig. 8.23 where the input and output signals are x(t) = Asin[wct + din(t)] and y(t) = Bsin[wet + Pour(t)]. The transfer function ou:(s)/Piq(s) of a second-order type II PLL is wl + s/w) HO) = Fy aeons Oe (8.32) If the input (excess) phase, ¢in(t), does not vary with time, that is, if the input to the PLL is a pure sinusoid, then s = 0 and H(s) = 1. Now, suppose $in(1) is varied so slowly that both the numerator and the denominator of (8.32) are still close to 2. Thus, H(s) remains close to unity, indicating that the output phase (or frequency) follows the input phase (or frequency), a natural property of the PLL as a tracking system. What happens if iq (t) varies at an increasingly higher rate? For the case shown in Fig. 8.23, Eq. (8.32) shows that the output excess phase, gout (t), drops,Sec. 8.2 Phase-Locked Loops 267 ; @-Lert H Po Pout| log Opt Oz Ope ° Figure 823 Noise transfer function of a PLL from input to output. eventually approaching zero and yielding y(1) = Bsinw turn off, their charge injection mismatch yields an error step at node X, causing the VCO frequency to shift. Consequently, by the next comparison instant, the VCO output phase is not equal to the input reference phase, thereby requiring the charge pump to produce a corrective pulse of current, Thus, Vy toggles between two values even under the locked condi- tion.272 — Chup.8 Frequency Synthesizers Figure 829 Periodic disturbance of VCO control line due to charge pump activitiy. ‘The above mechanisms can be quantified with the aid of simulation. For a realistic PD and charge pump design, the systematic error waveform due to feedthrough and charge injection can be obtained from time-domain sim- ulations. To estimate the effect of this waveform, let us assume the control line disturbance appears as narrow rectangular pulses having a width Ar and a height AV (Fig. 8.31). Denoting the periodic waveform by g(¢), we can express the VCO output as Vour(t) = Vo cos [over Kveo f acoat + Kveo f vat]. (8.34) Figure 830 Effect of charge injection mismatch in charge pump. ‘The Fourier series expansion of g(t) is given by AVAt a) = + San costnonert + On). (8.35) Ther where the first term represents the de component and can be merged with Vi. Thus,Sec. 8.3 RF Synthesizer Architectures 273 Trer Figure 8.31 Estimation of VCO modulation due to charge pump feedthrough. AVAr Trer Vour(t) * Vo cos (ore + Kvco: + Kyeoh)t Gn sinQr@gert + Pn) — Kveo | Wo Pry LORE F AVAr sin (crn + Kvco + Kveo¥i) t (8.36) REF indicating sidebands at Loner, bands are called “reference spurs is inversely proportional to waer. The problem of reference feedthroughis a difficult one, especially if wpe r issmall enough that wc+toaer fallsin the band of interest. Typical synthesizers employ large capacitors in the loop filter to reduce AV and minimize Kyco to lower the modulation index. At low supply voltages, the latter remedy is not feasible because the tuning range must be sufficiently wide to guarantee lock despite process and temperature variations. Another approach to suppressing reference feedthrough is to interpose a notch filter between the loop filter and the VCO. Depicted in Fig. 8.32, this technique creates a transmission zero at wger (and if necessary higher har- monics thereof) to minimize the disturbance of the oscillator control voltage. ‘Two drawbacks, however, accompany this method: (1) the filter may generate substantial noise unless it incorporates off-chip inductors and capacitors, and (2) the filter alters the loop transfer function, possibly degrading the settling behavior and even causing instability. In active implementations, the 1/f noise of such a filter is also troublesome for it is upconverted to the frequency range around the carrier (Chapter 7). r . with respect to the cartier. These side- Note that the magnitude of the sidebands Loop Bandwidth The integer-N architecture of Fig. 8.27 requires that the reference frequency, fe, be equal to the channel spacing, ¢.g., 30 kHz in IS-54 and 200 KHz in GSM. Now recall from Section 8.2.3 that stability considerations limit the bandwidth of type II phase-locked loops to roughly frer/10. Thus, with free = 30 kHz, the loop settling time constant may be274 Chap. 8 Frequency Synthesizers Figure 8.32 Use of a notch filter to suppress reference feedthrough, aslarge as 1 msec. Before quantifying the results, we need to revisit the concept of lock time. In many PLLs, the lock time is defined in terms of the phase difference between the input and the output: near the end of the lock transient, this dif- ference drops to acceptably low values and the loop is considered locked. This view is indeed appropriate for retiming and edge alignment in data communi- cations. In RF synthesis, on the other hand, the output parameter of interest during transients is the frequency rather than the phase. Because of closely spaced channels, the LO frequency in the receive and transmit paths must settle to within a few ppm with respect to its ideal value before the loop is considered locked. If the control voltage of the oscillator changes with time, so does the instantaneous value of the output frequency (Fig. 8.33). Thus, the downconversion or upconversion functions in the transceiver do not operate exactly on the desired channel until the LO frequency has settled. As depicted in Fig. 8.34, in the receive path this effect skews the center of the downconverted channel, corrupting the desired signal with an adjacent channel, and in the transmit path the frequency error causes the upconverted signal to leak into adjacent channels, Figure 833 Variation of VCO frequency during synthesizer settling.Sec. 8.3 RF Synthesizer Architectures 275 Transmitted Channel Received Channel Adjacent i yon Adjacent Desired ee Desired Channel Channel a» Channel ra o ® @) o Figure 834 Effect of synthesizer settling on received and transmitted channels. In the phase-locked architecture of Fig. 8.27, a loop transient occurs each time the divider modulus changes. Interestingly, a small change in M yields the same transient behavior as does a small change in the input frequency. This can be proved with the aid of the feedback system shown in Fig. 8.35, where A changes by a small amount € at ¢ = 0. The output after = 0 is then equal to H(s) "9 = aon em oe ew __, | _g 838 “Tyan trea” (38) H(s) eu. © Tamed 7 px (8.39) implying that the change is equivalent to multiplying X (s) by (1 — €/A) while retaining the same transfer function. Since in the synthesizer, x(t) is constant before ¢ = 0, multiplication by 1 — €/A can be viewed as a step from x(t) to (1=€/A)x(1) att =0. From the above analysis, we infer that when the divider modulus changes, the loop exhibits a response to a step input, requiring a finite time to settle Figure 8.35 Effect of a small change in the feedback factor.276 Chap. 8 Frequency Synthesizers Divider Kee Modulus NP+1 (NP+ 8) faer —TTSTaS t Figure 8.36 Worst-case switching in a synthesizer. within an acceptable margin around its final value. As shown in Fig. 8.36, the worst case occurs when the synthesizer output frequency must go from the first channel, (N P + 1) frer. to the last, (NP + S) fer. or vice versa. Suppose the divider modulus changes from M to M +k, where k < M. Howis the settling time estimated? Using the above notation, we write A = 1/M and A+ =1/(M +4). This is equivalent to a change in the reference frequency from frer to frer(1 +k/M). Writing Eq. (8.24) for the input and output frequencies of the loop, we have 1 Fra ieee sino /1 — $1 + sin /1 — Bu. (8.40) Soult) = Mfrer + kfrer : = Since the final value of the output frequency is (M +k) frep, we must calculate the time required for fy: to be within (1 + @)(M +) free, where a is the settling accuracy. 1 (14 a)(M +k) frer = Mfrer + kfrer : - FR hats) sin(ony/l — ¢?ts + sin 1 — =} (8.41) A sufficient condition for settling is that the exponential envelope decay to small values: sa(M +k) exp(—Se@ats) (8.42) It follows that ts. — In ——__ (8.43)Sec.8.3 RE Synthesizer Architectures 277 For example, consider a typical synthesizer with free = 200 kHz, Mfaer = 900 MHz, ¢ = J2/2, and k = 128. For 10 ppm settling accu- racy, the above equation yields ts © 8.3/(Cam); that is, the loop requires 8.3 time constants to settle, In practice, the settling time is longer than the value predicted by (8.43). Recall from Section 8.2.3 that most charge-pump PLLs in- corporate a second capacitor in parallel with the RC combination to suppress the disturbance on the VCO control line, especially if the reference spurs are to be minimized. Thus, the system is of third order, generally exhibiting slower settling to high precisions. For this reason, accurate simulations are required to calculate the settling time of the loop. Phase Noise Another drawback resulting from limited loop bandwidth is higher close-in phase noise at the output. As explained in Section 8.2.5 the phase noise of the oscillator is reduced by the feedback only within the bandwidth of the loop. For example, if the loop bandwidth ofa GSM synthesizer is equal to 20 kHz, then phase noise components at frequency offsets greater than a few kilohertz experience little attenuation, This is a serious issue in MOS implementations because the upconverted 1/f noise of the VCO is quite significant for offsets as large as several hundred kilohertz. The large division ratio required in typical RF synthesizers also intensifies the efffect of the reference and phase detector noise within the loop bandwidth For example, in IS-54, a division ratio of approximately 30,000 is required to generate a 900-MHz output from a 30-kHz reference. Consequently, at small frequency offsets the reference and PD noise floor is raised by 20 log 30000 ~ 90 dB [16]. 8.3.2 Fractional-N Architecture In the integer-N architecture, the loop bandwidth is limited because the input reference frequency must be equal to the channel spacing, This, in turn, results from the property that the output frequency changes by only integer multiples of frer. In “fractional-N” synthesizers, on the other hand, the output frequency can vary by a fraction of the input frequency, allowing the latter to be much greater than the channel spacing. Before studying the fractional-NV architecture, we make an observation. Suppose, as shown in Fig. 8.37(a), a pulse is removed every Tp seconds from a periodic signal x() that has a frequency fi. The resulting waveform, y(s), then exhibits f;.7p — 1 pulses every Tp seconds, ie., y(f) has an “average” frequency equal tof — 1/Tp. This method can be used to vary the average frequency of a signal by small steps. We should note, however, that y(t) is not a strictly periodic signal. In fact, y(t) can be viewed as the product of 2(f) and a rectangular waveform r(t) with period Tp [Fig. 8.37(b)], displaying sidebands at f, + k/Tp. The idea of removing pulses nevertheless proves useful in fine-step frequency synthesis.278 © Chap.8 Frequency Synthesizers Pulse Remover Har x(t) Pulse Remover ouent r(t) l ee eee —_ ———= ——— Tp 7 Te t @ (b) Figure 837 _(a) Periodic removal of a pulse from a periodic waveform, (b) removal viewed ‘as multiplication by r(t) Figure 8.38(a) shows a simple phase-locked fractional-N architecture. In addition to the PFD, LPF, and VCO, the loop incorporates a pulse remover, a circuit that blocks one input pulse upon assertion of the remove command. Since under locked condition the two frequencies presented to the phase de- tector must be equal, the average output frequency of the pulse remover equals frer,andhence fox: = farp +1/Tp, where Tp is the period with which the remove command is applied. Note that fou can vary by a fraction of frer because the frequency fp = 1/Tp can be derived from free by simple di- vision. Provided by a crystal oscillator, frzr is typically limited to a few tens of too Pulse Remover} Remove @) fout oe Figure 838 (a) Simple fractional-N synthesizer, (b) use of divider in the loop.Sec. 8.3. RF Synthesizer Architectures 279 megahertz. Thus, as shown in Fig. 8.38(b), fractional-N loops incorporate a divider in the feedback to generate high output frequencies. While the original fractional-N topology was based on the pulse re- mover concept [17], modern implementations of this architecture operate on a somewhat different principle. Depicted in Fig. 8.39, such a synthesizer re- places the pulse remover and the divider of Fig. 8.38(b) with a dual-modulus prescaler. If the prescaler divides by N for A output pulses (of the VCO) and by N +1 for B output pulses, then the equivalent divide ratio is equal to (A+ B)/[A/N + B/(N + 1)]. This value can vary between N and N +1 in fine steps by proper choice of A and B. The resulting modulus is sometimes written as NV. f, where the dot denotes a decimal point and N and f represent the integer and fractional parts of the modulus, Modulus Control Figure 8.39 Fractional-NV synthesizer using a dual-modulus divider. As an example, consider the circuit in Fig. 8.40, where fgzp = 1 MHz and N = 10, Letus assume the prescaler divides by 10 for 9 reference cycles and by 11 for one reference cycle. The total number of output pulses is therefore equal to 9 x 10+ 11 = 101, whereas the reference produces 10 pulses. In other words, the divide ratio is equal to 10.1 and fy: = 10.1 MHz. tree © Fout Modulus Control TT Tree, —— 7 Tree Figure 8.40 Example of « fractional-N' synthesizer,280 Chap. 8 Frequency Synthesizers With fger in the range of tens of megahertz, the loop bandwidth of a fractional-N synthesizer can be as high as a few megahertz, yielding a fast lock transient as well as suppressing the VCO close-in phase noise. Furthermore, the smaller division ratio lowers the effect of the reference and PD phase noise. Fractional Spurs Fractional-N synthesis suffers from a critical draw- back: “fractional spurs.” To understand the issue, let us examine the inputs and the output of the phase detector in Fig. 8.40. The analysis can be simplified ifwe first assume the VCO is disconnected from the LPF and its control voltage is set such that fou: = 10.1 MHz. As shown in Fig. 8.41, each of the first nine cycles of the divided signal is slightly shorter than the reference period. Con- sequently, the phase difference between the reference and the feedback signal grows in every period of gp. until it returns to zero when divide-by-11 oc- curs, Thus, the phase detector produces progressively wider pulses, creating a ramp waveform at the output of the LPF. From the above observation, we conclude that if the VCO output is to be equal to (N + @) faer. (eg. @ = 0.1 in Fig. 8.40), then the output of the LPF will be a repetitive ramp waveform with a period 1/(afger). If the loop were closed, such a waveform would modulate the VCO, creating sidebands at fare. 2afgep. etc. with respect to the center frequency. Such sidebands are called fractional spurs. From another point of view, since the feedback signal is not strictly periodic and hence contains significant sidebands, the mixing operation in the phase detector translates the sidebands to the vicinity of zero frequency. It is interesting to note that if the loop is closed, the LPF output is no longer a linear ramp waveform: as this voltage increases, the VCO period decreases and hence the phase difference between fgrr and fou grows faster than a linear function of time. ‘The problem of fractional spurs is a serious one, Since the phase differ- ence between the feedback and reference signals grows to significant values, the amplitude of the LPF output waveform is quite large, yielding fractional spurs typically only 20 to 30 dB below the carrier magnitude. Consequently, various methods of suppressing the spurs have been devised [17, 2]. Returning to Fig. 8.41, we note that the increment in the phase difference in every reference peri well defined. If four = (N +) frer. then the pe- riod of the feedback signal is equal to (1+-a/) far. giving aphase increment of a/{(N +@) frer] (in seconds). In other words, the current pulse generated by the charge pump grows in width by «/[(NV + a) free] seconds on every phase comparison instant. Thus, if another current pulse train with the same width and opposite sign is injected to the low-pass filter, the disturbance on the VCO control line can be minimized, This is called “fractional compensation.” ‘The above observation may suggest that the compensation current can be generated by simply a second charge pump driven by the same phase281 solouonboyy snoauen sazsamputs fenboun jo 199 Trg andy Sec. 8.3. RF Synthesizer Architectures su 0004 TLE LL LI vu su 0601 LE LD LD LA LI couse su 066 PLL LLL LPL li xe Li-Aq-apiaig. O3A282 Chap. 8 Frequency Synthesizers detector. However, itis important to understand the ultimate goal of fractional compensation. In fact, the reader may wonder what each phase comparison accomplishes if the two currents injected into the filter exactly cancel each other. If that were the case, choosing a high reference frequency and hence comparison rate would not lower the close-in phase noise of the VCO. In reality, the pulse generated by the phase detector experiences small random variations in width, reflecting the phase noise of the oscillator. Thus, the compensation current must be derived from a stable, low-noise source rather than the output, of the loop phase detector—so as to cancel only the deterministic component of the charge pump output. ‘The principal shortcoming of fractional compensation is the inaccuracy resulting from mismatches, Since the amplitude and width of the compensation current suffer from a finite mismatch with respect to those of the main charge pump, a residual disturbance on the VCO control line remains, For this reason, external adjustments may be necessary [18]. Another approach to suppressing fractional spurs is to randomize the choice of the modulus such that the average division factor is still given by N + a, but individual division factors occur for only short periods of time. This technique in effect converts the systematic fractional sidebands to random noise (Fig. 8.42). The idea can be taken one step further by shaping the resulting noise spectrum such that most of its energy appears at large frequency offsets (Fig. 8.43). Thus, the noise in the vicinity of the divided carrier is sufficiently small and the noise at higher offsets is suppressed by the low-pass filter after the feedback signal is translated to de by the phase detector. ToPD From VCO Figure 8.42 Randomization of modulus control to suppress spurs The noise-shaping function required in the above scheme can be realized by means of a E-A modulator [19]. Depicted in Fig. 8.44, the modulator generates a binary stream (in the case of dual-modulus divider) representing a well-defined average value accompanied by quantization noise. We perform a simple analysis to better understand the operation [19]. Suppose the divider has two moduli, V and N +1, and must provide an average modulus equal to N +a. With the binary modulus control, b(*), gen- erated by the ©-A modulator, the instantaneous division ratio can be written as N + b(t), where b(t) assumes a value of 0 or 1. Thus, the instantaneous frequency of xp(t) is fr(t) = fou/[N + 6(2)]. ‘The bit stream b(t) can beSec.8.3 RF Synthesizer Architectures 283 ToPD From VCO. > A Randomization free f free # and Noise Shaping Figure 8.43 Noise shaping in modulus control decomposed into an average value equal to and quantization noise q(t), thereby yielding f(t) = four/[N +e +q(0)]. It follows that the quantization noise in fp (t) is equal to nt) = fr(t) — (8.44) Nita fout qt) ot. 8.45) N+a N+a+q@) ee) Assuming g(f)/(N +a) < 1 and a < N, we find the power spectral density of the noise as, ou |OCA)P Sup F) = Wea we (8.46) where Q(f) is the spectrum of g(t) [19]. Thus, the quantization noise in the frequency of the feedback signal has the same spectral shape as Q(f). The Z-A modulator generates a well-defined shape for Q(f), concentrating the noise at high frequencies. Other fractional-N techniques are described in [20,21]. To PD From VCO b(t) Modulator Figure 8.44 Noise shaping by means of a B-A modulator284 © Chap.8 Frequency Synthesizers 8.3.3 Dual-Loop Architectures The relationship between the channel spacing and the reference frequency 0 integer- NV phase-locked synthesizers can he altered by employing two or mor loops. In this section, we study two dual-loop topologies and their design issue: A straightforward approach to generating fine frequency steps is to ad: a variable low frequency to a fixed high frequency. Shown in Fig. 8.45, thi technique utilizes PLL to generate the carrier frequency. f-, from a referene faeri and PLL» to produce increments equal to fgef2. Varying the divisio Frequency Adder Teer | rus Meer <> Channel Selection f+ M Frere @ Channel Selection (b) Figure 8.45 (a) Dual-loop synthesizer, (b) implementation of (a).Sec. 8.3 RF Synthesizer Architectures 285 ratio of PLL2 therefore yields the fine steps required in the output frequency, Note that frei can be several tens of megahertz. The addition of the two frequencies is performed by a single-sideband mixer (Chapter 7). The principal advantage of this architecture over single-loop integer-N topologies is that the close-in phase noise of VCO, is suppressed by the wide loop bandwidth because fgr ri is much greater than the channel spacing. The phase noise of VCO, can be much lower than that of VCO, because the former operatesat a much lower frequency. From the analysis of phase noise in Chapter 1, for the same power dissipation and at a given offset, the phase noise of VCO, is approximately equal to (M fe r2)"/f2 times the phase noise of VCO,. The primary drawback of the architecture shown in Fig, 8.45 is the need for accurate single-sideband mixing. As explained in Chapter 7, this requires precise generation of quadrature phases in both PLL; and PLL, as well as low harmonic distortion for one of the frequencies to be added. Thus, it is difficult to ensure that sidebands resulting from mismatches and nonlinearities are 60 to 70 dB below the carrier. Another issue is that the frequency of VCO> must vary by a large factor: a ratio equal to the number of channels in the implementation of Fig. 8.45 Consequently, the VCO must achieve a wide tuning range. Furthermore, as the channel (i., the division ratio) changes, the loop gain and hence the damping factor of PLL vary substantially. This drawback can be alleviated if f has a large offset, i.e. fo = fo + kfrer2, where fy isa fixed value. Another dual-loop architecture is shown in Fig. 8.46(a). In contrast to the synthesizer of Fig, 8.45, in this circuit the SSB mixer is placed in the feedback loop. Thus, if the mixer produces the difference between fou and fs, we have fo = Mfreri + f2- An interesting property of this architecture is that the unwanted sidebands generated by the SSB mixer are suppressed if, after frequency division, their offset with respect to the desired sideband is greater than the bandwidth of the low-pass filter. This is illustrated in Fig. 8.46(b), 8.3.4 Direct Digital Synthesis Our study of frequency synthesis techniques thus far has assumed a phase- locking mechanism in the system so as to establish a precisely defined relation- ship between generated frequencies and reference frequencies, Direct digital synthesis (DDS) is another approach to achieving the same goal, with certain advantages and disadvantages with respect to phase locking, ‘The basic idea in DDS is to generate the signal in the digital domain and utilize D/A conversion and filtering to reconstruct the waveform in the analog domain. To understand the principle of operation, first consider the simple circuit depicted in Fig. 8.47(a). A counter counts from 0 to N in steps of unity, generating a digital ramp waveform, Each number generated by the counter is then used to select a value from the ROM that corresponds to a sample of a sinusoid. The result is subsequently converted to analog form and filtered to suppress high-frequency components.286 © Chap. 8 Frequency Synthesizers tery Figure 846 (a) Dual-loop architecture with SSB mixing inthe feedback, (b) suppression of sideband Figure 847 (a) Simple digital synthesis of a sine wave, (b) increasing the output frequency by sampling fewer points.Sec.83 RF Synthesizer Architectures 287 Now suppose the output frequency must be varied while the clock has a fixed frequency fox . We postulate that if the counter addresses fewer (evenly spaced) points of one cycle of the sinusoid, then the output frequency is higher and vice versa [Fig. 8.47(b)]. This is possible if the counter increments its output by a programmable step, P. Such a counter can be implemented as an accumulator (Fig. 8.48), where a parallel-in, parallel-out M-bit register drives an adder in a feedback loop. On every clock cycle, a value equal to P is added to Yx, and the result is applied to the register, ie., Xg(k) = ¥e(k — 1) + P This relation holds until the register overflows, at which point part of P appears as an increment in the new value of ¥p, ic., Xe(k) = ¥e(k — 1) + P modulo ae , m4 [ren oe} cK M Bits Wide Figure 8.48 Direct digital synthesis using an accumulater. Let us consider an example to better understand the above operation Shown in Fig. 8.49 are the outputs of the accumulator and the ROM for M = 3. Ifthe increment, P, is equal to 1 [Fig. 8.49(a)], then as the register output goes from 000 to 111, one complete eycle of a sinewave is extracted from the ROM. In other words, each clock period increments the output phase by 27/8, Now, if P. isincreased to 2 [Fig. 8.49(b)], the accumulator overflows after 110, every other sample of the sinewave is read from the ROM, and the output phase changes in steps of 27/4. For P the accumulator output begins from 000 and overflows at 110, 111, and 101 in the first, second, and third cycles, respectively. Thus, as shown in Fig.8.49(c), three cycles of a sinusoid are produced by eight uniformly spaced samples. Finally, for P = 4, four cycles of the sinusoid are generated by Nyquist-rate sampling [Fig. 8.49(4)]. From the above analysis, we infer that the frequency of the sinewave generated in Fig. 8.48 is fex Fou = Pairs (8.47) noting that P/2™ need not be an integer. The minimum and maximum values of four are equal to fox /2™ and fcx /2, respectively. ‘The M-bit word applied to the ROM selects a value for the amplitude of the sinusoid. How many bits wide should the ROM output be? Since the288 Chap.8 Frequency Synthesizers P= ROM Output Accumulator; ‘Output © @ Figure 849. Waveforms in a 3-bit DDS. ROM output approximates the amplitude, the number of bits determines the “quantization error” in the reconstructed sinewave. It is interesting to note that in DDS the ratio of fox and fou is a rational number, 2” /P, making the quantization error appear as a periodic additive term rather than random noise. In fact, a period equal to 2” /fcx accommodates 2 clock cycles and P output cycles. Thus, for odd P the quantization error period is equal to 2 /fex and for even P, equal to 2~J/fcx, where j denotes the power of 2in P. The resulting error waveform and its harmonics appear as spurs in the output spectrum. It can be shown that the worst-case power of these spurs relative to the signal power is approximately equal to 2~*"*-") /3 [22], where it isassumed fcx = 2 four. For k = 12 bits, the spurs are about 71 dB below the carrier. The foregoing discussion indicates that in typical RF applications, the ROM output must have a resolution in the range of 10 to 12 bits, imposing a lower bound on one dimension of the ROM. The other dimension of the ROM is determined by the phase steps required in generating the sinusoid. Equation (8.47) suggests that increasing M yields arbitrarily small steps in the ‘output frequency—an important property of DDS. While the accumulator can be chosen to be relatively wide, the ROM may become prohibitively large. For example, if the widths of the accumulator and the ROM output words are 16Sec. 8.3 RF Synthesizer Architectures 289 bits and 10 bits, respectively, then the ROM requires 2'° x 10 © 6.55 x 10° cells, For this reason, the accumulator may still be designed with a wide output word so as to provide fine frequency steps, but only a limited number of the most significant bits of this word are applied to the ROM. If the ROM phase steps are not as small as those in the accumulator, a “phase truncation error” corrupts the output sinusoid. This type of error is also periodic, resulting in spurs whose worst-case power with respect to the carrier is equal to (28~'77)*, where B is the difference between the width of the accumulator output and the width of the ROM input [3]. Various techniques have been devised to reduce the size of the ROM. For example, only one quarter of a period of the sinusoid can be stored because the other three quarters can be obtained by virtue of vertical and horizontal symmetry. Other ROM compression methods are described in (23]. Direct digital synthesis offers a number of advantages over phase-locked architectures: (1) Avoiding the use of an analog VCO, DDS achieves a low phase noise—roughly equal to that of the clock. Since the clock frequency need not be variable, it can be derived from a crystal oscillator by means of a wideband phase-locked loop. Thus, the clock phase noise can be acceptably low. (2) DDS provides fine frequency steps. Increasing the word length in the accumulator reduces the relative value of the phase increment, albeit at the cost of more complexity. (3) DDS exhibits much faster channel switching than PLLs because it entails no analog feedback loop. (4) DDS can provide continuous-phase channel switching at the output, an important property in some modulation schemes. (5) DDS allows direct modulation of the output signal in the digital domain. Despite the above features, DDSsutffers from several drawbacks that have prevented its widespread use in the RF range. The primary issue is the speed: from Nyquist’s sampling theorem, the clock frequency must be at least twice the desired output frequency, 1.8 GHz in a 900-MHz system. In fact, to relax the LPF rejection requirements fcx is typically about three to four times fou. In today’s VLSI technologies, it is difficult to perform the operations shown in Fig. 8.48 at such speeds, especially if power dissipation is critical. Even if the digital section can be realized with acceptable complexity and power drain, the DAC remains the speed bottleneck. The trade-offs among the settling time, harmonic distortion, spurious response, and power dissipation of the DAC prevent its use in the RF range. ‘The low phase noise of DDS makes it attractive for use as the low- frequency generator in the dual-loop architectures of Fig, 8.45 and 8.46, re- placing the slower PLL. In this case, however, two issues must be considered. First, if the high-frequency VCO is on the same chip as the DDS circuits, the substrate and supply noise produced by the accumulator and the ROM may significantly corrupt the VCO output. Second, phase and gain mismatches in the SSB mixer still yield relatively large unwanted sidebands.290 Chap. 8 Frequency Synthesizers 8.4 FREQUENCY DIVIDERS In the study of frequency synthesizers and quadrature generation techniques, wwe have seen the need for frequency dividers, also called prescalers. In addi- tion to speed and power dissipation, the phase noise of dividers is also critical for it corrupts the feedback signal in synthesizers. While the phase noise of di- viders has been studied to some extent [24], analysis of this effect in monolithic implemenations requires further work. In this section, we describe a number of divider topologies often used in RF systems. 8.4.1 Divide-by-Two Circuits Divide-by-two circuits (DTCs) are widely used to produce quadrature outputs. Moreover, since they achieve a higher speed than dividers with other division factors, DTCs may follow a VCO in a phase-locked loop to lower the fre- quency to a range that can be applied to a programmable divider with small steps. Illustrated in Fig. 8.50, this remedy proves useful if the output frequency is comparable with the maximum speed of the technology, that is, if the pro- grammable divider cannot operate at fou but the DTC can. The drawback, however, is that fier must be halved so as to yield the same output frequency step as a loop containing no DTC free o [ Po | LPF vco fout <> Channel Selection Figure 8.80 PLL incorporating a divide-by-two circuit in feedback. As shown in Fig. 8.51(a), a divide-by-two circuit can be realized as two latches in a negative feedback loop. The implementation of the latches depends on the available type of transistors, buta current-steering topology consisting of a differential pair and a regenerative pair achieves a high speed in both bipolar and CMOS technologies [Fig. 8.51(b)]. Proper sizing of the transistors in this configuration results in a reasonable speed-power trade-off at gigahertz rates. ‘The divider configuration of Fig. 8.51 (a) provides quadrature phases at X and Y only if CK and CK are precisely complementary and the two latches match perfectly. Typical device mismatches result in phase imbalances as largeSec. 8.4 Frequency Dividers 291 @ () Figure 881 (a) Divide-by-1wo circuit, (b) implementation of each latch as 5°. Moreover, if CK and CK are not exactly differential, additional phase mbalance arises. A common example occurs when the divider is driven by an oscillator incorporating an off-chip resonator. As such, the oscillator usu- ally provides a single-ended output or heavily imbalanced differential outputs ‘Fig. 8.52). At high speeds, it is difficult to balance such outputs by means of additional differential pairs. Thus, the CK and CK phases applied to the divider still exhibit some phase mismatch. External Youtt Resonator Vourz Ves Figure 852 Oscillator with imprecise differential outputs, MOS current-steering latches can also be configured as shown in Fig. 8.53, However, the drain currents of the clocked transistors are not well defined, ‘esulting in unpredictable output swings. High-speed CMOS divide-by-two circuits can also incorporate dynamic atches. Figure 8.54 shows two examples. In the circuit of Fig. 8.54(a), the first ‘wo CMOS inverters operate as dynamic latches controlled by CK and CK, and the third inverter provides the overall inversion required in the negative292 Chap. 8 Frequency Synthesizers cK I-e oK Figure 853 Alternative MOS latch topology. feedback loop. Figure 8.54(b) is a divider based on the true single-phase clock- ing (TSPC) scheme [25], achieving a high speed. The drawback of both these circuits is the lack of precise complementary or quadrature outputs. Other CMOS frequency division techniques are described in [26, 27]. ,i. ) Figure 854 Dynamic CMOS dividers using (a) inverters, (b) TSPC. A high-speed divide-by-two method originally proposed by Miller is i Justrated in Fig. 8.55 [28]. Employing a mixer and a low-pass filter in a feedbackSec.84 Frequency Dividers 293 Joop, the circuit operates as follows. Upon multiplication of the input and out- put signals, the mixer generates components at fin + four and fin — fom. If the former is suppressed by the LPF but the latter is not, then fin — fout = fout and hence four = fin/2. The simplicity of the feedback loop has allowed this topology to operate at speeds exceeding half of the fr of its constituent devices [29], generally achieving the highest rate among all divider configurations. The Miller divider, however, is believed to suffer from substantial phase noise. fino—(X+] LPF Tout Figure 855 Miller divider. 8.4.2 Dual-Modulus Di Most phase-locked synthesizers incorporate high-speed dual- or multimodu- lus dividers. Such circuits divide the input frequency by one of the moduli according to a control input. A commonly used dual-modulus divider is a divide-by-23 circuit. We first consider a simple +3 circuit [Fig. 856(a)]. This divider employs two master-slave D-flipflops together with an AND gate to create only three states: Q:Q> = 01,10, L1. The state @,Q2 = 00 cannot occur (except at start-up) because it would require the previous values of Q2 and G to be ZERO and ONE, respectively, an impossible state. (@) (b) Figure 8.56 (a) Divide-by-3 circuit, (b) Divide-by-2/3 circuit294 Chap. 8 Frequency Synthesizers To convert the topology of Fig. 8.56(a) toa +2/3 circuit, we simply control Qy by interposing an OR gate between the first flipfiop and the AND gate. Shown in Fig. 8.56(b), this divider is configured as a +2 circuit when MC is high and a +3 circuit when MC is low. Divide-by-three circuits are generally much slower than their divide-by- two counterparts, In the circuit of Fig. 8.56(a), for example, following the clock edge on which Q2 must change, sufficient time must be allowed for the delay of G; and the input stage of F F> before the next clock transition. This can be seen in Fig. 8.57, where the transistor implementation of part of the circuit is shown, ‘The signal delay is nearly twice that in a simple +2 circuit. Furthermore, in Fig. 8.56(a) the output of F F; must drive the input capacitance of both G; and FF,. For these reasons, +3 circuits typically exhibit a maximum speed roughly half that of +2 circuits Figure 857 Implementation of part of divider shown in Fig. 8 56(b). Dual-modulus dividers with other moduli can be designed with a +2/3 or a +3/4 circuit serving as the core. For example, a +15/16 prescaler can be realized as depicted in Fig. 8.58. Here, FF;, FF:, G1, and Gy forma synchronous +3/4 circuit, dividing the clock frequency by four when MC is high and by three when both MC and M F are low. The asynchronous section consisting of FFs, F Fy, and Gs divides the output of FF; by four, and drives MF high when Q; Q, = 11. Thus if MC ishigh, the overall circuit divides the input frequency by 16. If MC is low, the circuit avoids the state 0000 because if 0; Oy = 00, the +3/4 circuit goes through only three states: 01, 10, 11. Note that the critical signal path in Fig. 8.58 now includes both G2 and Gy, mal the circuit slower than the divider of Fig. 8.56(b).Skip State Sec. 8.4 Frequency Dividers 295 Output Figure 88 | Divide-by-15/16 circuit. An important issue in employing both synchronous and asynchronous sections in Fig. 8.58 is potential race conditions when the circuit divides by 15. To understand the problem, first suppose F F; and F F, change their output state on the rising edge of their clock inputs. If MC is low, the circuit continues to divide by 16, that is, Q 2 goes through the cycle 01, 11, 10, 00 until both Qs and Qj are low. As depicted in Fig. 8.5%), Q1O> then skips the state 00 after the state 10. Since from the time Q3 goes low until the time Q1Q7 skips one state, three C Kin cycles have passed, the propagation delay through FF; and Gs need not be less than a cycle of CKin. a % % % a, @ G 0 0 4 0, Changein oo 7 f o 1 0 0 a o 1 4 1 1 1 0 oO 1 1 1 1 1 0 0 o Skip 1 oO o 0 o 1 1 1 State o 1 oO ° (a) (b) Figure 859 Delay budget in the circuit of Fig. 8.8 with FF; and FF, activated on (a) rising edge, and (b) falling edge of clock. Now consider a case where FF; and FF, change their output state on the falling edge of their clock inputs. Then, as shown in Fig. 8.59(b), immediately after 3 Q, has fallen to 00, the +3/4 circuit mustskip the state 00, mandating that the delay through FFs, FFs, and Gs be less than half of a CKin cycle. This is in general difficult to achieve, complicating the design and demanding higher power dissipation. Thus, the first choice is preferable.296 Chap. 8 Frequency Synthesizers REFERENCES [1] W. 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