POWER AMPLIFIERS Power amplifiers are typically the most power-hungry building blocks of RF transceivers. The design of PAs, especially for linear, low-voltage operation, remains a difficult problem, still defying an elegant solution. In practice, PA design has involved a substantial amount of trial and error—one reason why disorete or hybrid implementations of this circuit are favored. The goal of this chapter is to provide an understanding of the issues and challenges in PA design, particularly for portable applications, Following an overview of PA design considerations and operating classes, we study high- efficiency topologies such as class E and F circuits, Next, we describe the prob- Jem of large-signal impedance matching and analyze linearization techniques. Finally, we consider several design examples to further solidify the concepts presented in the chapter. 9.1 GENERAL CONSIDERATIONS 298 As the first step in our study, we consider a transmitter that delivers 1 W of power to a $0-@ antenna. The peak-to-peak swing, Vpp, at the antenna is then equal to 20 V and the peak current through the load equal to 200 mA. For acommon-source (or common-emitter) stage to drive the load directly, the configurations shown in Figs. 9.1(a) and (b) require a supply voltage greater than Vpp. However, if the current source in Fig. 9.1(b) is replaced with a large inductor [called a “radio-frequency choke” (RFC)], the supply voltage can be lowered by a factor of two because Vx can swing from approximately 0 to 2Vpp. In essence, the RFC approximates a current source that can sustain both positive and negative voltages. While allowing a lower supply voltage, the use of an RFC does not relax the “stress” on the active device, ie., the maximum drain-source voltage experienced by M;. Also, a Vpp greater than 10 V in this example still translates to a large number of batteries in portable systems,Sec. 9.1 General Considerations 299 Yoo Yoo Yoo A, RFC Fout x Vine mM, Vine my Ry Vino m, RA, @) ) o Figure 9.1 Common-source stages with different type of load connections. In order to deliver a power of 1 W to a 50-@ antenna at lower supply voltages, a matching network can be interposed between the PA and the load [Fig. 9.2(a)]. For example, as shown in Fig. 9.2(b), a lossless transformer with a turns ratio of 1:4 converts a 5-V pp swing at node X to a20-V pp swing at the output, From another point of view, the matching network transforms Ry 10a smaller value such that the limited voltage swing provided by the PA can still deliver the required output power. tt 162 @ oD) Figure 9.2 (a) Matching network as voltage amplifier, (b) use of a transformer as a matching network. ‘The need for transforming the voltage swings means that the current generated by the PA must be proportionally higher. In the example of Fig. 9.2(b), the peak current in the primary of the transformer exceeds 800 mA. Also, since M; must sink the currents flowing through both the RFC and the transformer when Vx * 0, the peak drain current is near 1.6 A. In practice, the efficiency may be less than 40%, implying a higher peak current through the output transistor. The enormous currents in the output device and the matching network are one of the difficulties in the design of power amplifiers and especially the package. If the peak current through the output transistor is several amperes, then the slew rate at 900 MHz is on the order of 10 A/ns. Thus, even a par- asitic inductance of 10 pH causes a 100-mV reduction in the voltage swing, Furthermore, parasitic inductances can introduce various resonances and even300 Chap.9 Power Amplifiers instability in the cireuit. Similarly, a series resistance of a few tens of milliohms in the transistor, the RFC, or the matching network may result in a consider- able loss, For these reasons, many layout and packaging issues that are usually unimportant in other analog and RF circuitsbecome crucial in power amplifiers. Itis interesting to note that, as with the input stage of LNAs, the output stage of PAs generally includes only one transistor, simply because the large currents would introduce much higher loss with more active devices in the signal path. Listed in Table 9.1 is the range of performance parameters available in PAs designed for portable systems. The efficiency of power amplifiersis defined by two metrics. The drain (or collector) efficiency, 7, is equal to the power delivered to the load (usually at the first harmonic) divided by the power drawn from the supply. The power-added efficiency (PAE) is the difference between the input and output powers divided by the supply power. If the PA has a relatively large power gain, then n * PAE. In addition to efficiency and, in some systems, linearity, the output spurs and harmonics of the PA must also satisfy the wireless standard and FCC constraints, TABLE 8.1 Typical PA performance. ‘Output Power +20 to +30 dBm Eificiency 30% to 60% IMD —30 dBe Supply Voltage 3.81058V Gain 20 to 30 dB Output Spurs and Harmonics —50 to —70 dBe Power Control (On-Off or 1-dB Steps Stability Factor pl ‘The output spurs and noise of the PA in the receive band are also criti- cal if the transceiver incorporates frequency-division duplexing with no offset between the transmit and receive time slots (Chapter 4). ‘This is because the finite isolation between the two bands in the duplexer leads to a significant feedthrough of the PA output to the LNA input [26]. Calculated from the noise figure and gain of the power amplifier, the output thermal noise must typically fall below —130 dBm/Hz so as to introduce negligible noise at the input of the LNA. Another feature required of power amplifiers in digital wireless standards is the control of the output power. For example, in TDMA systems such as IS— 54 and GSM, the PA is turned on and off periodically to save power. Also, as explained in Chapter 4, in IS-95 the output power must be variable in steps of 1dB.Sec, 9.2 Classification of Power Amplifiers 301 9.1.1 Linear and Nonlinear PAs In Chapter 3, we explained why the linearity of PAs becomes important with certain modulation schemes, e.g., "/4-OPSK. The issue is spectral regrowth and ultimately adjacent channel power. For example, in IS-54, the total integrated power in the adjacent channel must be at least 26 dB below that in the main channel {1}. Furthermore, nonlinearity in a dynamic system may lead to AM- PM conversion [2], corrupting the phase of the carrier. The nonlinearity of PAs is usually characterized by a two-tone test. As shown in Fig. 9.3, two equal-amplitude sinusoids with slightly different frequen- cies are applied to the circuit, and the resulting intermodulation products are measured at the output. For adjacent channel interference, the third-order IM components are important and for alternate adjacent channel power, the fifth- order products. Manufacturers usually specify the relative magnitude of the largest IM product when the main components at the output are 6 dB below full power [3]. For example, a 1-W power amplifier is characterized by adjust- ing the input level such that each tone at the output is at +24 dBm (in a 50-2 system). Ms Figure9.3 Two-tone test of a power amplifier. ‘The two-tone method, however, is not a realistic test of the behavior of PAs in some applications because it may not accurately predict the adjacent channel interference when a randomly modulated signal such as r/4-OPSK is applied. For this reason, the linearity of PAs must usually be assessed by measuring the spectral regrowth in response to a modulated waveform, Nev- ertheless, the two-tone test provides a rough measure that proves useful in the initial phases of the design. 9.2 CLASSIFICATION OF POWER AMPLIFIERS Power amplifiers have been traditionally categorized under many classes: A, B,C, D, E, Fete. [4]. An attribute of classical PAs is that both the input and output waveforms are considered sinusoidal, As we will see in Section 93, if this assumption is avoided, higher performance can be achieved. In this section, we briefly describe classes A through C, emphasizing their merits and drawbacks with respect to a portable environment.302 Chap.9 Power Amplifiers 9.2.1 Class A and B PAs ‘Class A amplifiers operate linearly across the full input and output range. Among the three one-transistor amplifier configurations, the common-source (miter) topology provides the highest efficiency: in common-gate (base) cir- cuits, the output current equally flows through the input network, introducing a substantial loss, and in common-drain (collector) stages, a bias current in ad- dition to the load current is required, lowering the efficiency by approximately a factor of 2 Shownin Fig. 9.4 are bipolarand FET versions of a class A amplifier. How do we define linear operation here? Ifthe operating point of the transistor does not change “significantly,” then the circuit can be considered linear, But if the device is to deliver several amperes of output current, what bias current should be chosen to ensure sufficient linearity? This is where the definition of class A becomes vague. Signal Current Bias _ Current @ ©) Figure 9.4 Class A stages using (a) MOS device, (b) bipolar transistor. The circuit of Fig, 9.4(b) can be driven by a current source so as to achieve ahigher linearity owing to the weak dependence of 8 upon the bias current [4]. For example, a transformer can convert the source impedance to a high value to approximate a current source [4]. The difficulty, however, is that the substantial base-emitter capacitance of the transistor shunts the input current, and the variation of this capacitance with the collector current, given by Cp = &mtr, introduces nonlinearity. Another issue is that the collector-emitter breakdown voltage is lower when the base is driven by a high impedance. To calculate the maximum drain (collector) efficiency of class A ampli- fiers, we note that (1) if the drain (collector) voltage in Fig. 9.4 is a sinusoid having a peak-to-peak voltage of approximately 2Vpp, then the power deliv-Sec. 9.2 Classification of Power Amplifiers. 303 ered to the matching network is equal to Vj y/(2Rin), and (2) for Vx to reach 2Vpp, the RFC must provide a current of Vp /Rin. Since the RFC current is, relatively constant, the power drawn from the supply equals Vj,p/Rin- Thus, the maximum efficiency is equal to 50%. The above calculation entails an interesting point. In Fig. 9.4, as Vx swings from 2Vpp to Vpp to near zero, the current of the transistor varies from zero to 2Vpp/ Rin. In other words, Vy can reach 2Vpp only if the transistor turns off; that is, the peak efficiency is 50% only if substantial nonlinearity is acceptable. This contradicts the general notion that class A stages are linear, leading to efficiencies less than 40% in practical designs. Class A stages are also said to have a “360° conduction angle” because they are on for the entire cycle. Note that the output stage dissipates maximum power when the RF input signal is zero ‘The efficiency of class A amplifiers at lower signal levelsis also of interest. Recall from Chapter 4 that in IS-95, for example, the output power varies so as tosave battery energy and minimize interference with other users, In the circuit of Fig. 9.4(a), if the transistor is biased at a current Vpp/Rin, the power drawn from the supply is equal to V3,)/ Rin regardless of the power delivered to the load. The efficiency therefore decreases as 7 = V2,/(2V3,)). Consequently, the bias current of the transistor must be reduced at low signal levels to conserve battery energy, Class B amplifiers achieve a higher efficiency than class A stages by incor porating two parallel sections each of which conducts for only 180°. A familiar example is the push-pull stage of Fig. 9.5, commonly used in low-frequency power amplifiers [5]. Here, as Vi: becomes more positive, Q; provides the output current, while Q» is nearly off. Similarly, as Vi, drops, Qy conducts while Q; carries little current. Intuitively, we note that the efficiency is higher here because the supply current always flows through the load, whereas in the class A stage of Fig. 9.4, the supply current flows through only the transistor for part of the cycle. Figure 95 Push-pull output stage.304 Chap.9 Power Amplifiers The lack of high-speed p-type devices in most bipolar and FET tech- nologies prohibits the use of the push-pull configuration of Fig. 9.5 in the RF range, Furthermore, the base-emitter voltages of Q and Q2 limit the output swing, lowering both the available power and the efficiency. Alternatively, two n-type devices can be configured so as to sense a differential input and drive a differential-to-single-ended converter. Shown in Fig. 9.6 is an example [4], where the drain currents of My and Mp are combined by transformer 7), thus driving the single-ended load. Figure 9.6 Class B stage using a transformer. ‘To compute the maximum efficiency of the class B stage shown in Fig. 9.6, we note that the maximum voltage swing at X and Y is equal to 2Vpp and the equivalent resistance seen between each of the nodes and Vpp equal to n?R,,, where nis the transformer turns ratio. Thus, the total input power of 7; is given by Pi, = V3p/(2n?R,). Also, the average current drawn from Vpp is given by 2 fT? Vpp Ipopave = =f @R, sin otdt, (9.1) where the factor 2 accounts for the two half-sinusoidal currents pulled by My and Mp, It follows that Ipp.avy = 2Vpp/(an?R,) and hence the average power drain is Peupy = 2Vjp/(en? Ry). The maximum efficiency is therefore equal to 7 = Pin/Paupp = 77/4 * 79%. Note that this derivation assumes 7; exhibits n0 loss. As their class A counterparts, class B amplifiers require substantial vari- ation in the bias currents of the transistors in order to achieve the maximum efficiency, thereby facing severe linearity issues. It is interesting to note that class B stages such as the circuit of Fig. 9.5 are commonly employed in high- performance audio power amplifiers because they can be embedded in a high- gain feedback loop so as to minimize the distortion, In the RF range, on the other hand, it is difficult to achieve the same effect because a high loop gain typically necessitates multiple stages, leading to serious stability problems.Sec. 9.2. Classification of Power Amplifiers. 305 Another important drawback of the class B amplifier shown in Fig. 9.6 is the need for a low-loss high-frequency transformer. The high currents flow- ing through the primary of 7; can introduce considerable resistive dissipation, lowering the overall efficiency. A similar, but less severe problem exists in the single-ended to differential conversion required at the input of the circuit We should point out that the term class B is also applied to half of the circuit shown in Fig, 9.6, ic., a common-emitter (source) stage conducting for half of the cycle (180° conduction angle). Such a circuit is quite nonlinear, but its efficiency is still equal to 77/4 if the output voltage waveform is assumed to be a sinusoid. 9.2.2 Class C PAs In the class B amplifier studied above, we noted that each transistor conducts for half of the carrier period. In class C stages, the output transistor is on for less than half cycle so as to improve the efficiency. The class A stage of Fig. 9.4 can be modified to operate in class C. Shown in Fig. 9.7, the circuit is biased such that Mj turns on if Vin > |Vo| + Vr. where V, isa negative voltage. In other words, the transistor stimulates the output with a narrow current waveform in each cycle, The matching circuit usually includes some filtering to suppress the harmonics . Yoo RFC S Vine AL Figure 9.7 Class C stage. The distinction between class C and one-transistor class B stages is in the conduction angle, @. As @ decreases, the transistor is on for a smaller fraction of the period, thus dissipating less power. For the same reason, however, the power delivered tothe load also decreases. If the current drawn by the transistor is assumed to be a piece of a sinusoid and the output voltage a sinusoid with a306 Chap.9 Power Amplifiers peak voltage equal to Vpp, then the efficiency can be calculated as a function of @. From [4], the efficiency is given by 1 6 — sind ae a ; = 4 sin(@/2) — 0/2.c0s(/2) 3 varying from 50% for @ = 360° (class A) to 79% for @ = 180° (class B) to 100% for 6 = 0 (class C). ‘The maximum efficiency of 100% is often considered a prominent feature of class C stages. However, another attribute that must also be taken into account is the actual power delivered to the load. From [4], @ — sine 1 = cos(6/2)" This quantity drops to zero as the conduction angle vanishes. In other words, a class C stage exhibits a high efficiency only if it delivers a fraction of the peak output power. For this reason, true class Cis not suited to portable transceivers, where the efficiency at full output power is of greatest concern. Pout % (9.3) 9.3 HIGH-EFFICIENCY POWER AMPLIFIERS ‘The main premise in class A, B, and C amplifiers has been that the output tran- sistor current and voltage waveforms are sinusoidal (or a section of a sinusoid), thus limiting the efficiency of classes A and B and the output power of class C. In reality, the existence of higher harmonics in these waveforms can be exploited to improve the performance. Class A Consider the class A stage shown in Fig. 9.4. While our anal- ysis in Section 9.2 assumed the drain current and voltage are sinusoidal, in practice the large-signal operation introduces some harmonics. Now suppose the matching network is designed such that its input impedance is low at the fundamental and quite high at the second harmonic. Then, the drain voltage exhibits sharper edges than a sinusoid does, raising the efficiency. This is be- cause sharper transitions reduce the time in which the transistor carries a large current while sustaining a large voltage. It is interesting that the above modification need not increase the har- monic content of the signal delivered to the load. The technique simply utilizes different termination impedances for different harmonics to make the drain voltage approach a square wave—although in practice the matching network becomes quite complex and lossy if it is to provide given impedances at more than one or two harmonics As an example, consider the class A circuit shown in Fig. 9.8(a), where Ly, C;, and Cy form a matching network that transforms the 50-Q load to Z,=924 jOat f = 850 MHzand Z, = 3302+ jOat2f = 1.7 GHz [7]. Figure 9.8(b) shows the simulated drain voltage. The circuit delivers a power ofSec.9.3. High-Efficiency Power Amplifiers 307 ) Figure 9.8 (a) PA with high harmonic termination, (b) drain voltage waveform. 2.9 W to the load with 73% efficiency and a third-order distortion of ~25 dBe [7]. Other considerations for harmonic termination are described in [8]. Class E Class E stages are nonlinear amplifiers that achieve efficiencies approaching 100% while delivering full power, a remarkable advantage over class C circuits. Before studying class E PAs in detail, we first revisit the simple circuit of Fig. 9.2(a), shown in Fig. 9.9. Figure 9.9 Switching output stage. Suppose in this circuit the transistor operates as a switch, rather than a voltage-dependent current source, ideally turning on and off abruptly, Called a “switching power amplifier,” such a circuit achieves a high efficiency if (1) M, sustains a small voltage when it carries current, (2) M, carries a small current when it sustains a finite voltage, and (3) inevitable transition times between on and off states are minimized [9]. From (1) and (3), we infer that the on-resistance of the switch must be very small and the voltage applied to the gate of M; must approximate a rectangular waveform. However, even with308 Chap. 9 Power Amplifiers these two conditions, (2) may still be violated if when M; turns on, Vy is high. Furthermore, in practice it is difficult to obtain sharp input transitions at high frequencies. Tt is important to recognize the fundamental difference between the PAs studied in previous sections and the switching stage of Fig. 9.9: in the former, the output matching network is designed with the assumption that the transis- tor operates as a current source, whereas in the latter, this assumption is not necessary, If the active device is to remain a current source, then the minimum, value of the drain (collector) voltage must be precisely controlled such that the transistor does not enter the triode region (saturation region in the case of bipolar devices), This requirement makes the efficiency a sensitive func- tion of the supply voltage, the component values, and the Q of the matching network. Furthermore, the minimum voltage that the transistor must sustain translates to limited efficiency even if all of the devices and waveforms are ideal. By contrast, in switching amplifiers the minimum drain (collector) voltage can approach zero (although heavy saturation of bipolar devices results in other undesirable effects [9].) Class E amplifiers deal with finite input and output transition times by proper foad design. Shown in Fig. 9.10, a class E stage consists of an output transistor M;, a grounded capacitor Cy, and a series network C) and Ly. The RFC has a high impedance at the frequency of operation and C; includes the drain junction capacitance of Mj [9]. ‘The values of C1, C2, Li, and Ry, are chosen such that Vx satisfies three conditions (Fig. 9.11): (1) as the switch turns off, Vy remains low long enough for the current to drop to zero, (2) Vx reaches zero just before the switch turns on, and (3) dV /d? is also near zero when the switch turns on, We examine these conditions to understand the properties of the circuit. Yoo RFC: My Vout Vine—| 7 A, Figure 9.10 Class E stage. ‘The first condition, guaranteed by C, resolves the issue of finite fall time at the gate of the transistor. Without C;, Vx would rise as Via dropped, introducing substantial power loss in My. ‘The second condition ensures that the voltage across and the current through the switch do not overlap in the vicinity of the turn-on point, thusSec.9.3 High-Efficiency Power Amplifiers 309 Ip Vy /dt r @ tb) Figure 9.11 Voltage and current waveforms in a class E stage. minimizing the power loss in the transistor even with finite input and output transition times The third condition lowers the sensitivity of the efficiency to violations of the second condition, That is, if component or supply voltage variations introduce some overlap between the voltage and current waveforms, the effi- ciency degrades only slightly because d Vy /dt = 0 means Vy does not change substantially near the turn-off point. ‘The implementation of the second and third conditions is less straight- forward. After the switch turns off, the load network operates as a damped second-order system (Fig, 9.12) [9] with initial conditions across C, and C; and in Ly. The time response depends on the Q of the network, appearing as shown in Fig. 9.12 for underdamped, overdamped, and critically damped conditions. We note that in the last case, Vx approaches zero volt with zero slope. Thus, if the switch begins to turn on at this time, the second and third conditions are met. xo ht T a Figure 9.12 Response of class E stage when the transistor turns off Class E stages exhibit a trade-off between efficiency and output harmonic content. For low harmonic distortion, the Q of the output network must be higher than that typically required by the second and third conditions. Addi- tional filtering can precede the load resistor, but at the cost of power loss in the filter [10]. Another property of class E amplifiers is the large peak voltage that the switch sustains in the off state, approximately 3.56Vpp — 2.56Vs, where Vs is the minimum voltage across the transistor [9]. With Vop = 3 Vand Vs = 200 mY, the peak exceeds 10 V, demanding a high transistor breakdown voltage. For design equations of class E stages, the reader is referred to [9].310 Chap.9 Power Amplifiers ClassF The idea of harmonic termination illustrated in Fig.9.8 for a lass Astage can be extended to nonlinear amplifiers as well. Ifin the generic switch- ing stage of Fig. 9.9 the load network provides a high termination impedance at the second or third harmonics, the voltage waveform across the switch exhibits sharper edges than a sinusoid, thereby lowering the power loss in the transistor. Such a circuit is called a class F stage [4, 11]. Figure 9.13 shows an example of the class F topology. The tank consisting of Ly and C; resonates at either 2 fin or 3 fin, boosting the second or third harmonic at X. As can be seen in Fig. 9.13, the voltage across the switch approaches a rectangular waveform as the third harmonic becomes stronger. Interestingly, if the drain current of M; isassumed to be a half sinusoid (i.e., half- wave rectified sinusoid), then it contains o third harmonic. In reality, however, the waveform exhibits some third-order distortion because the transistor I/V characteristic notably deviates from a square law. Figure 9.13 Class F stage, If the drain current of the transistor is assumed to be a half-wave rectified sinusoid, it can be proved that the peak efficiency of class F amplifiers is equal 10 88% for third-harmonic peaking and 85% for second-harmonic peaking [11]. 9.4 LARGE-SIGNAL IMPEDANCE MATCHING Power amplifiers usually employ a matching network between the output tran- sistor and the load. In a class A stage, if the transistor behaved as an ideal current source, the matching network would simply transform the load resis- tance to a lower value while presenting no reactive components. In practice, however, the output impedance of the active device is finite, exhibits both real and imaginary parts, and varies with the output voltage and current, Thus, a nonlinear complex output impedance must be matched to a linear load. While ‘we assume herein that the load is resistive and constant, in reality the impedanceSec. 9.4 Large-Signal Impedance Matching 311 of the antenna may both contain a reactive component and vary with the posi- tion of the transceiver with respect to external objects, Before dealing with the task of nonlinear impedance matching, let us first consider a simple case where the transistor is modeled as an ideal current source with a linear resistive output impedance [Fig. 9.14(a)]. An apparent contradiction that occurs here is that the maximum power transfer theorem mandates that R, = Ro, whereas our treatment in Section 9.1 requires that Ry be transformed to a small value, i, typically Ry « Ro. Which choice is logical here? If Ry, = Ro, two problems arise. First, the power delivered to Ry is equal to that dissipated in Ro, reducing the peak efficiency of a class A amplifier from 50% to 25%. In other words, maximum power transfer does not correspond to maximum efficiency. Second, if Ry is transformed to be as, high as Ro, the output power is quite small, unless a high supply voltage is used. For these reasons, in typical PAs, Ry, < Ro. eran tile (@) (b) + ub aa © Figure 9.14 Modeling of device output impedance with (a) linear resistance, (b) linear resistance and reactance, (c) simple matching network for (b). In the next step, suppose, as shown in Fig. 9.14(b), the transistor output impedance contains linear real and imaginary parts, Note that since the output transistor is typically several millimeters wide, the magnitude of Xo at high frequencies is relatively small. The matching network must therefore provide areactive component to cancel the effect of Xo. Fig. 9.14(c) illustrates a simple example where L; cancels Co, and C and L2 transform Ry, while resonating at the fundamental frequency. Now consider the general case of a nonlinear complex output impedance, A small-signal approximation of the impedance in the midrange of output volt- age can be used to obtain rough values for the matching network components, but modifying these values for maximum large-signal efficiency requires a great deal of trial and error, especially if package parasitics must be taken into ac- count. In practice, a more systematic approach called “load-pull measurement” is employed.312 Chap. 9 Power Amplifiers In a load-pull test, the output power is measured and plotted as a fune- tion of the complex load seen by the transistor [12, 13]. Since a complex load requires two axes, the plot actually appears as constant power contours on a complex impedance plane, for example, a Smith chart. Figure 9.15(a) shows a conceptual setup for load-pull measurement. A variable, precisely calibrated tuner operates as a matching network, presenting various complex impedances to the transistor according to a control input. With the aid of an automated system, the real and imaginary parts of Z; are gradually varied such that the power meter maintains a constant reading. The result is the contour corre- sponding to that power level [Fig. 9.15(b)]. In practice, as Z; varies so does Zin, necessitating the use of a second tuner between the signal generator and the transistor such that the impedance seen by the generator remains constant {and usually equal to 50 £2), Signal Generator Zin i 1 Impedance Control @ Impedance Plot for Py Impedance Plot for Po Zoot © Figure 9.15 (a) Load-pull test, (b) power contours on a Smith chart. If the power delivered to the input is constant, the output power increases as Z; approaches its optimum value, Zop:. This trend is accompanied by a narrower range for Zi, resulting in tighter contours and eventually a single impedance value, Zopi, a5 the output power reaches its maximum level, Prox In other words, the load-pull test systematically narrows down the values of Z1 so as to obtain both the maximum output power and the corresponding load impedance. Note the power contours also indicate the sensitivity of Poy with respect to errors in the choice of Z;.Sec.9.5 Linearization Techniques 313 ‘The load-pull technique has been widely used in power amplifier design, although it generally requires a computer-controlled setup with extremely pre- cise and stable tuners. This method, however, suffers from three drawbacks. First, the measured results for one device size cannot be directly applied to a different size. Second, the contours and impedance levels are measured at a single frequency and fail to predict the behavior at other frequencies. Third, since the load-pull algorithm does not necessarily provide peaking at higher harmonics, it cannot predict the efficiency and output power in the presence of multiharmonic termination. For these reasons, PA design using load pull data still entails some trial and error. In order to avoid complex test setups, the load-pull method can alterna- tively be implemented in circuit simulations [13]. Similar to the above pro- cedure, the load impedance is varied in small steps and constant power con- tours are constructed, eventually providing the value of Zo. Here, too, the procedure is lengthy and cumbersome unless the load variation is automated. Furthermore, such a simulation requires precise modeling of transistors [14], in particular their output impedance, whereas SPICE models do not accurately represent the output impedance of devices at high frequencies and under large variations of voltage and current. 9.5 LINEARIZATION TECHNIQUES, The need for linear power amplifiers arises in many RF applications. As ex- plained in Chapter 3, bandwidth-efficient modulation schemes such as filtered QPSK and /4-QPSK require linear PAs to minimize spectral regrowth. Fur- thermore, amplificrs that simultaneously process many channels may need to be linear enough to avoid cross modulation. This case occurs in “multicarrier” systems, for example, base station transmitters, cable television transmitters, and “orthogonal frequency-division multiplexing” (OFDM) applications [15] At present, most linear PAs designed for portable devices employ a class A output stage and exhibit efficiencies around 30% to 40%. To achieve a higher efficiency, it is possible to begin with a nonlinear PA and apply linearization techniques to the circuit. In the ideal case, this approach lowers the overall distortion to acceptable levels without significantly degrading the efficiency ‘The linearization techniques described in this section have occasionally been utilized in complex, expensive RF and microwave systems, but they have not yet found their way into low-cost portable terminals. This is because such methods generally complicate the design, require various adjustments, and be- come less effective as device characteristics change with the temperature and output power. Nevertheless, a basic understanding of these techniques and their limitations proves useful in PA design, especially as IC technologies af- ford higher levels of reproducible sophistication than is possible in discrete realizations,314 Chap.9 Power Amplifiers ‘An important drawback of many linearization methods is that they re- quire some linearity in the PA core, i., they are not effective if the output transistor operates as an ideal switch. ‘This issue is explained below. Further- more, each technique is suited to only some classes of amplifiers. 9.5.1 Feedforward A nonlinear power amplifier generates an output voltage waveform that can be viewed as the sum of a linear replica of the input signal and an error signal. A feedforward topology computes this error and, with proper scaling, subtracts it from the output waveform [16]. Shown in Fig. 9.16(a) is a simple example where the output of the main PA, Vy, is scaled by 1/Ay, generating Vy. The input is subtracted from Vy, and the resultis scaled by Ay and subtracted from Vig. We note that if Viz = Ay Vin + Vp, where Vp represents the distortion content, then Vy = Vin + Vp/Ay. yielding Vp = Vp/Ay. Vo = Vp, and hence Vo = AvVin. In practice, the two amplifiers in the circuit exhibit substantial phase shift at high frequencies, mandating the use of delay lines [Fig. 9.16(b)] such that A; compensates for the phase shift of the PA and A> for that of the error amplifier, The two paths leading from Viq to the first subtractor are sometimes called the “signal cancellation loop,” and the two from M and P to the second subtractor, the “error cancellation loop.” ‘The advantage of feedforward topologies over feedback methods is in herent stability even with finite bandwidth and substantial phase shift in each building block. This is particularly important in RF and microwave circuits be- cause inevitable poles and resonances at frequencies near the band of interest make it difficult to achieve stable feedback. Feedforward linearization nonetheless suffers from several shortcomings, First, the implementation of the analog delay elements requires passive devices such as microstrip lines, with the power loss of A> being especially critical. Second, the output subtractor must be realized using a low-loss component, ¢., a high-frequency transformer [17]. Third, the amount of linearization depends on the gain and phase matching of the signals sensed by each subtractor. It can be shown [17, 18] that if the two paths from Vi, to the inputs of the first subtractor exhibit a phase mismatch of Ag and a relative gain mismatch of AA/A, then the suppression of the magnitude of the IM products in Voue is, given by E (i -2(1+ SB) omae+ (14 SA). (94) Asan example, if AA/A = 5% and Ag = 5°, then E = 0.102, ie, feed- forward lowers the IM products by approximately 20 dB. The phase and gain mismatches in the error correction loop further degrade the performance.Sec. 9.5 Linearization Techniques 315 ©) Figure 9.16 (a) Simple feedforward topology, (b) addition of delay elements, The concept of feedforward can be extended to “nested loops” [19], wherein the topology of Fig. 9.16(b) is utilized as the main PA within another feedforward system. Of course, such a configuration is much more complex 9.5.2 Feedback While local and global feedback techniques are extensively used in high-speed circuits, they cannot be easily applied to RF power amplifiers. This is because, for a heavily nonlinear PA, a high loop gain must be achieved, a difficult task at high frequencies if loop instability due to various poles and resonances in the circuit is considered. Package parasitics, large transient currents, and inevitable feedback resulting from capacitive or magnetic coupling make power amplifiers prone to oscillation at different frequencies even without explicit feedback. ‘The two issues related to feedback, namely, insufficient gain and excessive phase shift, can be alleviated if most of the loop gain is obtained at fow frequen- cies. Ina transmitter, this is possible because the waveform processed by the PA in fact originates from upconverting a baseband or IF signal, Thus, if the PA output is downconverted, it can be compared with the original low-frequency signal in a negative-feedback loop. The concept is illustrated in Fig. 9.17(a), where the frequency translation required between the error amplifier Ay and316 Chap.9 Power Amplifiers PS ve sino.ot sin(@iot +8) Yon LPF ~ apreanle r Baseband , _| Q L., LO Quadrature Phases LPF r® Shifted =$ LO Quadrature Phases 0) Figure 9.17 (a) Feedback by frequeney translation, (b) Cartesian feedback. the PA is performed by the two mixers, In other words, the loop attempts to make Vp, a replica of Via, but at a different carrier frequency. Since the total phase shift through the mixers and the PA at high frequencies usually exceeds 180°, the excess phase, 9, is added to one of the LO signals so as to ensure stability. In transmitters incorporating upconversion of both 1 and Q signals, the PA output must be decomposed into quadrature phases before it is compared with the inputs [Fig. 9.17(b)]. In this form, the technique is called “Cartesian feedback” [20]. Cartesian feedback has not become a popular solution in portable sys- tems. The added complexity resulting from the feedback demodulator andSec. 9.5 Linearization Techniques 317 error amplifiers increases the power dissipation and cost of discrete imple- mentations (but it presents much less trouble in IC design). Moreover, the necessary value of @ in Fig. 9.17 varies with temperature, process parameters, and the output power level, making it difficult to guarantee stability. 9.5.3 Envelope Elimination and Restoration As mentioned in Chapter 3, any bandpass signal can be represented as v(r) = a(t) cos[wet + @(t)], that is, by an envelope a(r) and a phase (1). This observation leads to the idea of decomposing u(t) into an envelope signal and a phase-modulated signal, amplifying each separately, and combining the results at the end. Illustrated in Fig, 9.18(a), the concept is called “envelope elimination and restoration" (EER) [21]. ‘The input signal drives both an envelope detector (in the simplest case a diode detector) and a limiting stage, thus producing the a(t) PPAF ka(t) ) Figure 9.18 (a) Envelope elimination and restoration, (b) implementation of the output stage,318 Chap.9 Power Amplifiers envelope a(t) and the phase-modulated component b(t) = bo cos[eoct +(t)] ‘These signals are subsequently amplified and combined in the PA, as shown in Fig. 9.18(b). If transistor M; operates as a switch, then the current flowing through the RFC is a function of ka(#), thereby modulating the amplitude of the signal produced by M;. Note that envelope restoration is not possible if M, is a current source because a linear, time-invariant combination of ka(r) and [pi (t) cannot produce modulation, ‘The principal advantage of EER over feedforward and feedback tech- niques is that it requires no linearity in the PA core, allowing the output stage to be designed for maximum efficiency. However, it suffers from other draw- backs. First, the mismatch between the total phase shift and gain of the two paths in Fig. 9.18(a) must be maintained below an acceptable level, a difficult task because the two paths employ different types of circuits operating at vastly different frequencies. Second, limiters incorporating active stages such as dif- ferential pairs exhibit substantial AM-to-PM conversion at high frequencies (Chapter 7), corrupting the phase of b(t) in Fig. 9.18(a). Third, using ka(t) as the supply voltage of the output stage degrades the efficiency. For example, consider the topology shown in Fig. 9.19(a), where the error amplifier Aj forces Vx to track ka(t). Since the entire supply current of the PA output stage flows through Mz, this transistor dissipates a considerable amount of power. For this reason, the switching regulator of Fig. 9.19(b) is preferable. Here, the error amplifier controls the duty cycle of an oscillator that switches M between on and off states, ensuring that the average value of Vx equals ka(t). Neverthe- less, My must be an extremely wide device to dissipate negligible power in the on state. (Recall from calculations of Section 9.1 that resistances as low as a few tens of milliohms can significantly degrade the efficiency.) Also, C, must be large enough to provide the supply current when M; is off. Another undesirable effect in Fig. 9.18(b) is the variation of the drain junction capacitance of M; with ka(t). As a result, the phase of the signal produced by M; is corrupted by the envelope component. 9.5.4 LINC An interesting approach to avoiding amplitude variations in a PA system is “linear amplification with nonlinear components” (LINC) [22, 23]. Illustrated in Fig. 9.20, the idea is that a bandpass signal vig(¢) = a(t) cos[inet + $(1)] can be expressed as the sum of two constant-amplitude phase-modulated signals, v(t) = 0.5Vp sinfooct-+9 (1) +0(1)] and v2(t) = —0.5Vo sinfa.t + $() 6 ()], where 8(f) = sin-[a(t)/ Vo]. Thus, if u(r) and v2(t) are generated from Vin(t), amplified by means of nonlinear stages, and subsequently added, the output contains the same envelope and phase information as in vin(t).Sec. 9.5 Linearization Techniques 319 x RFC —tha, @ ka(t) ) Figure 9.19 Modulation of the PA output by (a) a low-frequency feedback amplifier, (b) pulse-width modulation. Realization of vy(f) and v2(¢) from vin(f) requires substantial complex- ity, primarily because their phase must be modulated by 8(¢), which itself is a nonlinear function of a(t). The use of nonlinear frequency-translating feed- back loops has been proposed [22, 24], but loop stability issues such as those Figure 9.20 Lincar amplification using nonlinear stages.320 Chap.9 Power Amplifiers in Fig, 9.17 limit the applicability of these techniques. Another approach [25] considers v(t) and v2(t) as u(t) = vj (t) cos(wet + $) + volt) sin(wet + $) (9.5) u(t) = —v7(t)cos(wet + ¢) + volt) sin(ot + 4), (9.6) where v/(t) = a(t)/2 and vg(t) = JV? —a2(t)/2. Since the nonlinear operation required to produce ug(t) can be performed at low frequencies (using either analog techniques or a look-up ROM), this method can simply employ quadrature upconversion to generate v;(t) and v2(t). In addition to complexity, LINC must deal with two other important is- sues. First, gain and phase mismatch between the two signal paths in Fig. 9.20 results in residual distortion [25]. Second, the output adder introduces signifi- cant loss because it must achieve a high isolation between the two PAs. While it may seem that the adder can assume a simple form such as that shown in Fig. 9.21, we note that if My and M; operate as switches, then the two phase- modulated signals corrupt each other's phases. Figure 9.21 Addition of the outputs of two PAs. 9.6 DESIGN EXAMPLES Most power amplifiers employ a two-stage configuration, with matching net- works placed at the input, between the two stages, and at the output (Fig. 9.22). Since the output stage typically exhibits a power gain of less than 10 dB, a high-gain driver is added so as to lower the minimum required input level. For example, if the PA must deliver +30 dBm (1 W), the circuit of Fig. 9.22 may provide a gain of 25 to 30 dB, allowing the input to be in the range of 0 to +5 dBm. The choice of the minimum input level depends on the driving ca- pability of the preceding stage—the modulator or the upconverter—but since PAs and modulators are often designed independently (and perhaps by dif- ferent manufacturers), the interface power value of 0 to +5 dBm has become quite common.Sec.9.6 Design Examples 321 Output Ny Driver Na Stage Na RL Matching Network } Figure 9.22. Typical PA system, ‘The input and output matching networks in Fig, 9.22 serve different pur- poses: Nj provides a 50-2 input impedance, while N3 amplifies the voltage swings produced by the output stage so as to deliver the required power to Ry, The 50-2 input impedance is necessary if the PA is designed as a stand-alone circuit that interfaces with the preceding circuit by means of external connec- tions. Also, ifa passive external filter is interposed between the modulator and the PA to suppress out-of-band harmonics and interferers, then the termination impedances seen by the filter must be equal to a standard value, 50 &, to avoid passband ripples or instability. ‘The matching network between the driver and the output stage in Fig. 9.22 is incorporated for practical reasons. Since the design usually begins with Joad-pull measurements on the output transistor, the source impedance that this device must see for maximum efficiency is determined when the design of, the output stage is completed. Thus, the driver must present such an output impedance, often necessitating a matching network. The use of N3 allows a modular design: first the output stage, next the driver, and last the interstage matching, with some iteration at the end. Without No, the driver and the output stage must be treated as a single circuit, substantially complicating the design procedure. Power amplifiers still lie in the realm of III-V technologies, particularly GaAs MESFETs, and recently, Gas and InP heterojunction bipolar transis- tors (HBTs). The higher product of the cutoff frequency and the breakdown voltage of III-V devices, the high mobility—and hence large current drive per unit width—and high-quality inductors and capacitors on semi-insulating sub- strates have made III-V technologies the dominant choice for high-eificieney PA design. It is not clear whether mainstream submicron CMOS processes can achieve a comparable performance, but they are under study for short-range applications such as local area networks. Shown in Fig. 9.23 is an example of a 900-MHz MESFET power amplifier developed in a hybrid technology [27]. Using a5.6-V supply, the circuit operates in class AB and delivers approximately +36 dBm. The design procedure begins with the output stage. From load-pull measurements, it is determined that for the dimensions chosen for M2 the optimum load resistance equals 4 2. The two-cell output matching network transforms the 50-2 load to this value; cell A produces Rigi = 10 &, and cell B yields Rigg = 4 2.322 Chap.9 Power Amplifiers Yoo RFC My Te Figure 9.23 Power amplifier reported in [27], The output stage exhibits an input resistance, Riss, of 2.7 @ and requires an input power of +23 dBm so that M; enters deep triode region. The in- terstage matching network transforms Rigs {0 Ring = 53 2, presenting the optimum load resistance to the driver for a power level of +23 dBm at a sup- ply voltage of 5.6 V [27]. The input matching network is designed in con- junetion with large-signal simulation of the input impedance of Mj, providing Rins = 50 2 ‘While designed for a 5.6-V supply, the power amplifier of Fig. 9.23 delivers a reasonable performance even with a 3.3-V supply: an output power of +31.5 dBm and an efficiency of approximately 50% [27]. Figure 9.24 shows another example of a 900-MHz PA design [10]. Im- plemented as a fully monolithic circuit in an 0.8-2m GaAs technology, the amplifier consists of a class F driver and a class E output stage. The driver incorporates two tanks in series, one tuned to the first harmonic and the other to the third, thus providing an approximation of a square wave at node X and hence shortening the switching transition times of M2. Unlike the class E stage of Fig. 9.10, the circuit of Fig. 9.24 employs a finite value for the load inductance of Mp, obviating the need for an external component but at the cost of more complex design [28]. The output network consists of the basic class E network and a parallel-series matching circuit, presenting the optimum load resistance to Mp. In reality, the two sections are designed as a single filter to relax the trade-offs between the loss and the Q of the transfer function. Operating from a 2.5-V supply, the power amplifier delivers an output power of 250 mW with a PAE of approximately 50%. Interestingly, the power Joss in the output matching network is about 1.5 times that in the output tran- sistor [10].Chap.9 References 323 Matching Class wore Load Figure 9.24 Power amplifier reported in [10]. Figure 9.25 shows a PA designed to operate in a dual-mode 900-MHz AMPS/CDMA system [29]. Shunt resistive feedback in each stage enhances the stability and linearizes the PA for CDMA operation. In the AMPS mode, the output stage operates with minimal quiescent current, thus achieving an efficiency of 55% while delivering +31.5 dBm. The output power and efficiency drop to +28 dBm and 35%, respectively, in the CDMA mode. Yoo Figure 9.25 Power amplifier reported in [29], REFERENCES [1] 1.S.Kenneyand A. Leke, “Power Amplifier Spectral Regrowth for Digital Cellular and PCS Applications,” Microwave J., pp. 74-92, October 1995. [2] S.A. Maas, Nonlinear Microwave Circuits, Norwood, MA: Artech House, 1988.