Chapter – 8 Microprocessor-10CS45

UNIT 8: I/O Interface – 2, Interrupts, and DMA

THE PROGRAMMABLE PERIPHERAL INTERFACE -82C55

The 8255 programmable peripheral interface (PPI) implements a general-purpose I/O interface to connect
peripheral equipment to a microcomputer system bus. The core's functional configuration is programmed by the
system software so that external logic is not required to interface peripheral devices.

Features
• Programmable peripheral Interface (PPI) 8255, is designed by Intel.
• The 8255 is a general purpose programmable I/O device interface used for parallel data transfer.
• It has 24 I/O pins which can be grouped in three 8-bit parallel ports: Port A, Port B, and Port C (Port C (u)
and Port C(L)).
• Each port has unique address and data can be read from or written to a port.
• The 8255 can be programmed in two basic modes:
– Bit Set/Reset (BSR) mode – is used to set or reset the bits in Port C
– I/O mode- further divided into 3 modes:
Mode 0: Simple Input/Output
Mode 1: Input/Output with handshake
Mode 2: Bi-directional I/O data transfer
• The function of I/O pins and modes of operation of I/O ports can be programmed by writing proper control
word in the control word register.
• 8-bit bidirectional system data bus with standard microprocessor interface controls
• Port A can operate in Mode 0,Mode1,Mode2 and Port B can operate in Mode 0& Mode1 only.

Functional Description

Figure 8.1: Functional block diagram of 8255

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Data Bus Buffer

This three-state bi-directional 8-bit buffer is used to interface the 82C55A to the system data bus. Data is transmitted
or received by the buffer upon execution of input or output instructions by the CPU. Control words and status
information are also transferred through the data bus buffer.

Read/Write and Control Logic

The function of this block is to manage all of the internal and external transfers of both Data and Control or Status
words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the
Control Groups.

( CS ) Chip Select. A “low” on this input pin enables the communication between the 82C55 and the CPU.

( RD ) Read. A “low” on this input pin enables 82C55A to send the data or status information to the CPU on the
data bus. In essence, it allows the CPU to “read from” the 82C55.

( WR ) Write. A “low” on this input pin enables the CPU to write data or control words into the 82C55A.

(A0 and A1) Port Select 0 and Port Select 1. These input signals, in conjunction with the RD and WR inputs,
control the selection of one of the three ports or the control word register. They are normally connected to the least
significant bits of the address bus (A0 and A1).

(RESET) Reset. A “high” on this input initializes the control register to 9Bh and all ports (A, B, C) are set to the
input mode. “Bus hold” devices internal to the 82C55 will hold the I/O port inputs to a logic “1” state with a
maximum hold current of 400mA.

82C55 BASIC OPERATION

CS WR A1 A0 Input Operation(READ)
RD
0 0 1 0 0 Port A to Data Bus
0 0 1 0 1 Port B to Data Bus
0 0 1 1 0 Port C to Data Bus
0 0 1 1 1 Illegal condition

CS WR A1 A0 Output Operation(WRITE)
RD
0 1 0 0 0 Data Bus to Port A
0 1 0 0 1 Data Bus to Port B
0 1 0 1 0 Data Bus to Port C
0 1 0 1 1 Data Bus to Control Word

CS RD WR A1 A0 Disable Function
1 X X X X Three State Data Bus
0 1 1 X X Three State Data Bus

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Ports A, B, and C

The 82C55A contains three 8-bit ports (A, B, and C).

Port A One 8-bit data output latch/buffer and one 8-bit data input latch.
Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer.
Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be
divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the
control signal output and status signal inputs in conjunction with ports A and B.

Group A and Group B Controls

The functional configuration of each port is programmed by the systems software. In essence, the CPU “outputs” a
control word to the 82C55A. The control word contains information such as “mode”, “bit set”, “bit reset”, etc., that
initializes the functional configuration of the 82C55A.

Each of the Control blocks (Group A and Group B) accepts “commands” from the Read/Write Control logic,
receives “control words” from the internal data bus and issues the proper commands to its associated ports.

Control Group A - Port A and Port C upper (C7 - C4)

Control Group B - Port B and Port C lower (C3 - C0)

The control word register can be both written and read as shown in the “Basic Operation” table. Figure 4 shows the
control word format for both Read and Write operations. When the control word is read, bit D7 will always be a
logic “1”, as this implies control word mode information.

Operational Description

Mode Selection

There are three basic modes of operation than can be selected by the system software:

Mode 0 - Basic Input/Output

Mode 1 - Strobed Input/Output
Mode 2 - Bi-directional Bus

Operating Modes

Mode 0 (Basic Input/output). This functional configuration provides simple input and output operations for each of
the three ports. No handshaking is required; data is simply written to or read from a specific port.

Mode 0 Basic Functional Definitions:

• Two 8-bit ports and two 4-bit ports

• Any Port can be input or output
• Outputs are latched
• Input are not latched
• 16 different Input/output configurations possible.
Mode 1 - (Strobed Input/output).

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• This functional configuration provides a means for transferring I/O data to or from a specified port in
conjunction with strobes or “hand shaking” signals.
Mode 1 Strobed Input:
• Port A and Port B to function as latching input devices.
• This allows external data to be stored into the port until the microprocessor is ready to retrieve it.
• Port C is used for control or “hand shaking” signals that help operate either or both Port A& Port B as
strobed input ports.
• Pc0,PC1, PC2 function as handshake lines for Port B.
• PC3,PC4,PC5 function as handshake lines for Port A if it is initialized as input port in mode 1. PC6,PC7
are available as I/O lines.
• PC3,PC6,PC7 function as handshake lines for Port A if it is initialized as output port in mode 1. PC4,PC5
are available as I/O lines.

FIGURE 8.2 Strobed input operation (mode 1) of the 82C55. (a) Internal structure and (b) timing diagram.

The strobed input port captures data from the port pins when the strobe ( STB ) is activated. Note that the strobe
captures the port data on the 0-to-1 transition. The STB signal causes data to be captured in the port, and it
activates the IBF (input buffer full) and INTR (interrupt request) signals. Once the microprocessor, through
software (IBF) or hardware (INTR), notices that data are strobed into the port, it executes an IN instruction to read
the port RD. The act of reading the port restores both IBF and INTR to their inactive states until the next datum is
strobed into the port.

Signal Definition for Mode1 Strobed Input

STB : The strobe input loads data into the port latch, which holds the information until it is input to the
microprocessor via the IN instruction.
IBF `Input buffer full is an output indicating that the input latch contains information.
INTR: Interrupt request is an output that requests an interrupt. The INTR pin becomes a logic 1 when
the input returns to a logic 1, and is cleared when the data are input from the port by the
microprocessor.
INTE The interrupt enable signal is neither an input nor an output; it is an internal bit programmed via
the port PC4 (port A) or PC 2(port B) bit position.
PC7,PC6 : The port C pins 7 and 6 are general-purpose I/O pins that are available for any purpose.

Good Example for strobed input device is keyboard. The keyboard encoder debounces the key switches and
provides a strobe signal whenever a key is depressed and the data output contain the ASCII-coded key code. Fig
shows the connection of Keyboard to 8255. The DAV(Active Low) is activated when the key is pressed on the

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Chapter – 8 Microprocessor-10CS45
keyboard. This causes the data to be strobed into Port A because the DAV is connected to the strobe input. Strobed
input also activates the Input buffer full signal indicating the data is available in port A.

FIGURE 8.3 Using the 82C55 for strobed input operation of a keyboard.

Mode 1 Strobed Output:

Whenever data are written to a port programmed as a strobed output port, the OBF (output buffer full) signal
becomes a logic 0 to indicate that data are present in th e port latch. This signal indicates that data are available to an
external I/O device that removes the data by strobing the ACK (acknowledge) input to the port. The ACK signal
returns the OBF signal to a logic 1, indicating that the buffer is not full.

FIGURE 8.4 Strobed output operation (mode 1) of the 82C55. (a) Internal structure and (b) timing diagram.

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Signal Definition for Mode1 Strobed Output

OBF Output buffer full is an output that goes low whenever data are output (OUT)
to the port A or port B latch. This signal is set to a logic 1 whenever the ACK
pulse returns from the external device.
ACK The acknowledge signal causes the OBF pin to return to a logic 1 level.
The ACK signal is a response from an external device, indicating that it has
received the data from the 82C55 port.
INTR Interrupt request is a signal that often interrupts the microprocessor when the external
device receives the data via the signal. This pin is qualified by the internal INTE
(interrupt enable) bit.
INTE Interrupt enable is neither an input nor an output; it is an internal bit programmed to
enable or disable the INTR pin. The INTE A bit is programmed using the PC 6bit and
INTE B is programmed using the PC2bit.
PC 4 , PC5 Port C pins PC4 and PC5 are general-purpose I/O pins. The bit set and reset command is
used to set or reset these two pins.

Strobed Output Example: Fig 8.5 Shows how 8255 is connected to the printer.

Mode 2 (Strobed Bi-Directional Bus I/O)

The functional configuration provides a means for communicating with a peripheral device or structure on a single
8-bit bus for both transmitting and receiving data (bi-directional bus I/O). “Hand shaking” signals are provided to
maintain proper bus flow discipline similar to Mode 1. Interrupt generation and enable/disable functions are also
available.

Mode 2 Basic Functional Definitions:

• Used in Group A only

• One 8-bit, bi-directional bus Port (Port A) and a 5-bit control Port (Port C)
• Both inputs and outputs are latched
• The 5-bit control port (Port C) is used for control and status for the 8-bit, bi-directional bus port (Port A)

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Mode Selection

CS A1 A0 Selects
0 0 0 Port A
0 0 1 Port B
0 1 0 Port C
0 1 1 Control register
1 X X 8255 is not selected

Signal Definitions for Bidirectional Mode 2

INTR Interrupt request is an output used to interrupt the microprocessor for both input and output conditions.
OBF Output buffer full is an output indicating that the output buffer contains data for the bidirectional bus.
ACK Acknowledge is an input that enables the three-state buffers so that data can appear on port A. If is a logic
1, the output buffers of port A are at their high-impedance state.
STB The strobe input loads the port A input latch with external data from the bidirectional port A bus.
IBF Input buffer full is an output used to signal that the input buffer contains data for the external bidirectional
bus.
INTE Interrupt enable are internal bits (INTE1 and INTE2) that enable the INTR pin. The state of the INTR pin
is controlled through port C bits PC6 (INTE1) and PC4 (INTE2).
PC0, PC1, and PC2 These pins are general-purpose I/O pins in mode 2 controlled by the bit set and reset
command.

FIGURE 8.6 Mode 2 operation of the 82C55. (a) Internal structure and (b) timing diagram.

The Bidirectional Bus. The bidirectional bus is used by referencing port A with the IN and OUT instructions. To
transmit data through the bidirectional bus, the program first tests the OBF signal to determine whether the output
buffer is empty. If it is, then data are sent to the output buffer via the OUT instruction.

CONTROL WORD

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Figure 8.7: MODE DEFINITION FORMAT

Ex. 1: Configure Port A as input in Mode 0, Port B as output in mode 0, Port C (Lower) as
output and Port C (Upper) as input ports.

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Ex. 2: Configure Port A as input in Mode 1, Port B as output in mode 1, Port C7-6 as input
ports. (PC5-0 are handshake lines, some are input lines and others are output. So they are
shown as X)

Ex. 3:Configure Port A in Mode 2, Port B as output in mode 1. (PC7-3 are handshake lines for
Port A and PC2-0 are handshake signals for port B)

Single Bit Set/Reset Feature

Any of the eight bits of Port C can be Set or Reset using a single output instruction. This feature reduces software
requirements in control-based applications. When Port C is being used as status/control for Port A or B, these bits
can be set or reset by using the Bit Set/Reset operation just as if they were output ports.

If a 0 is placed in bit position D7 of the command byte, command byte B is selected. This command allows any bit
of port C to be set (1) or reset (0), if the 82C55 is operated in either mode 1 or 2. Otherwise, this command byte is
not used for programming. The bit set/reset feature is often used in a control system to set or clear a control bit at
port C. The bit set/reset function is glitch-free, which means that the other port C pins will not change during the bit
set/reset command.
CONTROL WORD

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Figure 8.8: BIT SET/RESET FORMAT

Ex. 1: Set to 1 bit 4 of Port C

Ex. 2: Reset to 0 bit 6 of Port C

Programmable Interval Timer 8254

The 8254 programmable interval timer consists of three independent 16-bit programmable counters (timers). Each
counter is capable of counting in binary or binary-coded decimal (BCD). The maximum allowable input frequency
to any counter is 10 MHz. This device is useful wherever the microprocessor must control real-time events. Some
examples of usage include real-time clock and an events counter, and for motor speed and direction control.

This timer also appears in the personal computer to do the following:

1. Generate a basic timer interrupt that occurs at approximately 18.2 Hz.

2. Cause the DRAM memory system to be refreshed.
3. Provide a timing source to the internal speaker and other devices. The timer in the personal computer
is an 8253 instead of an 8254.

FUNCTIONAL DESCRIPTION

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The 8254 is a programmable interval timer/counter designed for use with Intel microcomputer systems. It is a
general purpose, multi-timing element that can be treated as an array of I/O ports in the system software.

The 8254 solves one of the most common problems in any microcomputer system, the generation of accurate time
delays under software control. Instead of setting up timing loops in software, the programmer configures the 8254 to
match his requirements and programs one of the counters for the desired delay. After the desired delay, the 8254 will
interrupt the CPU. Software overhead is minimal and variable length delays can easily be accommodated.

Some of the other counter/timer functions common to microcomputers which can be implemented with the 8254 are:

# Real time clock

# Event-counter
# Digital one-shot
# Programmable rate generator
# Square wave generator
# Binary rate multiplier
# Complex waveform generator
# Complex motor controller

Block Diagram

Figure 8.9: Block diagram of 8254 timer

DATA BUS BUFFER

This 3-state, bi-directional, 8-bit buffer is used to interface the 8254 to the system bus.

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Pin Definitions

A0, A1 The address inputs select one of four internal registers within the 8254. See Table 11–4 for the function
of the A1 and A0 address bits.

Address selection inputs to the 8254.

CLK The clock input is the timing source for each of the internal counters. This input is often connected to the
PCLK signal from the microprocessor system bus controller.

CS Chip select enables the 8254 for programming and reading or writing a counter.

G The gate input controls the operation of the counter in some modes of operation.

GND Ground connects to the system ground bus.

OUT A counter output is where the waveform generated by the timer is available.

RD Read causes data to be read from the 8254 and often connects to the IORC signal.

Vcc Power connects to the +5.0 V power supply.

WR Write causes data to be written to the 8254 and often connects to the write strobe ( IOWC ).

Timers
Timer 0 is programmed to generate an 18.2 Hz signal that interrupts the microprocessor at interrupt vector 8 for a
clock tick. The tick is often used to time programs and events in DOS.
Timer 1 is programmed for 15 μs, which is used on the personal computer to request a DMA action used to refresh
the dynamic RAM.
Timer 2 is programmed to generate a tone on the personal computer speaker.

Programming the 8254

Each counter is individually programmed by writing a control word, followed by the initial count. Figure 8.10 lists
the program control word structure of the 8254. The control word allows the programmer to select the counter, mode

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Chapter – 8 Microprocessor-10CS45
of operation, and type of operation (read/write). The control word also selects either a binary or BCD count. Each
counter may be programmed with a count of 1 to FFFFH. A count of 0 is equal to FFFFH+l (65,536) or 10,000 in
BCD. The minimum count of 1 applies to all modes of operation except modes 2 and 3 , which have a minimum
count of 2.

Figure 8.10: Control Word format for 8254

Timer 0 is used in the personal computer with a divide-by count of 64K (FFFFH) to generate the 18.2 Hz (18.196
Hz) interrupt clock tick. Timer 0 has a clock input frequency of 4.77 MHz + 4 or 1.1925 MHz.

The control word uses the BCD bit to select a BCD count (BCD = 1) or a binary count (BCD = 0). The M2, M1, and
M0 bits select one of the six different modes of operation (000–101) for the counter. The RW1 and RW0 bits
determine how the data are read from or written to the counter. The SC1 and SC0 bits select a counter or the special
read-back mode of operation.

Each counter has a program control word used to select the way the counter operates. If two bytes are programmed
into a counter, then the first byte (LSB) will stop the count, and the second byte (MSB) will start the counter with
the new count.
Modes of Operation

Six modes (mode 0–mode 5) of operation are available to each of the 8254 counters. Figure 8.6 shows how each of
these modes functions with the CLK input, the gate (G) control signal, and OUT signal. A description of each mode
follows:

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MODE 0: INTERRUPT ON TERMINAL COUNT

Allows the 8254 counter to be used as an events counter. In this mode, the output becomes a logic 0 when the
control word is written and remains there until N plus the number of programmed counts. For example, if a count of
5 is programmed, the output will remain a logic 0 for 6 counts beginning with N. Note that the gate (G) input must
be a logic 1 to allow the counter to count. If G becomes a logic 0 in the middle of the count, the counter will stop
until G again becomes a logic 1.

MODE 1: HARDWARE RETRIGGERABLE ONE-SHOT

Hardware causes the counter to function as a re-triggerable, mono-stable multivibrator (one-shot). In this mode the
G input triggers the counter so that it develops a pulse at the OUT connection that becomes a logic 0 for the duration
of the count. If the count is 10, then the OUT connection goes low for 10 clocking
periods when triggered. If the G input occurs within the duration of the output pulse, the counter is again reloaded
with the count and the OUT connection continues for the total length of the count.

MODE 2: RATE GENERATOR

This Mode functions like a divide-by-N counter. It is typically used to generate a Real Time Clock interrupt. Allows
the counter to generate a series of continuous pulses that are one clock pulse wide. The separation between pulses is
determined by the count. For example, for a count of 10, the output is a logic 1 for nine clock periods and low for
one clock period. This cycle is repeated until the counter is programmed with a new count or until the G pin is
placed at a logic 0 level. The G input must be a logic 1 for this mode to generate a continuous series of pulses.
Otherwise, the new count will be loaded at the end of the current counting cycle. In mode 2, a COUNT of 1 is
illegal.

MODE 3: SQUARE WAVE MODE

Mode 3 is typically used for Baud rate generation. Mode 3 is similar to Mode 2 except for the duty cycle of OUT.
Generates a continuous square wave at the OUT connection, provided that the G pin is a logic 1. For example, if the
counter is programmed for a count of 5, the output is high for three clocks and low for two clocks.

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MODE 4: SOFTWARE TRIGGERED STROBE

Allows the counter to produce a single pulse at the output. If the count is programmed as a 10, the output is high for
10 clocking periods and low for one clocking period. The cycle does not begin until the counter is loaded with its
complete count.

MODE 5: HARDWARE TRIGGERED STROBE (RETRIGGERABLE)

A hardware triggered one-shot that functions as mode 4, except that it is started by a trigger pulse on the G pin
instead of by software. This mode is also similar to mode 1 because it is retriggerable.

This program that generates a 100 KHz square-wave at OUT0 and a 200 KHz continuous pulse at OUT1. Counter 0
uses mode 3 and counter 1 uses mode 2. The count programmed into counter 0 is 80 and the count for counter 1 is
40. These counts generate the desired output frequencies with an 8 MHz input clock. Given CNT 0 = 700H, CNT 1
= 702H, CNT 2 = 704H, CR = 706H

Square wave = 100KHz

Continuous Pulse = 200KHz

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Speed of the Processor = 8MHz

Count1 = Speed of the processor / Square wave frequency

= 8M/100K
= 80

Count2 = Speed of the processor / Continuous pulse frequency

= 8M/200K
= 40

.MODEL SMALL

.DATA
CNT0 EQU 700H
CNT1 EQU 702H
CNT2 EQU 704H
CR EQU 706H
.CODE

MOV AX,@DATA
MOV DS,AX

MOV DX,CR ;program counter 0 for mode 3

MOV AL,36H ;Refer Control Word format of 8254
OUT DX,AL

MOV DX,CNT0 ;program counter 0 with 80

MOV AL,80
OUT DX,AL
MOV AL,0
OUT DX,AL

MOV DX,CR ;program counter 1 for mode 2

MOV AL74H ; Refer Control Word format of 8254
OUT DX,AL

MOV DX,CNT1 ;program counter 1 with 40

MOV AL,40
OUT DX,AL
MOV AL,0
OUT DX,AL

INT 3

END
Write Operations

The programming procedure for the 8254 is very flexible. Only two conventions need to be remembered:

1) For each Counter, the Control Word must be written before the initial count is written.
2) The initial count must follow the count format specified in the Control Word (least significant byte only,

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Chapter – 8 Microprocessor-10CS45
most significant byte only, or least significant byte and then most significant byte).

Since the Control Word Register and the three Counters have separate addresses (selected by the A1,A0 inputs), and
each Control Word specifies the Counter it applies to (SC0,SC1 bits), no special instruction sequence is required.

A new initial count may be written to a Counter at any time without affecting the Counter's programmed mode in
any way. Counting will be affected as described in the Mode definitions. The new count must follow the
programmed count format.

If a Counter is programmed to read/write two-byte counts, the following precaution applies:

A program must not transfer control between writing the first and second byte to another routine which also writes
into that same Counter. Otherwise, the Counter will be loaded with an incorrect count.

Read Operations

It is often desirable to read the value of a Counter without disturbing the count in progress. This is easily done in the
8254.

There are three possible methods for reading the counters: a simple read operation, the Counter Latch Command,
and the Read-Back Command.

The first method is to perform a simple read operation. To read the Counter, which is selected with the A1, A0
inputs, the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic.
Otherwise, the count may be in the process of changing when it is read, giving an undefined result.

Reading a Counter. Each counter has an internal latch that is read with the read counter port operation. These
latches will normally follow the count. If the contents of the counter are needed, then the latch can remember the
count by programming the counter latch control word (see Figure 11–37), which causes the contents of the counter
to be held in a latch until they is read.

Whenever a read from the latch or the counter is programmed, the latch tracks the contents of the counter. When it is
necessary for the contents of more than one counter to be read at the same time,
we use the read-back control word, illustrated in Figure 11–38. With the read-back control word, the CNT bit is a
logic 0 to cause the counters selected by CNT0, CNT1, and CNT2 to be latched.

If the status register is to be latched, then the ST bit is placed at a logic 0. Figure 11–39 shows the status register,
which shows the state of the output pin, whether the counter is at its null state (0), and how the counter is
programmed.

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Figure 8.11: The 8254-2 counter latch control word

Interrupts: Basic Interrupt Processing

The Purpose of Interrupts

Interrupts are particularly useful when interfacing I/O devices that provide or require data at relatively low data
transfer rates.

A time line that indicates interrupt usage in a typical system.

Figure 12–1 shows a time line that indicates a typist typing data on a keyboard, a printer removing data from the
memory, and a program executing. The program is the main program that is interrupted for each keystroke and each
character that is to print on the printer. Note that the keyboard interrupt service procedure, called by the keyboard
interrupt, and the printer interrupt service procedure each take little time to execute.

Interrupts

The interrupts of the entire Intel family of microprocessors include two hardware pins that request interrupts (INTR
and NMI), and one hardware pin ( INTA ) that acknowledges the interrupt requested through INTR.

The following interrupts are available in 8086.

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Interrupt Vectors. The interrupt vectors and vector table are crucial to an understanding of hardware and software
interrupts.

The following list describes the function of each dedicated interrupt in the microprocessor:

TYPE 0 The divide error whenever the result from a division overflows or an attempt is made to divide by zero.

TYPE 1 Single-step or trap occurs after the execution of each instruction if the trap (TF) flag bit is set. Upon
accepting this interrupt, the TF bit is cleared so that the interrupt service procedure executes at full speed.

TYPE 2 The non-maskable interrupt occurs when a logic 1 is placed on the NMI input pin to the
microprocessor. This input is non-maskable, which means that it cannot be disabled.

TYPE 3 A special one-byte instruction (INT 3) that uses this vector to access its interrupt service procedure. The
INT 3 instruction is often used to store a breakpoint in a program for debugging.

TYPE 4 Overflow is a special vector used with the INTO instruction. The INTO instruction interrupts the program
if an overflow condition exists, as reflected by the overflow flag (OF).

The Operation of a Real Mode Interrupt

When the microprocessor completes executing the current instruction, it determines whether an interrupt is active by
checking
(1) instruction executions
(2) single-step
(3) NMI
(4) coprocessor segment overrun
(5) INTR
(6) INT instructions in the order presented.

If one or more of these interrupt conditions are present, the following sequence of events occurs:

1. The contents of the flag register are pushed onto the stack.
2. Both the interrupt (IF) and trap (TF) flags are cleared. This disables the INTR pin and the trap or single-

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step feature.
3. The contents of the code segment register (CS) are pushed onto the stack.
4. The contents of the instruction pointer (IP) are pushed onto the stack.
5. The interrupt vector contents are fetched, and then placed into both IP and CS so that the next
instruction executes at the interrupt service procedure addressed by the vector.

Whenever an interrupt is accepted

1. The microprocessor stacks the contents of the flag register, CS and IP; clears both IF and TF; and
jumps to the procedure addressed by the interrupt vector. After the flags are pushed onto the stack, IF
and TF are cleared.
2. These flags are returned to the state prior to the interrupt when the IRET instruction is encountered at
the end of the interrupt service procedure.
3. If interrupts were enabled prior to the interrupt service procedure, they are automatically re-enabled by
the IRET instruction at the end of the procedure.
4. The return address (in CS and IP) is pushed onto the stack during the interrupt. Sometimes the return
address points to the next instruction in the program; sometimes it points to the instruction or point in
the program where the interrupt occurred.

Interrupt Flag Bits

The interrupt flag (IF) and the trap flag (TF) are both cleared after the contents of the flag register are stacked during
an interrupt. Figure 12–4 illustrates the contents of the flag register and the location of IF and TF. When the IF bit is
set, it allows the INTR pin to cause an interrupt; when the IF bit is cleared, it prevents the INTR pin from causing an
interrupt. When TF = 1, it causes a trap interrupt (type number 1) to occur after each instruction executes. This is
why we often call trap a single-step. When TF = 0, normal program execution occurs. This flag bit allows
debugging. The interrupt flag is set and cleared by the STI and CLI instructions, respectively.

HARDWARE INTERRUPTS

The microprocessor has two hardware interrupt inputs: non-maskable interrupt (NMI) and interrupt request (INTR).
Whenever the NMI input is activated, a type 2 interrupt occurs because NMI is internally decoded. The INTR input
must be externally decoded to select a vector. Any interrupt vector can be chosen for the INTR pin, but we usually
use an interrupt type number between 20H and FFH. Intel has reserved interrupts 00H through 1FH for internal and
future expansion. The INTA signal is also an interrupt pin on the microprocessor, but it is an output that is used in
response to the INTR input to apply a vector type number to the data bus connections D7–D0. Figure 12–5 shows the
three user interrupt connections on the microprocessor.

The non-maskable interrupt (NMI) is an edge-triggered input that requests an interrupt on the positive edge (0-
to-1 transition). After a positive edge, the NMI pin must remain a logic 1 until it is recognized by the
microprocessor. Note that before the positive edge is recognized, the NMI pin must be a logic 0 for at least two
clocking periods.

The NMI input is often used for parity errors and other major system faults, such as power failures. Power failures
are easily detected by monitoring the AC power line and causing an NMI interrupt whenever AC power drops out.
In response to this type of interrupt, the microprocessor stores all of the internal register in a battery-backed-up
memory or an EEPROM. Figure 12–6 shows a power failure detection circuit that provides a logic 1 to the NMI
input whenever AC power is interrupted.

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FIGURE 8.12 The interrupt pins on all versions of the Intel microprocessor.

INTR and INTA

The interrupt request input (INTR) is level-sensitive, which means that it must be held at a logic 1 level until it is
recognized. The INTR pin is set by an external event and cleared inside the interrupt service procedure. This input is
automatically disabled once it is accepted by the microprocessor and re-enabled by the IRET instruction at the end
of the interrupt service procedure.
The microprocessor responds to the INTR input by pulsing the INTA output in anticipation of receiving an
interrupt vector type number on data bus connections D 7–D0. Figure 12–8 shows the timing diagram for the INTR
and INTA pins of the microprocessor. There are two INTA pulses generated by the system that are used to insert
the vector type number on the data bus.
Figure 8.13 illustrates a simple circuit that applies interrupt vector type number FFH to the data bus in response to
an INTR. Notice that the INTA pin is not connected in this circuit.

FIGURE 8.13 A simple method for generating interrupt vector type number FFH in response to INTR.

BASIC DMA OPERATION

Two control signals are used to request and acknowledge a direct memory access (DMA) transfer in the
microprocessor-based system. The HOLD pin is an input that is used to request a DMA action and the HLDA pin is
an output that acknowledges the DMA action. Figure 8.14 shows the timing that is typically found on these two
DMA control pins.

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FIGURE 8.14 Timing diagram of DMA transfer

The microprocessor responds, within a few clocks, by suspending the execution of the program and by placing its
address, data, and control bus at their high-impedance states. The high-impedance state causes the microprocessor to
appear as if it has been removed from its socket. This state allows external I/O devices or other microprocessors to
gain access to the system buses so that memory can be accessed directly.

As the timing diagram indicates, HOLD is sampled in the middle of any clocking cycle. Thus, the hold can take
effect any time during the operation of any instruction in the microprocessor’s instruction set. As soon as the
microprocessor recognizes the hold, it stops executing software and enters hold cycles. Note that the HOLD input
has a higher priority than the INTR or NMI interrupt inputs. Interrupts take effect at the end of an instruction,
whereas a HOLD takes effect in the middle of an instruction. The only microprocessor pin that has a higher priority
than a HOLD is the RESET pin. Note that the HOLD input may not be active during a RESET or the reset is not
guaranteed.

The HLDA signal becomes active to indicate that the microprocessor has indeed placed its buses at their high-
impedance state, as can be seen in the timing diagram. Note that there are a few clock cycles between the time that
HOLD changes and until HLDA changes. The HLDA output is a signal to the external requesting device that the
microprocessor has relinquished control of its memory and I/O space. You could call the HOLD input a DMA
request input and the HLDA output a DMA grant signal.

Basic DMA Definitions

Direct memory accesses normally occur between an I/O device and memory without the use of the microprocessor.
A DMA read transfers data from the memory to the I/O device. A DMA write transfers data from an I/O device to
memory. In both operations, the memory and I/O are controlled simultaneously, which is why the system contains
separate memory and I/O control signals. This special control bus structure of the microprocessor allows DMA
transfers. A DMA read causes both the MRDC and IOWC signals to activate simultaneously, transferring data
from the memory to the I/O device. A DMA write causes the and signals to both activate.

These control bus signals are available to all microprocessors in the Intel family except the 8086/8088 system. The
DMA controller provides the memory with its address and a signal from the controller ( DACK ) selects the I/O
device during the DMA transfer.

The data transfer speed is determined by the speed of the memory device or a DMA controller that often controls
DMA transfers. If the memory speed is 50 ns, DMA transfers occur at rates of up to 1/50 ns or 20 M bytes per
second. If the DMA controller in a system functions at a maximum rate of 15 MHz and we still use 50 ns memory,
the maximum transfer rate is 15 MHz because the DMA controller is slower than the memory. In many cases, the
DMA controller slows the speed of the system when DMA transfers occur.

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