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Assignment 2 EC 4201

The document contains 14 questions related to electronics and semiconductor fabrication processes. The questions cover topics such as NMOS fabrication, CMOS logic gate design, transistor sizing, vacuum tube size calculations, SPICE parameters, device scaling trends, MOSFET characteristics, non-linear element modeling in SPICE, and MOSFET small signal models.

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Sathiyaseelan Sankarjee
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44 views2 pages

Assignment 2 EC 4201

The document contains 14 questions related to electronics and semiconductor fabrication processes. The questions cover topics such as NMOS fabrication, CMOS logic gate design, transistor sizing, vacuum tube size calculations, SPICE parameters, device scaling trends, MOSFET characteristics, non-linear element modeling in SPICE, and MOSFET small signal models.

Uploaded by

Sathiyaseelan Sankarjee
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ASSIGNMENT#2, Course id: EC 4201, Instructor: KKM, TA: JOY

1. Describe briefly NMOS fabrication process with sketches.


2. (a)Sketch the stick diagram of 2 input NOR gate in CMOS static style
(b) Draw the layout for the circuit drawn in Q # 2(a) above.
3. Implement the equation X = ((A’ + B’) (C’ + D’ + E’) + F’) G’ using complementary CMOS.
Size the devices so that the output resistance is the same as that of an inverter with
an NMOS W/L = 2 and PMOS W/L = 6. Which input pattern(s) would give the worst
and best equivalent pull-up or pull-down resistance?
4. Assume a cell phone contains 50 million transistors. How big such a cell phone if
phone used vacuum tubes instead of transistors, assuming a vacuum tube has a
volume of 1 cubic inch?
5. Explain briefly how would you determine SPICE parameter λ (LAMBDA)
experimentally?
6. The constant field model of MOS scaling applies a dimensionless factor α to
manufacturing dimensions (length, width and thickness), voltages and processing
concentrations, so that channel thickness remains unchanged. For example, with α
= 1, the dimensions are unchanged; with α = 2, they would be halved. Derive
approximate expressions for the consequent scaling of
• gate area
• channel resistance
• current
• load capacitance
• gate delay
• static power consumption (per gate)
• power density (per unit area)
• current density (in wires)

What are the main implications for speed, size and power?

7. Constant voltage is an alternative model in which the only manufacturing


dimensions are scaled, leaving voltages unchanged, so the channel thickness
increases by a factor α. Derive approximate expressions for the consequent scaling
and summarize the main implications.
8. Consider a CMOS inverter with the following parameters:

NMOS Vtn= 0. 6 V µn Cox = 60 µA/V2 (W/L)n = 8


PMOS Vtp = - 0. 7 V µp Cox = 25 µA/V2 (W/L)p = 12
Calculate the noise margins and the switching threshold voltage (V th) of this circuit.
Take VDD= 3. 3 V.

9. By scanning the literature, find the leading-edge devices at this point in time in the
following domains: microprocessor, signal processor, SRAM, and DRAM. Determine
for each of those, the number of integrated devices, the overall area and the
maximum clock speed. Evaluate the match with the trends predicted in section 1.2
in Prof. Rabaey’s book.
10. Consider an N channel MOS with the following characteristics. tox = 10 nm, n = 520
cm2/V-s, (W/L)= 8, Vtn = 0.70 V. Calculate the drain currents for VGSn = 2 V & VDSn = 2
V; and VGSn = 2 V & VDSn = 1.27 V
v
11. Find an expression for the drain to source resistance rDS  DS when v DS is small
iD
(linear region) of an NMOS Enhancement transistor.
12. Briefly explain how non-linear elements are handled in SPICE?
13. Explain one application of MOSFET operating in sub-threshold region?
14. Draw the small signal high frequency model for a NMOS taking into account the
effect of channel length modulation.

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