Integrated Electronics

& Design

IC Fabrication Techniques

Gary Chun Zhao, PhD

[email protected]
Reading: Chapter 4.0, 4.2, 4.3.1
Apr 2023
https://www.xjtlu.edu.cn/en/departments/academic-departments/electrical-and-electronic-engineering/staff/chun-zhao
 IC Fab. Tech. OUTLINE
⚫ Thin Film Formation
⚫ Photolithography and Etching
⚫ Doping
⚫ IC Resistor
⚫ Sheet Resistance
⚫ Diode
⚫ nMOSFET: Process Flow
⚫ nMOSFET: Fab. and Layout
⚫ nMOSFET: Layout Rules
2
Thin film formation

⚫ Thermal oxidation
⚫ CVD
⚫ PVD
3
Thermal oxidation
⚫ Dry oxidation
➢ Si + O2 → SiO2 (900-1200°C)
➢ 700nm oxide: 10 hours (1200°C)
➢ Good oxide quality: gate oxide
Gate oxide
⚫ Wet oxidation
➢ Si + H2O → SiO2 + 2H2 (900-1200°C)
➢ 700nm oxide: 0. 65 hours (1200°C)
➢ Poor oxide quality: field oxide/diffusion barrier (diffusion mask)

Field oxide
Thermal
H2O or O2
oxidation SiO2
Si Si
4
Thermal oxidation
⚫ Dry oxidation
➢ Si + O2 → SiO2 (900-1200°C)
➢ 700nm oxide: 10 hours (1200°C)
➢ Good oxide quality: gate oxide

⚫ Wet oxidation
➢ Si + H2O → SiO2 + 2H2 (900-1200°C)
➢ 700nm oxide: 0. 65 hours (1200°C)
➢ Poor oxide quality: field oxide/diffusion barrier (diffusion mask)

Thermal
H2O or O2
oxidation SiO2
Si Si
5
 Thermal SiO2 Properties
➢ (1) SiO2 is a good diffusion mask for common dopants

B, P, or As
Diffusion barrier layer
SiO2
(diffusion mask)
Si

➢ (2) Very good etching selectivity between Si and SiO2.

SiO2
HF
Si dip Si
6
Thin film formation

⚫ Thermal oxidation
⚫ CVD
⚫ PVD
7
Chemical Vapor Deposition (CVD)

⚫ Thin film formation from vapor phase

reactants. Deposited films range from metals
to semiconductors to insulators.

⚫ An essential process step in the

manufacturing of microelectronic devices.
High temperatures and low pressures are the
most common process conditions, but are not
necessary.

⚫ All CVD involves using an energy source to

break reactant gases into reactive species for
deposition.
8
 Si
gas gas solid
Sub-Si (wafer)

9
SiH4 + O2 → SiO2 + 2H2
SiO2
gas gas solid
Sub-Si

10
Examples of CVD
⚫ Metals/Conductors – W, Al, Cu,
doped poly-Si
⚫ Insulators (dielectrics) – BPSG,
Si3N4, SiO2
⚫ Semiconductors – Si, Ge, InP,
GaAsP
SiCl4 + 2H2 → Si + 4HCl
SiH4 + O2 → SiO2 + 2H2
11
Thin film formation

⚫ Thermal oxidation
⚫ CVD
⚫ PVD
12
Physical Vapor Deposition (PVD)

⚫ No chemical reaction involved

➢ Evaporation
➢ Sputtering
➢ …
⚫ Used to form metal films or metal
oxide films, such as
➢ Al
➢ HfO2
➢ …

13
 Physical Vapor Deposition - Evaporation
Al ring
Evaporation Al
(Tsource >>Tboiling of Al , 700OC)

Boiling point
H2O: 100oC
Al Al: 660oC

SiO2 Deposited Al film

Si Si Si

14
 Physical Vapor Deposition - Sputtering

Al target

Ar ions with ~ keV

Al atoms ejected Ar+ kinetic energy to
due to Ar ion
bomb the Al target
bombardment

Al

SiO2 Deposited Al film

Si Si Si

15
Physical Vapor Deposition - Sputtering

Thermal
H2O or O2
oxidation SiO2
Si Si

Al

SiO2 Deposited Al film

Si Si Si

16
 IC Fab. Tech. OUTLINE
⚫ Thin Film Formation
⚫ Photolithography and Etching
⚫ Doping
⚫ IC Resistor
⚫ Sheet Resistance
⚫ Diode
⚫ nMOSFET: Process Flow
⚫ nMOSFET: Fab. and Layout
⚫ nMOSFET: Layout Rules
17
 Photolithography & Etching

⚫ 1: Glass photomask (mask)

⚫ 2: Apply photoresist (coating)
⚫ 3: UV exposure
⚫ 4: Development
⚫ 5: Etching
VD G
S D
VG

VS

Circuit(电路符号) Layout(版图) 18
Photolithographic process

The process of using UV (Ultraviolet) light to transfer

patterns from a glass mask onto a surface of the Si
wafer.

19
The photolithographic process
⚫The process of using UV (Ultraviolet) light to transfer
patterns from a glass mask onto a surface of the Si
wafer.

20
1. Glass Photomask (mask)

Translucent
Opaque Region Region
(chromium)

• One mask for each

lithography level in process

21
Photolithography & Etching

⚫ 1: Glass photomask (mask)

⚫ 2: Apply photoresist (coating)
⚫ 3: UV exposure
⚫ 4: Development
⚫ 5: Etching

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 PR
SiO2
2. Coating Si

⚫ Spin coating process:

➢ A controlled volume of photoresist is dispensed onto a wafer
➢ The wafer is spun at high speed to produce a uniform
photoresist film.

23
 Using the mask
⚫ Preparing the surface:
➢ Grow a thin layer of SiO2
➢ Apply on top of the SiO2 layer a
negative photoresist (PR1);
thickness around 1 μm
mask1
PR1
SiO2 Spin photoresist
Si

⚫ Place a mask (M1) in close

proximity of the wafer

24
Photolithography & Etching

⚫ 1: Glass photomask (mask)

⚫ 2: Apply photoresist (coating)
⚫ 3: UV exposure
⚫ 4: Development
⚫ 5: Etching

25
 3. UV exposure
Ultraviolet Light source

mask1

PR1
SiO2
Si
⚫ After placing M1 in close proximity of the wafer, an project UV light
through the mask into PR1;
⚫ Induce changes in the polymer structure and these regions will be
insoluble to an organic solvent.
⚫ The regions where the mask was opaque will not be exposed.
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Photolithography & Etching

⚫ 1: Glass photomask (mask)

⚫ 2: Apply photoresist (coating)
⚫ 3: UV exposure
⚫ 4: Development
⚫ 5: Etching

Si

27
 4. Development (negative resist)

The exposed regions will be

insoluble to an organic solvent.

The regions, which is not exposed, will be soluble to

an organic solvent
Process of Development

28
Process steps 3.UV exp

SiO2
1. thin film
Si
PR
2. coating

4. develop

Etching

29
Photolithography & Etching

⚫ 1: Glass photomask (mask)

⚫ 2: Apply photoresist (coating)
⚫ 3: UV exposure
⚫ 4: Development
⚫ 5: Etching

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 5. Etching
SiO2
⚫ Wet Etching Si
➢ SiO2 + 6HF → H2SiF6+2H2O PR
(acid solution)

⚫ Dry Etching
➢ REI (e.g. CF4 plasma)

Etching

PR removing

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 Photoresist chromium

Positive Resist: Part exposed to light will be dissolved in

development solution. Negative Resist: …will not be…

32
32
 Positive
Photoresist

Mask
(clear field)

Part exposed to light

will be dissolved in
development solution

33
33
 Negative
Photoresist

Mask
(dark field)
Part exposed to light
will not be dissolved in
development solution

34
34
Example 1: negative photoresist

Hardened
photoresist

HF
Soluble

Exposed photoresist
becomes insoluble
35
 Example 2: positive photoresist
Deposited Film:
SiO2, Si3N4, Al, Cu, Poly-Si……
Insoluble photoresist

Exposed photoresist
becomes soluble

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 IC Fab. Tech. OUTLINE
⚫ Thin Film Formation
⚫ Photolithography and Etching
⚫ Doping
⚫ IC Resistor
⚫ Sheet Resistance
⚫ Diode
⚫ nMOSFET: Process Flow
⚫ nMOSFET: Fab. and Layout
⚫ nMOSFET: Layout Rules
37
 Doping

⚫ Thermal Diffusion
⚫ Ion Implantation

38
Intrinsic Semiconductor Lecture 3

Silicon has four valence electrons

⚫ It covalently bonds with 4 adjacent atoms in the
crystal lattice
⚫ Increasing Temperature Causes Creation of Free
Carriers. 1010cm-3 free carriers at 23oC (out of
2x1023cm-3): Intrinsic Conductivity.
outmost orbit: 4 valence electrons

39
Intrinsic Semiconductor Lecture 3

Si

Si Si Si

Si
Si Si
Covalent Bond : shared electrons

•
•
40
 The Doping Lecture 3

⚫ The addition of a small percentage of

foreign atoms in the regular crystal
lattice of silicon or germanium
produces dramatic changes in their
electrical properties, producing n-
type and p-type semiconductors.

41
Element periodic table Lecture 3

42
 Column V elements are
Doping (N type) donors, e.g. P, As, Sb

By substituting a Si atom with a special impurity atom (Column V

element), a conduction electron is created.
Lecture 3
Donors: P, As, Sb

43
 Lecture 3
Phosphorus has 5 valence electrons
⚫ ‘Donates’ one conduction electron to lattice Free
⚫ Our substrate has 1015cm-3 phosphorus (1 in 108)

44
 Column III elements are
Doping (P type) acceptors, e.g. B, Al, Ga

By substituting a Si atom with a special impurity atom (Column III

element), a conduction hole is created.
Lecture 3
Acceptors: B, Al, Ga, In

45
 Lecture 3
Boron has 3 valence electrons
⚫ ‘Accepts’ one electron from lattice
⚫ Creates a ‘hole’

46
 Diffusion

⚫ Diffusion is the movement of

one material through another
from a region of relatively higher
concentration into a region of
lower concentration. There are
two steps to thermal diffusion:
➢ Pre-deposition
➢ Drive-in

⚫ Dopant Diffusion Sources

➢ Gas Source: AsH3, PH3, B2H6

47
 B2H6
or PH3

Diffusion mask

B2H6 or PH3

48
48
 B2H6
or PH3
O2

Diffusion mask

49
49
 Thermal Diffusion Example
B2H6
p type Si
SiO2 SiO2

n type Si n type Si

NA > ND
Yellow region
ND=1015/cm3, NSi=5x1022/cm3

B B

Green region
50
 Thermal Diffusion Example
B2H6
p type Si
SiO2 SiO2

n type Si n type Si

Drive-in
PH3 SiO2 p type Si
SiO2
n type Si
n type Si

SiO2 n type Si

n type Si p type Si 51
ND=1019/cm3 n-type ND=1019/cm3

p-type NA=1017/cm3
P P P P

B B
n-type ND=1015/cm3

Brown region NA=1017/cm3

SiO2

n type Si
B B

PH3
SiO2 n type Si
Green region
n type Si p type Si 52
 Ion Implantation
As+ n type Si
SiO2 SiO2

p type Si p type Si
As+ with kinetic energy annealing
SiO2 n type Si
As+
p type Si

Implantation causes
(1) damaged region
(2) non-substitutional location
53
Green n Si
poly
region SiO2
n n
n-type
p-type Si
5454
 Annealing (Drive-in)
Implantation causes
(1) damaged region and disorder cluster
(2) non-substitutional location
To activate the implanted ions and to restore material
properties, the semiconductor must be annealed.

Next week:

Fab. Tech. examples

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