MOS Capacitance

• MOS structure
• MOS energy band diagram
• Effects of applied biases
• *Voltage drops Gary Chun Zhao, PhD
[email protected]

Mar 2023
https://www.xjtlu.edu.cn/en/departments/academic-departments/electrical-and-electronic-engineering/staff/chun-zhao
SiO2

2
MOS Capacitors

⚫ Why capacitors
➢ Foundation for understanding MOS
transistors
Metal
Oxide(SiO2)
⚫ Applications
➢ CCD camera Silicon
➢ Non-volatile memory
➢ Test structure during fabrication
➢ As a component

3
 MOS Capacitor Structure
⚫ Typical MOS capacitors and
MOS capacitor (cross-sectional view) transistors in ICs today employ
➢ heavily doped polycrystalline Si
(“poly-Si”) film as the gate-
electrode material
GATE
xo ▪ n+-type, for “n-channel” transistors
VG (NMOS)
+ ▪ p+-type, for “p-channel” transistors
_
(PMOS)
Si
➢ SiO2 as the gate dielectric
▪ band gap = 9 eV
▪ er,SiO2 = 3.9
➢ Si as the semiconductor material
▪ p-type, for “n-channel” transistors
(NMOS)
▪ n-type, for “p-channel” transistors
(PMOS) 4
 parallel-plate capacitor

t
≠
Si
Q Q

C=dQ/dV
C=Q/V
≠Q/V
V V

⚫ Definition: C = ε A/t = εrεo A/t

where εr (SiO2) = 3.9, εo = 8.85 x 10-14 F/cm
5
MOS Capacitance Measurement
• Vb: dc biasing voltage
and scanned slowly
DQm = DQacc • Vac: small ac signal
iac
GATE • Vg = Vb + Vac
dQGATE dQs dQ s
C= = =
Vac dVg dVg dVac
Si
• Capacitive current due
Vb
to Vac is measured

C-V Meter MOS Capacitor dVac

iac = C
dt
|Vb|>>|Vac|
6
MOS Capacitance

OUTLINE
• MOS structure
• MOS energy band diagram
• Effects of applied biases
• *Voltage drops

Reference reading: Chapter 6.0-6.4

7
Which one is the p-type Si?

EF
Ei Ei
EF

NA ND

8
Which one is the heavily doped Si?

EF
EF
Ei
Ei

ND1 < ND2

9
Poly-Si gate
“metal” oxide semiconductor
Electron
EC
energy

n+ poly-Si
SiO2
EC=EFM EC

EFS
p-type Si EV
EV

<

EV
10
Coordinate system
metal oxide semiconductor

EC
n+ poly-Si

p-type Si
SiO2

EC=EFM EC
EgSi = EgSi =
1.1eV EFS
1.1eV EV
EV

EgSiO2
x
x =9eV

EV
11
 Guidelines for Drawing MOS Band Diagrams
E0: vacuum energy level
cSiO2=0.95eV
EC cSi=
FS=cSi+ (EC-EFS)
FM 4.05eV

3.1eV
Electron barrier
EC=EFM EC

EFS
EV EV

4.8eV
E0-EF : work function Hole barrier

E0-EC : electron affinity qVFB = FM- FS

EV
12
Guidelines for Drawing MOS Band Diagrams
1) Fermi level EF is flat (constant with distance x) in the Si
➢ Since no current flows in the x direction, we can assume that
equilibrium conditions prevail

2) Band bending is linear in the oxide

➢ e
No charge in the oxide => d /dx =r/eox= 0, so e is constant
=> dEC/dx is constant

e= - dV/dx
EC=-qV

13
Guidelines for Drawing MOS Band Diagrams
3) The barrier height for conduction-band electron flow
from the Si into SiO2 is 3.1 eV
➢ This is equal to the electron-affinity difference (cSi and
cSiO2)

4) The barrier height for valence-band hole flow from the

Si into SiO2 is 4.8 eV

5) The vertical distance between the Fermi level in the

metal, EFM, and the Fermi level in the Si, EFS, is
equal to the applied gate voltage:

qVG = E FS − E FM

14
MOS Equilibrium Energy-Band Diagram
metal oxide semiconductor

n+ poly-Si
SiO2
EC

EC=EFM EFS
p-type Si EV

EV

Guideline 1:
Fermi Level is flat.

15
 MOS Equilibrium Energy-Band Diagram
Fermi Level is flat. metal oxide semiconductor
Virtual “Cable”… Q1
● As or P
n+ poly-Si
SiO2
EC
Q2
EC=EFM EFS
p-type Si EV
B
EV
⃝

After contact, there are two

questions: Q1 & Q2.
16
 Q1: Carrier and ion in silicon
metal oxide semiconductor
Guideline 2:
Q1
e=-dV/dx
EC=-qV

+
+
e xd
EC
+ SiO2
+
EC=EFM EFS
EV
V EV
x
-qV
E
x
C
17
Q2: Carrier and ion in silicon
metal oxide semiconductor

n+ poly-Si
SiO2
EC

EC=EFM Q2 EFS
p-type Si EV

EV

18
Q2: Carrier and ion in silicon
metal oxide semiconductor
n+ poly-Si

p-type Si
SiO2

EC

EC=EFM Q2 EFS
EV

EV

p-type p-type
EC
Ei
EF
EV 19
Flat-Band Voltage
metal oxide semiconductor

e
n+ poly-Si
++ + + + + - xd
SiO2 +
EC
EC=EFM
EFS
p-type Si EV

EV

20
Flat-Band Voltage

VFB
e
n+ poly-Si
- EFM
SiO2 +
EFS
p-type Si

⚫ The built-in potential can be “cancelled out” by applying a

gate voltage that is equal in magnitude (but of the opposite
polarity) as the built-in potential. This gate voltage is called
the flatband voltage because the resulting potential profile is
flat. 21
 Flat-Band Condition
Eo

Here
FM VG = VFB ≈ -1V
FS
EFM=

EFS

qVG = EFS- EFM

= F M- F S
VG = VFB

qVFB = FM- FS
22
MOS Capacitance

OUTLINE
• MOS structure
• MOS energy band diagram
• Effects of applied biases
• *Voltage drops

Reference reading: Chapter 6.0-6.4

23
Ec(O) and electric field direction

SiO2
e SiO2
e
Si
V V
x x
-qV =Ec(O) -qV =Ec(O)
x x

Ec e Ec e
EF
EF
24
Effects of applied biases Vg
SiO2

Vg increase from “-” to “+” :

1. Vg<VFB<0 Accumulation: Majority carriers

2. Vg=VFB Flatband

3. Vm≥Vg>VFB Depletion: Majority carriers

including Vg=0
~
~

4.1 VT>Vg>Vm Weak Inversion: Minority carriers

4.2 Vg≥VT Strong Inversion: Minority carriers

What is VFB, Vm and VT?

25
1. Accumulation (p-type Si) : Vg<VFB<0

Vg<0
Accumulation: gate
eeee
Majority carriers SiO2

p-Si

⚫ Physical process: Vg<0: holes attracted to the

oxide/Si interface and accumulate there.
⚫ Oxide: separation between “-” and “+” charges

26
 1. Accumulation:
Energy band & block charge density
Vg<0
More negative: higher electron energy (band bending up) eeee

DVg → DQacc

e
p-Si

SiO2
e qVg = EFS - EFM
Ec(O)
Si EFM Ec
V Ei
EFS
x Ev
-qV =Ec(O) Qacc
x Qm x
DQm = DQacc 27
 1. Capacitance in Accumulation
• As the gate voltage is varied, incremental charge is
added/subtracted to/from the gate and substrate.
• The incremental charges are separated by the gate oxide.
M O S dQacc
DQ C= = Cox
dVg
Q
e ox A
C = Cox = = constant
tox
-Q
eox=er’oxeo, er’ox=3.9 is the relative
−DQ
dielectric constant of the oxide
eo=8.8510-12 F/m is the permittivity
of free space, tox is the oxide thickness.
Normally, we consider the capacitance
Cox
per unit area, so A=1.
28
 1. Accumulation:
Capacitance-voltage (C-V) characteristics
⚫ Example: p-Si
iac GATE
C
e ox A Cox LFCV
C = Cox = Vac
tox Si
Flat-band
Vb

C-V Meter

Mid-band
HFCV

Vb

Accumulation Depletion Inversion

29
 2. Flatband Voltage, VFB
⚫ The built-in potential can be “cancelled out” by applying a gate
voltage that is equal in magnitude (but of the opposite polarity)
as the built-in potential. This gate voltage is called the flatband
voltage because the resulting potential profile is flat.

Vg=VFB
EFM Ec
- SiO2
Ei
+ EFS
Ev

Qm
=0
There is no net charge (i.e. r(x)=0) in
the semiconductor under VGB = VFB. QSD=0 x
30
 Depletion:
3. Depletion: Vg > VFB Majority carriers

⚫ Physical process:
➢ holes repelled from the interface
➢ fixed negative charge left behind
➢ More “+” charges on the gate, holes are
pushed further from the interface, to
expose more “-” space charges.
○: Hole
: B-
+ + ++++
tox tox
Xd
Xd

Vg>0
31
 3. Depletion:
Energy band diagram: Vg>VFB qVg = EFS - EFM

⚫ The band is bent downward now. + +

⚫ No mobile charges at the interface.

Vg>VFB

SiO2
e Vg EFM
Ec
xd Ei
EFS
V Ev
x Qm
xd
-qV =Ec(O)
QSD x
x
32
3. Depletion Capacitor
⚫ Capacitance Higher potential
e ox
tox
++++
Vox
Cox =
Cox tox
Xd
Cdep Vs (or fs) e Si
Cdep =
xd
⚫ When Vg increases, Xd increases and Cdep
reduces. This in turn reduces C.
⚫ Solving Poisson’s equation, we have

 2e SiVS 
1/ 2
e Si e ox
xd =   Cdep = Cox =
 qNa  xd tox C ??
33
3. Capacitance in Depletion
• As the gate voltage is varied, the width of the depletion
region varies.
Incremental charge is effectively added/subtracted at a
depth xd in the substrate.
M O S dQ
DQ C=
dVG
Q xd
1 1 1 1 xd
−DQ = + = +
-Q C Cox Cdep Cox e Si

eSi=er’Sieo , er’Si=11.9 is the

e Si relative dielectric constant
Cox Cdep =
xd of silicon,.

34
3. Depletion:
Capacitance-voltage (C-V) characteristics

⚫ Example: p-Si Vb=VFB

C
Cox LFCV

Flat-band

Mid-band HFCV

Vb

Accumulation Depletion Inversion

35
 Midband: further increase Vg
⚫ EFS = Ei = (Ec+Ev)/2 at interface
⚫ Silicon becomes “intrinsic” at surface
⚫ This is ‘Midband’: Vg=Vm

Vg>VFB

Ec
Ei
At the interface EFM EFS=Ei EFS
Ec Ev
EFS=Ei
Ev
36
 qVg = EFS - EFM
4. Energy band diagram: Vg>Vm
Qm Inversion:
Minority carriers
Vg
QSD x

As Vg>Vm, EFS
is at the up-half Qn +++++++
of the bandgap
xd

At the interface
Ei
EFS Ec EFS
EFM qfn
Ei
qfF
Ev qfs
37
Bulk Semiconductor Potential, fF

q f F  Ei − E F
⚫ p-type Si: Ec

kT
fF =
Ei
ln( N A / ni )  0 EF
qfF
Ev
q

⚫ n-type Si: Ec
EF
|qfF|
kT Ei
fF = − ln( N D / ni )  0 Ev
q
38
 4. Inversion: large positive (Vg-VFB)
➢ Weak Inversion: 0<fn<fF (fF < fS < 2fF) fs = fF + fn
➢ Strong Inversion: fn≥fF (fS ≥ 2fF), electron density at the
interface ≥ hole density in Si bulk.
➢ Vg for strong inversion: VT ‘threshold voltage’.

 ( E − Ei ,surf ) 
Vg = VT → fs = 2fF ns = ni exp  F 
→ ns = pb  kT 
 − ( EF − Ei ,bulk ) 
pb = ni exp  
 kT 
xd

f s = fF + fn

qfn EFS
EFM
Vg>0 qfs
qfF
39
Maximum Depletion Depth, xd,max
⚫ As VG is increased above VT, fS and hence the depth of the
depletion region (xd) increases very slowly.
fs ≈ 2fF
➢ This is because n increases exponentially with fS, whereas xd
increases with the square root of fS. Thus, most of the incremental
negative charge in the semiconductor comes from additional
conduction electrons rather than additional ionized acceptor atoms,
when n exceeds NA.

→ xd can be reasonably approximated to reach a maximum value

(xd,max) for VG ≥ VT.

2e Si (2fF )
xd ,max =
qN A
40
4. Capacitance in Inversion: Low Frequency
CASE 1: Inversion-layer charge can be supplied/removed
quickly enough to respond to changes in the gate voltage.
→ Incremental charge is effectively added/subtracted at the
surface of the substrate.
DQ Time required to build inversion-layer
M O S charge = 2NAto/ni , where
to = minority-carrier lifetime at surface
xdmax

−DQ
dQinv
C= = Cox
dVG
Cox Electrons can respond to the
change in Vac
41
4. Inversion:
CASE 1: Capacitance-voltage (C-V) characteristics
⚫ Example: p-Si
C
Cox LFCV=Low Frequency CV

Flat-band
dQinv
C= = Cox
dVG
Mid-band HFCV

Vb

Accumulation Depletion Inversion

42
4. Capacitance in Inversion: High Frequency
CASE 2: Inversion-layer charge cannot be supplied/removed
quickly enough to respond to changes in the gate voltage.
→ Incremental charge is effectively added/subtracted at a
depth xdmax in the substrate.
1 1 1 DQ
= + Time required to build inversion-layer
C Cox Cdep M O S charge = 2NAto/ni , where
xdmax to = minority-carrier lifetime at surface
1 x 1
= + d max 
Cox e Si C min −DQ
1. When Vac changes rapidly
(e.g., 1MHz), electron
creation cannot keep up.
2. Negative charges supplied
e Si by pushing holes away.
Cox Cdep =
xd max
43
4. Inversion
CASE 2: Capacitance-voltage (C-V) characteristics
⚫ Example: p-Si
C
Cox LFCV=Low Frequency CV

Flat-band
es
Cdep =
xd max

Mid-band 1 1 1
= +
Cmin Cox Cdep
HFCV=High Frequency CV
Vb

Accumulation Depletion Inversion

44
HW8
⚫ A MOS capacitor has:
Xox=40nm, Nd=1021m-3, fF=0.3V, eox=3.9, es=11.8
⚫ Determine:
(i) C(HF) in accumulation; (ii) C(HF) in strong inversion
(iii) C(LF) in strong inversion
⚫ Solution:
(i) C(HF)= Cox=eoeox/Xox
=8.85E-123.9/4.0E-8
=8.63E-4 F/m2 1/ 2
(ii) In inversion  2e oe sVS 
VS=2fF=0.6V xd =  
xd=8.85E-7 m  qNd 
Cs=eoes/xd =1.18E-4F/ m2
C(HF)=CoxCs/(Cox+Cs)=1.04E-4F/ m2
(iii) C(LF)=Cox=8.63E-4 F/m2
45
 HW9

⚫ An MOS capacitor is made on uniformly doped p type

material. With -20V on the gate with respect to the substrate it
has a capacitance of 20pF. With +20V on the gate it has a
capacitance of 10pF. What is the thickness of the depletion
layer if the capacitor has an area of 10-6m2.

⚫ Solution
⚫ With negative bias on the top electrode: C = Cox. (20pF)
⚫ With positive bias: 1/C = 1/Cox+1/Cs
⚫ since Cs=(1/C - 1/Cox)-1= (1/10 - 1/20 )-1 =20 pF. The thickness
of the depletion layer xd is obtained from Cs=Aese0/ xd,
⚫ xd =10-6*12* 8.8*10-12/ 20*10-12 =5*10-6m

46
HW10

⚫ A MOS capacitor has:

Xox=10nm, Na=1017m-3, eox=3.9, es=11.8
⚫ Determine:
(i) C(HF) in accumulation;
(ii) C(HF) in strong inversion;
(iii) C(LF) in strong inversion

47
Summary: Three diagrams

1. Block charge density diagram

2. Energy band diagram
3. CV diagram
Vg change from – to +: from accumulation to
inversion (p-type sub.)

48
Summary
Biasing Conditions for p-type Si
increase VG increase VG

VG = VFB VG < VFB VT > VG > VFB

49
Summary
(A) (C) (A) (B)

(B)
(D)

?
xdmax xdmax

(C) (D)
50
(A)

(B)

xdmax xdmax

51
MOS Capacitance

OUTLINE
• MOS structure
• MOS energy band diagram
• Effects of applied biases
• *Voltage drops

52
Voltage dropped in the silicon
M O S

Surface Potential qVox

Ec
qfS = qVS
EFS
qfS Ev
qfS = Ei (bulk ) − Ei ( surface ) qVG

qfS = EC (bulk ) − EC ( surface ) Ec= EFM

Ev
qfS = EV (bulk ) − EV ( surface )

Vox is the voltage dropped

across the oxide

53
Voltage Drops in the MOS System
M O S

qVox
VG
Ec
M EFS
O Vox qfS Ev
S qVG
fS Ec= EFM

Ev
VFB

VGV=GV-V +f + fs
ox FB =SVox ????????

54
Voltage Drops in the MOS System
⚫ In general,
VG = VFB + Vox + fs
where
qVFB = FMS = FM – FS
Vox is the voltage dropped across the oxide
(Vox = total amount of band bending in the oxide)
fs is the voltage dropped in the silicon
(total amount of band bending in the silicon)
qfS = Ei (bulk ) − Ei ( surface )

For example: When VG = VFB, Vox = fs = 0

i.e. there is no band bending
55
Voltage Drops in the MOS System

VG = VFB + Vox + fs

Vg=VT → VT = VFB + Vox + 2fF

fs = 2fF
2qN De Si 2fF
Vox = −
Cox

2qN De Si 2fF
VT = VFB + 2fF −
Cox
56
HW8
⚫ A MOS capacitor has:
Xox=40nm, Nd=1021m-3, fF=0.3V, eox=3.9, es=11.8
⚫ Determine:
(i) C(HF) in accumulation; (ii) C(HF) in strong inversion
(iii) C(LF) in strong inversion
⚫ Solution:
(i) C(HF)= Cox=eoeox/Xox
=8.85E-123.9/4.0E-8
=8.63E-4 F/m2 1/ 2
(ii) In inversion  2e oe sVS 
VS=2fF=0.6V xd =  
xd=8.85E-7 m  qNd 
Cs=eoes/xd =1.18E-4F/ m2
C(HF)=CoxCs/(Cox+Cs)=1.04E-4F/ m2
(iii) C(LF)=Cox=8.63E-4 F/m2
57
 HW9
⚫ Problem
⚫ An MOS capacitor is made on uniformly doped p type material.
With -20V on the gate with respect to the substrate it has a
capacitance of 20pF. With +20V on the gate it has a capacitance
of 10pF. What is the thickness of the depletion layer if the
capacitor has an area of 10-6m2.

⚫ Solution
⚫ With negative bias on the top electrode: C = Cox. (20pF)
⚫ With positive bias: 1/C = 1/Cox+1/Cs
⚫ since Cs=(1/C - 1/Cox)-1= (1/10 - 1/20 )-1 =20 pF. The thickness
of the depletion layer xd is obtained from Cs=Aese0/ xd,
⚫ xd =10-6*12* 8.8*10-12/ 20*10-12 =5*10-6m

58