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05 Machine Basics

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05 Machine Basics

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Carnegie Mellon

Machine-‐Level Programming I: Basics

15-‐213/18-‐213: Introduc�on to Computer Systems
5th Lecture, Sep. 15, 2015

Instructors:
Randal E. Bryant and David R. O’Hallaron

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 1

Carnegie Mellon

Today: Machine Programming I: Basics

¢  History of Intel processors and architectures
¢  C, assembly, machine code
¢  Assembly Basics: Registers, operands, move
¢  Arithme�c & logical opera�ons

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 2

Carnegie Mellon

Intel x86 Processors

¢  Dominate laptop/desktop/server market

¢  Evolu�onary design

§  Backwards compa�ble up un�l 8086, introduced in 1978
§  Added more features as �me goes on

¢  Complex instruc�on set computer (CISC)

§  Many diﬀerent instruc�ons with many diﬀerent formats
But, only small subset encountered with Linux programs
§ 
§  Hard to match performance of Reduced Instruc�on Set Computers
(RISC)
§  But, Intel has done just that!
§  In terms of speed. Less so for low power.

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 3

Carnegie Mellon

Intel x86 Evolu�on: Milestones

Name Date Transistors MHz
¢  8086 1978 29K 5-‐10
§  First 16-‐bit Intel processor. Basis for IBM PC & DOS
§  1MB address space
¢  386 1985 275K 16-‐33
§  First 32 bit Intel processor , referred to as IA32
§  Added “ﬂat addressing”, capable of running Unix
¢  Pen�um 4E 2004 125M 2800-‐3800
§  First 64-‐bit Intel x86 processor, referred to as x86-‐64
¢  Core 2 2006 291M 1060-‐3500
§  First mul�-‐core Intel processor
¢  Core i7 2008 731M 1700-‐3900
§  Four cores (our shark machines)
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 4
Carnegie Mellon

Intel x86 Processors, cont.

¢  Machine Evolu�on
§  386 1985 0.3M
§  Pen�um 1993 3.1M
§  Pen�um/MMX 1997 4.5M
§  Pen�umPro 1995 6.5M
§  Pen�um III 1999 8.2M
§  Pen�um 4 2001 42M
§  Core 2 Duo 2006 291M
§  Core i7 2008 731M
¢  Added Features
§  Instruc�ons to support mul�media opera�ons
§  Instruc�ons to enable more eﬃcient condi�onal opera�ons
§  Transi�on from 32 bits to 64 bits
§  More cores

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 5

Carnegie Mellon

2015 State of the Art

§  Core i7 Broadwell 2015

¢  Desktop Model

§  4 cores
§  Integrated graphics
§  3.3-‐3.8 GHz
§  65W

¢  Server Model

§  8 cores
§  Integrated I/O
§  2-‐2.6 GHz
§  45W

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 6

Carnegie Mellon

x86 Clones: Advanced Micro Devices

(AMD)
¢  Historically
§ AMD has followed just behind Intel
§ A li�le bit slower, a lot cheaper
¢  Then
§ Recruited top circuit designers from Digital Equipment Corp. and
other downward trending companies
§ Built Opteron: tough compe�tor to Pen�um 4
§ Developed x86-‐64, their own extension to 64 bits
¢  Recent Years
§ Intel got its act together
§  Leads the world in semiconductor technology
§ AMD has fallen behind
§  Relies on external semiconductor manufacturer

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 7

Carnegie Mellon

Intel’s 64-‐Bit History

¢  2001: Intel A�empts Radical Shi� from IA32 to IA64
§  Totally diﬀerent architecture (Itanium)
§  Executes IA32 code only as legacy
§  Performance disappoin�ng
¢  2003: AMD Steps in with Evolu�onary Solu�on
§  x86-‐64 (now called “AMD64”)
¢  Intel Felt Obligated to Focus on IA64
§  Hard to admit mistake or that AMD is be�er
¢  2004: Intel Announces EM64T extension to IA32
§  Extended Memory 64-‐bit Technology
§  Almost iden�cal to x86-‐64!
¢  All but low-‐end x86 processors support x86-‐64
§  But, lots of code s�ll runs in 32-‐bit mode

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 8

Carnegie Mellon

Our Coverage
¢  IA32
§  The tradi�onal x86
§  For 15/18-‐213: RIP, Summer 2015

¢  x86-‐64
§  The standard
§  shark> gcc hello.c
§  shark> gcc –m64 hello.c

¢  Presenta�on
§  Book covers x86-‐64
§  Web aside on IA32
§  We will only cover x86-‐64
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 9
Carnegie Mellon

Today: Machine Programming I: Basics

¢  History of Intel processors and architectures
¢  C, assembly, machine code
¢  Assembly Basics: Registers, operands, move
¢  Arithme�c & logical opera�ons

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 10

Carnegie Mellon

Deﬁni�ons
¢  Architecture: (also ISA: instruc�on set architecture) The
parts of a processor design that one needs to understand
or write assembly/machine code.
§  Examples: instruc�on set speciﬁca�on, registers.
¢  Microarchitecture: Implementa�on of the architecture.
§  Examples: cache sizes and core frequency.
¢  Code Forms:
§  Machine Code: The byte-‐level programs that a processor executes
§  Assembly Code: A text representa�on of machine code

¢  Example ISAs:
§  Intel: x86, IA32, Itanium, x86-‐64
§  ARM: Used in almost all mobile phones
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 11
Carnegie Mellon

Assembly/Machine Code View

CPU Memory
Addresses
Registers
Data Code
PC Data
Condi�on Instruc�ons Stack
Codes

Programmer-‐Visible State
§  PC: Program counter §  Memory
§  Address of next instruc�on §  Byte addressable array
§  Called “RIP” (x86-‐64) §  Code and user data
§  Stack to support procedures
§  Register ﬁle
§  Heavily used program data
§  Condi�on codes
§  Store status informa�on about most
recent arithme�c or logical opera�on
§  Used for condi�onal branching
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 12
Carnegie Mellon

Turning C into Object Code

§  Code in ﬁles p1.c p2.c
§  Compile with command: gcc –Og p1.c p2.c -o p
§  Use basic op�miza�ons (-Og) [New to recent versions of GCC]
§  Put resul�ng binary in ﬁle p

text C program (p1.c p2.c)

Compiler (gcc –Og -S)

text Asm program (p1.s p2.s)

Assembler (gcc or as)

binary Object program (p1.o p2.o) Sta�c libraries

(.a)
Linker (gcc or ld)

binary Executable program (p)

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 13

Carnegie Mellon

Compiling Into Assembly

C Code (sum.c) Generated x86-‐64 Assembly
long
plus(long x, long y); sumstore:
pushq %rbx
void sumstore(long x, long y, movq %rdx, %rbx
long *dest) call plus
{ movq %rax, (%rbx)
long t = plus(x, y); popq %rbx
*dest = t; ret
}
Obtain (on shark machine) with command
gcc –Og –S sum.c
Produces file sum.s
Warning: Will get very different results on non-‐Shark
machines (Andrew Linux, Mac OS-‐X, …) due to different
versions of gcc and different compiler se�ngs.
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 14
Carnegie Mellon

Assembly Characteris�cs: Data Types

¢  “Integer” data of 1, 2, 4, or 8 bytes
§  Data values
§  Addresses (untyped pointers)

¢  Floa�ng point data of 4, 8, or 10 bytes

¢  Code: Byte sequences encoding series of instruc�ons

¢  No aggregate types such as arrays or structures

§  Just con�guously allocated bytes in memory

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 15

Carnegie Mellon

Assembly Characteris�cs: Opera�ons

¢  Perform arithme�c func�on on register or memory data

¢  Transfer data between memory and register

§  Load data from memory into register
§  Store register data into memory

¢  Transfer control

§  Uncondi�onal jumps to/from procedures
§  Condi�onal branches

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 16

Carnegie Mellon

Object Code
Code for sumstore
0x0400595: ¢  Assembler
§  Translates .s into .o
0x53
0x48 §  Binary encoding of each instruc�on
0x89 §  Nearly-‐complete image of executable code
0xd3
0xe8
§  Missing linkages between code in different
0xf2 files
0xff ¢  Linker
0xff
0xff
§  Resolves references between files
•  Total of 14 bytes
0x48 §  Combines with sta�c run-‐�me libraries
0x89 •  Each instruc�on
E.g., code for malloc, printf
§ 
0x03 1, 3, or 5 bytes
0x5b •  Starts at address
§  Some libraries are dynamically linked
0xc3 0x0400595 §  Linking occurs when program begins
execu�on

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 17

Carnegie Mellon

Machine Instruc�on Example

¢  C Code
*dest = t;
§  Store value t where designated by
dest
¢  Assembly
movq %rax, (%rbx) §  Move 8-‐byte value to memory
§  Quad words in x86-‐64 parlance
§  Operands:
t: Register %rax
dest: Register %rbx
*dest: Memory M[%rbx]
¢  Object Code
0x40059e: 48 89 03
§  3-‐byte instruc�on
§  Stored at address 0x40059e

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 18

Carnegie Mellon

Disassembling Object Code

Disassembled

0000000000400595 <sumstore>:
400595: 53 push %rbx
400596: 48 89 d3 mov %rdx,%rbx
400599: e8 f2 ff ff ff callq 400590 <plus>
40059e: 48 89 03 mov %rax,(%rbx)
4005a1: 5b pop %rbx
4005a2: c3 retq

¢  Disassembler
objdump –d sum
§  Useful tool for examining object code
§  Analyzes bit pa�ern of series of instruc�ons
§  Produces approximate rendi�on of assembly code
§  Can be run on either a.out (complete executable) or .o ﬁle
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 19
Carnegie Mellon

Alternate Disassembly
Disassembled
Object

0x0400595:
0x53 Dump of assembler code for function sumstore:
0x48 0x0000000000400595 <+0>: push %rbx
0x89 0x0000000000400596 <+1>: mov %rdx,%rbx
0xd3 0x0000000000400599 <+4>: callq 0x400590 <plus>
0xe8 0x000000000040059e <+9>: mov %rax,(%rbx)
0xf2 0x00000000004005a1 <+12>:pop %rbx
0xff 0x00000000004005a2 <+13>:retq
0xff
0xff
0x48 ¢  Within gdb Debugger
0x89 gdb sum
0x03
0x5b disassemble sumstore
0xc3 §  Disassemble procedure
x/14xb sumstore
§  Examine the 14 bytes star�ng at sumstore
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 20
Carnegie Mellon

What Can be Disassembled?

% objdump -d WINWORD.EXE

WINWORD.EXE: file format pei-i386

No symbols in "WINWORD.EXE".
Disassembly of section .text:

30001000 <.text>:
30001000: 55 push %ebp
30001001: 8b ec mov %esp,%ebp
30001003: 6a ff
Reverse e ngineering
push
forbidden by
$0xffffffff
30001005: 68Microso�
90 10 00E30 nd push
User License Agreement
$0x30001090
3000100a: 68 91 dc 4c 30 push $0x304cdc91

¢  Anything that can be interpreted as executable code

¢  Disassembler examines bytes and reconstructs assembly source
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 21
Carnegie Mellon

Today: Machine Programming I: Basics

¢  History of Intel processors and architectures
¢  C, assembly, machine code
¢  Assembly Basics: Registers, operands, move
¢  Arithme�c & logical opera�ons

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 22

Carnegie Mellon

x86-‐64 Integer Registers

%rax %eax %r8 %r8d

%rbx %ebx %r9 %r9d

%rcx %ecx %r10 %r10d

%rdx %edx %r11 %r11d

%rsi %esi %r12 %r12d

%rdi %edi %r13 %r13d

%rsp %esp %r14 %r14d

%rbp %ebp %r15 %r15d

§  Can reference low-‐order 4 bytes (also low-‐order 1 & 2 bytes)

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 23
Carnegie Mellon

Some History: IA32 Registers Origin

(mostly obsolete)

%eax %ax %ah %al accumulate

%ecx %cx %ch %cl counter

general purpose

%edx %dx %dh %dl data

%ebx %bx %bh %bl base

%esi
source
%si index

%edi
destination
%di index
stack
%esp %sp pointer
base
%ebp %bp
pointer

16-‐bit virtual registers

(backwards compa�bility)
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 24
Carnegie Mellon

Moving Data %rax

¢  Moving Data %rcx
movq Source, Dest: %rdx
¢  Operand Types %rbx
§  Immediate: Constant integer data %rsi
Example: $0x400, $-533
§  %rdi
§  Like C constant, but preﬁxed with ‘$’
%rsp
§  Encoded with 1, 2, or 4 bytes
§  Register: One of 16 integer registers %rbp
§  Example: %rax, %r13
%rN
§  But %rsp reserved for special use
§  Others have special uses for par�cular instruc�ons
§  Memory: 8 consecu�ve bytes of memory at address given by register
§  Simplest example: (%rax)
§  Various other “address modes”
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 25
Carnegie Mellon

movq Operand Combina�ons

Source Dest Src,Dest C Analog

Reg movq $0x4,%rax temp = 0x4;

Imm
Mem movq $-147,(%rax) *p = -147;

Reg movq %rax,%rdx temp2 = temp1;

movq Reg
Mem movq %rax,(%rdx) *p = temp;

Mem Reg movq (%rax),%rdx temp = *p;

Cannot do memory-‐memory transfer with a single instruc�on

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 26
Carnegie Mellon

Simple Memory Addressing Modes

¢  Normal (R) Mem[Reg[R]]
§  Register R speciﬁes memory address
§  Aha! Pointer dereferencing in C

movq (%rcx),%rax

¢  Displacement D(R) Mem[Reg[R]+D]

§  Register R specifies start of memory region
§  Constant displacement D specifies offset

movq 8(%rbp),%rdx

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 27

Carnegie Mellon

Example of Simple Addressing Modes

void swap
(long *xp, long *yp)
{ swap:
long t0 = *xp; movq (%rdi), %rax
long t1 = *yp; movq (%rsi), %rdx
*xp = t1; movq %rdx, (%rdi)
*yp = t0; movq %rax, (%rsi)
} ret

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 28

Carnegie Mellon

Understanding Swap()
Memory
void swap Registers
(long *xp, long *yp)
{ %rdi
long t0 = *xp;
%rsi
long t1 = *yp;
*xp = t1; %rax
*yp = t0;
} %rdx

Register Value
%rdi xp
%rsi yp swap:
%rax t0 movq (%rdi), %rax # t0 = *xp
%rdx t1 movq (%rsi), %rdx # t1 = *yp
movq %rdx, (%rdi) # *xp = t1
movq %rax, (%rsi) # *yp = t0
ret
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 29
Carnegie Mellon

Understanding Swap()
Memory
Registers Address
123 0x120
%rdi 0x120
0x118
%rsi 0x100
0x110
%rax 0x108
%rdx 456 0x100