Digital Systems Design

Using Verilog 1st Edition

Roth

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Chapter 5: SM Charts and Microprogramming

5.1 (a)

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 (b)
module SM_desc(X1, X2, CLK, Z1, Z2);
input X1, X2, CLK;
output reg Z1, Z2;

reg [1:0] state, nextstate;

initial begin
state = 2'b00;
nextstate = 2'b00;
Z1 = 1'b0;
Z2 = 1'b0;
end

96
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 always @(state, X1, X2)
begin
Z1 = 1'b0;
Z2 = 1'b0;
case(state)
0: begin
if(X1 == 1'b1) begin
Z2 = 1'b1;
if(X2 == 1'b1)
nextstate = 2'b00;
else begin
Z1 = 1'b1;
nextstate = 2'b01;
end
end
else if(X2 == 1'b1) begin
Z1 = 1'b1;
nextstate = 2'b10;
end
else
nextstate = 2'b11;
end
1: begin
Z1 = 1'b1;
if(X1 == 1'b1) begin
Z2 = 1'b1;
if(X2 == 1'b1)
nextstate = 2'b11;
else
nextstate = 2'b10;
end
else if(X2 == 1'b1)
nextstate = 2'b01;
else
nextstate = 2'b00;
end
2: begin
if(X1 == 1'b1) begin
Z2 = 1'b1;
nextstate = 2'b01;
if(X2 == 1'b0)
Z1 = 1'b1;
end
else if(X2 == 1'b1) begin
Z1 = 1'b1;
nextstate = 2'b00;
end
else begin
nextstate = 2'b11;
end
end
3: begin
if(X1 == 1'b1) begin
Z2 = 1'b1;
if(X2 == 1'b1)
nextstate = 2'b00;
else
nextstate = 2'b01;
end
else
nextstate = 2'b10;
end

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 endcase
end

always @(posedge CLK)

begin
state <= nextstate;
end

endmodule

5.2

Z1 and Z2 are Mealy outputs; Z3 is a Moore output.

5.3 (a)

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 (b)

ENTER, LEAVE, READY, RED, GREEN, BLUE used as described in the problem
INC: increment counter by 1
DEC: decrement counter by 1
GE8: counter value is greater then or equal to 8
GE10: counter value is greater then or equal to 10
ODD: counter value is odd

(c)

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5.4 (a)

(b)

(c)
module DIV_SM_desc(CLK, St, Divisor, Dividend, V, Quotient);
input CLK, St;
input [4:0] Divisor;
input [7:0] Dividend;
output reg V;

100
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 output [2:0] Quotient;

reg [2:0] state, nextstate;

reg Load, Sh, Su;
reg [4:0] RegB;
reg [8:0] ACC;
wire [5:0] ACCin;
wire C;
wire [6:0] Diff;
wire [5:0] Subout;

initial begin
state = 3'b000;
nextstate = 3'b000;
ACC = 9'b000000000;
RegB = 5'b00000;
end

assign Quotient = ACC[2:0];

assign Diff = {1'b0, ACC[8:3]} - RegB;
assign Subout = Diff[5:0];
assign C = ~Diff[6];

always @(state, St, C)

begin
Load = 1'b0;
Sh = 1'b0;
Su = 1'b0;
V = 1'b0;
case(state)
0: begin
if(St == 1'b1) begin
Load = 1'b1;
nextstate = 3'b001;
end
else
nextstate = 3'b000;
end
1: begin
if(C == 1'b1) begin
V = 1'b1;
nextstate = 3'b000;
end
else begin
Sh = 1'b1;
nextstate = 3'b010;
end
end
2, 3: begin
if(C == 1'b1) begin
Su = 1'b1;
nextstate = state;
end
else begin
Sh = 1'b1;
nextstate = state + 3'b001;
end
end
4: begin
nextstate = 3'b000;
if(C == 1'b1)
Su = 1'b1;
end

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 default: begin
end
endcase
end

always @(posedge CLK)

begin
state <= nextstate;
if(Load == 1'b1) begin
ACC <= {1'b0, Dividend};
RegB <= Divisor;
end
else if(Sh == 1'b1)
ACC <= {ACC[7:0], 1'b0};
else if(Su == 1'b1) begin
ACC[8:3] <= Subout;
ACC[0] <= 1'b0;
end
else begin
end
end

endmodule

(d) add list *

add wave *
force Clk 0 0, 1 10 -repeat 20
force Dividend 01011101
force Divisor 10001
force St 1 5,0 15
run

5.5

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5.6

5.7

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5.8 (a)
A B
Start 0100011101
Shift #1 0 100011101
Shift #2 01 00011101
Shift #3 010 0011101
Shift #4 0100 011101
Shift #5 0 1000 11101
Add 0 1011 11101
Shift #6 1 0111 1101
Add 1 1010 1101
Shift #7 11 0101 101
Add 11 1000 101
Shift #8 111 0001 01
Add 1010 0001 01
Shift #9 1 0100 0010 1
Shift #10 10 1000 0101

(b)

(c)

104
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 (d)
module P5_8(St, Clk, Number, A, Done);
input St, Clk;
input [9:0] Number;
inout [11:0] A;
output reg Done;

reg [11:0] Atemp;

reg [9:0] B;
reg [1:0] state, nextstate;
reg [3:0] cnt;
reg Load, INC_D1, INC_D2, Sh;

wire C10, D1_GE5, D2_GE5;

initial begin
Atemp = A;
B = 10'b0000000000;
state = 2'b00;
nextstate = 2'b00;
cnt = 4'b0000;
end

assign A = Atemp;
assign C10 = (cnt == 4'b1010) ? 1'b1 : 1'b0;
assign D1_GE5 = (A[3:0] >= 4'b0101)? 1'b1 : 1'b0;
assign D2_GE5 = (A[7:4] >= 4'b0101)? 1'b1 : 1'b0;

always @(state, St, C10, D1_GE5, D2_GE5)

begin
Load = 1'b0;
INC_D1 = 1'b0;
INC_D2 = 1'b0;
Sh = 1'b0;
Done = 1'b0;
case(state)
0: begin
if(St == 1'b1) begin
nextstate = 2'b01;
Load = 1'b1;
end
else
nextstate = 2'b00;
end
1: begin
if(C10 == 1'b1) begin
nextstate = 2'b00;
Done = 1'b1;
end
else begin
nextstate = 2'b10;
if(D1_GE5 == 1'b1)
INC_D1 = 1'b1;
if(D2_GE5 == 1'b1)
INC_D2 = 1'b1;
end
end
2: begin
Sh = 1'b1;
nextstate = 2'b01;
end
default: begin

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 end
endcase
end

always @(posedge Clk)

begin
state <= nextstate;
if(INC_D1 == 1'b1)
Atemp[3:0] <= Atemp[3:0] + 4'b0011;
if(INC_D2 == 1'b1)
Atemp[7:4] <= Atemp[7:4] + 4'b0011;
if(Sh == 1'b1) begin
Atemp <= {Atemp[10:0], B[9]} ;
cnt <= cnt + 4'b0001;
B <= {B[8:0], 1'b0};
end
if(Load == 1'b1)
B <= Number;
end

endmodule

5.9 (a)

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 (b)

(c)
module P5_9(clk, St, Mplier, Mcand, Product, Done);
input clk, St;
input [15:0] Mplier, Mcand;
output [30:0] Product;
output Done;

reg [1:0] State;

reg [15:0] A, B;
reg [4:0] Counter;
wire K;
wire M;
wire [15:0] addout;

initial begin
State = 2'b00;
A = 16'h0000;
B = 16'h0000;
Counter = 5'b00000;
end

assign M = B[0];
assign Done = (State == 2'b10)? 1'b1: 1'b0;
assign Product = {A[14:0], B};
assign K = (Counter == 5'b01111)? 1'b1 : 1'b0;
assign addout = (K == 1'b0)? (A + Mcand) : (A + (~Mcand) + 16'h0001);

always @(posedge clk)

begin
case(State)
0: begin
if(St == 1'b1) begin
A <= 16'h0000;
B <= Mplier;
State <= 2'b01;
Counter <= 5'b00000;
end
end

107
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 1: begin
Counter <= Counter + 5'b00001;
if(K == 1'b0) begin
if(M == 1'b1) begin
A <= {Mcand[15], addout[15:1]};
B <= {addout[0], B[15:1]};
end
else begin
A <= {A[15], A[15:1]};
B <= {A[0], B[15:1]};
end
end
else begin
State <= 2'b10;
if(M == 1'b1) begin
A <= {(~Mcand[15]), addout[15:1]};
B <= {addout[0], B[15:1]};
end
else begin
A <= {A[15], A[15:1]};
B <= {A[0], B[15:1]};
end
end
end
2: begin
State <= 2'b00;
end
default: begin
end
endcase
end

endmodule

5.10

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5.11
module test_el;
reg CLK;
reg CALL1, CALL2, FB1, FB2, FS1, FS2, DC;
wire UP, DOWN, DO;

initial begin
CLK = 1'b0;
CALL1 = 1'b0;
CALL2 = 1'b0;
FB1 = 1'b0;
FB2 = 1'b0;
FS1 = 1'b0;
FS2 = 1'b0;
DC = 1'b0;
end

elev_control eltest(CALL1, CALL2, FB1, FB2, FS1, FS2, DC, CLK, UP, DOWN,
DO);

always
#6000 CLK = ~CLK;

always @(UP, DOWN)

begin
if(UP == 1'b1) begin
if(FS1 == 1'b1) begin
#3600 FS1 = 1'b0;
#39600 FS2 = 1'b1;
end
end
else if(DOWN == 1'b1) begin
if(FS2 == 1'b1) begin
#3600 FS2 = 1'b0;
#39600 FS1 = 1'b1;
end
end
end

always @(posedge DO)

begin
DC = 1'b0;
#18000;
DC = 1'b1;
end

always
begin
CALL1 = 1'b1;
#3600;
CALL1 = 1'b0;
#7200;
FB2 = 1'b1;
#3600;
FB2 = 1'b0;
#14400;
FB1 = 1'b1;
#3600;
FB1 = 1'b0;
#3600;
CALL2 = 1'b1;
#3600;
CALL2 = 1'b0;

109
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 #36000;
FB2 = 1'b1;
#3600;
FB2 = 1'b0;
end

endmodule

5.12 (a)

(b) A+ = A'BX2 + A'B'X2(X1' + X3) + {AB} = BX2 + A'X2(X1' + X3)

B+ = A'B'(X2' + X1X3') + AB'X1' + A'BX2' + {AB} = AX1' + A'B'X1X3' + A'X2'
Z1 = A + B + X 2
Z2 = A'B'X2'
Z3 = A'B'X1'X2

(c)
A B X1 X2 X3 A+ B+ Z1 Z2 Z3
- 1 - 1 - 1 0 0 0 0
0 - 0 1 - 1 0 0 0 0
0 - - 1 1 1 0 0 0 0
1 - 0 - - 0 1 0 0 0
0 0 1 - 0 0 1 0 0 0
0 - - 0 - 0 1 0 0 0
1 - - - - 0 0 1 0 0
- 1 - - - 0 0 1 0 0
- - - 1 - 0 0 1 0 0
0 0 - 0 - 0 0 0 1 0
0 0 0 1 - 0 0 0 0 1

(d) 32 words by 5 bits;

A B X1 X2 X3 A+ B+ Z1 Z2 Z3
0 0 0 0 0 0 1 0 1 0
0 0 0 0 1 0 1 0 1 0
0 0 0 1 0 1 0 0 0 1
0 0 0 1 1 1 0 1 0 1
0 0 1 0 0 0 1 0 1 0

110
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5.13 (a)

(b) Q1+ = Q1X 1' + Q3X 4'X 5

Q2+ = Q2X3+ Q 1X 1X 2' + Q 3X 4
Q3+ = Q3X 4'X5' + Q1X1X2+ Q 2X 3'
Z1 = Q1X1X2'
Z2 = Q2X3
Z3 = Q2 + Q3X4

(c)
module Egns_Desc(X1, X2, X3, X4, X5, CLK, Z1, Z2, Z3);
input X1, X2, X3, X4, X5, CLK;
output Z1, Z2, Z3;

reg Q1, Q2, Q3;

initial begin
Q1 = 1'b1;
Q2 = 1'b0;
Q3 = 1'b0;
end

assign Z1 = Q1 & X1 & (~X2);

assign Z2 = Q2 & X3;
assign Z3 = Q2 | (Q3 & X4);

always @(negedge CLK)

begin
Q1 <= (Q1 & ~X1) | (Q3 & ~X4 & X5);
Q2 <= (Q2 & X3) | (Q1 & X1 & ~X2) | (Q3 & X4);
Q3 <= (Q3 & ~X4 & ~X5) | (Q1 & X1 & X2) | (Q2 & ~X3);
end

endmodule

111
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5.14 (a)

(b)
A B C K Kd A+ B+ C+ C0 C1 C2 V
S0 0 0 0 - - 0 0 1 0 0 0 0
S1 0 0 1 1 1 0 1 0 1 1 1 0
0 0 1 0 - 0 0 1 1 1 1 0
0 0 1 - 0 0 0 1 1 1 1 0
S2 1 0 1 0 0 1 0 1 0 0 0
0 1 0 1 1 1 0 1 1 0 0 1
0 1 0 0 - 0 1 1 1 0 0 0
S3 0 1 1 1 0 0 1 1 0 1 0 0
0 1 1 1 1 1 0 1 0 1 0 1
0 1 1 0 - 1 0 0 0 1 0 0
S4 1 0 0 1 1 1 0 1 0 0 1 1
1 0 0 0 - 1 0 0 0 0 1 0
1 0 0 - 0 1 0 0 0 0 1 0
S5 1 0 1 - 0 0 0 1 1 1 1 0
1 0 1 - 1 1 0 1 1 1 1 0

(c) A+ = A'BC 'K Kd + A'BCK Kd + A'BCK' + AB'C ' + AB'CKd

112
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 (d) For state assignment S0 = 100000, S1 = 010000… and D flip-flops Q0Q1Q2Q3Q4Q5:
Q0 + = 0
Q1+ = Q0+ Q 1K' + Q1Kd' + Q 5Kd'
Q2+ = Q1KKd + Q2KKd'
Q3+ = Q2K' + Q3KKd'
Q4+ = Q3K' + Q4K' + Q 4Kd'
Q5+ = Q2KKd + Q 3KKd + Q 4KKd + Q 5Kd
V = Q2KKd + Q3KKd + Q4KKd
C0 = Q1 + Q2 + Q5
C1 = Q1 + Q3 + Q5
C2 = Q1 + Q4 + Q5

5.15 (a)
module P5_15(X1, X2, X3, Clk, Z1, Z2, Z3);
input X1, X2, X3, Clk;
output reg Z1, Z2, Z3;

reg [1:0] state, nextstate;

initial begin
state = 2'b00;
nextstate = 2'b00;
end

always @(state, X1, X2, X3)

begin
Z1 = 1'b0;
Z2 = 1'b0;
Z3 = 1'b0;
case(state)
0: begin
if(X1 == 1'b1)
nextstate = 2'b01;
else begin
Z2 = 1'b1;
if(X2 == 1'b1)
Z3 = 1'b1;
if(X3 == 1'b1)
nextstate = 2'b10;
else
nextstate = 2'b01;
end
end
1: begin
nextstate = 2'b00;
Z1 = 1'b1;
end
2: begin
if(X2 == 1'b1)
nextstate = 2'b10;
else begin
Z1 = 1'b1;
if(X1 == 1'b1)
nextstate = 2'b00;
else begin
Z3 = 1'b1;
nextstate = 2'b01;
end
end

113
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 end
default: begin
end
endcase
end

always @(negedge Clk)

begin
state <= nextstate;
end

endmodule

(b)
A B X1 X2 X3 A+ B+ Z1 Z2 Z3
S0 0 0 1 - - 0 1 0 0 0
0 0 0 0 0 0 1 0 1 0
0 0 0 0 1 1 0 0 1 0
0 0 0 1 0 0 1 0 1 1
0 0 0 1 1 1 0 0 1 1
S1 0 1 - - - 0 0 1 0 0
S2 1 0 - 1 - 1 0 0 0 0
1 0 1 0 - 0 0 1 0 0
1 0 0 0 - 0 1 1 0 1

(c)

5.16 (a) Block diagram is similar to Figure 5-33 with MUX inputs of 1, X1, X2, and X3; ROM outputs
of Z1, Z2 and Z3; 2 bits for test, and 3 bits for the NST and counter.

(b)

114
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 (c)
State Q1Q2Q3 Test NST Z1 Z2 Z3
S0 000 01 100 0 0 1
S02 001 11 111 0 0 0
S1 010 10 000 0 0 0
S2 011 00 000 0 0 0
S01 100 10 110 0 0 0
Sx 101 00 011 0 0 0
S03 110 00 010 1 0 0
S04 111 00 011 0 1 0

(d)
module P5_16(X1, X2, X3, CLK, Z1, Z2, Z3);
input X1, X2, X3, CLK;
output Z1, Z2, Z3;

reg [2:0] PST;

reg [7:0] ROM [0:7];
wire [7:0] ROM_Out;
wire Load;

initial begin
PST = 3'b000;
ROM[0] = 8'b01100001;
ROM[1] = 8'b11111000;
ROM[2] = 8'b10000000;
ROM[3] = 8'b00000000;
ROM[4] = 8'b10110000;
ROM[5] = 8'b00011000;
ROM[6] = 8'b00010100;
ROM[7] = 8'b00011010;
end

assign ROM_OUT = ROM[PST];

assign Z3 = ROM_Out[2];
assign Z2 = ROM_Out[1];
assign Z1 = ROM_Out[0];
assign Load = (ROM_Out[1] == 1'b0)? ((ROM_Out[0] == 1'b0)? 1'b1 : X1)
:
((ROM_Out[0] == 1'b0)? X2 : X3);

always @(posedge CLK)

begin
if(Load == 1'b1)
PST <= ROM_Out[5:3]; // NST
else
PST <= PST + 1;
end
endmodule

115
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5.17 (a)

(b)
Q1Q2Q3 TEST NSF NST Z1 Z2 Z3
000 01 S4 S3 0 0 1
001 10 S2 S0 0 0 0
010 00 S0 S0 0 0 0
011 10 S2 S5 0 0 0
100 11 S1 S6 0 0 0
101 00 S1 S1 1 0 0
110 00 S2 S2 0 1 0

(c) 7 × 11 or 8 × 11

(d) 25 × 5

5.18 (a)

116
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 (b)
State ABC Test NSF NST Z1 Z2 Z3
S0 000 01 010 001 0 0 0
S01 001 10 011 101 0 0 0
S03 010 11 110 101 1 0 0
S02 011 00 100 100 0 1 0
S1 100 01 101 100 0 0 0
S2 101 00 000 000 0 0 1
S3 110 10 101 000 0 1 0

(c) Block diagram is similar to Figure 5-29 with inputs of X1 and X2; PLA outputs of Z1, Z2 and Z3;
and a 3-bit, 2-to-1 MUX to select NSF or NST.

5.19 (a) 1. Only Moore outputs; 2. Only 1 decision box per state; 3. NSF for each state should be state
+1

(b) Same as Solution 5.16 (b)

5.20 (a) 1. Only Moore outputs; 2. Only 1 decision box per state; 3. NSF for each state should be state
+1

(b)

5.21 (a) Block diagram is similar to Figure 5-29 with MUX inputs of 1, X1, X2, and X3'; ROM outputs
of Z1, Z2 and Z3; and 3 bits for the NST and counter.

117
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 (b)

(c)
ABC Test NST Z1 Z2 Z3
000 01 100 0 0 0
001 11 000 1 0 0
010 01 110 0 0 0
011 00 000 0 1 0
100 10 110 0 0 0
101 00 110 0 1 0
110 00 000 0 0 1

5.22 (a) 1. Convert Mealy outputs to Moore outputs; 2. Only one input tested per state

118
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 (b)
Addr Test NSF NST Z1 Z2 Z3
S0 00 S3 S6 0 0 0
S3 11 S1 S1 1 0 0
S1 10 S0 S4 0 0 0
S4 00 S5 S2 0 0 0
S5 11 S0 S0 0 1 0
S6 01 S7 S2 0 0 0
S7 11 S2 S2 0 1 0
S2 11 S0 S0 0 0 1
Test 00 – X1; Test 01 – X2; Test 10 – X3; Test 11 – 1

(c) There are 8 address locations and each have 11 bits (2 test, 3 NSF, 3 NST, 3 outputs) so there
are 8 × 11 bits needed.

(d) 25 inputs are needed (2-bit FF state, 3 inputs) and 5 outputs are needed (2 for next state, 3
outputs) so 25 × 5 bits.

5.23 (a)

(b) Test 00: 1; Test 01: X1; Test 10: X2; Test 11: X3

Addr Test NST Z1 Z2

000 10 100 1 1
001 11 101 0 1
010 11 010 1 1
011 01 000 1 0
100 01 001 0 1
101 11 010 1 0
110 00 011 0 0

119
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 (c) The circuit has 26 possible inputs (3-bit FF state, 3 inputs) and 5 output functions (3-bit next
state, 2 outputs) so a 26 × 5 bit ROM is required.

5.24 (a) For flip-flops AB,

A+ = A'B'X1X3 + A'BX2'
B+ = A'B'X1' + A'B'X1X3'
Z1 = A'B'
Z2 = A'B'X1'X2
Z3 = A'B'X1X3 + A'B
Z4 = AB'

(b)

(c) Test 00: 1; Test 01: X1; Test 10: X2; Test 11: X3

Addr Test NST Z1 Z2 Z3 Z4

000 01 100 1 0 0 0
001 10 110 0 0 0 0
010 10 011 0 0 1 0
011 00 000 0 0 0 1
100 10 111 0 0 0 0
101 00 010 0 0 0 0
110 00 010 0 1 0 0
111 00 011 0 0 1 0

(d) 23 states, 2 test bits, 3 NST bits, 4 outputs: 23 × 9

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5.25

5.26

5.27 (a)

(b) State Assignment: S0: 100; S1: 010; S2: 001. For D flip-flops Q0Q1Q2:
Q0+ = Q0X1' + Q2
Q1+ = Q0 X1 + Q1 B'
Q2+ = Q1 B
A = Q 0 X1
Z 1 = Q2

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5.28 (a)

Note: R = Reset

(b) State Assignment: S0: 00; S1: 01; S2: 10; S3: 11. For D flip-flops AB:

A+ = A'BN + A'D + AB'R' + AB'N + B'D

B+ = B'D'N + A'BN'R' + A'BDN' + AB'D

A B D N R A+ B+ Z0 Z1 Z2 Z3 Z4
S0 0 0 0 0 - 0 0 1 0 0 0 0
0 0 0 1 - 0 1 1 0 0 0 0
0 0 1 - - 1 0 1 0 0 0 0
S1 0 1 0 0 0 0 1 0 1 0 0 0
0 1 0 0 1 0 0 1 1 0 0 0
0 1 - 1 - 1 0 0 1 0 0 0
0 1 1 0 - 1 1 0 1 0 0 0
S2 1 0 0 0 0 1 0 0 0 1 0 0
1 0 0 0 1 0 0 1 0 1 0 0
1 0 0 1 - 1 1 0 0 1 0 0
1 0 1 - - 1 1 0 0 1 0 0
S3 1 1 - - - 0 0 0 0 0 1 1

(c) A 32 x 7 ROM is required because there are 5 inputs and 7 outputs.

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 (d)

(e) Test 00: D; Test 01: N; Test 10: R; Test 11: 1

State Addr Test NST Z0 Z1 Z2 Z3 Z4

S0 0000 00 0111 1 0 0 0 0
SA 0001 01 0011 0 0 0 0 0
SB 0010 11 0000 0 0 0 0 0
S1 0011 01 0111 0 1 0 0 0
SC 0100 00 1011 0 0 0 0 0
SD 0101 10 0000 0 0 0 0 0
SE 0110 11 0011 0 0 0 0 0
S2 0111 00 1011 0 0 1 0 0
SF 1000 01 1011 0 0 0 0 0
SG 1001 10 1000 0 0 0 0 0
SH 1010 11 0111 0 0 0 0 0
S3 1011 11 0000 0 0 0 1 1

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