Memory and

Programmable Logic

7-1
 Outline
n Introduction
n Random-Access Memory
n Memory Decoding
n Error Detection and Correction
n Read-Only Memory
n Programmable Devices
n Sequential Programmable Devices

7-2
 Mass Memory Elements
n Memory is a collection of binary cells together
with associated circuits needed to transfer
information to or from any desired location

n Two primary categories of memory:

n Random access memory (RAM)
n Read only memory (ROM)
7-3
 Programmable Logic Device
n The binary information within the device can be
specified in some fashion and then embedded
within the hardware
n Most of them are programmed by breaking the fuses
of unnecessary connections
n Four kinds of PLD are introduced
n Read-only memory (ROM)
n Programmable logic array (PLA)
n Programmable array logic (PAL)
n Field-programmable gate array (FPGA)
7-4
 Outline
n Introduction
n Random-Access Memory
n Memory Decoding
n Error Detection and Correction
n Read-Only Memory
n Combinational Programmable Devices
n Sequential Programmable Devices

7-5
 Random Access Memory
n A word is the basic unit that
moves in and out of memory
n The length of a word is often
multiples of a byte (=8 bits)
n Memory units are specified
by its number of words
and the number of bits in
each word
n Ex: 1024(words) x 16(bits)
n Each word is assigned a
particular address, starting
from 0 up to 2k – 1
(k = number of address lines)
7-6
 Write and Read Operations
n Write to RAM
n Apply the binary address of the desired word
to the address lines
n Apply the data bits that must be stored in
memory to the data input lines
n Activate the write control
n Read from RAM
n Apply the binary address of the desired word
to the address lines
n Activate the read control
7-7
 Timing Waveforms
n CPU clock = 50 MHz
n cycle time = 20 ns
n Memory cycle time = 50
ns
n The time required to
complete a write
operation
n Memory access time
n The time required to read
it
n The control signals
must stay active for at
least 50 ns
n 3 CPU cycles are required
7-8
 Types of Memories
n Access mode:
n Random access: any locations can be accessed in any order
n Sequential access: accessed only when the requested word
has been reached (ex: hard disk)
n Operating mode:
n Static RAM (SRAM)
n Dynamic RAM (DRAM)
n Volatile mode:
n Volatile memory: lose stored information when power is
turned off (ex: RAM)
n Non-volatile memory: retain its storage after removal of
power (ex: flash, ROM, hard-disk, … )
7-9
 SRAM vs. DRAM
n Static RAM: n Dynamic RAM:
n Use internal latch to store n Use a capacitor to store the
the binary information binary information
n Stored information remains n Need periodically refreshing
valid as long as power is on to hold the stored info.
n Shorter read and write cycles n Longer read and write cycles
n Larger cell area and power n Smaller cell area and power
consumption consumption

7-10
Memory R/W Operations
module memory (Enable,ReadWrite,Address,DataIn,DataOut);
input Enable,ReadWrite;
input [3:0] DataIn;
input [5:0] Address;
output [3:0] DataOut;
reg [3:0] DataOut;
reg [3:0] Mem [0:63]; //64 x 4 memory
always @ (Enable or ReadWrite)
if (Enable)
if (ReadWrite)
DataOut = Mem[Address]; //Read
else
Mem[Address] = DataIn; //Write
else DataOut = 4'bz; //High impedance state
endmodule

7-11
 Outline
n Introduction
n Random-Access Memory
n Memory Decoding
n Error Detection and Correction
n Read-Only Memory
n Combinational Programmable Devices
n Sequential Programmable Devices

7-12
 Memory Construction

A SRAM Cell

Large memory
will require
large decoder

7-13
 Coincident Decoding
n Address decoders are often
divided into two parts
n A two-dimensional scheme
n The total number of gates in
decoders can be reduced
n Can arrange the
memory cells to a
square shape
n EX: 10-bit address
404 = 0110010100
X = 01100 (first five)
Y = 10100 (last five)
7-14
 Address Multiplexing
n Memory address lines often
occupy too much I/O pads
n 64K = 16 lines
n 256M = 28 lines
n Share the address lines of
X and Y domains
n Reduce the number of lines
to a half
n An extra register is required
for both domain to store the
address
n Two steps to send address
n RAS=0: send row address
n CAS=0: send column address
7-15
 Outline
n Introduction
n Random-Access Memory
n Memory Decoding
n Error Detection and Correction
n Read-Only Memory
n Combinational Programmable Devices
n Sequential Programmable Devices

7-16
 Error Detection & Correction
n Memory arrays are often very huge
n May cause occasional errors in data access
n Reliability of memory can be improved by
employing error-detecting and correcting codes
n Error-detecting code: only check for the existence
of errors
n Most common scheme is the parity bit
n Error-correcting code: check the existence and
locations of errors
n Use multiple parity check bits to generate a syndrome
that can indicate the erroneous bits
n Complement the erroneous bits can correct the errors
7-17
 Hamming Code (1/2)
n k parity bits are added to an n-bit data word
n The positions numbered as a power of 2 are
reserved for the parity bits
n Ex: original data is 11000100 (8-bit)
⇒ Bit position: 1 2 3 4 5 6 7 8 9 10 11 12
P1 P2 1 P4 1 0 0 P8 0 1 0 0
n P1 = XOR of bits (3,5,7,9,11) = 0

P2 = XOR of bits (3,6,7,10,11) =0

P4 = XOR of bits (5,6,7,12) = 1
P8 = XOR of bits (9,10,11,12) = 1
n The composite word is 001110010100 (12-bit)
7-18
 Hamming Code (2/2)
n When the 12 bits are read from memory, the parity
is checked over the same combination of bits
including the parity bit
n C1 = XOR of bits (1,3,5,7,9,11)
C2 = XOR of bits (2,3,6,7,10,11)
C4 = XOR of bits (4,5,6,7,12)
C8 = XOR of bits (8,9,10,11,12)
n (001110010100) à C = C8C4C2C1 = 0000 : no error
(101110010100) à C = C8C4C2C1 = 0001 : bit 1 error
(001100010100) à C = C8C4C2C1 = 0101 : bit 5 error
viewed as a binary number 7-19
 General Rules of Hamming Code
Number of Range of
n The number of parity bits: Check Bits, k Data Bits, n
n The syndrome C with k bits can 3 2-4
represent 2k – 1 error locations 4 5-11
5 12-26
(0 indicates no error) 6 27-57
n 2k – 1 = n + k à 2k – 1 – k = n 7 58-120

n The members of each parity bit:

n C1(P1): have a “1” in bit 1 of their location numbers
1(0001), 3(0011), 5(0101), 7(0111), 9(1001), …
n C2(P2): have a “1” in bit 2 of their location numbers
2(0010), 3(0011), 6(0110), 7(0111), 10(1010), …
n C: with parity bit; P: without parity bit itself
7-20
 Extension of Hamming Code
n Original Hamming code can detect and correct
only a single error
n Multiple errors are not detected
n Add an extra bit as the parity of total coded word
n Ex: 001110010100P 13 (P13=XOR of bits 1 to 12)
n Still single-error correction but double-error detection
n Four cases can occur:
n If C=0 and P=0, no error occurred
n If C≠0 and P=1, single error occurred (can be fixed)
n If C≠0 and P=0, double error occurred (cannot be fixed)
n If C=0 and P=1, an error occurred in the P 13 bit
7-21
 Outline
n Introduction
n Random-Access Memory
n Memory Decoding
n Error Detection and Correction
n Read-Only Memory
n Combinational Programmable Devices
n Sequential Programmable Devices

7-22
Basic ROM Structure

7-23
 Read Only Memory
n A memory device that can permanently keep binary data
n Even when power is turned off and on again
n For a 2k x n ROM,
it consists of
n k inputs (address line)
and n outputs (data)
n 2k words of n-bit each
n A k x 2k decoder
(generate all minterms)
n n OR gates with 2k inputs
n Initially, all inputs of OR gates
and all outputs of the decoder
are fully connected
7-24
 Programming the ROM
n Each intersection (crosspoint) in the ROM is often
implemented with a fuse
n Blow out
unnecessary
connections
according to
the truth table
n “1” means
connected
(marked as X)
n “0” means unconnected
n Cannot recovered after
programmed
7-25
 Design Comb. Circuit with ROM
Inputs Outputs
n Derive the truth A2 A1 A0 B5 B4 B3 B2 B1 B0 Decimal
0 0 0 0 0 0 0 0 0 0
table of the circuit 0 0 1 0 0 0 0 0 1 1
n Determine minimum 0 1 0 0 0 0 1 0 0 4
0 1 1 0 0 1 0 0 1 9
size of ROM 1 0 0 0 1 0 0 0 0 16
n Program the ROM 1 0 1 0 1 1 0 0 1 25
1 1 0 1 0 0 1 0 0 36
1 1 1 1 1 0 0 0 1 49

3 select lines
= 8 minterms

word
length
=4

7-26
Mealy Sequential Network

7-27
ROM Truth Table

7-28
 Types of ROMs
n Mask programming
n Program the ROM in the semiconductor factory
n Economic for large quantity of the same ROM
n Programmable ROM (PROM)
n Contain all fuses at the factory
n Program the ROM by burning out the undesired fuses
(irreversible process)
n Erasable PROM (EPROM)
n Can be restructured to the initial state under a special ultra-
violet light for a given period of time
n Electrically erasable PROM (EEPROM or E 2PROM)
n Like the EPROM except being erased with electrical signals
7-29
 Programmable Logic Devices
n ROM provides full decoding of variables
n Waste hardware if the functions are given
n For known combinational functions, Programmable
Logic Devices (PLD) are often used
n Programmable read-only memory (PROM)
n Programmable array logic (PAL)
n Programmable logic array (PLA)
n For sequential functions, we can use
n Sequential (simple) programmable logic device (SPLD)
n Complex programmable logic device (CPLD) most popular
n Field programmable gate array (FPGA)
7-30
 Outline
n Introduction
n Random-Access Memory
n Memory Decoding
n Error Detection and Correction
n Read-Only Memory
n Combinational Programmable
Devices
n Sequential Programmable Devices
7-31
Configurations of Three PLDs

7-32
PLA Structure

7-33
PLAs
n The decoder in ROM is replaced by an
AND array
n More than 1 product terms can be selected
n The OR array Ors together the product
terms to form the outputs

7-34
PLA
F0 = A’B’+ AC’
F1 = B + AC’
F2 = A’B’+ BC’
F3 = AC + B

7-35
Circuit Structure

7-36
 AND-OR Equivalent Structure

F0 = A’B’+ AC’
F1 = B + AC’
F2 = A’B’+ BC’
F3 = AC + B

7-37
PLA Table

7-38
Multiple-Output Optimization

7-39
Multiple-Output Function
n Minimize each function separately
n 8 product terms
F1 = bd + b’c + ab’
F2 = c + a’bd
F3 = bc + ab’c’+ abd

7-40
Reduced PLA Table

7-41
PLA Realization

7-42
 PLA vs ROM
n PLA
n Each row represents a term
n More than one rows may be selected by
each input combination
n Selected rows are Ored
n ROM
n Each row represents a minterm
n Exactly one row is selected
n Output is the bit pattern stored in each row
7-43
 Programmable Logic Array
n PLA does not provide full decoding F1 = AB’+ AC + A’BC’
F2 = (AC +BC)’
of the variables
n Only generate the terms
you need Generate complemented
outputs (if required)
n The decoder is replaced
by an array of AND gates
that can be programmed
Outputs
Inputs (T) (C)
Product Term A B C F1 F2
AB’ 1 1 0 - 1 -
AC 2 1 - 1 1 1
BC 3 - 1 1 - 1
A’BC’ 4 0 1 0 1 - 7-44
 Implementation with PLA
n Example 7-2: implement the two
functions with PLA
F1(A, B, C) = ∑ (0, 1, 2, 4)
F2(A, B, C) = ∑ (0, 5, 6, 7)
n Goal: minimize the number of
distinct product terms between
two functions

7-45
Programmable Array Logic (PAL)
n AND array is programmable
n Not shared
n OR array is fixed
n Less expensive
n Easier to program

7-46
Combinational PAL Segment

7-47
Programming PAL

7-48
Sequential PAL Segment

Q+=D=A’BQ’+AB’Q

7-49
Example
AND gate is logic 1 when there
are no connections to it

Z’=XQ 3’+X’Q3

D3=Q1Q2Q3+X’Q1Q3’+
XQ1’Q2’

7-50
16R4 PAL
n 8 dedicated inputs
n 4 I/O ports
n 4 D FFs with inverting tristate buffers
n Can be fed back to AND array
n AND array with 16 input variables
n Each OR gate is fed from 8 AND gates

7-51
 Programmable Array Logic
n PAL has a fixed OR array and
a programmable AND array
n Easier to program but not as
flexible as PLA
n Each input has a buffer-
inverter gate
n One of the outputs is fed back
as two inputs of the AND gates
n Unlike PLA, a product term
cannot be shared among gates
n Each function can be simplified by
itself without common terms
7-52
 Implementation with PAL
w=∑(2,12,13) x=∑(7,8,9,10,11,12,13,14,15)
y=∑(0,2,3,4,5,6,7,8,10,11,15) z=∑(1,2,8,12,13)

Product AND Inputs

Term A B C D W Outputs
1 1 1 0 - - w = ABC’
2 0 0 1 0 - + A’B’CD’
3 - - - - -
4 1 - - - - x=A
5 - 1 1 1 - + BCD
6 - - - - -
7 0 1 - - - y = A’B
8 - - 1 1 - + CD
9 - 0 - 0 - + B’D’
10 - - - - 1 z=w
11 1 - 0 0 - + AC’D’
12 0 0 0 1 - + A’B’C’D
7-53
 Outline
n Introduction
n Random-Access Memory
n Memory Decoding
n Error Detection and Correction
n Read-Only Memory
n Combinational Programmable Devices
n Sequential Programmable Devices

7-54
 Sequential PLD
n The most simple sequential PLD = PLA (PAL) + Flip-Flops

n The mostly used

configuration for SPLD
is constructed with
8 to 10 macrocells
as shown right

7-55
22V10

7-56
 22V10
n 12 dedicated inputs, 10 Input/Output
n 10 OR gates
n 8 to 16 AND gates
n Each OR drives an output logic macrocell
n 10 D FFs
n Common clock
n asynchronous reset (AR)
n Synchronous preset (SP)

7-57
Output Macrocell

7-58
Output Cell Configuration

7-59
 Complex PLD
n Complex digital systems often require the connection
of several devices to produce the complex specification
n More economical to use a complex PLD (CPLD)
n CPLD is a collection of individual PLDs on a single IC
with programmable interconnection structure

7-60
 Field Programmable Gate Array
n Gate array: a VLSI circuit with some pre-fabricated
gates repeated thousands of times
n Designers have to provide the desired interconnection
patterns to the manufacturer (factory)
n A field programmable gate array (FPGA) is a VLSI
circuit that can be programmed in the user’s location
n Easier to use and modify
n Getting popular for fast and reusable prototyping
n There are various implementations for FPGA
n More introductions are adopted from “Logic and Computer
Design Fundamentals”, 2nd Edition Updated, by M. Morris
Mano and Charles R. Kime, Prentice-Hall, 2001
7-61
FPGA Structure (Altera)

7-62
FPGA Structure (Xilinx)
Fig. 6-29:
Xilinx® XC4000™ FPGA Structure
(Adapted with Permission of Xilinx, Inc.)

7-63
 Xilinx XC3020
n 64 Configurable logic blocks (CLBs)
n 64 input-output interface blocks
n Interconnection programmed by storing
data in internal configurable memory
cells
n Each CLB with combinational logic and 2
D FFs
n Programmed logic functions and
interconnections are retained until power
is off
7-64
Configuration Memory Cell

Each memory is selected in turn

Each connection point has an associated memory
cell

7-65
Xilinx 3000 Series

7-66
CLB
n 5 logic inputs
n Data input (DI)
n Clock (K)
n Clock enable (EC)
n Direct reset (RD)
n 2 outputs (X,Y)

7-67
 Store the Programming Info.
n SRAM technology is
used
n M = 1-bit SRAM
n Loaded from the
PROM after power on
n Store control values
n Control pass transistor
n Control multiplexer
n Store logic functions
n Store the value of
each minterm in the
truth table

7-68
 Xilinx FPGA Routing
n Fast direct interconnect
n Adjacent CLBs
n General purpose
interconnect
n CLB – CLB or CLB – IOB
n Through switch matrix
n Long lines
n Across whole chip
n High fan-out, low skew
n Suitable for global signals
(CLK) and buses
n 2 tri-states per CLB for
busses
7-69
General Interconnect

7-70
Direct Interconnect

7-71
Long Lines

7-72
 Xilinx Switch Matrix
n Six pass transistors to control each switch node
n The two lines at point 1 are joined together
n At point 2, two distinct signal paths pass through one
switch node

7-73
Configurable Logic Block (CLB)
n Combinational logic via lookup table
n Any function(s) of available inputs
n Output registered and/or combinational

7-74
Simplified CLB Structure

7-75
I/O Block (IOB)
n Periphery of identical I/O blocks
n Input, output, or bidirectional
n Registered, latched, or combinational
n Three-state output
n Programmable output slew rate

7-76
 Input/Output Mode of an IOB
n Input
n 3-state control places
the output buffer into
high impedance
n Direct in and/or
registered in
n Output
n 3-state driver should be
enabled by TS signal
n Direct output or
registered output

7-77
 Design with FPGA
n Using HDL, schematic editor, SM chart or FSM
diagram to capture the design
n Simulate and debug the design
n Work out detail logic and feed the logic into
CLBs and IOBs
n Completed by a CAD tool
n Generate bit pattern for programming the
FPGA and download into the internal
configurable memory cells
n Test the operations
7-78
 FPGA Design Flow
logic + layout synthesis

n Advantages: Fast and reusable prototyping

n Can be reprogrammed and reused
n Implementation time is very short
n Disadvantages: Expensive and high volume
7-79
 Download to a FPGA Demo Board

Source: CIC training manual 7-80

 HDL Modeling for Memory
n Modeling ROM and combinational PLDs
n Similar to modeling a combinational code converter
n Modeling RAM
n Use memory array declaration in Verilog
ex: reg [3:0] MY_MEM [0:63]; // 64 4-bit registers
MY_MEM[0] ß 4-bit variable
n Can load memory by using a system task
ex: $readmemb(“mem_content”, MY_MEM, 0, 63);
n If synthesized, only SRAM (array of registers) will
be generated
n Use memory compiler or pre-designed layout instead
7-81