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Chap 5

This document discusses cache memory configurations and performance. It provides details on cache block size, word size, tag size, number of blocks, hit rate and access time for three sample cache configurations. The second configuration has the best performance with a miss rate of 10/12=83%. Formulas are also given for calculating total cache size based on parameters like data size, block size, word size and number of blocks. Increasing the block size from 2 words to 16 words reduces the tag size which allows using a larger cache size of 1024 blocks.

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Hicham Samer Wehbi
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19 views2 pages

Chap 5

This document discusses cache memory configurations and performance. It provides details on cache block size, word size, tag size, number of blocks, hit rate and access time for three sample cache configurations. The second configuration has the best performance with a miss rate of 10/12=83%. Formulas are also given for calculating total cache size based on parameters like data size, block size, word size and number of blocks. Increasing the block size from 2 words to 16 words reduces the tag size which allows using a larger cache size of 1024 blocks.

Uploaded by

Hicham Samer Wehbi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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5.1.

1 4

5.1.2 I, J

5.1.3 A[I][J]

5.1.4 3596 8 800/4 288/4 8000/4

5.1.5 I, J

5.1.6 A(J, I)

5.2.1

Word Address Binary Address Tag Index Hit/Miss 3 0000 0011 0 3 M 180 1011 0100 11 4 M 43 0010
1011 2 11 M 2 0000 0010 0 2 M 191 1011 1111 11 15 M 88 0101 1000 5 8 M 190 1011 1110 11 14 M 14
0000 1110 0 14 M 181 1011 0101 11 5 M 44 0010 1100 2 12 M 186 1011 1010 11 10 M 253 1111 1101
15 13 M

5.2.2

Word Address Binary Address Tag Index Hit/Miss 3 0000 0011 0 1 M 180 1011 0100 11 2 M 43 0010
1011 2 5 M 2 0000 0010 0 1 H 191 1011 1111 11 7 M 88 0101 1000 5 4 M 190 1011 1110 11 7 H 14 0000
1110 0 7 M 181 1011 0101 11 2 H 44 0010 1100 2 6 M 186 1011 1010 11 5 M 253 1111 1101 15 6 M

5.2.3

Cache 1 Cache 2 Cache 3 Word Address Binary Address Tag index hit/miss index hit/miss index hit/miss
3 0000 0011 0 3 M 1 M 0 M 180 1011 0100 22 4 M 2 M 1 M 43 0010 1011 5 3 M 1 M 0 M 2 0000 0010 0
2 M 1 M 0 M 191 1011 1111 23 7 M 3 M 1 M 88 0101 1000 11 0 M 0 M 0 M 190 1011 1110 23 6 M 3 H 1
H 14 0000 1110 1 6 M 3 M 1 M 181 1011 0101 22 5 M 2 H 1 M 44 0010 1100 5 4 M 2 M 1 M 186 1011
1010 23 2 M 1 M 0 M 253 1111 1101 31 5 M 2 M 1 M

Cache 1 miss rate 100%

Cache 1 total cycles 12 25 12 2 324

Cache 2 miss rate 10/12 83%

Cache 2 total cycles 10 25 12 3 286

Cache 3 miss rate 11/12 92%

cache 3 total cycles 11 25 12 5 335

Cache 2 provides the best performance.

5.2.4

First we must compute the number of cache blocks in the initial cache confi guration. For this, we divide
32 KiB by 4 (for the number of bytes per word) and again by 2 (for the number of words per block). Th is
gives us 4096 blocks and a resulting index fi eld width of 12 bits. We also have a word off set size of 1 bit
and a byte off set size of 2 bits. Th is gives us a tag fi eld size of 32 15 17 bits. Th ese tag bits, along with
one valid bit per block, will require 18 4096 73728 bits or 9216 bytes. Th e total cache size is thus 9216
32768 41984 bytes

Th e total cache size can be generalized to

totalsize datasize (validbitsize tagsize) blocks

totalsize 41984

datasize blocks blocksize wordsize wordsize 4 tagsize 32 log2(blocks) log2(blocksize) log2(wordsize)


validbitsize 1

Increasing from 2-word blocks to 16-word blocks will reduce the tag size from 17 bits to 14 bits. In order
to determine the number of blocks, we solve the inequality: 41984 64 blocks 15 blocks Solving this
inequality gives us 531 blocks, and rounding to the next power of two gives us a 1024-block cache. Th e
larger block size may require an increased hit time and an increased miss penalty than the original
cache. Th e fewer number of blocks may cause a higher confl ict miss rate than the original cache.

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