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in

No part of this publication may be reproduced or distributed in any form or any means, electronic, mechanical,
photocopying, or otherwise without the prior permission of the author.

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GATE SOLVED PAPER
Electronics & Communication
Digital Circuits
e eri
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Copyright © By NODIA & COMPANY
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Information contained in this book has been obtained by authors, from sources believes to be reliable. However,
neither Nodia nor its authors guarantee the accuracy or completeness of any information herein, and Nodia nor its
authors shall be responsible for any error, omissions, or damages arising out of use of this information. This book
is published with the understanding that Nodia and its authors are supplying information but are not attempting
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to render engineering or other professional services.

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Ph : +91 - 141 - 2101150
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GATE SOLVED PAPER - EC

DIGITAL CIRCUITS

2013 ONE MARK

Q. 1 A bulb in a staircase has two switches, one switch being at the ground floor
and the other one at the first floor. The bulb can be turned ON and also can

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be turned OFF by any one of the switches irrespective of the state of the other

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switch. The logic of switching of the bulb resembles
(A) and AND gate (B) an OR gate
(C) an XOR gate (D) a NAND gate

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Q. 2 For 8085 microprocessor, the following program is executed.

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MVI A, 05H;
MVI B, 05H;
PTR: ADD B;
DCR B;
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JNZ PTR;
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ADI 03H;
HLT;
At the end of program, accumulator contains
(A) 17H (B) 20H
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(C) 23H (D) 05H

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2013 TWO MARKS

Q. 3 There are four chips each of 1024 bytes connected to a 16 bit address bus as shown
in the figure below, RAMs 1, 2, 3 and 4 respectively are mappped to addresses
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(A) 0C00H-0FFFH, 1C00H-1FFFH, 2C00H-2FFFH, 3C00H-3FFFH

(B) 1800H-1FFFH, 2800H-2FFFH, 3800H-3FFFH, 4800H-4FFFH
(C) 0500H-08FFH, 1500H-18FFH, 3500H-38FFH, 5500H-58FFH
(D) 0800H-0BFFH, 1800H-1BFFH, 2800H-2BFFH, 3800H-3BFFH

2012 ONE MARK

Q. 4 Consider the given circuit

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In this circuit, the race around
(A) does not occur
(B) occur when CLK = 0
(C) occur when CLK 1 and A = B
(D) occur when CLK 1 and A = B
e 1
0
eri =
=
=
=
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Q. 5 The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is
greater than the 2-bit input B . The number of combinations for which the output
is logic 1, is
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(A) 4 (B) 6
(C) 8 (D) 10
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Q. 6 In the circuit shown

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(A) Y A B =C + (B) Y (A =B) C +

(C) Y (A =B ) C + (D) Y AB =C +

Q. 7 In the sum of products function f (X, Y, Z) = / (2, 3, 4, 5), the prime implicants
are
(A) XY, XY (B) XY, X Y Z , XY Z
(C) XY Z , XYZ, XY (D) XY Z , XYZ, XY Z , XY Z

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2012 TWO MARKS

Q. 8 The state transition diagram for the logic circuit shown is

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2011 ONE MARK

Q. 9 The output Y in the circuit below is always ‘1’ when

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(A) two or more of the inputs P, Q, R are ‘0’

(B) two or more of the inputs P, Q, R are ‘1’
(C) any odd number of the inputs P, Q, R is ‘0’
(D) any odd number of the inputs P, Q, R is ‘1’
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Q. 10 When the output Y in the circuit below is “1”, it implies that data has
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(A) changed from “0” to “1”

(B) changed from “1” to “0”
(C) changed in either direction
(D) not changed

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Q. 11 The logic function implemented by the circuit below is (ground implies a logic
“0”)

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(A) F AND ^P, Q h
= (B) F OR ^P, Q h
=
(C) F XNOR ^P, Q h
= (D) F XOR ^P, Q h
=

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2011 TWO MARKS

Q. 12

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The output of a 3-stage Johnson (twisted ring) counter is fed to a digital-to
analog (D/A) converter as shown in the figure below. Assume all states of the
counter to be unset initially. The waveform which represents the D/A converter
output Vo is
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En
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Q. 13 Two D flip-flops are connected as a synchronous counter that goes through the
following QB QA sequence 00 " 11 " 01 " 10 " 00 "
The connections to the inputs DA and DB are
(A) DA QB, DB = QA =
(B) DA Q A, DB = Q B =
(C) DA (QA Q B =Q A QB), DB QA + =
(D) DA (QA QB =Q A Q B), DB Q B + =

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GATE SOLVED PAPER - EC DIGITAL CIRCUITS

Q. 14 An 8085 assembly language program is given below. Assume that the carry flag is
initially unset. The content of the accumulator after the execution of the program
is

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(A) 8CH (B) 64H

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(C) 23H (D) 15H

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2010 ONE MARK

eri
Q. 15 Match the logic gates in Column A with their equivalents in Column B
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En
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(A) P-2, Q-4, R-1, S-3 (B) P-4, Q-2, R-1, S-3
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(C) P-2, Q-4, R-3, S-1 (D) P-4, Q-2, R-3, S-1

Q. 16 In the circuit shown, the device connected Y5 can have address in the range
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(A) 2000 - 20FF (B) 2D00 - 2DFF

(C) 2E00 - 2EFF (D) FD00 - FDFF

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Q. 17 For the output F to be 1 in the logic circuit shown, the input combination should
be

(A) A 1, B = 1, C 0 = (B) =
A 1, B = 0, C 0 = =
(C) A 0, B = 1, C 0 = (D) =
A 0, B = 0, C 1 = =

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2010 TWO MARKS

Q. 18 Assuming that the flip-flop are in reset condition initially, the count sequence
observed at QA , in the circuit shown is

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(A) 0010111... (B) 0001011...

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(C) 0101111... (D) 0110100....

Q. 19 The Boolean function realized by the logic circuit shown is

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(A) F =m
S(0, 1, 3, 5, 9, 10, 14) (B) F =m
S(2, 3, 5, 7, 8, 12, 13)
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(C) F =m
S(1, 2, 4, 5, 11, 14, 15) (D) F =m
S(2, 3, 5, 7, 8, 9, 12)
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Q. 20 For the 8085 assembly language program given below, the content of the
accumulator after the execution of the program is

(A) 00H (B) 45H

(C) 67H (D) E7H

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2009 ONE MARK

Q. 21 The full form of the abbreviations TTL and CMOS in reference to logic families
are
(A) Triple Transistor Logic and Chip Metal Oxide Semiconductor
(B) Tristate Transistor Logic and Chip Metal Oxide Semiconductor
(C) Transistor Transistor Logic and Complementary Metal Oxide
Semiconductor
(D) Tristate Transistor Logic and Complementary Metal Oxide Silicon

Q. 22 In a microprocessor, the service routine for a certain interrupt starts from a fixed

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location of memory which cannot be externally set, but the interrupt can be

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delayed or rejected Such an interrupt is
(A) non-maskable and non-vectored
(B) maskable and non-vectored

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(C) non-maskable and vectored

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(D) maskable and vectored

2009 TWO MARKS

e
Q. 23 If X =1 in logic equation 6X Z {Y +(Z XY )}@{X
+ X (X Y+
)} 1, then +
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(A) Y = Z (B) Y =Z
(C) Z = 1 (D) Z =0

Q. 24 What are the minimum number of 2- to -1 multiplexers required to generate a

En

2- input AND gate and a 2- input Ex-OR gate

(A) 1 and 2 (B) 1 and 3
(C) 1 and 1 (D) 2 and 2
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Q. 25 What are the counting states (Q1, Q2) for the counter shown in the figure below
w .Le

(A) 11, 10, 00, 11, 10,... (B) 01, 10, 11, 00, 01...
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(C) 00, 11, 01, 10, 00... (D) 01, 10, 00, 01, 10...

Statement for Linked Answer Question 26 & 27 :

Two products are sold from a vending machine, which has two push buttons P1
and P2 .
When a buttons is pressed, the price of the corresponding product is displayed in
a 7 - segment display. If no buttons are pressed, '0' is displayed signifying ‘Rs 0’.
If only P1 is pressed, ‘2’ is displayed, signifying ‘Rs. 2’
If only P2 is pressed ‘5’ is displayed, signifying ‘Rs. 5’
If both P1 and P2 are pressed, 'E' is displayed, signifying ‘Error’

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GATE SOLVED PAPER - EC DIGITAL CIRCUITS

The names of the segments in the 7 - segment display, and the glow of the display
for ‘0’, ‘2’, ‘5’ and ‘E’ are shown below.

Consider
(1) push buttons pressed/not pressed in equivalent to logic 1/0 respectively.

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(2) a segment glowing/not glowing in the display is equivalent to logic 1/0
respectively.

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Q. 26 If segments a to g are considered as functions of P1 and P2 , then which of the
following is correct

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(A) g P 1 =P2, d c + e = (B) g+ P1 =P2, d c+ e = +
(C) g P1 =P2, e b+ c = + g P1 =P2, e b+ c
(D) = +

Q. 27

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What are the minimum numbers of NOT gates and 2 - input OR gates required
to design the logic of the driver for this 7 - Segment display
(A) 3 NOT and 4 OR
e
(B) 2 NOT and 4 OR
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(C) 1 NOT and 3 OR (D) 2 NOT and 3 OR

Q. 28 Refer to the NAND and NOR latches shown in the figure. The inputs (P1, P2) for
both latches are first made (0, 1) and then, after a few seconds, made (1, 1). The
corresponding stable outputs (Q1, Q2) are
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(A) NAND: first (0, 1) then (0, 1) NOR: first (1, 0) then (0, 0)
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(B) NAND : first (1, 0) then (1, 0) NOR : first (1, 0) then (1, 0)
(C) NAND : first (1, 0) then (1, 0) NOR : first (1, 0) then (0, 0)
(D) NAND : first (1, 0) then (1, 1) NOR : first (0, 1) then (0, 1)
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2008 TWO MARKS

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Q. 29 The logic function implemented by the following circuit at the terminal OUT is

(A) P NOR Q (B) P NAND Q

(C) P OR Q (D) P AND Q

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GATE SOLVED PAPER - EC DIGITAL CIRCUITS

Q. 30 +
The two numbers represented in signed 2’s complement form are P 11101101
and Q = 11100110 . If Q is subtracted from P , the value obtained in signed 2’s
complement is
(A) 1000001111 (B) 00000111
(C) 11111001 (D) 111111001

Q. 31 Which of the following Boolean Expressions correctly represents the relation

between P, Q, R and M1

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(A) M1 =
(P OR Q) XOR R

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(B) M1 = (P AND Q) X OR R
(C) M1 = (P NOR Q) X OR R
(D) M1 =
(P XOR Q) XOR R
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Q. 32 For the circuit shown in the figure, D has a transition from 0 to 1 after CLK
changes from 1 to 0. Assume gate delays to be negligible
Which of the following statements is true
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(A) Q goes to 1 at the CLK transition and stays at 1

(B) Q goes to 0 at the CLK transition and stays 0
(C) Q goes to 1 at the CLK tradition and goes to 0 when D goes to 1
(D) Q goes to 0 at the CLK transition and goes to 1 when D goes to 1
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Q. 33 For each of the positive edge-triggered J - flip flop used in the following
K
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figure, the propagation delay is 3 t .

Which of the following wave forms correctly represents the output at Q1 ?

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Statement For Linked Answer Question 34 & 35 :

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In the following circuit, the comparators output is logic “1” if V1 >
V2 and is logic

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3
"0" otherwise. The D/A conversion is done as per the relation VDAC = / 2n - 1bn
Volts, where b3 (MSB), b1, b2 and b0 (LSB) are the counter outputs. Then =counter
0

starts from the clear state.

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Q. 34 The stable reading of the LED displays is

(A) 06 (B) 07
(C) 12 (D) 13
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Q. 35 The magnitude of the error between VDAC and Vin at steady state in volts is
(A) 0.2 (B) 0.3
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(C) 0.5 (D) 1.0

Q. 36 For the circuit shown in the following, I0 I-3 are inputs to the 4:1 multiplexers,
R(MSB) and S are control bits. The output Z can be represented by

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GATE SOLVED PAPER - EC DIGITAL CIRCUITS

(A) PQ PQS +QRS +

(B) PQ + PQR + PQS
(C) PQR PQR +PARS QRS + +
(D) PQR PQRS +PQRS QRS + +

Q. 37 An 8085 executes the following instructions

2710 LXI H, 30A0 H
2713 DAD H
2414 PCHL
All address and constants are in Hex. Let PC be the contents of the program

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counter and HL be the contents of the HL register pair just after executing

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PCHL. Which of the following statements is correct ?
PC = 2715H PC = 30A0H
(A) (B)
HL = 30A0H HL = 2715H

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PC =
6140H PC =
6140H
(C) (D)

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HL =
6140H HL =
2715H

2007 ONE MARK

e
Q. 38 X = 01110 and Y = 11001 are two 5-bit binary numbers represented in two’s
gin
complement format. The sum of X and Y represented in two’s complement
format using 6 bits is
(A) 100111 (B) 0010000
(C) 000111 (D) 101001
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Q. 39 The Boolean function Y AB =CD is to be+realized using only 2 - input NAND

gates. The minimum number of gates required is
arn

(A) 2 (B) 3
(C) 4 (D) 5

2007 TWO MARKS

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Q. 40 In the following circuit, X is given by

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(A) X ABC = ABC ABC +ABC (B) X+ ABC = ABC+ ABC +ABC +
(C) X AB =BC AC + + (D) X AB =BC AC + +

Q. 41 The Boolean expression Y ABC D =ABCD ABC D +ABC D can be +

minimized to
(A) Y ABC D =ABC AC D + (B) Y ABC +
D =BCD ABC D +
(C) Y ABCD =BC D ABC D + + =BC D ABC D +
(D) Y ABCD

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Q. 42 The circuit diagram of a standard TTL NOT gate is shown in the figure. Vi =
25
V, the modes of operation of the transistors will be

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(A) Q1: revere active; Q2: normal active; Q3: saturation; Q4: cut-off

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(B) Q1: revere active; Q2: saturation; Q3: saturation; Q4: cut-off
(C) Q1: normal active; Q2: cut-off; Q3: cut-off; Q4: saturation
(D) Q1: saturation; Q2: saturation; Q3: saturation; Q4: normal active
e
Q. 43 The following binary values were applied to the X and Y inputs of NAND latch
gin
shown in the figure in the sequence indicated below :
X 0,Y = 1; X 0, Y = 0; X 1; Y= 1 = = =
The corresponding stable P, Q output will be.
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arn

(A) P 1, Q =0; P 1, Q = 0; P 1, Q =0 or P 0, Q== 1 == =

(B) P 1, Q = 0; P 0, Q = 1; or P 0, Q= = 1; P 0, Q= = 1 = =
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(C) P 1, Q = 0; P 1, Q = 1; P 1, Q =0 or P 0, Q= = 1 =
(D) P 1, Q = 0; P 1, Q = 1; P 1, Q = 1 = =

Q. 44 An 8255 chip is interfaced to an 8085 microprocessor system as an I/O mapped

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I/O as show in the figure. The address lines A0 and A1 of the 8085 are used by
the 8255 chip to decode internally its thee ports and the Control register. The
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address lines A3 to A7 as well as the IO/M signal are used for address decoding.
The range of addresses for which the 8255 chip would get selected is

(A) F8H - FBH (B) F8GH - FCH

(C) F8H - FFH (D) F0H - F7H

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Statement for Linked Answer Question 45 and 46 :

In the Digital-to-Analog converter circuit shown in the figure below,
VR =
10V and R =
10k W

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g.i
Q. 45 The current is
(A) 31.25 Am (B) 62.5 Am

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(C) 125 Am (D) 250 Am

Q. 46 The voltage V0 is
(A) 0-.781 V
(C) 3-.125 V
e eri (B)
(D)
1-.562 V
6-.250 V
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Statement for Linked Answer Questions 47 & 48 :
An 8085 assembly language program is given below.
Line 1: MVI A, B5H
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2: MVI B, OEH
3: XRI 69H
4: ADD B
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5: ANI 9BH
6: CPI 9FH
7: STA 3010H
8: HLT
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Q. 47 The contents of the accumulator just execution of the ADD instruction in line 4
will be
(A) C3H (B) EAH
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(C) DCH (D) 69H

Q. 48 After execution of line 7 of the program, the status of the CY and Z flags will be
ww

(A) CY 0, Z = 0 = (B) CY 0, Z = 1 =
(C) CY 1, Z = 0 = (D) CY 1, Z = 1 =

Q. 49 For the circuit shown, the counter state (Q1 Q0) follows the sequence

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(A) 00, 01, 10, 11, 00 (B) 00, 01, 10, 00, 01
(C) 00, 01, 11, 00, 01 (D) 00, 10, 11, 00, 10

2006 ONE MARK

Q. 50 The number of product terms in the minimized sum-of-product expression

obtained through the following K - map is (where, "d" denotes don’t care states)

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(A) 2 (B) 3

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(C) 4 (D) 5

Q. 51
2006
eri TWO MARKS

An I/O peripheral device shown in Fig. (b) below is to be interfaced to an 8085

e
microprocessor. To select the I/O device in the I/O address range D4 H - D7 H,
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its chip-select (CS ) should be connected to the output of the decoder shown in
as below :
En
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(A) output 7 (B) output 5

(C) output 2 (D) output 0

Q. 52 For the circuit shown in figures below, two 4 - bit parallel - in serial - out shift
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registers loaded with the data shown are used to feed the data to a full adder.
Initially, all the flip - flops are in clear state. After applying two clock pulse, the
output of the full-adder should be
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(A) S 0, C0 = 0 = (B) S 0, C0 = 1 =
(C) S 1, C0 = 0 = (D) S 1, C0 = 1 =

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Q. 53 A new Binary Coded Pentary (BCP) number system is proposed in which every
digit of a base-5 number is represented by its corresponding 3-bit binary code. For
example, the base-5 number 24 will be represented by its BCP code 010100. In
this numbering system, the BCP code 10001001101 corresponds of the following
number is base-5 system
(A) 423 (B) 1324
(C) 2201 (D) 4231

Q. 54 A 4 - bit DAC is connected to a free - running 3 - big UP counter, as shown in

the following figure. Which of the following waveforms will be observed at V0 ?

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eri
In the figure shown above, the ground has been shown by the symbol 4
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gin
En

Q. 55 Following is the segment of a 8085 assembly language program

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LXI SP, EFFF H

CALL 3000 H
:
:
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:
3000 H LXI H, 3CF4
PUSH PSW
SPHL
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POP PSW
RET
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On completion of RET execution, the contents of SP is

(A) 3CF0 H (B) 3CF8 H
(C) EFFD H (D) EFFF H

Q. 56 Two D - flip - flops, as shown below, are to be connected as a synchronous

counter that goes through the sequence 00 " 01 " 11 " 10 " 00 " ...
The inputs D0 and D1 respectively should be connected as,

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(A) Q 1 and Q0 (B) Q 0 and Q1

(C) Q1 Q0 and Q 1 Q0 (D) Q 1 Q 0 and Q1 Q0

Q. 57 The point P in the following figure is stuck at 1. The output f will be

(A) ABC (B) A

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(C) ABC (D) A

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2005 ONE MARK

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Q. 58 Decimal 43 in Hexadecimal and BCD number system is respectively
(A) B2, 0100 011 (B) 2B, 0100 0011

Q. 59
(C) 2B, 0011 0100

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(D) B2, 0100 0100

The Boolean function f implemented in the figure using two input multiplexes is
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gin
En
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(A) ABC +
ABC (B) ABC +
ABC
(C) ABC +
ABC (D) ABC +
ABC
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2005 TWO MARKS

Q. 60 The transistors used in a portion of the TTL gate show in the figure have b =100
. The base emitter voltage of is 0.7 V for a transistor in active region and 0.75
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V for a transistor in saturation. If the sink current I =1 A and the output is at

logic 0, then the current IR will be equal to
ww

(A) 0.65 mA (B) 0.70 mA

(C) 0.75 mA (D) 1.00 mA

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Q. 61 The Boolean expression for the truth table shown is

n
(A) B (A C)( A +C ) + (B) B (A C )( A +C) +

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(C) B (A C )( A +C) + (D) B (A C)( A +C ) +

Q. 62 The present output Qn of an edge triggered JK flip-flop is logic 0. If J =

1, then

n
Qn + 1
(A) Cannot be determined (B) Will be logic 0

Q. 63
(C) will be logic 1
e eri(D) will rave around

The given figure shows a ripple counter using positive edge triggered flip-flops. If
the present state of the counter is Q2 Q1 Q0 =
001 then is next state Q2 Q1 Q will be
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(A) 010 (B) 111

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(C) 100 (D) 101

Q. 64 What memory address range is NOT represents by chip # 1 and chip # 2 in the
figure A0 to A15 in this figure are the address lines and CS means chip select.
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(A) 0100 - 02FF (B) 1500 - 16FF

(C) F900 - FAFF (D) F800 - F9FF

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Statement For Linked Answer Questions 65 & 66 :

Consider an 8085 microprocessor system.
Q. 65 The following program starts at location 0100H.
LXI SP, OOFF
LXI H, 0701
MVI A, 20H
SUB M
The content of accumulator when the program counter reaches 0109 H is
(A) 20 H (B) 02 H

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(C) 00 H (D) FF H

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Q. 66 If in addition following code exists from 019H onwards,
ORI 40 H
ADD M

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What will be the result in the accumulator after the last instruction is executed ?
(A) 40 H (B) 20 H
(C) 60 H

2004
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(D) 42 H

ONE MARK
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Q. 67 A master - slave flip flop has the characteristic that
(A) change in the output immediately reflected in the output
(B) change in the output occurs when the state of the master is affected
En

(C) change in the output occurs when the state of the slave is affected
(D) both the master and the slave states are affected at the same time

Q. 68 The range of signed decimal numbers that can be represented by 6-bits 1’s
arn

complement number is
(A) -31 to +31 (B) -63 to +63
(C) -64 to +63 (D) -32 to +31
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Q. 69 A digital system is required to amplify a binary-encoded audio signal. The user

should be able to control the gain of the amplifier from minimum to a maximum
in 100 increments. The minimum number of bits required to encode, in straight
binary, is
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(A) 8 (B) 6
(C) 5 (D) 7
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Q. 70 Choose the correct one from among the alternatives A, B, C, D after matching an
item from Group 1 most appropriate item in Group 2.
Group 1 Group 2
P. Shift register 1. Frequency division
Q. Counter 2. Addressing in memory chips
R. Decoder 3. Serial to parallel data conversion
(A) P 3, Q -2, R 1 - -(B) P 3, Q -1, R 2 - -
(C) P 2, Q -1, R 3 - -(D) P 1, Q -2, R 2 - -

Q. 71 The figure the internal schematic of a TTL AND-OR-OR-Invert (AOI) gate. For
the inputs shown in the figure, the output Y is

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(A) 0 (B) 1
(C) AB (D) AB

2004 TWO MARKS

Q. 72 11001, 1001, 111001 correspond to the 2’s complement representation of which

one of the following sets of number

n
(A) 25,9, and 57 respectively (B) -6, -6, and -6 respectively

g.i
(C) -7, -7 and -7 respectively (D) -25, -9 and -57 respectively

Q. 73 In the modulo-6 ripple counter shown in figure, the output of the 2- input gate is

n
used to clear the J-K flip-flop
The 2-input gate is

e eri
gin
En

(A) a NAND gate (B) a NOR gate

(C) an OR gate (D) a AND gare
arn

Q. 74 The minimum number of 2- to -1 multiplexers required to realize a 4- to -1

multiplexers is
(A) 1 (B) 2
(C) 3 (D) 4
.Le

Q. 75 + is equivalent to
The Boolean expression AC BC
(A) AC BC +AC + (B) BC AC +BC ACB+ +
(C) AC BC +BC ABC+ +(D) ABC ABC +ABC ABC + +
w

Q. 76 A Boolean function f of two variables x and y is defined as follows :

ww

f (0, 0) f (0, 1) = f (1, 1) 1; f (1, 0)= 0 = =

Assuming complements of x and y are not available, a minimum cost solution
for realizing f using only 2-input NOR gates and 2- input OR gates (each
having unit cost) would have a total cost of
(A) 1 unit (B) 4 unit
(C) 3 unit (D) 2 unit

Q. 77 The 8255 Programmable Peripheral Interface is used as described below.

(i) An A/D converter is interface to a microprocessor through an 8255.
The conversion is initiated by a signal from the 8255 on Port C. A signal on Port
C causes data to be stobed into Port A.

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(ii) Two computers exchange data using a pair of 8255s. Port A works as a
bidirectional data port supported by appropriate handshaking signals.
The appropriate modes of operation of the 8255 for (i) and (ii) would be
(A) Mode 0 for (i) and Mode 1 for (ii)
(B) Mode 1 for (i) and Mode 2 for (ii)
(C) Mode for (i) and Mode 0 for (ii)
(D) Mode 2 for (i) and Mode 1 for (ii)

Q. 78 The number of memory cycles required to execute the following 8085 instructions
(i) LDA 3000 H

n
(ii) LXI D, FOF1H

g.i
would be
(A) 2 for (i) and 2 for (ii) (B) 4 for (i) and 3 for (ii)
(C) 3 for (i) and 3 for (ii) (D) 3 for (i) and 4 for (ii)

n
Q. 79 Consider the sequence of 8085 instructions given below

eri
LXI H, 9258
MOV A, M
CMA
MOV M, A
e
Which one of the following is performed by this sequence ?
gin
(A) Contents of location 9258 are moved to the accumulator
(B) Contents of location 9258 are compared with the contents of the
accumulator
En

(C) Contents of location 8529 are complemented and stored in location 8529
(D) Contents of location 5892 are complemented and stored in location 5892

Q. 80 It is desired to multiply the numbers 0AH by 0BH and store the result in the
arn

accumulator. The numbers are available in registers B and C respectively. A part

of the 8085 program for this purpose is given below :
MVI A, 00H
LOOP ------
.Le

------
-----
HLT
END
w

The sequence of instructions to complete the program would be

(A) JNX LOOP, ADD B, DCR C
ww

(B) ADD B, JNZ LOOP, DCR C

(C) DCR C, JNZ LOOP, ADD B
(D) ADD B, DCR C, JNZ LOOP

2003 ONE MARK

Q. 81 The number of distinct Boolean expressions of 4 variables is

(A) 16 (B) 256
(C) 1023 (D) 65536

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Q. 82 The minimum number of comparators required to build an 8-bits flash ADC is

(A) 8 (B) 63
(C) 255 (D) 256

Q. 83 The output of the 74 series of GATE of TTL gates is taken from a BJT in
(A) totem pole and common collector configuration
(B) either totem pole or open collector configuration
(C) common base configuration
(D) common collector configuration

n
Q. 84 Without any additional circuitry, an 8:1 MUX can be used to obtain
(A) some but not all Boolean functions of 3 variables

g.i
(B) all functions of 3 variables but non of 4 variables
(C) all functions of 3 variables and some but not all of 4 variables

n
(D) all functions of 4 variables

eri
Q. 85 A 0 to 6 counter consists of 3 flip flops and a combination circuit of 2 input gate
(s). The common circuit consists of
(A) one AND gate
e
(B) one OR gate
gin
(C) one AND gate and one OR gate
(D) two AND gates
En

2003 TWO MARKS

Q. 86 The circuit in the figure has 4 boxes each described by inputs P, Q, R and outputs
Y, Z with Y = P 5 Q 5 R and Z RQ =PR QP + +
arn

The circuit acts as a

w .Le
ww

(A) 4 bit adder giving P Q +

(B) 4 bit subtractor giving P -
Q
(C) 4 bit subtractor giving Q-P
(D) 4 bit adder giving P Q +R +

Q. 87 If the function W, X, Y and Z are as follows

W R =PQ RS + X+ PQRS =PQRS PQRS + +
Y RS =PR PQ +P .Q Z R+=S PQ ++P .Q .R + PQ .S + +
Then,
(A) W Z, X = Z = (B) W Z, X = Y =
(C) W = Y (D) W Y = Z =

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Q. 88 A 4 bit ripple counter and a bit synchronous counter are made using flip flops
having a propagation delay of 10 ns each. If the worst case delay in the ripple
counter and the synchronous counter be R and S respectively, then
(A) R = 10 ns, S = 40 ns (B) R = 40 ns, S =10 ns
(C) R = 10 ns S = 30 ns (D) R = 30 ns, S =10 ns

Q. 89 In the circuit shown in the figure, A is parallel-in, parallel-out 4 bit register,

which loads at the rising edge of the clock C . The input lines are connected to a
4 bit bus, W . Its output acts at input to a 16 # 4 ROM whose output is floating
when the input to a partial table of the contents of the ROM is as follows

n
Data 0011 1111 0100 1010 1011 1000 0010 1000

g.i
Address 0 2 4 6 8 10 11 14

The clock to the register is shown, and the data on the W bus at time t1 is 0110.

n
The data on the bus at time t2 is

e eri
gin
En
arn
w .Le
ww

(A) 1111 (B) 1011

(C) 1000 (D) 0010

Q. 90 The DTL, TTL, ECL and CMOS famil GATE of digital ICs are compared in the
following 4 columns

(P) (Q) (R) (S)

Fanout is minimum DTL DTL TTL CMOS
Power consumption is minimum TTL CMOS ECL DTL
Propagation delay is minimum CMOS ECL TTL TTL

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The correct column is

(A) P (B) Q
(C) R (D) S

Q. 91 The circuit shown in figure converts

n
g.i
(A) BCD to binary code (B) Binary to excess - 3 code

n
(C) Excess -3 to gray code (D) Gray to Binary code

Q. 92

eri
In an 8085 microprocessor, the instruction CMP B has been executed while the
content of the accumulator is less than that of register B . As a result
e
(A) Carry flag will be set but Zero flag will be reset
(B) Carry flag will be rest but Zero flag will be set
gin
(C) Both Carry flag and Zero flag will be rest
(D) Both Carry flag and Zero flag will be set
En

Q. 93 The circuit shown in the figure is a 4 bit DAC

arn
.Le

The input bits 0 and 1 are represented by 0 and 5 V respectively. The OP AMP
w

is ideal, but all the resistance and the 5 v inputs have a tolerance of !10%. The
specification (rounded to nearest multiple of 5%) for the tolerance of the DAC is
ww

(A) !35% (B) !20%

(C) !10% (D) !5%

2002 ONE MARK

Q. 94 4 - bit 2’s complement representation of a decimal number is 1000. The number is

(A) +8 (B) 0
(C) -7 (D) -8

Q. 95 The number of comparators required in a 3-bit comparators type ADC

(A) 2 (B) 3
(C) 7 (D) 8

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Q. 96 If the input to the digital circuit (in the figure) consisting of a cascade of 20 XOR
- gates is X , then the output Y is equal to

(A) 0 (B) 1
(C) X (D) X

n
2002 TWO MARKS

g.i
Q. 97 The gates G1 and G2 in the figure have propagation delays of 10 ns and 20 ns
respectively. If the input V1, makes an output change from logic 0 to 1 at time

n
t =,t0 then the output waveform V0 is

e eri
gin
En

Q. 98 If the input X3, X2, X1, X0 to the ROM in the figure are 8 4 2 1 BCD numbers, then
arn

the outputs Y3, Y2, Y1, Y0 are

w .Le
ww

(A) gray code numbers (B) 2 4 2 1 BCD numbers

(C) excess - 3 code numbers (D) none of the above

Q. 99 Consider the following assembly language program

MVI B, 87H
MOV A, B
START : JMP NEXT
MVI B, 00H
XRA B

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OUT PORT1
HLT
NEXT : XRA B
JP START
OUT PORT2
HTL
The execution of above program in an 8085 microprocessor will result in
(A) an output of 87H at PORT1
(B) an output of 87H at PORT2
(C) infinite looping of the program execution with accumulator data remaining

n
at 00H

g.i
(D) infinite looping of the program execution with accumulator data alternating
between 00H and 87H

Q. 100 The circuit in the figure has two CMOS NOR gates. This circuit functions as a:

n
e eri
gin
(A) flip-flop (B) Schmitt trigger
(C) Monostable multivibrator (D) astable multivibrator
En

2001 ONE MARKS

Q. 101 The 2’s complement representation of -17 is

arn

(A) 101110 (B) 101111

(C) 111110 (D) 110001

Q. 102 For the ring oscillator shown in the figure, the propagation delay of each inverter
.Le

is 100 pico sec. What is the fundamental frequency of the oscillator output
w

(A) 10 MHz (B) 100 MHz

ww

(C) 1 GHz (D) 2 GHz

Q. 103 Ab 8085 microprocessor based system uses a 4K # 8 bit RAM whose starting
address is AA00H. The address of the last byte in this RAM is
(A) OFFFH (B) 1000H
(C) B9FFH (D) BA00H

2001 TWO MARKS

Q. 104 In the TTL circuit in the figure, S2 and S0 are select lines and X7 and X0 are input
lines. S0 and X0 are LSBs. The output Y is

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(A) indeterminate (B) A 5 B

(C) A 5 B (D) C (A 5 B ) +(A 5 B)
C

n
Q. 105 The digital block in the figure is realized using two positive edge triggered D-flip-
flop. Assume that for t < t0, Q1 Q2 = 0 . The circuit
= in the digital block is given

g.i
by

n
e eri
gin
En
arn
w .Le

Q. 106 In the DRAM cell in the figure, the Vt of the NMOSFET is 1 V. For the following
ww

three combinations of WL and BL voltages.

(A) 5 V; 3 V; 7 V
(B) 4 V; 3 V; 4 V
(C) 5 V; 5 V; 5 V
(D) 4 V; 4 V; 4 V

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Q. 107 In the figure, the LED

(A) emits light when both S1 and S2 are closed

n
(B) emits light when both S1 and S2 are open

g.i
(C) emits light when only of S1 and S2 is closed
(D) does not emit light, irrespective of the switch positions.

n
2000 ONE MARKS

Q. 108

(A) 10 sm
e eri
An 8 bit successive approximation analog to digital communication has full scale
reading of 2.55 V and its conversion time for an analog input of 1 V is 20 s.m The
conversion time for a 2 V input will be
(B) 20 sm
gin
(C) 40 sm (D) 50 sm

Q. 109 The number of comparator in a 4-bit flash ADC is

(A) 4 (B) 5
En

(C) 15 (D) 16

Q. 110 For the logic circuit shown in the figure, the required input condition (A, B, C) to
arn

make the output (X) = 1 is

.Le

(A) 1,0,1
w

(B) 0,0,1
(C) 1,1,1
ww

(D) 0,1,1

Q. 111 The number of hardware interrupts (which require an external signal to interrupt)
present in an 8085 microprocessor are
(A) 1 (B) 4
(C) 5 (D) 13

Q. 112 In the microprocessor, the RST6 instruction transfer the program execution to
the following location :
(A)30 H (B) 24 H
(C) 48 H (D) 60 H

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2000 TWO MARKS

Q. 113 The contents of register (B) and accumulator (A) of 8085 microprocessor are 49J
are 3AH respectively. The contents of A and status of carry (CY) and sign (S)
after execution SUB B instructions are
(A) A = F1, CY = 1, S = 1 (B) A = 0F, CY = 1, S = 1
(C) A = F0, CY = 0, S = 0 (D) A = 1F, CY = 1, S = 1

Q. 114 For the logic circuit shown in the figure, the simplified Boolean expression for the
output Y is

n
n g.i
(A) A B +C + (B) A

Q. 115
(C) B

eri
(D) C

For the 4 bit DAC shown in the figure, the output voltage V0 is
e
gin
En
arn

(A) 10 V (B) 5 V
(C) 4 V (D) 8 V

Q. 116 A sequential circuit using D flip-flop and logic gates is shown in the figure, where
.Le

X and Y are the inputs and Z is the inputs. The circuit is

w
ww

(A) S - Flip-Flop with inputs X =

R R and Y =
S
(B) S - Flip-Flop with inputs X =
R S and Y =
R
(C) J - Flip-Flop with inputs X =
K J and Y =
K
(D) J - Flip-Flop with input X =
K K and Y =
J

Q. 117 In the figure, the J and K inputs of all the four Flip-Flips are made high. The
frequency of the signal at output Y is

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(A) 0.833 kHz (B) 1.0 kHz

(C) 0.91 kHz (D) 0.77 kHz

n
1999 ONE MARK

g.i
Q. 118 The logical expression y A =AB is equivalent
+ to
(A) y = AB (B) y = AB

n
(C) y A =B + (D) y A =B +

eri
Q. 119 A Darlington emitter follower circuit is sometimes used in the output stage of a
TTL gate in order to
(A) increase its IOL
e
(B) reduce its IOH
gin
(C) increase its speed of operation
(D) reduce power dissipation

Q. 120 Commercially available ECL gears use two ground lines and one negative supply
En

in order to
(A) reduce power dissipation
(B) increase fan-out
arn

(C) reduce loading effect

(D) eliminate the effect of power line glitches or the biasing circuit

Q. 121 The resolution of a 4-bit counting ADC is 0.5 volts. For an analog input of
.Le

6.6 volts, the digital output of the ADC will be

(A) 1011 (B) 1101
(C) 1100 (D) 1110
w

1999 TWO MARKS

ww

Q. 122 The minimized form of the logical expression

(ABC ABC +ABC ABC ) + is +
(A) AC BC +AB + (B) AC BC +AB +
(C) AC BC +AB + (D) AC BC +AB +

Q. 123 For a binary half-subtractor having two inputs A and B, the correct set of logical
expressions for the outputs D ( =A minus B) and X ( = borrow) are
(A) D AB =AB, X AB + =
(B) D AB =AB AB , X + AB + =
(C) D AB =AB , X AB + =
(D) D AB =AB , X AB + =

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Q. 124 If CS = A15 A14 A13 is used as the chip select logic of a 4 K RAM in an 8085 system,
then its memory range will be
(A) 3000 H - 3 FFF H
(B) 7000 H - 7 FFF H
(C) 5000 H - 5 FFF H and 6000 H - 6 FFF H
(D) 6000 H - 6 FFF H and 7000 H - 7 FFF H

Q. 125 The ripple counter shown in the given figure is works as a

n
n g.i
(A) mod-3 up counter
(C) mod-3 down counter
e eri
(B) mod-5 up counter
(D) mod-5 down counter
gin
1998 ONE MARK

Q. 126 The minimum number of 2-input NAND gates required to implement of Boolean
function Z =
ABC , assuming that A, B and C are available, is
En

(A) two (B) three

(C) five (D) six

Q. 127 The noise margin of a TTL gate is about

arn

(A) 0.2 V (B) 0.4 V

(C) 0.6 V (D) 0.8 V

Q. 128 In the figure is A =

1 and B = 1, the input B is now replaced by a sequence
.Le

101010. , the output x and y will be

w
ww

(A) fixed at 0 and 1, respectively

(B) x 1010.....while y = 0101. =
(C) x 1010.....and y = 1010. =
(D) fixed at 1 and 0, respectively

Q. 129 An equivalent 2’s complement representation of the 2’s complement number 1101
is
(A) 110100 (B) 01101
(C) 110111 (D) 111101

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Q. 130 The threshold voltage for each transistor in the figure is 2 V. For this circuit to
work as an inverter, Vi must take the values

n
(A) 5-V and 0 V (B) 5-V and 5 V

g.i
(C) 0-V and 3 V (D) 3 V and 5 V

Q. 131 An I/O processor control the flow of information between

(A) cache memory and I/O devices

n
(B) main memory and I/O devices

eri
(C) two I/O devices
(D) cache and main memories e
Q. 132 Two 2’s complement number having sign bits x and y are added and the sign bit
of the result is z . Then, the occurrence of overflow is indicated by the Boolean
gin
function
(A) xyz (B) x y z
+
(C) x yz xyz (D) xy yz +zx +
En

Q. 133 The advantage of using a dual slope ADC in a digital voltmeter is that
(A) its conversion time is small
(B) its accuracy is high
arn

(C) it gives output in BCD format

(D) it does not require a

For the identity AB AC +BC AB +AC , the dual

= form is +
.Le

Q. 134
(A) (A B) (A +C) (B C) (A + B) (A C) + = + +
(B) (A B ) (A +C ) (B C ) (A
+ B ) (A C ) + = +
(C) (A B) (A +C) (B C) (A + B ) (A C ) + = + +
w

(D) AB AC +BC AB +AC = +

ww

Q. 135 An instruction used to set the carry Flag in a computer can be classified as
(A) data transfer (B) arithmetic
(C) logical (D) program control

Q. 136 The figure is shows a mod-K counter, here K is equal to

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(A) 1 (B) 2
(C) 3 (D) 4

Q. 137 The current I through resistance r in the circuit shown in the figure is

n
(A) -
V (B) V
12R 12R

g.i
(C) V (D) V
6R 3T

n
Q. 138 The K -map for a Boolean function is shown in the figure is the number of
essential prime implicates for this function is

e eri
gin
En

(A) 4 (B) 5
arn

(C) 6 (D) 8

1997 ONE MARK

.Le

Q. 139 Each cell of a static Random Access Memory contains

(A) 6 MOS transistors
(B) 4 MOS transistors and 2 capacitors
w

(C) 2 MOS transistors and 4 capacitors

(D) 1 MOS transistors and 1 capacitors
ww

Q. 140 A 2 bit binary multiplier can be implemented using

(A) 2 inputs ANSs only
(B) 2 input XORs and 4 input AND gates only
(C) Two 2 inputs NORs and one XNO gate
(D) XOR gates and shift registers

Q. 141 In standard TTL, the ‘totem pole’ stage refers to

(A) the multi-emitter input stage
(B) the phase splitter
(C) the output buffer
(D) open collector output stage

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Q. 142 The inverter 74 ALSO4 has the following specifications

IOH max =0.4-A, IOL max 8 mA=, IIH max 20 mA, I=IL max 0.1 mA = -
The fan out based on the above will be
(A) 10 (B) 20
(C) 60 (D) 100

Q. 143 The output of the logic gate in the figure is

n
(A) 0 (B) 1

g.i
(C) A (D) F

Q. 144 In an 8085 Pm system, the RST instruction will cause an interrupt

n
(A) only if an interrupt service routine is not being executed

eri
(B) only if a bit in the interrupt mask is made 0
(C) only if interrupts have been enabled by an EI instruction
(D) None of the above
e
Q. 145 The decoding circuit shown in the figure is has been used to generate the active
gin
low chip select signal for a microprocessor peripheral. (The address lines are
designated as AO to A7 for I/O address)
En
arn

The peripheral will correspond to I/O address in the range

.Le

(A) 60 H to 63 H (B) A4 to A 7H
(C) 30 H to 33 H (D) 70 H to 73 H

Q. 146 The following instructions have been executed by an 8085 Pm

w

ADDRESS (HEX) INSTRUCTION

ww

6010 LXI H, 8 A 79 H
6013 MOV A, L
6015 ADDH
6016 DAA
6017 MOV H, A
6018 PCHL
From which address will the next instruction be fetched ?
(A) 6019 (B) 6379
(C) 6979 (D) None of the above

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Q. 147 A signed integer has been stored in a byte using the 2’s complement format. We
wish to store the same integer in a 16 bit word. We should
(A) copy the original byte to the less significant byte of the word and fill the
more significant with zeros
(B) copy the original byte to the more significant byte of the word and fill the
less significant byte with zeros
(C) copy the original byte to the less significant byte of the word and make
each fit of the more significant byte equal to the most significant bit of the
original byte
(D) copy the original byte to the less significant byte as well as the more

n
significant byte of the word

g.i
1997 TWO MARKS

n
Q. 148 For the NMOS logic gate shown in the figure is the logic function implemented is

e eri
gin
En

(A) ABCDE (B) (AB C ) : (D +E ) +

arn

(C) A : (B C) +D : E + (D) (A B ) : C +D : E +

Q. 149 In a J–K flip-flop we have J = Q and K = 1. Assuming the flip flop was initially
cleared and then clocked for 6 pulses, the sequence at the Q output will be
w .Le
ww

(A) 010000 (B) 011001

(C) 010010 (D) 010101

Q. 150 The gate delay of an NMOS inverter is dominated by charge time rather than
discharge time because
(A) the driver transistor has larger threshold voltage than the load transistor
(B) the driver transistor has larger leakage currents compared to the load
transistor
(C) the load transistor has a smaller W/L ratio compared to the driver
transistor

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(D) none of the above

Q. 151 The boolean function A + is a reduced form of

BC
(A) AB BC+ (B) (A B) : (A +C) +
+
(C) AB ABC (D) (A C +) : B

1996 ONE MARK

Q. 152 Schottky clamping is resorted in TTl gates

(A) to reduce propagation delay (B) to increase noise margins

n
(C) to increase packing density (D) to increase fan-out

g.i
Q. 153 A pulse train can be delayed by a finite number of clock periods using
(A) a serial-in serial-out shift register

n
(B) a serial-in parallel-out shift register
(C) a parallel-in serial-out shift register

Q. 154
e eri
(D) a parallel-in parallel-out shift register

m clock period and the total conversion

A 12-bit ADC is operating with a 1 sec
m . The ADC must be of the
time is seen to be 14 sec
gin
(A) flash type (B) counting type
(C) intergrating type (D) successive approximation type

Q. 155 The total number of memory accesses involved (inclusive of the op-code fetch)
En

when an 8085 processor executes the instruction LDA 2003 is

(A) 1 (B) 2
(C) 3 (D) 4
arn

1996 TWO MARKS

Q. 156 A dynamic RAM cell which hold 5 V has to be refreshed every 20 m sec, so that
.Le

the stored voltage does not fall by more than 0.5 V. If the cell has a constant
discharge current of 1 pA, the storage capacitance of the cell is
(A) 4 # 10 6-F (B) 4 # 10 9-F
(C) 4 # 10 12- F (D) 4 # 10 15- F
w

Q. 157 A 10-bit ADC with a full scale output voltage of 10.24 V is designed to have
ww

a !LSB/2 accuracy. If the ADC is calibrated at 25c C and the operating

temperature ranges from 0c C to 25c C , then the maximum net temperature
coefficient of the ADC should not exceed
(A) ! 200 Vm/cC (B) ! 400 Vm/cC
(C) ! 600 Vm/cC (D) ! 800 Vm/cC

Q. 158 A memory system of size 26 K bytes is required to be designed using memory

chips which have 12 address lines and 4 data lines each. The number of such chips
required to design the memory system is
(A) 2 (B) 4
(C) 8 (D) 13

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GATE SOLVED PAPER - EC DIGITAL CIRCUITS

Q. 159 The following sequence of instructions are executed by an 8085 microprocessor:

1000 LXI SP, 27 FF
1003 CALL 1006
1006 POP H
The contents of the stack pointer (SP) and the HL, register pair on completion of
execution of these instruction are
(A) SP = 27 FF, HL = 1003 (B) SP = 27 FD, HL = 1003
(C) SP = 27 FF, HL = 1006 (D) SP = 27 FD, HL = 1006

***********

n
n g.i
e eri
gin
En
arn
w .Le
ww

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GATE SOLVED PAPER - EC DIGITAL CIRCUITS

SOLUTIONS

Sol. 1 Option (C) is correct.

Let A denotes the position of switch at ground floor and B denotes the position
of switch at upper floor. The switch can be either in up position or down position.
Following are the truth table given for different combinations of A and B

n
A B Y(Bulb)

g.i
up(1) up(1) OFF(0)
Down(0) Down(0) OFF(0)
up(1) Down(0) ON(1)

n
Down(0) up(1) ON(1)

Y =
A5B
e eri
When the switches A and B are both up or both down, output will be zero (i.e.
Bulb will be OFF). Any of the switch changes its position leads to the ON state
of bulb. Hence, from the truth table, we get
gin
i.e., the XOR gate
Sol. 2 Option (A) is correct.
The program is being executed as follows
En

MVI A, 0.5H; A = 05H

MVI B, 0.5H; B = 05H
At the next instruction, a loop is being introduced in which for the instruction
“DCR B” if the result is zero then it exits from loop so, the loop is executed five
arn

times as follows :
Content in B Output of ADD B (Stored value at A)
05 05 + 05
.Le

04 05 + 05 + 04
03 05 + 05 + 04 + 03
02 05 + 05 + 04 + 03 + 02
w

01 05 + 05 + 04 + 03 + 02 + 01
00 System is out of loop
ww

i.e., A 05 = 05 04 +03 02 +01 144 + + + =

At this stage, the 8085 microprocessor exits from the loop and reads the next
instruction. i.e., the accumulator is being added to 03 H. Hence, we obtain
A A =03 H 14+ 03 17 H= + =
Sol. 3 Option (D) is correct.
For chip-1, we have the following conclusions:
it is enable when (i) S1 S 0 =
0 0
and (ii) Input =
1
For S1 S 0 =
00
We have A13 A12 = 0 =

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and for I/p =

1we obtain
A10 = 1 or A10 = 0
A11 = 1
A14 = 1 or A14 = 0
A15 = 1 or A15 = 0
Since, A 0 A-9 can have any value 0 or 1
Therefore, we have the address range as
A15 A14 A13 A12 A11 A10 A 9 A 8 A7 A 6 A5 A 4 A 3 A2 A1 A 0

n
From 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
to 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1

g.i
In Hexadecimal & 0800 H to 0BFFH
Similarly, for chip 2, we obtain the range as follows

n
E =
1 for S1 S 0 =0 1
so, A13 =
0 and A12 = 1
and also the I/P =
A10 =, 0 A11 =
1 for
1, A14 =,
so, the fixed I/ps are
0 A15 =
0
e eri
gin
A15 A14 A13 A12 A11 A10
0 0 0 1 1 0
Therefore, the address range is
En

A15 A14 A13 A12 A11 A10 A 9 A 8 A7 A 6 A5 A 4 A 3 A2 A1 A 0

From 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0
to 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1
arn

In hexadecimal it is from 1800 H to 1BFFH . There is no need to obtain rest of

address ranged as only (D) is matching to two results.
Sol. 4 Option (A) is correct.
.Le

The given circuit is

w
ww

Condition for the race-around

It occurs when the output of the circuit (Y1, Y2) oscillates between ‘0’ and ‘1’
checking it from the options.
1. Option (A): When CLK = 0
Output of the NAND gate will be A1 B1 = 0 1. Due = to these=input to the next
NAND gate, Y2 Y1 : 1 = Y1 and Y1 Y2 :=1 = Y2 . =
If Y1 =,
0 Y2 Y1 = 1 and it will
= remain the same and doesn’t oscillate.
If Y2 =,
0 Y1 Y2 = 1 and it will
= also remain the same for the clock period. So,
it won’t oscillate for CLK =.0
So, here race around doesn’t occur for the condition CLK =. 0

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2. Option (C): When CLK 1, A = B 1 = =

A1 = B1 = 0 and so Y1 Y2 = 1 =
And it will remain same for the clock period. So race around doesn’t occur for
the condition.
3. Option (D): When CLK 1, A = B 0 = =
So, A1 =B1 = 1
And again as described for Option (B) race around doesn’t occur for the
condition.
Sol. 5 Option (B ) is correct.

n
n g.i
Y =
1, when A >
B

eri
A a1 a 0, B = b1 b 0 =

a1 a0 b1 b0 Y
0 1 0 0 1
e
gin
1 0 0 0 1
1 0 0 1 1
1 1 0 0 1
1 1 0 1 1
En

1 1 1 0 1

Total combination =
6
arn

Sol. 6 Option (A) is correct.

Parallel connection of MOS & OR operation
Series connection of MOS & AND operation
.Le

The pull-up network acts as an inverter. From pull down network we write
Y (A =B) C + =B)
(A C +A B =C + +
Sol. 7 Option (A) is correct.
w

Prime implicants are the terms that we get by solving K-map

ww

F XY =XY +
1prime
44 2 44 3
implicants

Sol. 8 Option (D) is correct.

Let Qn 1+ is next state and Qn is the present state. From the given below figure.
D Y = AX 0 AX =1 +
Qn 1+ D = AX 0 AX =1 +
Qn 1+ A Qn =AQn + X 0 Q , X1 = Q =

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If A = 0, Qn 1+ =
Qn (toggle of previous state)
If A = 1, Qn 1+ =
Qn
So state diagram is

Sol. 9 Option (B) is correct.

The given circuit is shown below:

n
n g.i
(PQ QR ) PR (PQ =QR PR ) PQ
e eri
+ =QR PR + PQ =QR +PR +
If any two or more inputs are ‘1’ then output y will be 1.
+
gin
Sol. 10 Option (A) is correct.
For the output to be high, both inputs to AND gate should be high.
The D-Flip Flop output is the same, after a delay.
En

Let initial input be 0; (Consider Option A)

then Q = 1 (For 1 D-Flip Flop). This is given as input to 2nd FF.
st

Let the second input be 1. Now, considering after 1 time interval; The output of
1st Flip Flop is 1 and 2nd FF is also 1. Thus Output = 1.
arn

Sol. 11 Option (D) is correct.

F S1 S 0 I 0 =S1 S 0 I1 S1 S 0 I2 +S1 S 0 I 3 + +
I0 I3 = 0 =
.Le

F PQ =PQ XOR+
(P, Q) = ( S1 P, S 0 = Q ) =
Sol. 12 Option (A) is correct.
All the states of the counter are initially unset.
w
ww

State Initially are shown below in table :

Q2 Q1 Q0
0 0 0 0
1 0 0 4
1 1 0 6
1 1 1 7

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0 1 1 3
0 0 1 1
0 0 0 0
Sol. 13 Option (D) is correct.
The sequence is QB QA
00 " 11 " 01 " 10 " 00 " ...
QB QA QB (t 1+) QA (t 1+)
0 0 1 1

n
1 1 0 1
0 1 1 0

g.i
1 0 0 0
QB ^t 1+h

n
QB ^t
e eri
1h + Q A =
gin

DA Q A Q B =QA QB +
En

Sol. 14 Option (C) is correct.

Initially Carry Flag, C = 0
MVI A, 07 H ;A = 0000 0111
arn

RLC ; Rotate left without carry. A =0000 1110

MVO B, A ;B = A = 0000 1110
RLC ;A = 0001 1100
.Le

RLC ;A = 0011 1000

ADD B ; A =0011 1000
; 0000
+ 1110
; 0100 0110
w

RRC ; Rotate Right with out carry, A = 0010 0011

Thus A = 23 H
ww

Sol. 15 Option ( ) is correct.

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Sol. 16 Option (B) is correct.

Since G2 is active low input, output of NAND gate must be 0
G2 A15 : A14 A13 A12 A11 = 0 =
So, A15 A14 A13 A12 A11 =
00101
To select Y5 Decoder input
ABC A 8 A 9 A10 = 101 =
Address range
A15 A14 A13 A12 A11 A10 A 9 A 8 A0
0011101 A0
S S

n
2 D
^2D00 2-DFF h

g.i
Sol. 17 Option (A) (B) (C) are correct.
In the circuit F =
(A 5 B) 9 (A 9 B) 9 C
For two variables A5B =
A9B

n
So, (A 5 B) 9 (A 9 B) =
0 (always)

Sol. 18
So, F =
1 when C
Option (D) is correct.
=
1 or C =
0 eF

eri
0 9 C= 0 $ C

Let QA (n), QB (n), QC (n) are present states and QA (n

1 $ C =C

1), QB (n +1), QC (n
+

+
1) +
=
gin
are next states of flop-flops.
In the circuit
QA (n 1+) =
QB (n) 9 QC (n)
En

QB (n 1+) QA (n)
QC (n 1+) QB (n)
Initially all flip-flops are reset
arn

1st clock pulse

QA 0 9 0 =1 =
QB =
0
.Le

QC =
0
nd
2 clock pulse
QA 0 9 0 =1 =
QB =
1
w

QC =
0
3 rd clock pulse
ww

QA 1 9 0 =0 =
QB =
1
QC =
1
4 th clock pulse
QA 1 9 1 =1 =
QB =
0
QC =
1
So, sequence QA = 01101.
Sol. 19 Option (D) is correct.

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Output of the MUX can be written as

F I 0 S 0 S1 =I1 S 0 S1 I2 S 0 S1 +I 3 S 0 S1 + +
Here, I 0 C, I1 = D, I2 C , I 3 = CD = =
and S 0 A, S1 = B =
So, F C A B =D A B CAB +
C DA B + +
Writing all SOP terms
F A B C D =A B C D A BCD + BC D
A AB C D A+B C D ABC D +
1 44 2
m
44 3 1 44 2
m
44 3 S m 7
14 2
m
43 14 2
m
43 1 44 2
m
44 3 S m
12
3 2 5 9 8

F / m (2, 3, 5, 7, 8, 9, 12)
=

n
Sol. 20 Option (C) is correct.

g.i
By executing instruction one by one
MVI A, 45 H & MOV 45 H into accumulator, A =
45 H
STC & Set carry, C = 1

n
CMC & Complement carry flag, C =
0

eri
RAR & Rotate accumulator right through carry
e
gin

A =00100010
XRA B & XOR A and B
En

A =
A5B =
00100010 5 01000101 01100111 = 674 =
Sol. 21 Option (C) is correct.
TTL " Transistor - Transistor logic
arn

CMOS " Complementary Metal Oxide Semi-conductor

Sol. 22 Option (D) is correct.
Vectored interrupts : Vectored interrupts are those interrupts in which program
.Le

control transferred to a fixed memory location.

Maskable interrupts : Maskable interrupts are those interrupts which can be
rejected or delayed by microprocessor if it is performing some critical task.
Sol. 23 Option (D) is correct.
w

We have 6X Z {Y +(Z XY )}@[X+ Z (X Y)]+ 1 + +

Substituting X = 1 and X = 0 we get
ww

[1 Z {Y +(Z 1Y )}][ 0 + Z (1 Y)] + = 1 + +

or [1][ Z (1)] =1 1 A + 1 and 0 = A + A =
or Z 1 ) Z =0 =
Sol. 24 Option (A) is correct.
The AND gate implementation by 2:1 mux is as follows

Y AI 0 =AI1 AB + =

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The EX - gate implementation by 2:1 mux is as follows

OR

Y BI0 =BI1 AB +BA = +

Sol. 25 Option (A) is correct.

n
The given circuit is as follows.

n g.i
eri
The truth table is as shown below. Sequence is 00, 11, 10, 00 ...
e
CLK J1 K1 Q1 J2 K2 Q2
gin
1 1 1 0 1 1 0
2 1 1 1 1 1 1
3 0 0 1 0 1 0
En

4 1 1 0 1 1 0

Sol. 26 Option (B) is correct.

arn

The given situation is as follows

w .Le

The truth table is as shown below

P1 P2 a b c d e f g
ww

0 0 1 1 1 1 1 1 0
0 1 1 0 1 1 0 1 1
1 0 1 1 0 1 1 0 1
1 1 1 0 0 1 1 1 1
From truth table we can write
a =
1
b P 1 P 2 =P1 P 2 P2 + = 1 NOT Gate
c P1 P2 =P1 P2 P1 + = 1 NOT Gate
d 1 =c e = +

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and c P1 P2 = P1 P2 = + 1 OR GATE
+2
f = P1 P2 = P1 P 1 OR GATE
g P1 P2 = P1 P2 = + 1 OR GATE
Thus we have g P1 =P2 and d+ 1 = c = may be+observed easily from
e . It
figure that
Led g does not glow only when both P1 and P2 are 0. Thus
g P1 =P2 +
LED d is 1 all condition and also it depends on
d c =e +

n
Sol. 27 Option (D) is correct.

g.i
As shown in previous solution 2 NOT gates and 3-OR gates are required.
Sol. 28 Option (C) is correct.

n
For the NAND latche the stable states are as follows

e eri
gin
For the NOR latche the stable states are as follows
En
arn

Sol. 29 Option (D) is correct.

From the figure shown below it may be easily seen upper MOSFET are shorted
and connected to Vdd thus OUT is 1 only when the node S is 0,
w .Le
ww

Since the lower MOSFETs are shorted to ground, node S is 0 only when input P
and Q are 1. This is the function of AND gate.
Sol. 30 Option (B) is correct.
MSB of both number are 1, thus both are negative number. Now we get
11101101 ( =19) 10 -
and 11100110 ( =26) 10 -
P Q - ( =19) - ( 26) -
7 - =
Thus 7 signed two’s complements form is
(7) 10 = 00000111

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Sol. 31 Option (D) is correct.

The circuit is as shown below

X =
PQ

n
Y (P =Q) +
So Z PQ (P =Q) +

g.i
(P =Q )( P Q+ ) PQ =PQ+ P 5 Q+ =
and M1 Z5R =
= (P 5 Q) 5 R

n
Sol. 32 Option (A) is correct.

eri
The circuit is as shown below
e
gin
En

The truth table is shown below. When CLK make transition Q goes to 1 and
when D goes to 1, Q goes to 0
Sol. 33 Option (B) is correct.
arn

Since the input to both JK flip-flop is 11, the output will change every time with
clock pulse. The input to clock is
.Le

The output Q0 of first FF occurs after time 3 T and it is as shown below

w
ww

The output Q1 of second FF occurs after time 3 T when it gets input (i.e. after
3 T from t1) and it is as shown below

Sol. 34 Option (D) is correct.

We have

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3
VDAC / 2n - 1bn
= 2 - 1 b0 =20 b1 21 b2 2
2+ b3 + +
n=0
or VDAC 0.5b0 =b1 2b2 4b3 + + +
The counter outputs will increase by 1 from 0000 till Vth >VDAC . The output of
counter and VDAC is as shown below

Clock b3 b3 b2 b0 VDAC
1 0001 0
2 0010 0.5

n
3 0011 1

g.i
4 0100 1.5
5 0101 2
6 0110 2.5

n
7 0111 3

eri
8 1000 3.5
9 1001 4
10 1010 4.5
e
11 1011 5
gin
12 1100 5.5
13 1101 6
14 1110 6.5
En

and when VADC = 6.5 V (at 1101), the output of AND is zero and the counter
stops. The stable output of LED display is 13.
arn

Sol. 35 Option (B) is correct.

The VADC V -in at steady state is
6.5 =6.2 0.3V- =
.Le

Sol. 36 Option (A) is correct.

Z I0 RS =I1 RS I2 RS +I3 RS + +
(P =Q ) RS PRS+ PQRS +PRS + +
PRS =QRS PRS +PQRS PRS + + +
w

The k -
Map is as shown below
ww

Z PQ =PQS +
QRS +
Sol. 37 Option (C) is correct.
2710H LXI H, 30A0H ; Load 16 bit data 30A0 in HL pair
2713H DAD H ; 6140H " HL

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2714H PCHL ; Copy the contents 6140H of HL in PC

Thus after execution above instruction contests of PC and HL are same and that
is 6140H
Sol. 38 Option (C) is correct.
MSB of Y is 1, thus it is negative number and X is positive number
Now we have X 01110 = (14) 10 =
and Y 11001 = ( 7) 10 = -
X Y + (14) =( 7) 7 + - =
In signed two’s complements from 7 is

n
(7) 10 =
000111

g.i
Sol. 39 Option (B) is correct.
Y AB =CD = +
AB .CD
This is SOP form and we require only 3 NAND gate

n
Sol. 40 Option (A) is correct.

eri
The circuit is as shown below
e
gin
En

Y AB =AB +
and X YC =YC (AB +=AB ) C (AB+ AB ) C + +
arn

(AB =AB) C (AB+ AB ) C + +

ABC = ABC ABC +ABC + +
Sol. 41 Option (D) is correct.
.Le

Y ABCD =ABCD ABC D +ABC D + +

ABCD =ABC D ABC D +ABC D + +
ABCD =ABC D BC D (A+ A) + +
ABCD =ABC D BC D + + A A +1 =
w

Sol. 42 Option (B) is correct.

ww

In given TTL NOT gate when Vi = 2.5 (HIGH), then

Q1 " Reverse active
Q2 " Saturation
Q3 " Saturation
Q4 " cut - off region
Sol. 43 Option (C) is correct.
For X 0, Y = 1 =
P 1, Q = 0 =
For X 0, Y = 0 =
P 1, Q = 1 =
For X 1, Y = 1 =
P 1, Q = 0 or P 0, Q= = 1 =

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Sol. 44 Option (C) is correct.

Chip 8255 will be selected if bits A3 to A7 are 1. Bit A0 to A2 can be 0 or.
1. Thus address range is
11111000 F8H
11111111 FFH
Sol. 45 Option (B) is correct.
Since the inverting terminal is at virtual ground the resistor network can be
reduced as follows

n
n g.i
e eri
gin
The current from voltage source is
I VR = 10 =
1 mA =
R 10k
En

This current will be divide as shown below

arn
.Le

I = 1 # 10 - 3
w

Now i =62.5 m
A =
16 16
ww

Sol. 46 Option (C) is correct.

The net current in inverting terminal of OP - amp is
I- 1 =1 5I+ =
4 16 16
So that V0 =R #-5I = -
3.125
16
Sol. 47 Option (B) is correct.
Line
1 : MVI A, B5H ; Move B5H to A
2 : MVI B, 0EH ; Move 0EH to B
3 : XRI 69H ; [A] XOR 69H and store in A
; Contents of A is CDH

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4 : ADDB ; Add the contents of A to contents of B and

; store in A, contents of A is EAH
5 : ANI 9BH ; [a] AND 9BH, and store in A,
; Contents of A is 8 AH
6 : CPI 9FH ; Compare 9FH with the contents of A
; Since 8 AH < 9BH, CY = 1
7 : STA 3010 H ; Store the contents of A to location 3010 H
8 : HLT ; Stop
Thus the contents of accumulator after execution of ADD instruction is EAH.
Sol. 48 Option (C) is correct.

n
The CY = 1 and Z = 0

g.i
Sol. 49 Option (A) is correct.
For this circuit the counter state (Q1, Q0) follows the sequence 00, 01, 10, 00 ... as
shown below

n
eri
Clock D1 D0 Q1 Q0 Q1 NOR Q0
00 1
1st 01 10 0
e
2nd 10 01 0
gin
3rd 00 00 0
En
arn

Sol. 50 Option (A) is correct.

As shown below there are 2 terms in the minimized sum of product expression.
.Le

1 0 0 1
0 d 0 0
0 0 d 1
1 0 0 1
w

Sol. 51 Option (B) is correct.

ww

The output is taken from the 5th line.

Sol. 52 Option (D) is correct.
After applying two clock poles, the outputs of the full adder is S =
1, C0 =
1
A B Ci S Co
1st 1 0 0 0 1
2nd 1 1 1 1 1
Sol. 53 Option (D) is correct.
SSSS
100010011001
4 2 3 1

Sol. 54 Option (B) is correct.

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In this the diode D2 is connected to the ground. The following table shows the
state of counter and D/A converter

Q2 Q1 Q0 D3 =
Q2 D2 =
0 D1 =
Q1 D0 =
Q0 Vo
000 0 0 0 0 0
001 0 0 0 1 1
010 0 0 1 0 2
011 0 0 1 1 3
100 1 0 0 0 8

n
101 1 0 0 1 9

g.i
110 1 0 1 0 10
111 1 0 1 1 11
000 0 0 0 0 0

n
001 0 0 0 1 1

Sol. 55
Thus option (B) is correct
Option (B) is correct.
LXI, EFFF H
CALL 3000 H
e eri
; Load SP with data EFFH
; Jump to location 3000 H
gin
:
:
:
En

3000H LXI H, 3CF4 ; Load HL with data 3CF4H

PUSH PSW ; Store contnets of PSW to Stack
POP PSW ; Restore contents of PSW from stack
PRE ; stop
arn

Before instruction SPHL the contents of SP is 3CF4H.

After execution of POP PSW, SP + 2 " SP
After execution of RET, SP + 2 " SP
.Le

Thus the contents of SP will be 3CF4H + 4 = 3CF8H

Sol. 56 Option (A) is correct.
The inputs D0 and D1 respectively should be connected as Q1 and Q0
where Q0 " D1 and Q1 " D0
w

Sol. 57 Option (D) is correct.

If the point P is stuck at 1, then output f is equal to A
ww

Sol. 58 Option (B) is correct.

Dividing 43 by 16 we get

g
2
16 43
32
11

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11 in decimal is equivalent is B in hexamal.

Thus 4310 * 2B16
Now 410 * 01002
310 * 00112
Thus 4310 * 01000011BCD
Sol. 59 Option (A) is correct.
The diagram is as shown in fig

n
n g.i
f'
f
BC =BC
f'A =f'0
=
+
f'A ABC =ABC
e eri
+

+
gin
Sol. 60 Option (C) is correct.
The circuit is as shown below
En
arn
.Le

If output is at logic 0, the we have V0 =

0 which signifies BJT Q3 is in saturation
and applying KVL we have
VBE3 =
IR # 1k
or 0.75 =
IR # 1k
w

or IR =
0.75 mA
ww

Sol. 61 Option (A) is correct.

We have f ABC =ABC +
B (AC =AC ) B (A =C)(
+A C) + +
Sol. 62 Option (C) is correct.
Characteristic equation for a jk flip-flop is written as
Qn 1+ JQ n =K Qn +
Where Qn is the present output
Qn 1+ is next output
So, Qn 1+ 10 =K : 0 + Qn =
0
Qn 1+ =
1

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Sol. 63 Option (C) is correct.

Since T2 T1 T0 is at 111, at every clock Q2 Q1 Q0 will be changes. Ir present state is
011, the next state will be 100.
Sol. 64 Option (D) is correct.
Sol. 65 Option (C) is correct.
0100H LXI SP, 00FF ; Load SP with 00FFG
0103H LXI H, 0701 ; Load HL with 0107H
0106H MVI A, 20H ; Move A with 20 H
0108 H SUB M ; Subtract the contents of memory

n
; location whose address is stored in HL
; from the A and store in A

g.i
0109H ORI 40H ; 40H OR [A] and store in A
010BH ADD M ; Add the contents of memeory location
; whose address is stored in HL to A

n
; and store in A

eri
HL contains 0107H and contents of 0107H is 20H
Thus after execution of SUB the data of A is 20H - 20H = 00
Sol. 66 Option (C) is correct.
e
Before ORI instruction the contents of A is 00H. On execution the ORI 40H the
gin
contents of A will be 40H
00H = 00000000
40H = 01000000
ORI 01000000
En

After ADD instruction the contents of memory location whose address is stored
in HL will be added to and will be stored in A
arn

40H + 20 H = 60 H
Sol. 67 Option (C) is correct.
A master slave D-flip flop is shown in the figure.
w .Le

In the circuit we can see that output of flip-flop call be triggered only by transition
ww

of clock from 1 to 0 or when state of slave latch is affected.

Sol. 68 Option (A) is correct.
The range of signed decimal numbers that can be represented by n -
bits 1’s
complement number is (2n - 1 -1) to (2n - 1 -
+1). -
Thus for n = 6 we have
-1 -
Range =(26- + (26 1
1) to - -
1)
=31 -
to + 31
Sol. 69 Option (D) is correct.
The minimum number of bit require to encode 100 increment is
2n $ 100

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or n $7
Sol. 70 Option (B) is correct.
Shift Register " Serial to parallel data conversion
Counter " Frequency division
Decoder " Addressing in memory chips.
Sol. 71 Option (A) is correct.
For the TTL family if terminal is floating, then it is at logic 1.
Thus Y (AB =1) AB .0 =+
0 =
Sol. 72 Option (C) is correct.

n
11001 1001 111001

g.i
00110 0110 000110
+1 +1 +1
00111 0111 000111

n
7 7 7
Thus 2’s complement of 11001, 1001 and 111001 is 7. So the number given in the

Sol. 73
eri
question are 2’s complement correspond to -7.
Option (C) is correct.
In the modulo - 6 ripple counter at the end of sixth pulse (i.e. after 101 or at 110)
e
all states must be cleared. Thus when CB is 11 the all states must be cleared. The
gin
input to 2-input gate is C and B and the desired output should be low since the
CLEAR is active low
Thus when C and B are 0, 0, then output must be 0. In all other case the output
must be 1. OR gate can implement this functions.
En

Sol. 74 Option (C) is correct.

Number of MUX is 4 2 and 2
= =
1. Thus the total number 3 multiplexers is
3 2
arn

required.
Sol. 75 Option (D) is correct.
AC +
BC AC1 =BC 1 AC (B+=B ) BC (A A)+ + +
ACB =ACB BC A +BC A + +
.Le

Sol. 76 Option (D) is correct.

We have f (x, y) xy =xy xy +x (y =y) +xy x+=xy ++
or f (x, y) x =y +
w

Here compliments are not available, so to get x we use NOR gate. Thus desired
circuit require 1 unit OR and 1 unit NOR gate giving total cost 2 unit.
ww

Sol. 77 Option (D) is correct.

For 8255, various modes are described as following.
Mode 1 : Input or output with hand shake
In this mode following actions are executed
1. Two port (A & B) function as 8 - bit input output ports.
2. Each port uses three lines from C as a hand shake signal
3. Input & output data are latched.
Form (ii) the mode is 1.
Mode 2 : Bi-directional data transfer
This mode is used to transfer data between two computer. In this mode port A

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can be configured as bidirectional port. Port A uses five signal from port C as
hand shake signal.
For (1), mode is 2
Sol. 78 Option (B) is correct.
LDA 16 bit & Load accumulator directly this instruction copies data byte from
memory location (specified within the instruction) the accumulator.
It takes 4 memory cycle-as following.
1. in instruction fetch
2. in reading 16 bit address

n
1. in copying data from memory to accumulator
LXI D, (F0F1) 4 & It copies 16 bit data into register pair D and E.

g.i
It takes 3 memory cycles.
Sol. 79 Option (A) is correct.

n
LXI H, 9258H ; 9258H " HL

eri
MOV A, M ; (9258H) " A
CMa ; A"A
MOV M, A ; A"M
This program complement the data of memory location 9258H.
e
Option (D) is correct.
gin
Sol. 80

MVI A, 00H ; Clear accumulator

LOOP ADD B ; Add the contents of B to A
DCR C ; Decrement C
En

JNZ LOOP ; If C is not zero jump to loop

HLT
END
This instruction set add the contents of B to accumulator to contents of C times.
arn

Sol. 81 Option (D) is correct.

The number of distinct boolean expression of n variable is 22n . Thus
22 216 = 65536
4

=
.Le

Sol. 82 Option (C) is correct.

In the flash analog to digital converter, the no. of comparators is equal to 2n - 1,
where n is no. of bit.s
w

So, 2n - 1 28 =1 255 - =
Sol. 83 Option (B) is correct.
ww

When output of the 74 series gate of TTL gates is taken from BJT then the
configuration is either totem pole or open collector configuration .
Sol. 84 Option (D) is correct.
A 2n: 1 MUX can implement all logic functions of (n 1+) variable without andy
additional circuitry. Here n =.
3 Thus a 8 : 1 MUX can implement all logic
functions of 4 variable.
Sol. 85 Option (D) is correct.
Counter must be reset when it count 111. This can be implemented by following
circuitry

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Sol. 86 Option (B) is correct.

We have Y =
P5Q5R
Z = RQ + PR + QP
Here every block is a full subtractor giving P Q -R where-R is borrow. Thus
circuit acts as a 4 bit subtractor giving P Q-.
Sol. 87 Option (A) is correct.

n
W R =PQ RS+ +

g.i
X PQRS =PQRS PQRS + +
Y RS =PR PQ +PQ RS +
=PR $ PQ $ PQ
+
RS =(P R )( P+ Q)( P Q+) + +

n
RS =(P PQ +PR QR )(+P Q) + + +

Z
RS =PQ QR (+
R =S
R =S
PQ + PQR +PQS
e eri
P P ) QR+ RS =PQ +QR +

(P +Q )( P +Q R)( P+ Q S)
+
R+=S PQ $+PQR
+
+ $ PQS
+
+
+

+ +
gin
R =S PQ PQ + PQS + PR PQR+ + + +
PRS +PQ PQS +
PQR QRS + +
R S= PQ PQS+ PR +
PQR PRS +
PQS PQR +
QRS +
S= PQ (1 S)+ PR (1 + + PQR + +
En

R P) PRS PQS QRS

R S= PQ PR + PRS +
PQS PQR +
QRS + +
R =S PQ + PR (1 +Q ) PQS+ QRS + + +
arn

R =S PQ + PR PQS+ QRS+ + +
Thus W =
Z and X =Z
Sol. 88 Option (B) is correct.
Propagation delay of flip flop is
.Le

tpd = 10 nsec
Propagation delay of 4 bit ripple counter
R 4tpd = 40 ns =
w

and in synchronous counter all flip-flop are given clock simultaneously, so

S tpd = 10 ns =
ww

Sol. 89 Option (C) is correct.

After t =,t1 at first rising edge of clock, the output of shift register is 0110, which
in input to address line of ROM. At 0110 is applied to register. So at this time
data stroed in ROM at 1010 (10), 1000 will be on bus.
When W has the data 0110 and it is 6 in decimal, and it’s data value at that add
is 1010
then 1010 i.e. 10 is acting as odd, at time t2 and data at that movement is 1000.
Sol. 90 Option (B) is correct.
The DTL has minimum fan out and CMOS has minimum power consumption.
Propagation delay is minimum in ECL.

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Sol. 91 Option (D) is correct.

Let input be 1010; output will be 1101
Let input be 0110; output will be 0100
Thus it convert gray to Binary code.
Sol. 92 Option (A) is correct.
CMP B & Compare the accumulator content with context of Register B
If A <R CY is set and zero flag will be reset.
Sol. 93 Option (A) is correct.
Vo Rb
=V1 :- R b+ R b +R b 3D +
R o 2R 1 4R 2 4R

n
g.i
Exact value when V1 =,
5 for maximum output
VoExact =5 :1- 1 1+ 1 D + 9.375
+ = -
2 4 8

n
Maximum Vout due to tolerance
110 110 + 110 + 110
Vo max =5.5- : 90 4 # 90 8 # 90 D
+

eri
2 # 90
=12.-
604
Tolerance 34.44% = 35% =
e
Sol. 94 Option (D) is correct.
gin
If the 4- bit 2’s complement representation of a decimal number is 1000, then the
number is -8
Sol. 95 Option (C) is correct.
En

In the comparator type ADC, the no. of comparators is equal to 2n - 1, where n is

no. of bit.s
So, 23 1- =
7
arn

Sol. 96 Option (B) is correct.

Output of 1 st XOR = X $ 1 =X $ 1 X + =
Output of 2 nd XOR X X =XX 1 + =
So after 4,6,8,...20 XOR output will be 1.
.Le

Sol. 97 Option (B) is correct.

They have prorogation delay as respectively,
G1 " 10 nsec
w

G2 " 20 nsec
For abrupt change in Vi from 0 to 1 at time t =
t0 we have to assume the output
ww

of NOR then we can say that option (B) is correct waveform.

Sol. 98 Option (B) is correct.

Let X3 X2 X1 X0 be 1001 then Y3 Y2 Y1 Y0 will be 1111.

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Let X3 X2 X1 X0 be 1000 then Y3 Y2 Y1 Y0 will be 1110

Let X3 X2 X1 X0 be 0110 then Y3 Y2 Y1 Y0 will be 1100
So this converts 2-4-2-1 BCD numbers.
Sol. 99 Option (B) is correct.
MVI B, 87H ; B = 87
MOV A, B ; A = B = 87
START : JMP NEXT ; Jump to next
XRA B ; A 5 B " A,
; A 00, B = 87 =
JP START ; Since A = 00 is positive

n
; so jump to START

g.i
JMP NEXT ;Jump to NEXT ; unconditionally
NEXT : XRA ; B ; A 5 B " A, A = 87 ,
; B = 87 H

n
JP START ; will not jump as D7 , of A is 1
OUT PORT2 ;A = 87 " PORT2
Sol. 100 Option (C) is correct.
The circuit is as shown below
e eri
gin
En

The circuit shown is monostable multivibrator as it requires an external triggering

and it has one stable and one quasistable state.
arn

Sol. 101 Option (B) is correct.

The two’s compliment representation of 17 is
17 = 010001
Its 1’s complement is 101110
.Le

So 2’s compliment is
101110
+ 1
w

101111
Sol. 102 Option (C) is correct.
ww

The propagation delay of each inverter is tpd then The fundamental frequency of
oscillator output is
f =1 1 = 1 GHz =
2ntpd 2 # 5 # 100 # 10 - 12
Sol. 103 Option (C) is correct.
4K # 8 bit means 102410 location of byte are present
Now 102410 * 1000H
It starting address is AA00H then address of last byte is
AA00H 1000H +0001H =
B9FFH -

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Sol. 104 Option (D) is correct.

Y I0 =I3 I5 +I6 C BA
+ =C AB+ CBA +
CBA +
C (BA =AB) C (AB BA +) + +
or Y C (A 5 B ) =C (A 5 B) +
Sol. 105 Option (C) is correct.
The output of options (C) satisfy the given conditions

n
n g.i
Sol. 106

Sol. 107
Option (B) is correct.
Option (D) is correct.
e eri
For the LED to glow it must be forward biased. Thus output of NAND must be
gin
LOW for LED to emit light. So both input to NAND must be HIGH. If any one
or both switch are closed, output of AND will be LOW. If both switch are open,
output of XOR will be LOW. So there can’t be both input HIGH to NAND. So
En

LED doesn’t emit light.

Sol. 108 Option (B) is correct.
Conversion time of successive approximate analog to digital converters is
arn

independent of input voltage. It depends upon the number of bits only. Thus it
remains unchanged.
Sol. 109 Option (C) is correct.
In the flash analog to digital converter, the no. of comparators is equal to 2n - 1,
.Le

where n is no. of bits.

So, 2 4 1- = 15
Sol. 110 Option (D) is correct.
w

As the output of AND is X =

1, the all input of this AND must be 1. Thus
AB AB + =
1 ...(1)
ww

BC BC + =
1 ...(2)
C =
1 ...(3)
From (2) and (3), if C = 1, then B =1
If B =1, then from (1) A =. 0 Thus A 0, B = 1 and C =
1=
Sol. 111 Option (C) is correct.
Interrupt is a process of data transfer by which an external device can inform
the processor that it is ready for communication. 8085 microprocessor have five
interrupts namely TRAP, INTR, RST 7.5, RST 6.5 and RST 5.5

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Sol. 112 Option (A) is correct.

For any RST instruction, location of program transfer is obtained in following
way.
RST x & (x ) 8) 10 " convert in hexadecimal
So for RST 6 & (6 ) 8) 10 (48) 10 = (30) H =
Sol. 113 Option (A) is correct.
Accumulator contains A =
49 H
Register B =
3 AH
SUB B A = minus B

n
A 49 H = 01001001 =

g.i
B 3 AH = 00111010 =
-)
2’s complement of ( B =
11000110
A -
B A =( B) + -

n
010 010 01

eri
& 1+1 0 0 0 1 1 0
0 0 0 0 1111
Carry =
1
e
so here outputA =
0F
gin
Carry CY =
1
Sign flag S =
1
Sol. 114 Option (C) is correct.
En

The circuit is as shown below :

arn
.Le

Y B =(B C )+ B (B =+
C) B + =
Sol. 115 Option (B) is correct.
w

The circuit is as shown below

ww

The voltage at non-inverting terminal is

V+ 1 =1 5 + =
8 2 8

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V- V+ = 5 = ...(1)
8
Now applying voltage divider rule
V- = 1k V% 1V
= ...(2)
1k 7+k 8 o
From (1) and (2) we have
Vo 8 # 5 = 5V =
8
Sol. 116 Option (D) is correct.
The truth table is shown below

n
Z XQ =YQ +

g.i
Comparing from the truth table of J - FF
K
Y =,
J
X =
K

n
eri
X Y Z
0 0 Q
0 1 0
e
1 0 1
gin
1 1 Q1

Sol. 117 Option (B) is correct.

In the figure the given counter is mod-10 counter, so frequency of output is
En

10k = 1k
10
Sol. 118 Option (D) is correct.
arn

We have y A =AB +
we know from Distributive property
x +
yz (x =y) (x z)+ +
.Le

Thus y (A =A) (A B+ ) A =B ++ ` A A +1 =
Sol. 119 Option (C) is correct.
Darligton emitter follower provides a low output impedance in both logical state
(1 or 0). Due to this low output impedance, any stray capacitance is rapidly
w

charged and discharged, so the output state changes quickly. It improves speed
of operation.
ww

Sol. 120 Option (D) is correct.

Sol. 121 Option (B) is correct.
For ADC we can write
Analog input =
(decimal eq of digital output) # resol
6.6 =
(decimal eq. of digital output) # 0.5
6.6 =
decimal eq of digital. output
0. 5
13.2 =
decimal equivalent of digital output so output of ADC is 1101.
Sol. 122 Option (A) is correct.
We use the K -map as below.

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So given expression equal to

AC =BC AB + +
Sol. 123 Option (C) is correct.

n
For a binary half-subtractor truth table si given below.

n g.i
D
X
A 5 B = AB AB
=
AB
e eri
from truth table we can find expressions of D & X
= +
gin
Sol. 124 Option (B) is correct.
We have 4 K RAM (12 address lines)
En
arn
w .Le
ww

S so here chip select logic CS =

A15 A14 A13
address range (111)
A15 A14 A13 A12 A11 A10 A 9 A 8 A7 A6 A5 A 4 A 3 A2 A1 A 0
initial 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
address &7000H
final 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11
address &7FFFH
so address range is (7 0 0 0 H – 7 F F F H)

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Sol. 125 Option (D) is correct.

From the given figure we can write the output

n
g.i
For the state 010 all preset =
1 and output QA QB QC =
111 so here total no. of
states = 5 (down counter)

n
Sol. 126 Option (C) is correct.
Given boolean function is

Now
Thus Z
Z
Z
e
AC =B
=
ABC
=
ABC eri ACB = AC
+
B = +
gin
we have Z X =Y (1 NOR + gate)
where X =
AC (1 NAND gate)
To implement a NOR gate we required 4 NAND gates as shown below in figure.
En
arn

here total no. of NAND gates required

4 =1 5 + =
.Le

Sol. 127 Option (B) is correct.

For TTL worst cases low voltages are
VOL (max) = 0.4 V
VIL (max) = 0.8 V
w

Worst case high voltages are

VOH (min) = 2.4 V
ww

VIH (min) = 2V
The difference between maximum input low voltage and maximum output low
voltage is called noise margin. It is 0.4 V in case of TTL.
Sol. 128 Option (D) is correct.
From the figure we can see
If A 1 B =0 =
then y 1 x =0 =
If A 1 B =1 =
then also y 1 x =0 =
so for sequence B =
101010....output x and y will be fixed at 0 and 1 respectively.

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Sol. 129 Option (D) is correct.

Given 2’s complement no. 1101; the no. is 0011
for 6 digit output we can write the no. is – 000011
2’s complement representation of above no. is 111101
Sol. 130 Option (A) is correct.
Sol. 131 Option (B) is correct.
An I/O Microprocessor controls data flow between main memory and the I/O
device which wants to communicate.
Sol. 132 Option (D) is correct.

n
Sol. 133 Option (B) is correct.

g.i
Dual slope ADC is more accurate.
Sol. 134 Option (A) is correct.
Dual form of any identity can be find by replacing all AND function to OR and

n
vice-versa. so here dual form will be

eri
(A B) (A +C) (B C) + =B) (A
(A C)+ + +
Sol. 135 Option (B) is correct.
Carry flag will be affected by arithmetic instructions only.
e
Sol. 136 Option (C) is correct.
gin
This is a synchronous counter. we can find output as
QA QB
0 0
1 0
En

0 1
0 0
h
arn

So It counts only three states. It is a mod-3 counter.

K =
3
Sol. 137 Option (B) is correct.
.Le

Sol. 138 Option (A) is correct.

Essential prime implicates for a function is no. of terms that we get by solving K
-map. Here we get 4 terms when solve the K -map.
w
ww

y B D =A C D +
C AB CA B + +
so no of prime implicates is 4

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Sol. 139 Option (A) is correct.

Sol. 140 Option (B) is correct.
For a 2 bit multiplier
B1 B0
# A1 A0
A 0 B1 A0 B0
# A1 B1 A1 B 0
C3 C2 C1 C0
This multiplication is identical to AND operation and then addition.

n
Sol. 141 Option (C) is correct.

g.i
In totem pole stage output resistance will be small so it acts like a output buffer.
Sol. 142 Option (B) is correct.
Consider high output state

n
fan out IOH max = 400 mA 20 = =
IIH max 20 mA
Consider low output state
fan out IOL max = 8 mA
IIL max
Thus fan out is 20
0.1 mA
e 80 eri = =
gin
Sol. 143 Option (A) is correct.
The given gate is ex-OR so output
F AB =AB +
En

Here input B =
0 so,
F A1 =A0 =
A +
Sol. 144 Option (C) is correct.
arn

EI =
Enabled Interput flag ,RST will cause an Interrupt only it we
enable EI .
Sol. 145 Option (A) is correct.
.Le

Here only for the range 60 to 63 H chipselect will be 0, so peripheral will correspond
in this range only chipselect = 1 for rest of the given address ranges.
Sol. 146 Option (B) is correct.
w

By executing instructions one by one

LXI H, 8A79 H (Load HL pair by value 8A79)
ww

H 8AH L = 79 H =
MOV A, L (copy contain of L to accumulator)
A = 79 H
ADDH (add contain of H to accumulator)
A 79 H = 0 1111 0=
01
H 8AH = add 1 0 0 0 1 0 = 10 A = 00= 0 0 0 0 11
Carry = 1
DAA (Carry Flag is set, so DAA adds 6 to high order four bits)
0 1111 0 0 1
DAA add 1 0 0 0 1 0 1 0

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A 0 0 0 0 0 0 1 1 = 63 H =
MOV H, A (copy contain of A to H)
H = 63 H
PCHL (Load program counter by HL pair)
PC = 6379 H
Sol. 147 Option (C) is correct.
Sol. 148 Option (C) is correct.
NMOS In parallel makes OR Gate & in series makes AND so here we can have
F A (B =C) DE + +

n
we took complement because there is another NMOS given above (works as an

g.i
inverter)
Sol. 149 Option (D) is correct.
For a J -K flip flop we have characteristic equation as

n
Q (t 1+) JQ (t) =KQ (t) +

eri
Q (t) & Q (t 1+) are present & next states.
In given figure J Q (t), K = 1 so =
Q (t 1+) Q (t) Q (t) =0Q (t) +
e
Q (t 1+) = Q (t)[complement of previous state]
gin
we have initial input Q (t) = 0
so for 6 clock pulses sequence at output Q will be 010101
Sol. 150 Option (C) is correct.
En

Sol. 151 Option (B) is correct.

By distributive property in boolean algebra we have
(A BC+ ) (A =B) (A C)+ +
arn

(A B) (A +C) AA =AC+ AB +BC + +

A (1 =C) AB BC+ A =AB+ BC
+ + +
A (1 =B) BC + =BC
A +
+
.Le

Sol. 152 Option (A) is correct.

The current in a p n junction diode is controlled by diffusion of majority carriers
while current in schottky diode dominated by the flow of majority carrier over the
potential barrier at metallurgical junction. So there is no minority carrier storage
w

in schottky diode, so switching time from forward bias to reverse bias is very
short compared to p n junction diode. Hence the propagation delay will reduces.
ww

Sol. 153 Option (B) is correct.

Sol. 154 Option (D) is correct.
The total conversion time for different type of ADC are given as–
t clock period
is
For flash type & 1 t
Counter type & (2n ) - 4095 tsec= m
n = no.of bits
Integrating type conver time 4095 >sec m
successive approximation type n t = m
12 sec

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here n =12 so
n t =
12
12 t =
12
so this is succ. app. type ADC.
Sol. 155 Option (D) is correct.
LDA 2003 (Load accumulator by a value 2003 H) so here total no. of memory
access will be 4.
1 = Fetching instruction
2 = Read the value from memory

n
1 = write value to accumulator

g.i
Sol. 156 Option (D) is correct.
Storage capacitance
-
12
=i =1 # 10

n
C
dv 5 0-.5
b dt l b 20 10 3-l

eri
#
12 -3 -
1 # 10
= # 20 # 10 =
4.4 # 10 -
15
F
4.5
e
Sol. 157 Option (A) is correct.
gin
Accuracy ! 1 LSB = Tcoff # D
T
2
or 1 10.24 = Tcoff # TD
2 # 210
En

or Tcoff = 10.24 =
200 Vm/cC
2 # 1024 # (50 - ) cC
25
Sol. 158 Option (D) is correct.
26 # 210 # 8
arn

No. of chips = =
13
212 # 4
Sol. 159 Option (C) is correct.
Given instruction set
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1000 LXI SP 27FF

1003 CALL 1006
1006 POP H
First Instruction will initialize the SP by a value
w

27FF SP ! 27FF
CALL 1006 will “Push PC” and Load PC by value 1006
ww

PUSH PC will store value of PC in stack

PC =
1006

now POP H will be executed

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GATE SOLVED PAPER - EC DIGITAL CIRCUITS

which load HL pair by stack values

HL =
1006 and
SP SPl =2 +
SP SPl =2 SP 2 +2 SP = - + =
SP =
27FF

***********

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