Compal Confidential: MCP79-MX
Compal Confidential: MCP79-MX
Compal Confidential: MCP79-MX
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1 1
2 Compal Confidential 2
Schematic Document
MCP79-MX
2009 / 02 / 19 Rev:1.0
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4631P
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 1 of 42
A B C D E
A B C D E
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Compal confidential
Braxton 14"
Project Code: KCM00
File Name : LA-4631P
PCB
Intel Penryn
1 Fan Driver uFCPGA-478 CPU
1
ZZZ1
RT9027BPS
P.4
P.4,5,6
X76
Thermal Sensor
EMC1402-1-ACZL-TR H_A#(3..35) FSB
P.4 667/800/1066MHz 1.05V
ZZZ2
H_D#(0..63)
Memory
Channel A DDR3 / 1GB on board
14" LED Panel ( 128Mx8) x8pcs P.17,18
LVDS Dual Channel
HD 1366 x 768 DDR3 800/1066 MHz +1.5V
HD+ 1600 x 900 DDR3-SO-DIMM x1
P.20 BANK 0, 1, 2, 3
Channel B P.19
2
HDMI Conn. 1:2 Switch 2
P.21
TI HDMI / TMDS
SATA HDD Conn
Display Port
SN75DP122A P.21
nVIDIA SATA
SATA_A0 P.20
P.21
MCP79-MX SATA_A1
B to B USB/E-SATA Conn
On Right Side P.29
USB2
FCBGA 1437
PCI-E x1 USB1 USB Conn
On Right Side P.29
B to B
PCIE0 PCIE1 PCIE2 PCIE3 USB2.0 USB0 USB Conn
On Left Side P.27
USB4 Camera
P.27
Digital Microphone
KBC P.27
Power On/Off CKT.
P.29
ENE KB926
P.28
Audio Codec Tweeter (0.5W x2)
P.25, 29
P.25
DC/DC Interface CKT. RTC CKT. IDT 92HD83
P.30 P.14,15,32,33 Speaker (1W x2) P.25
4
Touch Pad Conn Int.KB BIOS(System/EC) 4
P.29 P.29 P.28
Power Circuit DC/DC Power OK CKT. Audio Jack x3 P.29
P.32~40 B to B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4631P 1.0
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 2 of 42
A B C D E
A
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Voltage Rails O MEANS ON X MEANS OFF Symbol Note :
THERMAL
SERIAL SENSOR
SOURCE INVERTER BATT EEPROM (CPU) SODIMM EXP CARD MINI CARD1 MINI CARD2
EC_SMB_CK1
EC_SMB_DA1
KB926 X V X X X X X X
EC_SMB_CK2
EC_SMB_DA2
KB926 X X X V X X X X
MEM_SMBCLK
MEM_SMBDATA MCP79 X X X X V X X X
MCP_SMB_CLK
MCP_SMB_DATA MCP79
X X X X X V V V
MINI CARD 1 RESERVED +3VALW TO PULL HIGH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4631P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 3 of 42
A
5 4 3 2 1
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ADDR GROUP_0
H_A#4 L5 E2 H_BNR#
A[4]# BNR# H_BNR# 7
H_A#5 L4 G5 H_BPRI# H_PROCHOT# R519 2 1 68_0402_5%
A[5]# BPRI# H_BPRI# 7
H_A#6 K5
H_A#7 A[6]# H_DEFER# H_BR0# R520 1 @ 62_0402_5%
M3 A[7]# DEFER# H5 H_DEFER# 7 2
H_A#8 N2 F21 H_DRD Y#
A[8]# DRDY# H_DRDY# 7
H_A#9 J1 E1 H_DBSY# H_FERR# R521 1 2 62_0402_5%
A[9]# DBSY# H_DBSY# 7
H_A#10 N3
H_A#11 A[10]# H_BR0# H_INTR R522 1 @ 150_0402_1%
P5 A[11]# BR0# F1 H_BR0# 7 2
H_A#12 P2 AA7 H_BR1#
A[12]# BR1# H_BR1# 7
H_A#13 L2 D20 H_IERR# H_NMI R523 1 @ 2 150_0402_1%
CONTROL
H_A#14 A[13]# IERR# H_INIT#
P4 A[14]# INIT# B3 H_INIT# 7
H_A#15 P1 H_RESET# R524 1 @ 2 200_0402_1%
H_A#16 A[15]# H_LOCK#
R1 A[16]# LOCK# H4 H_LOCK# 7
H_ADSTB#0 M1 H_BR1# R1275 1 2 62_0402_5%
7 H_ADSTB#0 ADSTB[0]#
C1 H_RESET#
RESET# H_RESET# 7
H_REQ#0 K3 F3 H_RS#0 XDP_TCK R525 2 1 49.9_0402_1%
C 7 H_REQ#0 REQ[0]# RS[0]# H_RS#0 7 C
H_REQ#1 H2 F4 H_RS#1
7 H_REQ#1 REQ[1]# RS[1]# H_RS#1 7
H_REQ#2 K2 G3 H_RS#2 XDP_TRST# R526 2 1 649_0402_1%
7 H_REQ#2 REQ[2]# RS[2]# H_RS#2 7
H_REQ#3 J3 G2 H_TRDY#
7 H_REQ#3 REQ[3]# TRDY# H_TRDY# 7
H_REQ#4 L1
7 H_REQ#4 REQ[4]#
G6 H_HIT#
7 H_A#[17..35] HIT# H_HIT# 7
H_A#17 Y2 E4 H_HITM#
A[17]# HITM# H_HITM# 7
H_A#18 U5
H_A#19 A[18]# XDP_BPM#0
R3 A[19]# BPM[0]# AD4 T1
ADDR GROUP_1
A[23]# PRDY# T5
H_A#24 R4 AC1 XDP_PREQ# T6
H_A#25 A[24]# PREQ# XDP_TCK
T5 A[25]# TCK AC5
H_A#26 T3 AA6 XDP_TDI C3 +5VS
H_A#27 A[26]# TDI XDP_TDO 10U_1206_16V4Z~N
W2 A[27]# TDO AB3 T7
H_A#28 W5 AB5 XDP_TMS 2 1 C4
H_A#29 A[28]# TMS XDP_TRST#
Y4 A[29]# TRST# AB6 1 2
H_A#30 U2 C20 XDP_DBRESET#
H_A#31 A[30]# DBR# 10U_1206_16V4Z~N
V4 A[31]# 1 2
H_A#32 W3
H_A#33 A[32]# C5 U3
AA4 A[33]# THERMAL
H_A#34 AB2 1000P_0402_50V7K~N 1 8
A[34]# H_PROCHOT# 7 VEN GND
H_A#35 AA3 D21 H_PROCHOT# 2 7
H_ADSTB#1 A[35]# PROCHOT# H_THERMDA_R R7 +3VS VIN GND
7 H_ADSTB#1 V1 ADSTB[1]# THERMDA A24 1 2 100_0402_5% H_THERMDA 3 VO GND 6
B25 H_THERMDC_R R8 1 2 100_0402_5% H_THERMDC EN_DFAN1 4 5
THERMDC 28 EN_DFAN1 VSET GND
1
H_A20M# A6
7 H_A20M# A20M#
ICH
2
H_INTR STPCLK# Trace width / Spacing = 10 / 10 mil 1
7 H_INTR C6 LINT0 H CLK 28 FAN_SPEED1 2 2
B H_NMI CLK_CPU_BCLK B
7 H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK 7 2 3 3
H_SMI# A3 A21 CLK_CPU_BCLK# C6
7 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 7
0.01U_0402_16V7K 4 GND
M4 RSVD[01] 5 GND
1
N5 RSVD[02]
T2 RSVD[03] MOLEX_53780-0370~D
V3 CONN@
RSVD[04]
B2
RESERVED
RSVD[05]
D2 RSVD[06]
D22 RSVD[07]
D3
F6
RSVD[08]
RSVD[09]
Thermal Sensor
+3VS
0.1U_0402_16V4Z
TYCO_2-1871873-3_Merom~D
CONN@ 1
C1
2
U2
1 8 EC_SMB_CK2 EC_SMB_CK2 28
VDD SCLK
H_THERMDA 2 7 EC_SMB_DA2
D+ SDATA EC_SMB_DA2 28
1 2 H_THERMDC 3 6
C2 2200P_0402_50V7K D- ALERT#
+3VS 1 R9 2 L_THERM# 4 5
10K_0402_5% THERM# GND
A EMC1402-1-ACZL-TR MSOP 8P A
SMBus Address:100_1100
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(1/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4631P 1.0
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 4 of 42
5 4 3 2 1
5 4 3 2 1
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+CPU_CORE +CPU_CORE
7 H_D#[0..15] H_D#[32..47] 7
JCPU1B 47A JCPU1C
H_D#0 E22 Y22 H_D#32 A7 AB20
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
F24 D[1]# D[33]# AB24 A9 VCC[002] VCC[069] AB7
H_D#2 E26 V24 H_D#34 A10 AC7
D[2]# D[34]# VCC[003] VCC[070]
DATA GRP 0
H_D#3 G22 V26 H_D#35 A12 AC9
D[3]# D[35]# VCC[004] VCC[071]
DATA GRP 2
D H_D#4 H_D#36 D
F23 D[4]# D[36]# V23 A13 VCC[005] VCC[072] AC12
H_D#5 G25 T22 H_D#37 A15 AC13
H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
E25 D[6]# D[38]# U25 A17 VCC[007] VCC[074] AC15
H_D#7 E23 U23 H_D#39 A18 AC17
H_D#8 D[7]# D[39]# H_D#40 VCC[008] VCC[075]
K24 D[8]# D[40]# Y25 A20 VCC[009] VCC[076] AC18
H_D#9 G24 W22 H_D#41 B7 AD7
H_D#10 D[9]# D[41]# H_D#42 VCC[010] VCC[077]
J24 D[10]# D[42]# Y23 B9 VCC[011] VCC[078] AD9
H_D#11 J23 W24 H_D#43 B10 AD10
H_D#12 D[11]# D[43]# H_D#44 VCC[012] VCC[079]
H22 D[12]# D[44]# W25 B12 VCC[013] VCC[080] AD12
H_D#13 F26 AA23 H_D#45 B14 AD14
H_D#14 D[13]# D[45]# H_D#46 VCC[014] VCC[081]
K22 D[14]# D[46]# AA24 B15 VCC[015] VCC[082] AD15
H_D#15 H23 AB25 H_D#47 B17 AD17
H_DSTBN#0 D[15]# D[47]# H_DSTBN#2 VCC[016] VCC[083]
7 H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 7 B18 VCC[017] VCC[084] AD18
H_DSTBP#0 H26 AA26 H_DSTBP#2 B20 AE9
7 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 7 VCC[018] VCC[085]
H_DINV#0 H25 U22 H_DINV#2 C9 AE10
7 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 7 VCC[019] VCC[086]
7 H_D#[16..31] H_D#[48..63] 7 C10 VCC[020] VCC[087] AE12
C12 VCC[021] VCC[088] AE13
H_D#16 N22 AE24 H_D#48 C13 AE15
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
K25 D[17]# D[49]# AD24 C15 VCC[023] VCC[090] AE17
H_D#18 P26 AA21 H_D#50 C17 AE18
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
R23 D[19]# D[51]# AB22 C18 VCC[025] VCC[092] AE20
H_D#20 L23 AB21 H_D#52 D9 AF9
D[20]# D[52]# VCC[026] VCC[093]
DATA GRP 1
H_D#21 M24 AC26 H_D#53 D10 AF10
D[21]# D[53]# VCC[027] VCC[094]
DATA GRP 3
H_D#22 L22 AD20 H_D#54 D12 AF12
H_D#23 D[22]# D[54]# H_D#55 VCC[028] VCC[095]
M23 D[23]# D[55]# AE22 D14 VCC[029] VCC[096] AF14
H_D#24 P25 AF23 H_D#56 D15 AF15
H_D#25 D[24]# D[56]# H_D#57 VCC[030] VCC[097]
P23 D[25]# D[57]# AC25 D17 VCC[031] VCC[098] AF17
H_D#26 P22 AE21 H_D#58 D18 AF18
H_D#27 D[26]# D[58]# H_D#59 VCC[032] VCC[099] +VCCP
T24 D[27]# D[59]# AD21 E7 VCC[033] VCC[100] AF20
H_D#28 R24 AC22 H_D#60 E9 4.5A
H_D#29 D[28]# D[60]# H_D#61 VCC[034]
L25 D[29]# D[61]# AD23 E10 VCC[035] VCCP[01] G21
H_D#30 T25 AF22 H_D#62 E12 V6
C H_D#31 D[30]# D[62]# H_D#63 VCC[036] VCCP[02] C
N25 D[31]# D[63]# AC23 E13 VCC[037] VCCP[03] J6
H_DSTBN#1 L26 AE25 H_DSTBN#3 E15 K6 1
7 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 7 VCC[038] VCCP[04]
H_DSTBP#1 M26 AF24 H_DSTBP#3 E17 M6
7 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 7 VCC[039] VCCP[05] + C7
H_DINV#1 N24 AC20 H_DINV#3 E18 J21
7 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 7 VCC[040] VCCP[06]
E20 K21 330U 2.5V Y D2 LESR15M CX H1.9
V_CPU_GTLREF COMP0 VCC[041] VCCP[07]
AD26 GTLREF COMP[0] R26 F7 VCC[042] VCCP[08] M21
@ R13 2
1 2 1K_0402_5% TEST1 C23 TEST1 MISC COMP[1] U26 COMP1 F9 VCC[043] VCCP[09] N21
@ R14 1 2 1K_0402_5% TEST2 D25 AA1 COMP2 F10 N6
TEST3 TEST2 COMP[2] COMP3 VCC[044] VCCP[10]
T8 C24 TEST3 COMP[3] Y1 F12 VCC[045] VCCP[11] R21
@ C308 1 2 0.1U_0402_16V4Z TEST4 AF26 F14 R6
TEST5 TEST4 H_DPRSTP# R15 R16 R17 R18 VCC[046] VCCP[12]
T10 AF1 TEST5 DPRSTP# E5 H_DPRSTP# 7,38 F15 VCC[047] VCCP[13] T21
54.9_0402_1%
27.4_0402_1%
54.9_0402_1%
27.4_0402_1%
TEST6 A26 B5 H_DPSLP# F17 T6
T11 TEST6 DPSLP# H_DPSLP# 7 VCC[048] VCCP[14]
1
TEST7 C3 D24 H_DPWR# F18 V21
T12 TEST7 DPWR# H_DPWR# 7 VCC[049] VCCP[15]
CPU_BSEL0 B22 D6 H_PW RGOOD F20 W21 R1283
7 CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD 7 VCC[050] VCCP[16]
CPU_BSEL1 B23 D7 H_CPUSLP# 10mil 0_0805_5%
7 CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# 7
CPU_BSEL2 C21 AE6 H_PSI# AA9 B26 +1.5VS_VCCA 1 2
7 CPU_BSEL2 BSEL[2] PSI# H_PSI# 38 VCC[052] VCCA[01] +1.5VS
AA10 C26
2
VCC[053] VCCA[02]
0.01U_0402_16V7K
10U_0805_6.3V6M
TYCO_2-1871873-3_Merom~D To IMVP AA12
CONN@ VCC[054]
AA13 VCC[055] VID[0] AD6 CPU_VID0 38
AA15 VCC[056] VID[1] AF5 CPU_VID1 38 1 1
AA17 VCC[057] VID[2] AE5 CPU_VID2 38
AA18 AF4 C8 C9
VCC[058] VID[3] CPU_VID3 38
layout note: Rout H_DPRSTP# from ICH9 to IMVP6 then to GMCH & CPU 49.9 25.5 29.9 25.5 AA20 VCC[059] VID[4] AE3 CPU_VID4 38 2 2
AB9 VCC[060] VID[5] AF3 CPU_VID5 38
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs AC10 VCC[061] VID[6] AE2 CPU_VID6 38
Resistor placed within AB10 VCC[062]
AB12
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 0.5" of CPU pin.Trace AB14
VCC[063]
AF7 VCCSENSE Near pin B26
VCC[064] VCCSENSE VCCSENSE 38
+VCCP should be at least 25 AB15 VCC[065]
mils away from any other AB17 VCC[066]
AB18 AE7 VSSSENSE VSSSENSE 38
VCC[067] VSSSENSE
166 0 1 1 H_PW RGOOD R527 1 2@ 150_0402_1% toggling signal. Layout Note:
B TYCO_2-1871873-3_Merom~D B
H_CPUSLP# R528 1 2@ 51_0402_1%
COMP[0,2] trace width is CONN@ .
Route VCCSENSE and VSSSENSE traces at
18 mils. COMP[1,3] trace For 8 layer condition 27.4 Ohms with 50 mil spacing.
200 0 0 H_DPRSTP# R529 1 2@ 220_0402_1%
1 width is 4
H_DPRSTP#
Length match within 25 mils.
266 0 0 0 The trace width/space/other is
1
@ C649 20/7/25.
0.01U 16V K X7R 0402
2
+CPU_CORE
+VCCP
R19
1K_0402_1% R23 1 2 100_0402_1% VSSSENSE
2
V_CPU_GTLREF
For 6 layer
Z=27.4 ohm
1
R20
VCCSENSE, VSSSENSE/ 14mils (MS),
A Close to CPU pin A
Dual Core CPU 2K_0402_1% 16mils (SL) width, 7mils space, 25mils
within 500mils.
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(2/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4631P 1.0
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 5 of 42
5 4 3 2 1
5 4 3 2 1
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1
C11 C12 C13 C14 C457 C484 C485 C488 C489 C490
10U_0805_4V 10U_0805_4V 10U_0805_4V 10U_0805_4V 10U_0805_4V 10U_0805_4V 10U_0805_4V 10U_0805_4V 10U_0805_4V 10U_0805_4V
2
D D
JCPU1D
A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21
+CPU_CORE
A11 VSS[003] VSS[084] P24
A14 VSS[004] VSS[085] R2
A16 VSS[005] VSS[086] R5
A19 VSS[006] VSS[087] R22
A23 VSS[007] VSS[088] R25
AF2 VSS[008] VSS[089] T1
1
B6 T4 C492 C493 C577 C578 C579 C580
VSS[009] VSS[090] 10U_0805_4V 10U_0805_4V 10U_0805_4V 10U_0805_4V 10U_0805_4V 10U_0805_4V
B8 VSS[010] VSS[091] T23
B11 T26
2
VSS[011] VSS[092]
B13 VSS[012] VSS[093] U3
B16 VSS[013] VSS[094] U6 16pcs on TOP side
B19 VSS[014] VSS[095] U21
B21 VSS[015] VSS[096] U24
B24 VSS[016] VSS[097] V2
C5 VSS[017] VSS[098] V5
C8 VSS[018] VSS[099] V22
C11 VSS[019] VSS[100] V25
C14 VSS[020] VSS[101] W1
C16 VSS[021] VSS[102] W4
C19 VSS[022] VSS[103] W23
+CPU_CORE
C2 VSS[023] VSS[104] W26
C22 VSS[024] VSS[105] Y3
C25 VSS[025] VSS[106] Y6
D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24
D8 VSS[028] VSS[109] AA2
D11 VSS[029] VSS[110] AA5
1
C C27 C22 C26 C28 C591 C587 C588 C589 C590 C592 C
D13 VSS[030] VSS[111] AA8
D16 AA11 10U_0805_4V 10U_0805_4V 10U_0805_4V 10U_0805_4V 10U_0805_4V 10U_0805_4V 10U_0805_4V 10U_0805_4V 10U_0805_4V 10U_0805_4V
VSS[031] VSS[112]
D19 AA14
2
VSS[032] VSS[113]
D23 VSS[033] VSS[114] AA16
D26 VSS[034] VSS[115] AA19
E3 VSS[035] VSS[116] AA22
E6 VSS[036] VSS[117] AA25
E8 VSS[037] VSS[118] AB1
E11 VSS[038] VSS[119] AB4
E14 VSS[039] VSS[120] AB8
+CPU_CORE
E16 VSS[040] VSS[121] AB11
E19 VSS[041] VSS[122] AB13
E21 VSS[042] VSS[123] AB16
E24 VSS[043] VSS[124] AB19
F5 VSS[044] VSS[125] AB23
F8 VSS[045] VSS[126] AB26
1
1
F11 AC3 C581 C582 C584 C583 C586 C585
VSS[046] VSS[127] 10U_0805_4V 10U_0805_4V 10U_0805_4V 10U_0805_4V 10U_0805_4V 10U_0805_4V
F13 VSS[047] VSS[128] AC6
F16 AC8
2
2
VSS[048] VSS[129]
F19 VSS[049] VSS[130] AC11 16pcs on bottom side
F2 VSS[050] VSS[131] AC14
F22 VSS[051] VSS[132] AC16
F25 VSS[052] VSS[133] AC19
G4 VSS[053] VSS[134] AC21
G1 VSS[054] VSS[135] AC24
G23 VSS[055] VSS[136] AD2
G26 VSS[056] VSS[137] AD5
H3 VSS[057] VSS[138] AD8
H6 VSS[058] VSS[139] AD11
H21 VSS[059] VSS[140] AD13
H24 VSS[060] VSS[141] AD16
J2 AD19 +VCCP
B VSS[061] VSS[142] B
J5 VSS[062] VSS[143] AD22
J22 VSS[063] VSS[144] AD25
J25
K1
VSS[064] VSS[145] AE1
AE4 1 1 1 1 1 1
Place these caps inside the
VSS[065] VSS[146] C15 C16 C17 C18 C19 C20
K4
K23
VSS[066] VSS[147] AE8
AE11 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K socket cavity on Bottom side.
VSS[067] VSS[148]
K26 AE14
L3
VSS[068] VSS[149]
AE16
2 2 2 2 2 2 (North side Secondary)
VSS[069] VSS[150]
L6 VSS[070] VSS[151] AE19
L21 VSS[071] VSS[152] AE23
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2
M5 VSS[074] VSS[155] AF6
M22 VSS[075] VSS[156] AF8
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16
N23 VSS[079] VSS[160] AF19
+CPU_CORE +CPU_CORE +CPU_CORE +CPU_CORE
N26 VSS[080] VSS[161] AF21
P3 VSS[081] VSS[162] A25
VSS[163] AF25
TYCO_2-1871873-3_Merom~D 1 1 1 1
CONN@ .
+ C456 + C458 + C576 + C522
330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9
2 2 2 2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(3/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4631P 1.0
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 6 of 42
5 4 3 2 1
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D U4A H_D#[0..63] D
H_D#[0..63] 5
H_DSTBP#0 T40 Y43 H_D#0
5 H_DSTBP#0 CPU_DSTBP0# CPU_D0#
H_DSTBN#0 U40 W42 H_D#1
5 H_DSTBN#0 CPU_DSTBN0# CPU_D1#
H_DINV#0 V41 Y40 H_D#2
5 H_DINV#0 CPU_DBI0# CPU_D2#
W41 H_D#3
H_DSTBP#1 CPU_D3# H_D#4
5 H_DSTBP#1 W39 CPU_DSTBP1# CPU_D4# Y39
H_DSTBN#1 W37 V42 H_D#5
5 H_DSTBN#1 CPU_DSTBN1# CPU_D5#
H_DINV#1 V35 Y41 H_D#6
5 H_DINV#1 CPU_DBI1# CPU_D6#
Y42 H_D#7
H_DSTBP#2 CPU_D7# H_D#8
5 H_DSTBP#2 N37 CPU_DSTBP2# CPU_D8# P42
H_DSTBN#2 L36 U41 H_D#9
5 H_DSTBN#2 CPU_DSTBN2# CPU_D9#
H_DINV#2 N35 R42 H_D#10
5 H_DINV#2 CPU_DBI2# CPU_D10#
T39 H_D#11
H_DSTBP#3 CPU_D11# H_D#12
5 H_DSTBP#3 M39 CPU_DSTBP3# CPU_D12# T42
H_DSTBN#3 M41 T41 H_D#13
5 H_DSTBN#3 CPU_DSTBN3# CPU_D13#
H_DINV#3 J41 R41 H_D#14
5 H_DINV#3 CPU_DBI3# CPU_D14#
T43 H_D#15
4 H_A#[3..35] CPU_D15#
H_A#3 AC34 W35 H_D#16
H_A#4 CPU_A3# CPU_D16# H_D#17
AE38 CPU_A4# CPU_D17# AA37
H_A#5 AE34 W33 H_D#18
H_A#6 CPU_A5# CPU_D18# H_D#19
AC37 CPU_A6# CPU_D19# W34
H_A#7 AE37 AA36 H_D#20
H_A#8 CPU_A7# CPU_D20# H_D#21
AE35 CPU_A8# CPU_D21# AA34
H_A#9 AB35 AA38 H_D#22
H_A#10 CPU_A9# CPU_D22# H_D#23
AF35 CPU_A10# CPU_D23# AA35
H_A#11 AG35 U38 H_D#24
H_A#12 CPU_A11# CPU_D24# H_D#25
AG39 CPU_A12# CPU_D25# U36
H_A#13 AE33 U35 H_D#26
H_A#14 CPU_A13# CPU_D26# H_D#27
AG37 CPU_A14# CPU_D27# U33
H_A#15 AG38 U34 H_D#28
H_A#16 CPU_A15# CPU_D28# H_D#29
AG34 CPU_A16# CPU_D29# W38
H_A#17 AN38 R33 H_D#30
C H_A#18 CPU_A17# CPU_D30# H_D#31 C
AL39 CPU_A18# CPU_D31# U37
CPU_BSEL2 H_A#19 AG33 N34 H_D#32
H_A#20 CPU_A19# CPU_D32# H_D#33
AL33 CPU_A20# CPU_D33# N33
H_A#21 AJ33 R34 H_D#34
CPU_A21# CPU_D34#
1
1K_0402_5%
CPU_A26# CPU_D39#
+VCCP
H_A#27
H_A#28
H_A#29
AL37
AL34
CPU_A27#
CPU_A28#
FSB CPU_D40#
CPU_D41#
L37
L39
H_D#40
H_D#41
H_D#42
AN37 CPU_A29# CPU_D42# L38
H_A#30 AJ34 N36 H_D#43
H_A#31 CPU_A30# CPU_D43# H_D#44
AL38 CPU_A31# CPU_D44# N38
H_A#32 AL35 J39 H_D#45
CPU_A32# CPU_D45#
1
1
1K_0402_5%
1K_0402_5%
1K_0402_5%
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 7 of 42
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DDR_A_DQS#[0..7] DDR_B_DQS#[0..7]
DDR_A_DQS#[0..7] 17,18 DDR_B_DQS#[0..7] 19
DDR_A_DQS[0..7] DDR_B_DQS[0..7]
DDR_A_DQS[0..7] 17,18 DDR_B_DQS[0..7] 19
D U4B U4C D
19 DDR_B_D[0..63]
17,18 DDR_A_D[0..63]
DDR_A_D63 AL8 AL10 DDR_A_DQS7 DDR_B_D63 AT4 AT2 DDR_B_DQS7
DDR_A_D62 MDQ0_63 MDQS0_7_P DDR_A_DQS#7 DDR_B_D62 MDQ1_63 MDQS1_7_P DDR_B_DQS#7
AL9 MDQ0_62 MDQS0_7_N AL11 AT3 MDQ1_62 MDQS1_7_N AT1
DDR_A_D61 AP9 AR8 DDR_A_DQS6 DDR_B_D61 AV2 AY2 DDR_B_DQS6
DDR_A_D60 MDQ0_61 MDQS0_6_P DDR_A_DQS#6 DDR_B_D60 MDQ1_61 MDQS1_6_P DDR_B_DQS#6
AN9 MDQ0_60 MDQS0_6_N AR9 AV3 MDQ1_60 MDQS1_6_N AY1
DDR_A_D59 AL6 AW7 DDR_A_DQS5 DDR_B_D59 AR4 BB6 DDR_B_DQS5
DDR_A_D58 MDQ0_59 MDQS0_5_P DDR_A_DQS#5 DDR_B_D58 MDQ1_59 MDQS1_5_P DDR_B_DQS#5
AL7 MDQ0_58 MDQS0_5_N AW8 AR3 MDQ1_58 MDQS1_5_N BA6
DDR_A_D57 AN6 AP13 DDR_A_DQS4 DDR_B_D57 AU2 BA10 DDR_B_DQS4
DDR_A_D56 MDQ0_57 MDQS0_4_P DDR_A_DQS#4 DDR_B_D56 MDQ1_57 MDQS1_4_P DDR_B_DQS#4
AN7 MDQ0_56 MDQS0_4_N AR13 AU3 MDQ1_56 MDQS1_4_N AY11
DDR_A_D55 AR6 AV25 DDR_A_DQS3 DDR_B_D55 AY4 BB33 DDR_B_DQS3
DDR_A_D54 MDQ0_55 MDQS0_3_P DDR_A_DQS#3 DDR_B_D54 MDQ1_55 MDQS1_3_P DDR_B_DQS#3
AR7 MDQ0_54 MDQS0_3_N AW25 AY3 MDQ1_54 MDQS1_3_N BA33
DDR_A_D53 AV6 AU30 DDR_A_DQS2 DDR_B_D53 BB3 BB37 DDR_B_DQS2
DDR_A_D52 MDQ0_53 MDQS0_2_P DDR_A_DQS#2 DDR_B_D52 MDQ1_53 MDQS1_2_P DDR_B_DQS#2
AW5 MDQ0_52 MDQS0_2_N AU29 BC3 MDQ1_52 MDQS1_2_N BA37
DDR_A_D51 AN10 AT35 DDR_A_DQS1 DDR_B_D51 AW4 BA43 DDR_B_DQS1
DDR_A_D50 MDQ0_51 MDQS0_1_P DDR_A_DQS#1 DDR_B_D50 MDQ1_51 MDQS1_1_P DDR_B_DQS#1
AR5 MDQ0_50 MDQS0_1_N AU35 AW3 MDQ1_50 MDQS1_1_N AY42
DDR_A_D49 AU6 AU39 DDR_A_DQS0 DDR_B_D49 BA3 AT42 DDR_B_DQS0
DDR_A_D48 MDQ0_49 MDQS0_0_P DDR_A_DQS#0 DDR_B_D48 MDQ1_49 MDQS1_0_P DDR_B_DQS#0
AV5 MDQ0_48 MDQS0_0_N AT39 BB2 MDQ1_48 MDQS1_0_N AT43
DDR_A_D47 AU7 DDR_B_D47 BB5
DDR_A_D46 MDQ0_47 MEMORY DDR_B_D46 MDQ1_47 MEMORY
AU8 MDQ0_46 BA5 MDQ1_46
DDR_A_D45 AW9 DDR_B_D45 BA8
DDR_A_D44 MDQ0_45 DDR_B_D44 MDQ1_45
AP11 MDQ0_44 PARTITION 0 BC8 MDQ1_44 PARTITION 1
DDR_A_D43 AW6 DDR_B_D43 BB4
DDR_A_D42 MDQ0_43 DDR_A_RAS# DDR_B_D42 MDQ1_43 DDR_B_RAS#
AY5 MDQ0_42 MRAS0# AV17 DDR_A_RAS# 17,18 BC4 MDQ1_42 MRAS1# AW16 DDR_B_RAS# 19
DDR_A_D41 AU9 AP17 DDR_A_CAS# DDR_B_D41 BA7 BA15 DDR_B_CAS#
MDQ0_41 MCAS0# DDR_A_CAS# 17,18 MDQ1_41 MCAS1# DDR_B_CAS# 19
DDR_A_D40 AV9 AR17 DDR_A_WE# DDR_B_D40 AY8 BA16 DDR_B_WE#
MDQ0_40 MWE0# DDR_A_WE# 17,18 MDQ1_40 MWE1# DDR_B_WE# 19
DDR_A_D39 AU11 DDR_B_D39 BA9
MDQ0_39 DDR_A_BS[0..2] 17,18 MDQ1_39 DDR_B_BS[0..2] 19
DDR_A_D38 AV11 DDR_B_D38 BB10
DDR_A_D37 MDQ0_38 DDR_A_BS2 DDR_B_D37 MDQ1_38 DDR_B_BS2
AV13 MDQ0_37 MBA0_2 AP23 BB12 MDQ1_37 MBA1_2 BB29
C DDR_A_D36 DDR_A_BS1 DDR_B_D36 DDR_B_BS1 C
AW13 MDQ0_36 MBA0_1 AP19 AW12 MDQ1_36 MBA1_1 BB18
DDR_A_D35 AR11 AW17 DDR_A_BS0 DDR_B_D35 BB8 BB17 DDR_B_BS0
DDR_A_D34 MDQ0_35 MBA0_0 DDR_B_D34 MDQ1_35 MBA1_0
AT11 MDQ0_34 BB9 MDQ1_34
DDR_A_D33 AR14 DDR_B_D33 AY12
MDQ0_33 DDR_A_MA[0..14] 17,18 MDQ1_33 DDR_B_MA[0..14] 19
DDR_A_D32 AU13 DDR_B_D32 BA12
DDR_A_D31 MDQ0_32 DDR_A_MA14 DDR_B_D31 MDQ1_32 DDR_B_MA14
AR26 MDQ0_31 MA0_14 AR23 BC32 MDQ1_31 MA1_14 BA29
DDR_A_D30 AU25 AU15 DDR_A_MA13 DDR_B_D30 AW32 BA14 DDR_B_MA13
DDR_A_D29 MDQ0_30 MA0_13 DDR_A_MA12 DDR_B_D29 MDQ1_30 MA1_13 DDR_B_MA12
AT27 MDQ0_29 MA0_12 AN23 BA35 MDQ1_29 MA1_12 AW28
DDR_A_D28 AU27 AW21 DDR_A_MA11 DDR_B_D28 AY36 BC28 DDR_B_MA11
DDR_A_D27 MDQ0_28 MA0_11 DDR_A_MA10 DDR_B_D27 MDQ1_28 MA1_11 DDR_B_MA10
AP25 MDQ0_27 MA0_10 AN19 BA32 MDQ1_27 MA1_10 BA17
DDR_A_D26 AR25 AV21 DDR_A_MA9 DDR_B_D26 BB32 BB28 DDR_B_MA9
DDR_A_D25 MDQ0_26 MA0_9 DDR_A_MA8 DDR_B_D25 MDQ1_26 MA1_9 DDR_B_MA8
AP27 MDQ0_25 MA0_8 AR22 BA34 MDQ1_25 MA1_8 AY28
DDR_A_D24 AR27 AU21 DDR_A_MA7 DDR_B_D24 AY35 BA28 DDR_B_MA7
DDR_A_D23 MDQ0_24 MA0_7 DDR_A_MA6 DDR_B_D23 MDQ1_24 MA1_7 DDR_B_MA6
AP29 MDQ0_23 MA0_6 AP21 BC36 MDQ1_23 MA1_6 AY27
DDR_A_D22 AR29 AR21 DDR_A_MA5 DDR_B_D22 AW36 BA27 DDR_B_MA5
DDR_A_D21 MDQ0_22 MA0_5 DDR_A_MA4 DDR_B_D21 MDQ1_22 MA1_5 DDR_B_MA4
AP31 MDQ0_21 MA0_4 AN21 BA39 MDQ1_21 MA1_4 BA26
DDR_A_D20 AR31 AV19 DDR_A_MA3 DDR_B_D20 AY40 BB26 DDR_B_MA3
DDR_A_D19 MDQ0_20 MA0_3 DDR_A_MA2 DDR_B_D19 MDQ1_20 MA1_3 DDR_B_MA2
AV27 MDQ0_19 MA0_2 AU19 BA36 MDQ1_19 MA1_2 BA25
DDR_A_D18 AN29 AT19 DDR_A_MA1 DDR_B_D18 BB36 BB25 DDR_B_MA1
DDR_A_D17 MDQ0_18 MA0_1 DDR_A_MA0 DDR_B_D17 MDQ1_18 MA1_1 DDR_B_MA0
AV29 MDQ0_17 MA0_0 AR19 BA38 MDQ1_17 MA1_0 BA18
DDR_A_D16 AN31 DDR_B_D16 AY39
DDR_A_D15 MDQ0_16 DDR_B_D15 MDQ1_16
AU31 MDQ0_15 BB40 MDQ1_15
DDR_A_D14 AR33 DDR_B_D14 AW40
DDR_A_D13 MDQ0_14 DDR_B_D13 MDQ1_14
AV37 MDQ0_13 T30 AV42 MDQ1_13
DDR_A_D12 AW37 DDR_B_D12 AV41
MDQ0_12 MDQ1_12
1
75_0402_1%
DDR_A_D11 AT31 DDR_B_D11 BA40
DDR_A_D10 MDQ0_11 R40 DDR_B_D10 MDQ1_11
AV31 MDQ0_10 MCLK0A_2_P AW33 BC40 MDQ1_10 MCLK1A_2_P BA42
DDR_A_D9 AT37 AV33 DDR_B_D9 AW42 BB42
DDR_A_D8 MDQ0_9 MCLK0A_2_N DDR_B_D8 MDQ1_9 MCLK1A_2_N
AU37 MDQ0_8 AW41 MDQ1_8
DDR_A_D7 AW39 BA24 M_CLK_DDR1 DDR_B_D7 AT40 BB22 M_CLK_DDR3
M_CLK_DDR3 19
2
MEMORY CONTROL 1A
B DDR_A_D4 MDQ0_5 M_CLK_DDR0 DDR_B_D4 MDQ1_5 M_CLK_DDR2 B
AR38 MDQ0_4 MCLK0A_0_P BB20 M_CLK_DDR0 17,18 AN40 MDQ1_4 MCLK1A_0_P BA19 M_CLK_DDR2 19
DDR_A_D3 AV38 BC20 M_CLK_DDR#0 DDR_B_D3 AU40 AY19 M_CLK_DDR#2
MDQ0_3 MCLK0A_0_N M_CLK_DDR#0 17,18 MDQ1_3 MCLK1A_0_N M_CLK_DDR#2 19
DDR_A_D2 AW38 DDR_B_D2 AU41
DDR_A_D1 MDQ0_2 DDR_B_D1 MDQ1_2
AR35 MDQ0_1 AR41 MDQ1_1
DDR_A_D0 AP35 AT15 DDR_CS1_DIMMA# DDR_B_D0 AP42 BB14 DDR_CS3_DIMMB#
MDQ0_0 MCS0A_1# T34 MDQ1_0 MCS1A_1# DDR_CS3_DIMMB# 19
17,18 DDR_A_DM[0..7] AR18 DDR_CS0_DIMMA# 19 DDR_B_DM[0..7] BB16 DDR_CS2_DIMMB#
MCS0A_0# DDR_CS0_DIMMA# 17,18 MCS1A_0# DDR_CS2_DIMMB# 19
DDR_A_DM7 AN5 DDR_B_DM7 AT5
DDR_A_DM6 MDQM0_7 M_ODT1 DDR_B_DM6 MDQM1_7 M_ODT3_DIMMB
AU5 MDQM0_6 MODT0A_1 AP15 T35 BA2 MDQM1_6 MODT1A_1 BB13 M_ODT3_DIMMB 19
DDR_A_DM5 AR10 AV15 M_ODT0 DDR_B_DM5 AY7 AY15 M_ODT2_DIMMB
MDQM0_5 MODT0A_0 M_ODT0 17,18 MDQM1_5 MODT1A_0 M_ODT2_DIMMB 19
DDR_A_DM4 AN13 DDR_B_DM4 BA11
DDR_A_DM3 MDQM0_4 DDR_B_DM3 MDQM1_4
AN27 MDQM0_3 BB34 MDQM1_3
DDR_A_DM2 AW29 AU23 DDR_CKE1_DIMMA DDR_B_DM2 BB38 AY31 DDR_CKE3_DIMMB
MDQM0_2 MCKE0A_1 T36 MDQM1_2 MCKE1A_1 DDR_CKE3_DIMMB 19
DDR_A_DM1 AV35 AT23 DDR_CKE0_DIMMA DDR_B_DM1 AY43 BB30 DDR_CKE2_DIMMB
MDQM0_1 MCKE0A_0 DDR_CKE0_DIMMA 17,18 MDQM1_1 MCKE1A_0 DDR_CKE2_DIMMB 19
DDR_A_DM0 AR34 DDR_B_DM0 AR42
MDQM0_0 MDQM1_0
A A
Security Classification
2009/02/19
Compal Secret Data
2009/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP79(2/10)-MEM PARTS 0 & 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4631P 1.0
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 8 of 42
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U4D
D D
MEMORY CONTROL 0B
MEMORY CONTROL 1B
BA21 MCLK0B_0_P MCLK1B_0_P BA20
BB21 MCLK0B_0_N MCLK1B_0_N AY20
AH27
197 mA
+V_PLL_MCLK
+V_DLL_DLCELL_AVDD AG27
+V_PLL_FSB AG28
R537
MRESET0# 2 DDR_RST#
C 8mil MRESET0# AY32 1
0_0402_5%
DDR_RST# 17,18,19 C
2 R34 1 40.2_0402_1% MEM_COMP_VDD AN41 +1.5V
MEM_COMP_VDD
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
10U_0805_10V4Z
AG24 AR16 C29 C30 C31 C32 C33 C34
GND16 +VDD_MEM18
AH35 GND17 +VDD_MEM19 AR20
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
AK7 GND18 +VDD_MEM20 AR24
2 1 1 1
AM28 GND19 +VDD_MEM21 AW15
AT25 GND20 +VDD_MEM22 AP22
AP30 GND21 +VDD_MEM23 AP18
AR36 GND22 +VDD_MEM24 AU16
AU10 GND23 +VDD_MEM25 AN18
F28 GND24 +VDD_MEM26 AU24
BC21 GND25 +VDD_MEM27 AT21
AY9 AY29 +1.5V
GND26 +VDD_MEM28
BC9 GND27 +VDD_MEM29 AV24
B B
D34 GND28 +VDD_MEM30 AU20
F24 GND29 +VDD_MEM31 AU22
G32 GND30 +VDD_MEM32 AW27
H31 GND31 +VDD_MEM33 BC17
K7 GND32 +VDD_MEM34 AV20 2 2 2 2 2 2 2 2
M38 AY17 C35 C36 C37 C38 C39 C40 C41 C349
GND33 +VDD_MEM35
M5 GND34 +VDD_MEM36 AY18
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
M6 GND35 +VDD_MEM37 AM15
1 1 1 1 1 1 1 1
M7 GND36 +VDD_MEM38 AU18
M9 GND37 +VDD_MEM39 AY25
N39 GND38 +VDD_MEM40 AY26
N8 GND39 +VDD_MEM41 AW19
P33 GND40 +VDD_MEM42 AW24
P34 GND41 +VDD_MEM43 BC25
P37 GND42 +VDD_MEM44 AL30
P4 GND43 +VDD_MEM45 AM31
P40 GND44
P7 GND45 GND55 T33
R36 GND46 GND56 T34
R40 GND47 GND57 T35
R43 GND48 GND58 T37
R5 GND49 GND59 T38
T18 GND50 GND60 T7
T20 GND51 GND61 T9
AK11 GND52 GND62 U18
T24 GND53 GND63 U20
T26 GND54 GND64 U22
A A
Security Classification
2009/02/19
Compal Secret Data
2009/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP79(3/10)-MEM CNTL 0B&1B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4631P 1.0
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 9 of 42
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U4E
F7 PE0_RX0_P PE0_TX0_P C5
E7 PE0_RX0_N PE0_TX0_N D4
D D
D7 PE0_RX1_P PE0_TX1_P C4
C7 PE0_RX1_N PE0_TX1_N B4
E6 PE0_RX2_P PE0_TX2_P A4
F6 PE0_RX2_N PE0_TX2_N A3
E5 PE0_RX3_P PE0_TX3_P B3
F5 PE0_RX3_N PE0_TX3_N B2
E4 PE0_RX4_P PE0_TX4_P C1
E3 PE0_RX4_N PE0_TX4_N D1
C3 PE0_RX5_P PE0_TX5_P D2
D3 PE0_RX5_N PE0_TX5_N E1
G5 PE0_RX6_P PE0_TX6_P E2
H5 F2
J7
J6
PE0_RX6_N
PE0_RX7_P PCIE PE0_TX6_N
PE0_TX7_P F3
F4
MCP79_PCIE_RST# 1 R35 2
0_0402_5%
PCIE_RST# 22,23,24,26
PE0_RX7_N PE0_TX7_N
J5 PE0_RX8_P PE0_TX8_P G3 2
J4 H4 C43
PE0_RX8_N PE0_TX8_N 0.1U_0402_16V7K
L11 PE0_RX9_P PE0_TX9_P H3
L10 H2 @
PE0_RX9_N PE0_TX9_N 1
L9 PE0_RX10_P PE0_TX10_P H1
L8 PE0_RX10_N PE0_TX10_N J1
L7 PE0_RX11_P PE0_TX11_P J2
L6 PE0_RX11_N PE0_TX11_N J3
N11 PE0_RX12_P PE0_TX12_P K2
N10 PE0_RX12_N PE0_TX12_N K3
N9 PE0_RX13_P PE0_TX13_P L4
P9 PE0_RX13_N PE0_TX13_N L3
N7 PE0_RX14_P PE0_TX14_P M4
N6 PE0_RX14_N PE0_TX14_N M3
N5 PE0_RX15_P PE0_TX15_P M2
N4 PE0_RX15_N PE0_TX15_N M1
T17 Y12
+VCCP R52 1 2 0_0402_5% 430 mA +DVDD_PEX W19
+DVDD0_PEX1
+DVDD0_PEX2
+AVDD0_PEX1
+AVDD0_PEX2 AA12
U17 +DVDD0_PEX3 +AVDD0_PEX3 AB12
2 2 2 1 1 V19 +DVDD0_PEX4 +AVDD0_PEX4 M12
1.1VS C54 C55 C56 C57 C58 W16 P12
+DVDD0_PEX5 +AVDD0_PEX5
W17 +DVDD0_PEX6 +AVDD0_PEX6 R12
2.2U_0402_6.3VM
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
M13
L3 1 2 10NH_LQG15HS10NJ02D_5%_0402~D +V_PLL_PEX 161 mA T16
+AVDD1_PEX1
N13
L11
+VCCP +V_PLL_PEX +AVDD1_PEX2
+AVDD1_PEX3 P13 +AVDD_PEX 1.2A 1 2 +VCCP
C66 2 C67 PE_COMP A11 2 2 1 1 2 1 BLM21PG221SN1D_0805~D
PEX_CLK_COMP C59 C60 C61 C62 C63 C64
1.1VS
1
4.7U_0603_6.3V6K
2.2U_0402_6.3VM
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2.2U_0402_6.3VM
10U_0805_10V4Z
R53 MCP79MX-B2 PBGA 1437P 1.1VS
1 2.37K_0402_1% 1 1 2 2 1 2
@
2
A A
Security Classification
2009/02/19
Compal Secret Data
2009/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP79(4/10)-PCI EXPRESS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4631P 1.0
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 10 of 42
5 4 3 2 1
5 4 3 2 1
2
MCP79_AUX- @
MCP79_AUX+ R1301 R1302 +1.05VALW
1
0_0603_1% 0_0603_1%
2
2
R1306
@ R54 @R55 0_0603_1%
1
1K_0402_5% 1K_0402_5%
+3.3VALW_MAC_R 2.2U
264 mA
2
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
U4F R57 0_0603_1%
1 264 mA +1.05VALW_MAC_R
1
1
C69 C70 1 2
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
+3.3V_DUAL_RMGT1 J24 1
D K24 C71 C72 @ D
+3.3V_DUAL_RMGT2 2
1.1VALW_MAC
RXD0 C23
RXD1 RGMII_RXD0 2
B23 RGMII_RXD1 +V_DUAL_RMGT1 U23
RXD2 E24 V23
+1.05VALW_MAC RXD3 RGMII_RXD2 +V_DUAL_RMGT2
A24 RGMII_RXD3
RXCLK A23 RGMII_RXC/MII_RXCLK LAN MII_VREF E28 +3.3VALW_MAC_REF
BLM18AG121SN1D_0603
1
47K_0402_5% B24
RGMII_TXD0 R63
1 2 F23 MII_RXER/GPIO_36 RGMII_TXD1 C24
B26 MII_COL/GPIO_20/MSMB_DATA RGMII_TXD2 C25 10K_0402_5%
L4 R61 B22 D25
MII_CRS/GPIO_21/MSMB_CLK RGMII_TXD3 TXCLK_R R67 10K_0402_5%
D24 1 2
2
RGMII_TXC/MII_TXCLK
C26
2
RGMII_INT RGMII_TXCTL/MII_TXEN
J22 RGMII_INTR/GPIO_35
9 mA +V_DUAL_MACPLL T23
RGMII_MDC D21
C21 R1262 1 2 10K_0402_5%
+V_DUAL_MACPLL RGMII_MDIO
1
C75 C76 +3.3VALW_MAC R69 1 2 +MII_COMP_VDD C27 G23
MII_COMP_VDD RGMII_PWRDWN/GPIO_37
4.7U_0603_6.3V6K
49.9_0402_1%
2.2U_0402_6.3VM
MII_RESET# J23
1
2.7K_0402_5%
2.7K_0402_5%
E36 B31 LCD_DDC_CLK LCD_DDC_CLK 20 R163 R186
TV_DAC_RSET DDC_CLK0 LCD_DDC_DATA
A35 TV_DAC_VREF DDC_DATA0 A31 LCD_DDC_DATA 20
+1.05VS_PLL PHY_25MHZ
66 mA B39
DACS
2
+1.05VS_PLL RGB_DAC_RED
T28 +V_VPLL RGB_DAC_GREEN A39
0.1U_0402_16V4Z
U27 B40 @ 1 LCD_DDC_CLK
+V_PLL_CORE RGB_DAC_BLUE C309 LCD_DDC_DATA
RGB_DAC_HSYNC A40
RGB_DAC_VSYNC A41
C38 XTALIN_TV 2 1.1VS
C D38 XTALOUT_TV C
TV_DAC_RED A36
TV_DAC_GREEN B36
TI_PRIORITY E16 C36 +1.05VS_PLL
21 TI_PRIORITY GPIO_6/FERR/IGPU_GPIO_6# TV_DAC_BLUE +VCCP
MCP_DP_CBL_DET B15 D36
21 MCP_DP_CBL_DET GPIO_7/NFERR/IGPU_GPIO_7# TV_DAC_HSYNC/GPIO_44
TV_DAC_VSYNC/GPIO_45 C37
MCP79_ENVDD MCP79_LCD_PWM G39
20 MCP79_LCD_PWM LCD_BKL_CTL/GPIO_57
MCP79_ENBKL E37
28 MCP79_ENBKL LCD_BKL_ON/GPIO_59
MCP79_ENVDD F40 L13
20,28 MCP79_ENVDD LCD_PANEL_PWR/GPIO_58
1
R1279 1 2
22K_0402_5%
2.2U_0402_6.3VM
4.7U_0603_6.3V6K
MCP79_DP3- E35
21 MCP79_DP3- HDMI_TXC_N/ML0_LANE3_N
MCP79_DP2+ G35 B35 LVDSAC+ 1
21 MCP79_DP2+ LVDSAC+ 20
2
+1.8VS
FLAT IFPA_TXD2_N
IFPA_TXD3_P
C33
B34
LVDSA2-
LVDSA2- 20
1 2
PANEL IFPB_TXC_P
IFPB_TXC_N K31 LVDSBC-
LVDSBC+ 20
LVDSBC- 20 Signal : TXD0_R
C83 @ 10U_0805_10V4Z LVDSB0+ Strap: Networking select
1 R80 2 0_0603_1%
190 mA +1.8VS_IFP IFPB_TXD4_P J29
H29 LVDSB0-
LVDSB0+ 20
Strapped Value : 0: MII 1: RGMII
IFPB_TXD4_N LVDSB0- 20
2.2U 1 2 L29 LVDSB1+
IFPB_TXD5_P LVDSB1+ 20 Description : Selects an MII interface or an RGMII interface for MAC.
2.2U_0402_6.3VM C84 K29 LVDSB1-
+3VS IFPB_TXD5_N LVDSB1- 20
2 1 L30 LVDSB2+
IFPB_TXD6_P LVDSB2+ 20
R81 0.1U_0402_16V4Z C85 LVDSB2-
16 mA 1 2 0_0603_1% +3VS_PLL_HDMI
M27
M26
+VDD_IFPA IFPB_TXD6_N K30
N30
LVDSB2- 20
+VDD_IFPB IFPB_TXD7_P
IFPB_TXD7_N M30
B 4.7U_0603_6.3V6K C86 M28 B
+VCCP +V_PLL_IFPAB SCL_DP_MCP
1.1VS 2 1 M29 +V_PLL_HDMI DDC_CLK2/GPIO_23 C30 SCL_DP_MCP 21
0.1U_0402_16V4Z
2 1 C87 B30 SDA_DP_MCP +3VALW
DDC_DATA2/GPIO_24 SDA_DP_MCP 21
0.1U_0402_16V4Z C448 1.1VALW_MAC
95 mA T25 D31 SCL_HDMI_MCP
+VDD_HDMI DDC_CLK3 SCL_HDMI_MCP 21
1 1 E31 SDA_HDMI_MCP
DDC_DATA3 SDA_HDMI_MCP 21 +1.05VALW
C88 C89 1K_0402_1% 1 R82 2 HDMI_RSET J31
HDMI_VPROBE HDMI_RSET IFPAB_RSET @ R83
2 1 J30 HDMI_VPROBE IFPAB_RSET E32 1 2 1K_0402_1%
1
2.2U_0402_6.3VM
2.2U_0402_6.3VM
2
AO3416_SOT23
1
D
1 2 2 Q67 +1.05VALW_MAC
14 SLP_RMGT#
1 @ G
R1308 C656 S
3
0_0402_5%
0.01U_0402_25V7K
+1.05VALW_MAC1
2 C657
2 @ 1 20 mil 0.1U_0402_16V4Z
28 SLP_MCP79_MAC#
R1311
0_0402_5% 2
+3VALW +3VALW
RGMII_INT
RXCTL
1
RXCLK
RXD3 R1309 20 mil
RXD2 10K_0402_5%
RXD1
RXD0 R1310 Q68
3
S
0_0402_5%
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
G
1 2 2 AO3413_SOT23
0.01U_0402_25V7K
A A
1
D @ 1 D
1
R1263
R1264
R1265
R1266
R1267
R1268
R1269
2 Q69 C658
G 2N7002_SOT23 +3.3VALW_MAC
2
3
2
20 mil
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP79(5/10)-LAN,RGB,TV,LVD
Www.alliancelaptoptraining.com
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4631P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 11 of 42
5 4 3 2 1
5 4 3 2 1
Www.alliancelaptoptraining.com +3VS
GPIO 39 41 53
R192 2
2
8.2K_0402_5% 8.2K_0402_5%
8.2K_0402_5% 8.2K_0402_5%
8.2K_0402_5% 8.2K_0402_5%
X76L02@
R191
X76L01@
R193
@
1 0 0
Hynix 1G
(R192) (R194) (R196)
1
0 1 0
R194 2
R195 2
R196 2
X76L01@
X76L01@X76L02@
Samsung 1G
X76L02@
D D
U4G (R195) (R191) (R196)
1 R94 2 8.2K_0402_5% PCI_REQ#0 T2 R3
+3VS
1
R95 8.2K_0402_5% PCI_REQ#1 PCI_REQ0# PCI_GNT0#
1 2 V9 PCI_REQ1/FANRPM2# PCI_GNT1/FANCTL2# U10
1 R92 2 8.2K_0402_5% PCI_REQ#2 T3 R4
R98 8.2K_0402_5% HB_PWR_EN PCI_REQ2#/GPIO_40/RS232_DSR# PCI_GNT2#/GPIO_41/RS232_DTR#
1 2 U9 PCI_REQ3#/GPIO_38/RS232_CTS# PCI_GNT3#/GPIO_39/RS232_RTS# U11
1 R97 2 8.2K_0402_5% PCI_REQ#4 T4 P3
PCI_REQ4#/GPIO_52/RS232_SIN# PCI_GNT4#/GPIO_53/RS232_SOUT#
10P_0402_50V8J
U2 C95
PCI_AD26
U5 PCI_AD27
U1 @
PCI_AD28 2
U6 PCI_AD29
T5 PCI_AD30
U7 PCI_AD31
1 R99 2 8.2K_0402_5% PCI_PIRQE# P2 AD4 R_LPC_FRAME# 1 R101 2 LPC_FRAME#
+3VS PCI_INTW# LPC_FRAME# LPC_FRAME# 24,28
1 R124 2 8.2K_0402_5% PCI_PIRQF# N3 AE12 22_0402_5%
R138 8.2K_0402_5% PCI_PIRQG# PCI_INTX# LPC_PWRDWN#/GPIO_54/EXT_NMI#
1 2 N2 PCI_INTY#
1 R140 2 8.2K_0402_5% PCI_PIRQH# N1 AE5 R104 1 2
PCI_INTZ# LPC_RESET0# PLT_RST# 24,28
1
33_0402_5%
1 R147 2 8.2K_0402_5% PCI_TRDY# Y3 PCI_TRDY# LPC LPC_AD0 AD3 R_LPC_AD0
R_LPC_AD1
R105
R107
1 2 22_0402_5%
22_0402_5%
LPC_AD0 24,28
R106
10K_0402_5%
AD11 PCI_CLKRUN/GPIO_42# LPC_AD1 AD2 1 2 LPC_AD1 24,28
AD1 R_LPC_AD2 R108 1 2 22_0402_5%
LPC_AD2 24,28
2
LPC_AD2 R_LPC_AD3 R109 22_0402_5%
AE2 LPC_DRQ1/GPIO_19# LPC_AD3 AD5 1 2 LPC_AD3 24,28
AE1 LPC_DRQ0#
SERIRQ AE6 AE9 LPC_CLK0_R 1 R110 2 LPC_CLK0
28 SERIRQ LPC_SERIRQ LPC_CLK0 LPC_CLK0 24,28
22_0402_5%
A A
Security Classification
2009/02/19
Compal Secret Data
2009/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP79(6/10)-PCI & LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4631P 1.0
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 12 of 42
5 4 3 2 1
5 4 3 2 1
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U4H
2
AM1 L21 USB_OC#0
SATA_C0_TX_N USB_OC0/GPIO_25# USB_OC#0 27
K21 USB_OC#1
USB_OC1/GPIO_26# USB_OC#1 29
AM2 J21 USB_OC#2 L7
SATA_C0_RX_N USB_OC2/GPIO_27/MGPIO# USB_OC#2 29
1
1
10NH_LQG15HS10NJ02D_5%_0402~D L28 +V_PLL_USB
+V_PLL_USB
4.7U_0603_6.3V6K
81 mA 2.2U 2 2
2
2.2U_0402_6.3VM
+V_PLL_SATA AP2
C100 SATA_C1_TX_N
0.1U_0402_16V7K
G26
2
C101 AN3 SATA_C1_RX_N
+3.3V_DUAL_USB1
+3.3V_DUAL_USB2 H27 200 mA 1 1
4.7U_0603_6.3V6K
2.2U_0402_6.3VM
4.7U_0603_6.3V6K
GND131 AD35 2
R115 E12 AD37 R116 C104 C105
0_0603_1% SATA_LED# GND132 806_0402_1%
GND133 AD38
2.2U_0402_6.3VM
GND134 AE22
1
AE16 AE24
1
B +V_PLL_SATA GND135 B
AE39
53 mA +DVDD_SATA AF19 +DVDD0_SATA1
GND136
GND137 AE4
1.1VS AG16 +DVDD0_SATA2 GND138 AD6
2 2 AG17 +DVDD0_SATA3 GND139 AF16
+VCCP C106 C107 AG19 +DVDD0_SATA4 GND140 AF17
2.2U_0402_6.3VM
GND141 AF18
0.1U_0402_16V7K
1 1
AH19 +DVDD1_SATA2 GND143 AF22
L9 AF26
GND144
AJ12 +AVDD0_SATA1 GND145 AF27
BLM18AG121SN1D_0603 AN11 AF28
+AVDD0_SATA2 GND146
AK12 +AVDD0_SATA3 GND147 AF33
AK13 AF34
1
+AVDD0_SATA4 GND148
AL12 AF37
136 mA
+AVDD_SATA AM11
+AVDD0_SATA5
+AVDD0_SATA6
GND149
GND150 AF40
1 2 2 2 2 AM12 +AVDD0_SATA7 GND151 AG18
10U_0805_10V4Z
0.1U_0402_16V7K
0.1U_0402_16V7K
GND154 AG26
2 1 1 1 1
AN14 +AVDD1_SATA1 GND155 AG36
AL14 +AVDD1_SATA2 GND156 AG40
AM13 +AVDD1_SATA3 GND157 AH18
AM14 +AVDD1_SATA4 GND158 AH20
GND159 AH22
SATA_TERMP AE3 AH24
SATA_TERMP GND160
MCP79MX-B2 PBGA 1437P
1
R117
2.49K_0402_1%
2
A A
Security Classification
2009/02/19
Compal Secret Data
2009/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP79(7/10)-SATA & USB
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4631P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 13 of 42
5 4 3 2 1
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5 4 3 2 1
+3VS +3VS
Www.alliancelaptoptraining.com@
R118
10K_0402_5%
7
U8 @
VDD CLKIN
@ R197
1 EMI_HD_IN_D 2
0_0402_5%
1EMI_HD_IN
R119
HDA_BITCLK 6 2 @ 10K_0402_5%
CLKOUT NC
1
@ 5 8
C112 SSON NC
For Audio code use
0.1U_0402_16V4Z 4 3
2 GND SS
ASM3P623S00BF-08TR_TSSOP8
@ +3VALW
R122
10K_0402_5%
20 mA
0.1U_0402_16V7K
0.1U_0402_16V7K
2 2
D C455 C113 C114 D
4.7U_0603_6.3V6K
U4I 1 1
10P_0402_50V8J
10P_0402_50V8J
2 1 J15 C1181 C1191 R126 22_0402_5%
HDA_SDATA_IN2/GPIO_3/PS2_KB_DATA
1
+3VALW
10K_0402_5%
10P_0402_50V8J @ C117 R127
E15 EMI_HD_IN 2 1 R128
HDA_BITCLK
1
+VCCP +3VALW
10K_0402_5%
0_0402_5%
HDA 2 2 R129
2
1
R130
L10 R131
2
49.9_0402_1% K15 HDA_RESET# 1 2
HDA_RESET# ACZ_RST# 25
10NH_LQG15HS10NJ02D_5%_0402~D 22_0402_5%
2
H DA_SYNC 1R132
92 mA A15 HDA_PULLDN_COMP HDA_SYNC L15
K17
2
22_0402_5%
ACZ_SYNC 25
2
HDA_DOCK_EN/GPIO_4/PS2_MS_CLK#
1
+1.05VS_PLL
10P_0402_50V8J
+V_PLL_NV L17 @ 1 R133 1
HDA_DOCK_RST/GPIO_5/PS2_MS_DATA#
22K_0402_5%
C120 @
0.1U_0402_10V6K
0.1U_0402_10V6K
4.7U_0603_6.3V6K
2.2U_0402_6.3VM
2.2U_0402_6.3VM
1 1 2 2 C121
C82 C81 C123 C124 C125 10P_0402_50V8J
2 2
2
AE18 +V_PLL_NV_H
2 2 1 1
T27 +V_PLL_XREF_XS
AE17 +V_PLL_SP_SPREF
SLP_S3# G17 PM_SLP_S3# 28
J17 +3VS
SLP_RMGT# SLP_RMGT# 11
SLP_S5# H17 PM_SLP_S5# 28
PLACE 0.1UF NEAR AE18 and AE17 BALL
1
R134 R135 R136
1
L24 GPIO_1/PWRDN_OK/SPI_CS1
22K_0402_5%
22K_0402_5%
22K_0402_5%
C @ @ @ R137 C
10K_0402_5%
@
2
B11
2
THERM_DIODE_P MCP_SPKR
L26 GPIO_12/SUS_STAT/ACCLMTR_EXT_TRIG# THERM_DIODE_N C11
1
EC_GA20 +3VALW +3VS +3VALW
28 EC_GA20 K13 A20GATE
EC_KBRST# L13 R139
28 EC_KBRST# KBRDRSTIN#
C19 L20 10K_0402_5%
28 EC_SCI# SIO_PME# MCP_VID0/GPIO_13 MCP_CORE_VID0 36
28 EC_SMI# C18 EXT_SMI/GPIO_32# MCP_VID1/GPIO_14 M20 MCP_CORE_VID1 36
1
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.7K_0402_5%
M21 MCP_CORE_VID2 36
2
INTRUDER# MCP_VID2/GPIO_15 R142 R143 R144 R145 R146
+RTCVCC 1 2 B20 INTRUDER#
R141 49.9K_0402_1%
C13 MCP_SPKR
SPKR MCP_SPKR 25
28 LID_SW# M25 HD Audio Codec
2
LID#
M24
R149 0_0402_5%
LLB#
MISC SMB_CLK0 L19
K19
MCP_SMB_CLK
MCP_SMB_DATA
MCP_SMB_CLK 24
SMB_DATA0 MCP_SMB_DATA 24
1 2 M22 G21 MEM_SMBCLK
38 DPRSLPVR CPU_DPRSLPVR SMB_CLK1/MSMB_CLK MEM_SMBCLK 18,19
F21 MEM_SMBDATA
SMB_DATA1/MSMB_DATA MEM_SMBDATA 18,19
PWRBTN# C16 M23 SMB_ALERT#
28 PWRBTN# PWRBTN# SMB_ALERT/GPIO_64#
+3VALW R151 2 @ 1 10K_0402_5% D16
R152 RSTBTN# +3VALW +3VALW
FANRPM0/GPIO_60 B12
+RTCVCC 1 2 RTC_RST# C20 A12
49.9K_0402_1% RTC_RST# FANCTL0/GPIO_61 EC_LID_OUT#
FANRPM1/GPIO_63 D12 EC_LID_OUT# 28
3
10K_0402_5%
Close to RAM door D20 C12 R153 +3VALW @
28 EC_RSMRST# PWRGD_SB FANCTL1/GPIO_62
E20 @10K_0402_5% R154 R155 D3
28 MCP_PWRGD PS_PWRGD
JCMOS1 @ D17 2 R156 1VR_ON 332K_0402_1% PJDLC05_SOT23
CPUVDD_EN VR_ON 28,38
1 2 0_0402_5% ENABLE +1.05V POWER @
C17 R_ACIN 2 1
28,38 VGATE
2
NO SHORT PAD CPU_VLD SDMK0340L-7-F D4 ACIN 28,32,33
C14
1
SPI_CS0/GPIO_10
SPI_CLK/GPIO_11 D13
T25 PAD E19 JTAG_TDI SPI_DI/GPIO_8 C15
C126 @ T16 PAD F19 B14
JTAG_TDO SPI_DO/GPIO_9
1 2 T28 PAD J19 JTAG_TMS
1
10K_0402_5%
10K_0402_5%
R159 2 1 10K_0402_5% J18
1U_0402_6.3V4Z R160 2 JTAG_TRST#
1 10K_0402_5% G19 JTAG_TCK
@ R161 R162
B B
SUS_CLK_R 2 R296
B18 1 T32 PAD EC
2
SUS_CLK/GPIO_34 0_0402_5%
XTALIN A16
XTALOUT XTALIN
1 2 XTALOUT_R B16 XTALOUT BUF_SIO_CLK AE7 T33 PAD
X1 R534 0_0402_5%~D
1 2 C127
1 1 2 XTALIN_RTC A19
25MHZ 12PF 30PPM XTAOUT_RTC_R XTALIN_RTC
1 15P_0402_50V8J B19 XTALOUT_RTC TEST_MODE_EN K22
C128 L22
X2 PKG_TEST
10P_0402_50V8J
10P_0402_50V8J C129
2
2 NC IN 1
1
2 MCP79MX-B2 PBGA 1437P
3 NC R164
OUT 4 R549 A20GATE,KBRDRSTIN*, RI* & EXTSMI* 1K_0402_1% +3VALW
32.768KHZ 1TJS125BJ4A421P 0_0402_5%~D HAVE INTERNAL PULLUPS
2 1XTAOUT_RTC 1 2
2
12P_0402_50V8J
10K_0402_5%
C130 @ C131
@ R165 1 2 0.1U_0402_16V4Z
EC_GA20 EC_KBRST#
SPKR
1 1 U9
0 = User Mode Boot Init table
2
@ @ 8 1
C454 C453 1 = Safe Mode Boot Init table VCC A0
7 WP A1 2
Suggest use user mode. MCP_SMB_CLK 6 3
220P_0402_50V7K 2 220P_0402_50V7K 2 MCP_SMB_DATA SCL A2
5 SDA GND 4
@ AT24C16AN-10SI-2.7_SO8
10K_0402_5%
@ R166
2
HDCP 2-WIRE ROM
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP79(8/10)-HDA & MISC
Www.alliancelaptoptraining.com
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4631P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 14 of 42
5 4 3 2 1
5 4 3 2 1
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0.75V ~ 1.05 V
+1.0VS
330U_D2E_2.5VM_R9
1 1 1 1
C132 C133 C134
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
C135 +
2 2 2
2
D U4J D
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
10U_0805_10V4Z
1 1 1 1 2 AC23 +VDD_CORE2 +VTT_CPU2 AC32
C136 C137 C138 C139 C140 C141 C142 U25 E40 2 2 2 2 2 1 1 1
+VDD_CORE3 +VTT_CPU3 C143 C144 C145 C146 C147 C148 C149 C150 C151
AH12 +VDD_CORE4 +VTT_CPU4 J36
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V7K
AG10 +VDD_CORE5 +VTT_CPU5 N32
2 2 2 2 1
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
4.7U_0603_6.3V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
10U_0805_10V4Z
0.1U_0402_16V7K
AG5 +VDD_CORE6 +VTT_CPU6 T32
1 1 1 1 1 2 2 2
Y21 +VDD_CORE7 +VTT_CPU7 U32
Y23 +VDD_CORE8 +VTT_CPU8 V32
AA16 +VDD_CORE9 +VTT_CPU9 W32
AA26 +VDD_CORE10 +VTT_CPU10 P31
AA27 +VDD_CORE11 +VTT_CPU11 AF32
AA28 +VDD_CORE12 +VTT_CPU12 AE32
2 2 2 2 2 2 2 AC16 +VDD_CORE13 +VTT_CPU13 AH32
C152 C153 C154 C155 C156 C157 C158 AC17 AJ32
+VDD_CORE14 +VTT_CPU14
AC18 +VDD_CORE15 +VTT_CPU15 AK31
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
AC19 +VDD_CORE16 +VTT_CPU16 AK32
1 1 1 1 1 1 1
AC20 +VDD_CORE17 +VTT_CPU17 AD32
AC21 +VDD_CORE18 +VTT_CPU18 AL31
AA17 +VDD_CORE19
AC24 +VDD_CORE20 +VTT_CPU20 B41
AC25 +VDD_CORE21 +VTT_CPU21 B42
AC26 +VDD_CORE22 +VTT_CPU22 C40
AC27 +VDD_CORE23 +VTT_CPU23 C41
AC28 +VDD_CORE24 +VTT_CPU24 C42
AD21 +VDD_CORE25 +VTT_CPU25 D39
AD23 +VDD_CORE26 +VTT_CPU26 D40
2 2 2 2 2 2 2 W27 +VDD_CORE27 +VTT_CPU27 D41
C159 C160 C161 C162 C163 C164 C165 V25 E38
+VDD_CORE28 +VTT_CPU28
AA18 +VDD_CORE29 +VTT_CPU29 E39
C C
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
AE19 +VDD_CORE30 +VTT_CPU30 F37
1 1 1 1 1 1 1
AE21 +VDD_CORE31 +VTT_CPU31 F38
AE23 +VDD_CORE32 +VTT_CPU32 F39
AE25 +VDD_CORE33 +VTT_CPU33 G36
AE26 +VDD_CORE34 +VTT_CPU34 G37
AE27 +VDD_CORE35 +VTT_CPU35 G38
AE28 +VDD_CORE36 +VTT_CPU36 H35
AF10 +VDD_CORE37 +VTT_CPU37 H37
AF11 +VDD_CORE38 +VTT_CPU38 J34
AA19 +VDD_CORE39 +VTT_CPU39 J35
AF2
AF21
+VDD_CORE40 POWER +VTT_CPU40 K33
K34
+VDD_CORE41 +VTT_CPU41
AF23 +VDD_CORE42 +VTT_CPU42 K35
AF25 +VDD_CORE43 +VTT_CPU43 L32
AF3 +VDD_CORE44 +VTT_CPU44 L33
AF4 +VDD_CORE45 +VTT_CPU45 L34
AF7 +VDD_CORE46 +VTT_CPU46 M31
AH23 +VDD_CORE47 +VTT_CPU47 M32
AF9 +VDD_CORE48 +VTT_CPU48 M33
AA20 +VDD_CORE49 +VTT_CPU49 N31
AG11 +VDD_CORE50 +VTT_CPU50 P32
AG12 +VDD_CORE51 +VTT_CPU51 Y32
+3VS
AG21 +VDD_CORE52 +VTT_CPU52 AA32
AG23 +VDD_CORE53 +VTT_CPU53 AB32
AG25 +VDD_CORE54
AG3 +VDD_CORE55
AG4 R167
+VDD_CORE56 0_0603_1%
AA21 +VDD_CORE57 +VTT_CPUCLK AG32
AG6 +VDD_CORE58
AG7 +VDD_CORE59
AG8
AG9
+VDD_CORE60
+VDD_CORE61 +3.3V_1 AD10 +3.3V_MCP79 368 mA
B B
AH1 +VDD_CORE62 +3.3V_2 AE8
AH10 AB10
RTC Battery AH11
W26
+VDD_CORE63
+VDD_CORE64
+3.3V_3
+3.3V_4 AD9
Y10
2
C166
2
C167
2
C168
2
C169 C170
+VDD_CORE65 +3.3V_5
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
4.7U_0603_6.3V6K
AH2 +VDD_CORE66 +3.3V_6 AB11
1 1 1 1
AA23 +VDD_CORE67 +3.3V_7 AA8
W28 +VDD_CORE68 +3.3V_8 Y9
AH25 +VDD_CORE69 1.1VALW
AH21 +VDD_CORE70
AH3 +VDD_CORE71
AH4 +VDD_CORE72
+COINCELL +1.05VALW
AH5 +VDD_CORE73
AH6
AH7
+VDD_CORE74
+VDD_CORE75 +VDD_AUXC1 T21 +VDD_AUXC 139 mA 1 R168 2
RTCVREF AH9 U21 0_0402_5%
+VDD_CORE76 +VDD_AUXC2 2 2
1
J20
+RTCVCC +3.3V_DUAL3
+3.3V_DUAL4 K20 +3.3V_DUAL 33 mA 1 R170 2
2 0_0402_5%
C173 C174
3 mA A20 4.7U_0603_6.3V6K 0.1U_0402_16V7K
+RTCVCC +VBAT
D17
1
1
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_16V7K
BAT54CW_SOT323~D
1 2
C541 C249 C248 C177
1U_0603_10V4Z~D
MCP79MX-B2 PBGA 1437P
A 2 1 A
Security Classification
2009/02/19
Compal Secret Data
2009/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP79(9/10)-POWER&RTC Batt
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4631P 1.0
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 15 of 42
5 4 3 2 1
5 4 3 2 1
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U4K
D D
AH26 GND161 GND253 AV40
AH33 GND162 GND254 BA1
AH34 GND163 GND255 BA4
AH37 GND164 GND256 AW31
AH38 GND165 GND257 AY6
AJ39 GND166 GND258 L35
AJ8 GND167 GND259 BC33
AK10 GND168 GND260 BC37
AK33 GND169 GND261 BC41
AK34 GND170 GND262 AY14
AK37 GND171 GND263 BC5
AK4 GND172 GND264 C2
AK40 GND173 GND265 D10
AL36 GND174 GND266 D14
AL40 GND175 GND267 D15
AL5 GND176 GND268 D18
AM10 GND177 GND269 D19
AM16 GND178 GND270 D22
AM18 GND179 GND271 D23
AM20 GND180 GND272 D26
AM22 GND181 GND273 D30
AM24 GND182 GND274 D37
AM26 GND183 GND275 D6
AM30 GND184 GND276 E13
AM34 GND185 GND277 E17
AM35 GND186 GND278 E21
AM37 GND187 GND279 E25
AM38 GND188 GND280 E29
AM5 GND189 GND281 E33
AM6 GND190 GND282 F12
AM7 GND191 GND283 F16
AM9 GND192 GND284 F32
C
AP26
AN28
GND193
GND194
GND GND285
GND286
F8
G10
C
A A
Security Classification
2009/02/19
Compal Secret Data
2009/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP79(10/10)-GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4631P 1.0
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 16 of 42
5 4 3 2 1
5 4 3 2 1
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U10 +1.5V U11 +1.5V U12 +1.5V U13 +1.5V
8 DDR_A_DQS0 C4 DQS VDDQ B10 8 DDR_A_DQS2 C4 DQS VDDQ B10 8 DDR_A_DQS4 C4 DQS VDDQ B10 8 DDR_A_DQS6 C4 DQS VDDQ B10
8 DDR_A_DQS#0 D4 DQS# VDDQ C2 8 DDR_A_DQS#2 D4 DQS# VDDQ C2 8 DDR_A_DQS#4 D4 DQS# VDDQ C2 8 DDR_A_DQS#6 D4 DQS# VDDQ C2
8 DDR_A_D[0..7] VDDQ E3 8 DDR_A_D[16..23] VDDQ E3 8 DDR_A_D[32..39] VDDQ E3 8 DDR_A_D[48..55] VDDQ E3
DDR_A_D1 B4 E10 DDR_A_D21 B4 E10 DDR_A_D39 B4 E10 DDR_A_D54 B4 E10
D DDR_A_D7 DQ0 VDDQ DDR_A_D18 DQ0 VDDQ DDR_A_D34 DQ0 VDDQ DDR_A_D51 DQ0 VDDQ D
C8 DQ1 C8 DQ1 C8 DQ1 C8 DQ1
DDR_A_D0 C3 A3 DDR_A_D17 C3 A3 DDR_A_D32 C3 A3 DDR_A_D49 C3 A3
DDR_A_D6 DQ2 VDD DDR_A_D19 DQ2 VDD DDR_A_D35 DQ2 VDD DDR_A_D50 DQ2 VDD
C9 DQ3 VDD A10 C9 DQ3 VDD A10 C9 DQ3 VDD A10 C9 DQ3 VDD A10
DDR_A_D4 E4 D8 DDR_A_D22 E4 D8 DDR_A_D36 E4 D8 DDR_A_D52 E4 D8
DDR_A_D3 DQ4 VDD DDR_A_D16 DQ4 VDD DDR_A_D33 DQ4 VDD DDR_A_D48 DQ4 VDD
E9 DQ5 VDD G3 E9 DQ5 VDD G3 E9 DQ5 VDD G3 E9 DQ5 VDD G3
DDR_A_D5 D3 G9 DDR_A_D20 D3 G9 DDR_A_D37 D3 G9 DDR_A_D53 D3 G9
DDR_A_D2 DQ6 VDD DDR_A_D23 DQ6 VDD DDR_A_D38 DQ6 VDD DDR_A_D55 DQ6 VDD
E8 DQ7 VDD K2 E8 DQ7 VDD K2 E8 DQ7 VDD K2 E8 DQ7 VDD K2
VDD K10 VDD K10 VDD K10 VDD K10
A8 NU/TDQS# VDD M2 A8 NU/TDQS# VDD M2 A8 NU/TDQS# VDD M2 A8 NU/TDQS# VDD M2
8 DDR_A_DM0 B8 DM/TDQS VDD M10 8 DDR_A_DM2 B8 DM/TDQS VDD M10 8 DDR_A_DM4 B8 DM/TDQS VDD M10 8 DDR_A_DM6 B8 DM/TDQS VDD M10
1 2 H9 ZQ 1 2 H9 ZQ 1 2 H9 ZQ 1 2 H9 ZQ
R171 240_0402_5%~D G2 M_ODT0 R172 240_0402_5%~D G2 M_ODT0 R173 240_0402_5%~D G2 M_ODT0 R174 240_0402_5%~D G2 M_ODT0
ODT M_CLK_DDR0 ODT M_CLK_DDR0 ODT M_CLK_DDR0 ODT M_CLK_DDR0
+V_DDR_MCH_REF E2 VREFDQ CK F8 +V_DDR_MCH_REF E2 VREFDQ CK F8 +V_DDR_MCH_REF E2 VREFDQ CK F8 +V_DDR_MCH_REF E2 VREFDQ CK F8
J9 G8 M_CLK_DDR#0 J9 G8 M_CLK_DDR#0 J9 G8 M_CLK_DDR#0 J9 G8 M_CLK_DDR#0
VREFCA CK# DDR_CKE0_DIMMA VREFCA CK# DDR_CKE0_DIMMA VREFCA CK# DDR_CKE0_DIMMA VREFCA CK# DDR_CKE0_DIMMA
CKE G10 CKE G10 CKE G10 CKE G10
DDR_A_MA0 K4 DDR_A_MA0 K4 DDR_A_MA0 K4 DDR_A_MA0 K4
DDR_A_MA1 A0 DDR_A_BS0 DDR_A_MA1 A0 DDR_A_BS0 DDR_A_MA1 A0 DDR_A_BS0 DDR_A_MA1 A0 DDR_A_BS0
L8 A1 BA0 J3 L8 A1 BA0 J3 L8 A1 BA0 J3 L8 A1 BA0 J3
DDR_A_MA2 L4 K9 DDR_A_BS1 DDR_A_MA2 L4 K9 DDR_A_BS1 DDR_A_MA2 L4 K9 DDR_A_BS1 DDR_A_MA2 L4 K9 DDR_A_BS1
DDR_A_MA3 A2 BA1 DDR_A_BS2 DDR_A_MA3 A2 BA1 DDR_A_BS2 DDR_A_MA3 A2 BA1 DDR_A_BS2 DDR_A_MA3 A2 BA1 DDR_A_BS2
K3 A3 BA2 J4 K3 A3 BA2 J4 K3 A3 BA2 J4 K3 A3 BA2 J4
DDR_A_MA4 L9 DDR_A_MA4 L9 DDR_A_MA4 L9 DDR_A_MA4 L9
DDR_A_MA5 A4 DDR_CS0_DIMMA# DDR_A_MA5 A4 DDR_CS0_DIMMA# DDR_A_MA5 A4 DDR_CS0_DIMMA# DDR_A_MA5 A4 DDR_CS0_DIMMA#
L3 A5 CS# H3 L3 A5 CS# H3 L3 A5 CS# H3 L3 A5 CS# H3
DDR_A_MA6 M9 F4 DDR_A_RAS# DDR_A_MA6 M9 F4 DDR_A_RAS# DDR_A_MA6 M9 F4 DDR_A_RAS# DDR_A_MA6 M9 F4 DDR_A_RAS#
DDR_A_MA7 A6 RAS# A6 RAS# A6 RAS# A6 RAS#
M3 A7 CAS# G4 DDR_A_CAS# DDR_A_MA7 M3 A7 CAS# G4 DDR_A_CAS# DDR_A_MA7 M3 A7 CAS# G4 DDR_A_CAS# DDR_A_MA7 M3 A7 CAS# G4 DDR_A_CAS#
DDR_A_MA8 N9 H4 DDR_A_WE# DDR_A_MA8 N9 H4 DDR_A_WE# DDR_A_MA8 N9 H4 DDR_A_WE# DDR_A_MA8 N9 H4 DDR_A_WE#
DDR_A_MA9 A8 WE# DDR_RST# DDR_A_MA9 A8 WE# DDR_RST# DDR_A_MA9 A8 WE# DDR_RST# DDR_A_MA9 A8 WE# DDR_RST#
M4 A9 RESET# N3 M4 A9 RESET# N3 M4 A9 RESET# N3 M4 A9 RESET# N3
DDR_A_MA10 H8 DDR_A_MA10 H8 DDR_A_MA10 H8 DDR_A_MA10 H8
DDR_A_MA11 A10/AP DDR_A_MA11 A10/AP DDR_A_MA11 A10/AP DDR_A_MA11 A10/AP
M8 A11 VSSQ B3 M8 A11 VSSQ B3 M8 A11 VSSQ B3 M8 A11 VSSQ B3
DDR_A_MA12 K8 B9 DDR_A_MA12 K8 B9 DDR_A_MA12 K8 B9 DDR_A_MA12 K8 B9
DDR_A_MA13 A12/BC# VSSQ DDR_A_MA13 A12/BC# VSSQ DDR_A_MA13 A12/BC# VSSQ DDR_A_MA13 A12/BC# VSSQ
N4 A13 VSSQ C10 N4 A13 VSSQ C10 N4 A13 VSSQ C10 N4 A13 VSSQ C10
VSSQ D2 VSSQ D2 VSSQ D2 VSSQ D2
VSSQ D10 VSSQ D10 VSSQ D10 VSSQ D10
VSS A2 VSS A2 VSS A2 VSS A2
C C
J8 NC VSS A9 J8 NC VSS A9 J8 NC VSS A9 J8 NC VSS A9
F10 NC VSS B2 F10 NC VSS B2 F10 NC VSS B2 F10 NC VSS B2
H2 NC VSS F3 H2 NC VSS F3 H2 NC VSS F3 H2 NC VSS F3
F2 NC VSS F9 F2 NC VSS F9 F2 NC VSS F9 F2 NC VSS F9
H10 NC VSS D9 H10 NC VSS D9 H10 NC VSS D9 H10 NC VSS D9
A1 NC VSS J2 A1 NC VSS J2 A1 NC VSS J2 A1 NC VSS J2
DDR_A_MA14 N8 J10 DDR_A_MA14 N8 J10 DDR_A_MA14 N8 J10 DDR_A_MA14 N8 J10
NC VSS NC VSS NC VSS NC VSS
A11 NC VSS L2 A11 NC VSS L2 A11 NC VSS L2 A11 NC VSS L2
A4 NC VSS L10 A4 NC VSS L10 A4 NC VSS L10 A4 NC VSS L10
N1 NC VSS N2 N1 NC VSS N2 N1 NC VSS N2 N1 NC VSS N2
N11 NC VSS N10 N11 NC VSS N10 N11 NC VSS N10 N11 NC VSS N10
H5TQ1G83AFP-G7C FBGA 78P H5TQ1G83AFP-G7C FBGA 78P H5TQ1G83AFP-G7C FBGA 78P H5TQ1G83AFP-G7C FBGA 78P
+1.5V +1.5V
8,18 DDR_A_MA[0..14] +V_DDR_MCH_REF
M_ODT0
8,18 M_ODT0
330U_D2_2.5VY_R15M
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
M_CLK_DDR0 1
8,18 M_CLK_DDR0
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 1 1 1
C178
C180
C181
C182
C184
M_CLK_DDR#0 +
8,18 M_CLK_DDR#0 C185 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
C186
C187
C188
C189
C190
C191
C192
C195
C196
C197
C198
C199
C200
C201
C202
C203
C204
DDR_CKE0_DIMMA
8,18 DDR_CKE0_DIMMA 2 2 2 2 2
DDR_A_BS0 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2
B 8,18 DDR_A_BS0 B
DDR_A_BS1
8,18 DDR_A_BS1
DDR_A_BS2
8,18 DDR_A_BS2
DDR_CS0_DIMMA# +1.5V
8,18 DDR_CS0_DIMMA#
DDR_A_RAS#
8,18 DDR_A_RAS#
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
DDR_A_CAS#
8,18 DDR_A_CAS#
DDR_A_WE# 2 2 2 2 2 2 2 2
8,18 DDR_A_WE#
C247
C253
C599
C251
C256
C255
C250
C254
DDR_RST#
9,18,19 DDR_RST#
1 1 1 1 1 1 1 1
1
R175
C252
30_0402_1%~D
3.3P_0402_50V8C~D
2
Vendor Package
1
2
C193
0.1U_0402_10V7K~D
C194
R176
30_0402_1%~D 2 DELL CONFIDENTIAL/PROPRIETARY
2
M_CLK_DDR#0
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRIII-Memory Down (Top)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-4631P
5 4
Www.alliancelaptoptraining.com 3 2
Date: Tuesday, February 24, 2009
1
Sheet 17 of 42
5 4 3 2 1
Www.alliancelaptoptraining.com
U14 +1.5V U15 +1.5V U16 +1.5V U17 +1.5V
8 DDR_A_DQS1 C4 DQS VDDQ B10 8 DDR_A_DQS3 C4 DQS VDDQ B10 8 DDR_A_DQS5 C4 DQS VDDQ B10 8 DDR_A_DQS7 C4 DQS VDDQ B10
8 DDR_A_DQS#1 D4 DQS# VDDQ C2 8 DDR_A_DQS#3 D4 DQS# VDDQ C2 8 DDR_A_DQS#5 D4 DQS# VDDQ C2 8 DDR_A_DQS#7 D4 DQS# VDDQ C2
8 DDR_A_D[8..15] VDDQ E3 8 DDR_A_D[24..31] VDDQ E3 8 DDR_A_D[40..47] VDDQ E3 8 DDR_A_D[56..63] VDDQ E3
DDR_A_D10 B4 E10 DDR_A_D27 B4 E10 DDR_A_D42 B4 E10 DDR_A_D58 B4 E10
D DDR_A_D13 DQ0 VDDQ DDR_A_D30 DQ0 VDDQ DDR_A_D41 DQ0 VDDQ DDR_A_D61 DQ0 VDDQ D
C8 DQ1 C8 DQ1 C8 DQ1 C8 DQ1
DDR_A_D11 C3 A3 DDR_A_D26 C3 A3 DDR_A_D43 C3 A3 DDR_A_D59 C3 A3
DDR_A_D8 DQ2 VDD DDR_A_D25 DQ2 VDD DDR_A_D47 DQ2 VDD DDR_A_D60 DQ2 VDD
C9 DQ3 VDD A10 C9 DQ3 VDD A10 C9 DQ3 VDD A10 C9 DQ3 VDD A10
DDR_A_D9 E4 D8 DDR_A_D31 E4 D8 DDR_A_D46 E4 D8 DDR_A_D63 E4 D8
DDR_A_D14 DQ4 VDD DDR_A_D28 DQ4 VDD DDR_A_D40 DQ4 VDD DDR_A_D57 DQ4 VDD
E9 DQ5 VDD G3 E9 DQ5 VDD G3 E9 DQ5 VDD G3 E9 DQ5 VDD G3
DDR_A_D12 D3 G9 DDR_A_D24 D3 G9 DDR_A_D44 D3 G9 DDR_A_D62 D3 G9
DDR_A_D15 DQ6 VDD DDR_A_D29 DQ6 VDD DDR_A_D45 DQ6 VDD DDR_A_D56 DQ6 VDD
E8 DQ7 VDD K2 E8 DQ7 VDD K2 E8 DQ7 VDD K2 E8 DQ7 VDD K2
VDD K10 VDD K10 VDD K10 VDD K10
A8 NU/TDQS# VDD M2 A8 NU/TDQS# VDD M2 A8 NU/TDQS# VDD M2 A8 NU/TDQS# VDD M2
8 DDR_A_DM1 B8 DM/TDQS VDD M10 8 DDR_A_DM3 B8 DM/TDQS VDD M10 8 DDR_A_DM5 B8 DM/TDQS VDD M10 8 DDR_A_DM7 B8 DM/TDQS VDD M10
1 2 H9 ZQ 1 2 H9 ZQ 1 2 H9 ZQ 1 2 H9 ZQ
R177 240_0402_5%~D G2 M_ODT0 R178 240_0402_5%~D G2 M_ODT0 R179 240_0402_5%~D G2 M_ODT0 R180 240_0402_5%~D G2 M_ODT0
ODT M_CLK_DDR0 ODT M_CLK_DDR0 ODT M_CLK_DDR0 ODT M_CLK_DDR0
+V_DDR_MCH_REF E2 VREFDQ CK F8 +V_DDR_MCH_REF E2 VREFDQ CK F8 +V_DDR_MCH_REF E2 VREFDQ CK F8 +V_DDR_MCH_REF E2 VREFDQ CK F8
J9 G8 M_CLK_DDR#0 J9 G8 M_CLK_DDR#0 J9 G8 M_CLK_DDR#0 J9 G8 M_CLK_DDR#0
VREFCA CK# DDR_CKE0_DIMMA VREFCA CK# DDR_CKE0_DIMMA VREFCA CK# DDR_CKE0_DIMMA VREFCA CK# DDR_CKE0_DIMMA
CKE G10 CKE G10 CKE G10 CKE G10
DDR_A_MA0 K4 DDR_A_MA0 K4 DDR_A_MA0 K4 DDR_A_MA0 K4
DDR_A_MA1 A0 DDR_A_BS0 DDR_A_MA1 A0 DDR_A_BS0 DDR_A_MA1 A0 DDR_A_BS0 DDR_A_MA1 A0 DDR_A_BS0
L8 A1 BA0 J3 L8 A1 BA0 J3 L8 A1 BA0 J3 L8 A1 BA0 J3
DDR_A_MA2 L4 K9 DDR_A_BS1 DDR_A_MA2 L4 K9 DDR_A_BS1 DDR_A_MA2 L4 K9 DDR_A_BS1 DDR_A_MA2 L4 K9 DDR_A_BS1
DDR_A_MA3 A2 BA1 DDR_A_BS2 DDR_A_MA3 A2 BA1 DDR_A_BS2 DDR_A_MA3 A2 BA1 DDR_A_BS2 DDR_A_MA3 A2 BA1 DDR_A_BS2
K3 A3 BA2 J4 K3 A3 BA2 J4 K3 A3 BA2 J4 K3 A3 BA2 J4
DDR_A_MA4 L9 DDR_A_MA4 L9 DDR_A_MA4 L9 DDR_A_MA4 L9
DDR_A_MA5 A4 DDR_CS0_DIMMA# DDR_A_MA5 A4 DDR_CS0_DIMMA# DDR_A_MA5 A4 DDR_CS0_DIMMA# DDR_A_MA5 A4 DDR_CS0_DIMMA#
L3 A5 CS# H3 L3 A5 CS# H3 L3 A5 CS# H3 L3 A5 CS# H3
DDR_A_MA6 M9 F4 DDR_A_RAS# DDR_A_MA6 M9 F4 DDR_A_RAS# DDR_A_MA6 M9 F4 DDR_A_RAS# DDR_A_MA6 M9 F4 DDR_A_RAS#
DDR_A_MA7 A6 RAS# A6 RAS# A6 RAS# A6 RAS#
M3 A7 CAS# G4 DDR_A_CAS# DDR_A_MA7 M3 A7 CAS# G4 DDR_A_CAS# DDR_A_MA7 M3 A7 CAS# G4 DDR_A_CAS# DDR_A_MA7 M3 A7 CAS# G4 DDR_A_CAS#
DDR_A_MA8 N9 H4 DDR_A_WE# DDR_A_MA8 N9 H4 DDR_A_WE# DDR_A_MA8 N9 H4 DDR_A_WE# DDR_A_MA8 N9 H4 DDR_A_WE#
DDR_A_MA9 A8 WE# DDR_RST# DDR_A_MA9 A8 WE# DDR_RST# DDR_A_MA9 A8 WE# DDR_RST# DDR_A_MA9 A8 WE# DDR_RST#
M4 A9 RESET# N3 M4 A9 RESET# N3 M4 A9 RESET# N3 M4 A9 RESET# N3
DDR_A_MA10 H8 DDR_A_MA10 H8 DDR_A_MA10 H8 DDR_A_MA10 H8
DDR_A_MA11 A10/AP DDR_A_MA11 A10/AP DDR_A_MA11 A10/AP DDR_A_MA11 A10/AP
M8 A11 VSSQ B3 M8 A11 VSSQ B3 M8 A11 VSSQ B3 M8 A11 VSSQ B3
DDR_A_MA12 K8 B9 DDR_A_MA12 K8 B9 DDR_A_MA12 K8 B9 DDR_A_MA12 K8 B9
DDR_A_MA13 A12/BC# VSSQ DDR_A_MA13 A12/BC# VSSQ DDR_A_MA13 A12/BC# VSSQ DDR_A_MA13 A12/BC# VSSQ
N4 A13 VSSQ C10 N4 A13 VSSQ C10 N4 A13 VSSQ C10 N4 A13 VSSQ C10
VSSQ D2 VSSQ D2 VSSQ D2 VSSQ D2
VSSQ D10 VSSQ D10 VSSQ D10 VSSQ D10
VSS A2 VSS A2 VSS A2 VSS A2
C C
J8 NC VSS A9 J8 NC VSS A9 J8 NC VSS A9 J8 NC VSS A9
F10 NC VSS B2 F10 NC VSS B2 F10 NC VSS B2 F10 NC VSS B2
H2 NC VSS F3 H2 NC VSS F3 H2 NC VSS F3 H2 NC VSS F3
F2 NC VSS F9 F2 NC VSS F9 F2 NC VSS F9 F2 NC VSS F9
H10 NC VSS D9 H10 NC VSS D9 H10 NC VSS D9 H10 NC VSS D9
A1 NC VSS J2 A1 NC VSS J2 A1 NC VSS J2 A1 NC VSS J2
DDR_A_MA14 N8 J10 DDR_A_MA14 N8 J10 DDR_A_MA14 N8 J10 DDR_A_MA14 N8 J10
NC VSS NC VSS NC VSS NC VSS
A11 NC VSS L2 A11 NC VSS L2 A11 NC VSS L2 A11 NC VSS L2
A4 NC VSS L10 A4 NC VSS L10 A4 NC VSS L10 A4 NC VSS L10
N1 NC VSS N2 N1 NC VSS N2 N1 NC VSS N2 N1 NC VSS N2
N11 NC VSS N10 N11 NC VSS N10 N11 NC VSS N10 N11 NC VSS N10
H5TQ1G83AFP-G7C FBGA 78P H5TQ1G83AFP-G7C FBGA 78P H5TQ1G83AFP-G7C FBGA 78P H5TQ1G83AFP-G7C FBGA 78P
+V_DDR_MCH_REF
DDR_A_BS1
8,17 DDR_A_MA[0..14] 8,17 DDR_A_BS1
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
M_ODT0 DDR_A_BS2
8,17 M_ODT0 8,17 DDR_A_BS2
1 1 1 1 1 1 1 1 1 1
C205
C206
C207
C208
C209
C210
C211
C212
C213
C214
M_CLK_DDR0 DDR_CS0_DIMMA#
8,17 M_CLK_DDR0 8,17 DDR_CS0_DIMMA#
M_CLK_DDR#0 DDR_A_RAS#
8,17 M_CLK_DDR#0 8,17 DDR_A_RAS# 2 2 2 2 2 2 2 2 2 2
DDR_CKE0_DIMMA DDR_A_CAS#
DDR3 Terminations
8,17 DDR_CKE0_DIMMA 8,17 DDR_A_CAS#
DDR_A_BS0 DDR_A_WE# +0.75VS
8,17 DDR_A_BS0 8,17 DDR_A_WE#
B DDR_RST# RP5 RP6 B
9,17,19 DDR_RST#
DDR_A_CAS# 1 4 1 4 DDR_A_RAS#
DDR_CKE0_DIMMA 2 3 2 3 M_ODT0
36_0404_4P2R_5%~D 36_0404_4P2R_5%~D
RP7 RP8
DDR_CS0_DIMMA# 1 4 1 4 DDR_A_MA2
DDR_A_WE# 2 3 2 3 DDR_A_MA3
36_0404_4P2R_5%~D 36_0404_4P2R_5%~D
RP9 RP10
DDR_A_MA12 1 4 1 4 DDR_A_MA6
DDR_A_BS1 2 3 2 3 DDR_A_MA8 +0.75VS
36_0404_4P2R_5%~D 36_0404_4P2R_5%~D
RP11 RP12
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
DDR_A_MA10 1 4 1 4 DDR_A_MA5
DDR_A_BS2 2 3 2 3 DDR_A_MA9
2 2 2 2 2 2
+0.75VS
C215
36_0404_4P2R_5%~D 36_0404_4P2R_5%~D
C216
C217
C218
C219
C220
RP13 RP14
+3VS DDR_A_BS0 1 4 1 4 DDR_A_MA11
C221 DDR_A_MA0 DDR_A_MA14 1 1 1 1 1 1
2 3 2 3
0.1U 50V K X7R 0603
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
@ 1 2
U18 1 1 1 1 1 1 1 1 1 @ 1 1 36_0404_4P2R_5%~D 36_0404_4P2R_5%~D
@
C647
C648
C603
C604
C605
C606
C607
C608
C651
C652
C653
@ 1K_0402_5%~D
MEM_SMBDATA 2 2 2 2 2 2 2 2 2 2 2
4 GND SDA 5 MEM_SMBDATA 14,19
R182
36_0404_4P2R_5%~D 36_0404_4P2R_5%~D
R181
AT24C02BN-SH-T_SO8~D
A A
2
Place decaps close end termination resistors, one decap for 4 resistors
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRIII-Memory Down (Bottom)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-4631P
5 4
Www.alliancelaptoptraining.com 3 2
Date: Tuesday, February 24, 2009
1
Sheet 18 of 42
5 4 3 2 1
+V_DDR_MCH_REF
+V_DDR_MCH_REF
8 DDR_B_D[0..63]
8 DDR_B_DQS[0..7]
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
JDIMM1
1 VREF_DQ VSS 2
3 4 DDR_B_D4 1 1
VSS DQ4 8 DDR_B_DQS#[0..7]
C222
C223
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 DQ0 DQ5 +1.5V
7 DQ1 VSS 8
9 10 DDR_B_DQS#0
VSS DQS0# 2 2 8 DDR_B_DM[0..7]
DDR_B_DM0 11 12 DDR_B_DQS0
DM0 DQS0
13 VSS VSS 14
DDR_B_D2 15 16 DDR_B_D6
DQ2 DQ6 8 DDR_B_MA[0..14]
2
D DDR_B_D3 DDR_B_D7 D
17 DQ3 DQ7 18
19 20 R509
DDR_B_D8 VSS VSS DDR_B_D12 1K_0402_5%
21 DQ8 DQ12 22
DDR_B_D9 23 24 DDR_B_D13
DQ9 DQ13
25 26
1
DDR_B_DQS#1 VSS VSS DDR_B_DM1
27 DQS1# DM1 28
DDR_B_DQS1 29 30 DDR_RST# DDR_RST# 9,17,18
DQS1 RESET#
31 VSS VSS 32
DDR_B_D10 33 34 DDR_B_D14 Place close to SO-DIMM
DDR_B_D11 DQ10 DQ14 DDR_B_D15 +5VALW
35 DQ11 DQ15 36
37 VSS VSS 38
DDR_B_D16 39 40 DDR_B_D20 +1.5V
DQ16 DQ20
2
DDR_B_D17 41 42 DDR_B_D21 +1.5V
DQ17 DQ21 R510
43 VSS VSS 44
15.4K_0402_1%
DDR_B_DQS#2 45 46 DDR_B_DM2 4.7K_0402_5%
DQS2# DM2
1
DDR_B_DQS2 47 48
DQS2 VSS
1
D
R511
330U_D2_2.5VY_R15M
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2.2U_0402_6.3VM
2.2U_0402_6.3VM
49 50 DDR_B_D22
1
DDR_B_D18 VSS DQ22 DDR_B_D23 Q5
51 DQ18 DQ23 52 2 1
@ C224
DDR_B_D19 53 54 G 2N7002_SOT23 1 1 1 1 1 1
DQ19 VSS
C225
C226
C227
C228
C229
C230
55 56 DDR_B_D28 C S +
3
DDR_B_D24 VSS DQ28 DDR_B_D29 Q38
57 DQ24 DQ29 58 2
0.1U_0402_16V4Z~D
DDR_B_D25 59 60 B MMBT3904_SOT23
DQ25 VSS
1
2 2 2 2 2 2 2
15.4K_0402_1%
61 62 DDR_B_DQS#3 1 E
3
DDR_B_DM3 VSS DQS3# DDR_B_DQS3 @
63 DM3 DQS3 64
R512
C347
65 VSS VSS 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31 2
69 70
2
DQ27 DQ31
71 VSS VSS 72
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
75 VDD VDD 76
C C
77 NC A15 78 T17 1 1 1 1
C231
C232
C233
C234
DDR_B_BS2 79 80 DDR_B_MA14
8 DDR_B_BS2 BA2 A14
81 VDD VDD 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7 2 2 2 2
85 A9 A7 86
87 VDD VDD 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD VDD 100
M_CLK_DDR2 101 102 M_CLK_DDR3 M_CLK_DDR3 8
8 M_CLK_DDR2 CK0 CK1
M_CLK_DDR#2 103 104 M_CLK_DDR#3 M_CLK_DDR#3 8
8 M_CLK_DDR#2 CK0# CK1#
105 VDD VDD 106
DDR_B_MA10 107 108 DDR_B_BS1 DDR_B_BS1 8
DDR_B_BS0 A10/AP BA1 DDR_B_RAS# +0.75VS
8 DDR_B_BS0 109 BA0 RAS# 110 DDR_B_RAS# 8
111 VDD VDD 112
DDR_B_WE# 113 114 DDR_CS2_DIMMB# DDR_CS2_DIMMB# 8
8 DDR_B_WE# WE# S0#
DDR_B_CAS# 115 116 M_ODT2_DIMMB M_ODT2_DIMMB 8
8 DDR_B_CAS# CAS# ODT0
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
117 VDD VDD 118
DDR_B_MA13 119 120 M_ODT3_DIMMB M_ODT3_DIMMB 8
DDR_CS3_DIMMB# A13 ODT1
8 DDR_CS3_DIMMB# 121 S1# NC 122 2 2 2 2
C237
C238
C239
C240
123 124 R187
VDD VDD +V_DDR_MCH_REF_R +V_DDR_MCH_REF
T18 125 TEST VREF_CA 126 1 2 +V_DDR_MCH_REF
127 128 0_0402_5%~D
VSS VSS 1 1 1 1
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 DQ33 DQ37 132
133 VSS VSS 134 1 1
C235
C236
DDR_B_DQS#4 135 136 DDR_B_DM4
DDR_B_DQS4 DQS4# DM4
137 DQS4 VSS 138
139 140 DDR_B_D38
B DDR_B_D34 VSS DQ38 DDR_B_D39 2 2 B
DDR_B_D35
141 DQ34 DQ39 142 Place close to JDIMM pin 203 and 204
143 DQ35 VSS 144
145 146 DDR_B_D44
DDR_B_D40 VSS DQ44 DDR_B_D45
147 DQ40 DQ45 148
DDR_B_D41 149 150
DQ41 VSS DDR_B_DQS#5
151 VSS DQS5# 152
DDR_B_DM5 153 154 DDR_B_DQS5
DM5 DQS5
155 VSS VSS 156
DDR_B_D42 157 158 DDR_B_D46 +1.5V
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 VSS VSS 162
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166
1
167 VSS VSS 168
DDR_B_DQS#6 169 170 DDR_B_DM6 +3VALW
DDR_B_DQS6 DQS6# DM6 R27
171 DQS6 VSS 172
173 174 DDR_B_D54 1K_0402_1% +V_DDR_MCH_REF
DDR_B_D50 VSS DQ54 DDR_B_D55
175 176
2
DDR_B_D51 DQ50 DQ55
177 DQ51 VSS 178
179 180 DDR_B_D60 +V_DDR_MCH_REF
VSS DQ60
1
+3VS
2.7K_0402_5%
1
10K_0402_5%~D
2
DQ59 DQ63 0_0402_5%~D
195 196
2
2.2U_0603_6.3V6K~D
A A
1
10K_0402_5%~D
C242
R185
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRIII SO-DIMM SLOT
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-4631P
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Date: Tuesday, February 24, 2009
1
Sheet 19 of 42
A B C D E
Www.alliancelaptoptraining.com
LCD
JLVDS1
G11 51
50 G10 G9 49
48 G8 G7 47
46 G6 G5 45
44 G4 G3 43
R556 1 +LCDVDD +LCDVDD +3VS
+3VALW 2 47K_0402_5% 42 G2 G1 41
4.7U_0805_6.3V6K~N
0.1U_0402_16V7K~N
LVDSA2+ 26 25
2 2 11 LVDSA2+ 26 25
AOZ1320CI-04_SOT23-6 LVDSAC- 24 23 LVDSAC+
11 LVDSAC- 24 23 LVDSAC+ 11
@ D6 22 21 LVDSB0-
22 21 LVDSB0- 11
11,28 MCP79_ENVDD MCP79_ENVDD 2 1 LVDSB0+ 20 19
11 LVDSB0+ 20 19
CH751H-40PT_SOD323-2 LVDSB1- 18 17 LVDSB1+
11 LVDSB1- 18 17 LVDSB1+ 11
16 15 LVDSB2-
16 15 LVDSB2- 11
1
28 LCD_VCC_TEST_EN LCD_VCC_TEST_EN 2 R211 1 LVDSB2+ 14 13
11 LVDSB2+ 14 13
0_0402_5% R210 LVDSBC- 12 11 LVDSBC+
11 LVDSBC- 12 11 LVDSBC+ 11
10K_0402_1% LCD_TST 10 9
10 9 DISPOFF#
8 8 7 7 need swap DISPOFF# to pin 36 on Pannel side.
INVT_PWM 6 5
28 INVT_PWM
2
6 5 INVPW R_B+
1 4 4 3 3 1 2 B+
Change from 10K to 100k - 0102. C600 INVPW R_B+ 2 1 L12
2 1 FBMA-L11-201209-121LMA50T
100P_0402_50V W=60mils
2 I-PEX_20439-040E-02
D29
1 VN VP 4 +3VALW
X01 change JLVDS connect signal (for layout)
INVT_PWM 2 3 DISPOFF#
CH1 CH2
CM1213-02SR_SOT143-4 +3VS
Place D29 close to JLVDS1
1
R212
4.7K_0402_5%
2 2
D7
2
BKOFF# 1 2 DISPOFF#
28 BKOFF#
SDMK0340L-7-F SOD-323
C569 2 1 0.01U_0402_25V7K~N 1
13 SATA_A0_TXP GND
SATA_A0_TXP_C 2 A+
13 SATA_A0_TXN
C518 2 1 0.01U_0402_25V7K~N SATA_A0_TXN_C 3 A-
4 GND
13 SATA_A0_RXN
C568 2 1 0.01U_0402_25V7K~N SATA_A0_RXN_C 5 B-
SATA_A0_RXP_C 6
C570 B+
13 SATA_A0_RXP 2 1 0.01U_0402_25V7K~N 7 GND
+3VS 8 VCC3.3
9 VCC3.3
3 10 VCC3.3
3
11 GND
12 GND
13 GND
+5VS 14 VCC5
15 VCC5
16 VCC5
17 GND
18 RESERVED Close to JSATA1.
19 GND
20 VCC12
21 23 +5VS
VCC12 GND
22 VCC12 GND 24
SUYIN_127043FB022G345ZR_NR 1
CONN@ 1 1 1 1
+ C394 C390 C392 C391 C393
150U_B2_6.3VM_R45M 10U_0805_10V4Z~N 0.1U_0402_16V7K~N 0.1U_0402_16V7K~N 1000P_0402_50V7K~N
2 2 2 2 2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD/SATA HDD
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4631P
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 20 of 42
A B C D E
5 4 3 2 1
+5VS 2 1 2 1
D19 BAT1000-7-F SOT23-3
F1
@ 1A_6VDC_MINISMDC110 1 0.1U_0402_16V7K
+5VS 2 R1282 1 C450
0_0402_5% C449
1
0.1U_0402_16V7K 2 1 1
2 C451
100K_0402_5% 0.1U_0402_16V7K
+3VS R396
2
2
1
JHDMI1
D R399 HDMI_DET_C D
28 HDMI_DET_C 19 HP_DET
2.2K_0402_5% +5VS_HDMI +5VS_HDMI 18 +5V
1
5
17 DDC/CEC_GND
HDMI_SDA 16
OE#
P
2
HDMI_HPD HDMI_SCL SDA
11 HDMI_HPD 4 Y A 2 15 SCL
14 Reserved
G
U36 13
SN74AHCT1G125GW_SOT353-5 DVI_TXC- CEC
12
3
CK-
11 CK_shield
DVI_TXC+ 10
DVI_TXD0- CK+
9 D0-
8 D0_shield
DVI_TXD0+ 7
DVI_TXD1- D0+
6 D1-
5 D1_shield
DVI_TXD1+ 4 20
DVI_TXD2- D1+ GND
3 D2- GND 21
2 D2_shield GND 22
DVI_TXD2+ 1 23
SCL_HDMI_MCP DVI_SCLK D2+ GND
11 SCL_HDMI_MCP 1 2 R404
0_0402_5% FOX_QJ5119L-NVBT-7F
SDA_HDMI_MCP 1 2 R405 DVI_SDATA CONN@
11 SDA_HDMI_MCP
0_0402_5%
Close to JHDMI connector
L23 L24
VGA_DVI_TXD1- 1 2 DVI_TXD1- VGA_DVI_TXC- 1 2 DVI_TXC-
1 2 1 2
1
R412 R413 R414 R415
VGA_DVI_TXD1+ 4 3 DVI_TXD1+ VGA_DVI_TXC+ 4 3 DVI_TXC+
4 3 4 3 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5%
SUPERWORLD OCE2012120YZF SUPERWORLD OCE2012120YZF
2
2
G
Q12
@ R416 1 2 @ R417 1 2 0_0402_5%
0_0402_5% DVI_SCLK 3 1 HDMI_SCL
2N7002_SOT23
D
C C
@ R418 1 2 0_0402_5% @ R423 1 2 0_0402_5%
L25 L26
VGA_DVI_TXD2- 1 2 DVI_TXD2- VGA_DVI_TXD0- 1 2 DVI_TXD0-
1 2 1 2
2
G
Q13
D
SUPERWORLD OCE2012120YZF SUPERWORLD OCE2012120YZF
0.1U_0402_16V7K
MCP79_DP1+ 2 1 SW_DP1+ 6 2 2 1
11 MCP79_DP1+ ML_IN 1(P) VDD
MCP79_DP1- C464 2 0.1U_0402_16V7K
1 SW_DP1- 7 8 C465 2 1 0.1U_0402_16V4Z C468
11 MCP79_DP1- ML_IN 1(N) VDD
C466 0.1U_0402_16V7K 34 C467 2 1 0.1U_0402_16V4Z
MCP79_DP2+ SW_DP2+ VDD C469 2 1
11 MCP79_DP2+ 2 1 9 ML_IN 2(P) VDD 48 1 0.1U_0402_16V4Z
MCP79_DP2- C470 2 0.1U_0402_16V7K
1 SW_DP2- 10 54 C471 2 1 0.1U_0402_16V4Z
11 MCP79_DP2- ML_IN 2(N) VDD
C472 0.1U_0402_16V7K C473 0.1U_0402_16V4Z U39 U40
MCP79_DP3+ SW_DP3+ @ @
10
10
11 MCP79_DP3+ 2 1 12 ML_IN 3(P) VDD*1 38 1 2
8
AZ1045-04QU_MSOP10
AZ1045-04QU_MSOP10
MCP79_DP3- C474 2 0.1U_0402_16V7K
1 SW_DP3- 13 R427 0_0402_5%
11 MCP79_DP3- ML_IN 3(N)
C475 0.1U_0402_16V7K 16 VGA_DVI_TXC+
NC
NC
NC
NC
Line 4 GND
NC
NC
NC
NC
Line 4 GND
MCP79_AUX+ TMDS_SINK_CLK(P)
11 MCP79_AUX+
R488 1 @ 2 0_0402_5% DP+ 45 AUX_SINK (P) TMDS_SINK_CLK(N) 15 VGA_DVI_TXC-
MCP79_AUX- R487 1 @ 2 0_0402_5% DP- 43
11 MCP79_AUX- AUX_SINK (N)
Line 1
Line 2
Line 3
Line 1
Line 2
Line 3
19 VGA_DVI_TXD0+
VDD
VDD
SCL_DP_MCP R490 1 @ TMDS_SINK 0(P) VGA_DVI_TXD0-
11 SCL_DP_MCP 2 0_0402_5% 36 AUX(P)_I2C(SCL) TMDS_SINK 0(N) 18
SDA_DP_MCP R489 1 @ 2 0_0402_5% 35
11 SDA_DP_MCP AUX(N)_I2C(SDA)
22 VGA_DVI_TXD1+
3
1
3
1
5
B SCL_HDMI_MCP R407 1 @ TMDS_SINK 1(P) VGA_DVI_TXD1- B
11 SCL_HDMI_MCP 2 0_0402_5% 29 I2C_SCL TMDS_SINK 1(N) 21
SDA_HDMI_MCP R408 1 @ 2 0_0402_5% 28 JDP1
11 SDA_HDMI_MCP I2C_SDA
+3VS R428 1 2 4.7K_0402_5% 25 VGA_DVI_TXD2+
R429 1 @ TMDS_SINK 2(P) VGA_DVI_TXD2-
2 4.7K_0402_5% 30 LP TMDS_SINK 2(N) 24
1
LANE1_N
100K_0402_5%
HDMI_HPD 32 50 DP_TX2+ DP_TX2+ 1 2 DP_TXD2+ 7
TMDS_HPD_SINK DP_SINK 2(P) LANE2_P
49 DP_TX2- R120 R433 DP_TX2- 0.1U_0402_16V7K C480 1 2 DP_TXD2- 8
DP_SINK 2(N) GND
DP_HPD 40 @ 0.1U_0402_16V7K C481 9
DP_HPD_SINK LANE2_N
47 DP_TX3+ 100K_0402_5% DP_TX3+ 1 2 DP_TXC+ 10
+3VS DP_SINK 3(P) DP_TX3- DP_TX3- 0.1U_0402_16V7K C482 DP_TXC-
LANE3_P
5 46 1 2 11
2
0_0402_5% 42 DP_AUXN 16
GND GND
44 1 L29 17 AUXCH_N
GND DPVADJ DP_HPD
51 28 DP_HPD 1 R437 2 1 2 BLM18AG121SN1D_0603 18
1
RETURN
6.49K_0402_1%
1
DP_PWR
100K_0402_5%
4.7K_0402_1%
100K_0402_5%
R441 R444
100P_0402_50V8J
SN75DP122A_QFN56_8X8 R440 R438 100K_0402_5% @ R443 C487 21
2
100K_0402_5%
100K_0402_5% 180P_0402_50V8J 22
2 2
GR OUND
R445 23
1
2
0_0402_5%
24
1
2
1
+3VS FOX_3V102P1-RB2BT-8F_20P
@ 2 1
C491 0.1U_0402_16V4Z
R447 1 @ 2 4.7K_0402_5% +3VS
+3VS
MCP_DP_CBL_DET
MCP_DP_CBL_DET 11
5
PIN 14
74LVC1G14GW_SOT353-5
P
NC
2
S
A R486 0_0402_5% A
G
1
CBL_DET 2
G
0_0402_5% R452 INSIDE DONGLE
1
@ U41 R453
3
2M_0402_5%
2
2
2
R457 R460
2
G
100K_0402_5% BSS138W-7-F_SOT323-3
100K_0402_5%
MCP79_AUX+ 3 1 SCL_DP 1 2 DP_AUXP
11 MCP79_AUX+
1
0.1U_0402_16V4Z C495
S
11 SCL_DP_MCP
R458 1 2 0_0402_5% DP_AUXP Q16 Security Classification Compal Secret Data Compal Electronics, Inc.
2
G
11 SDA_DP_MCP
R459 1 2 0_0402_5% DP_AUXN 2@ R477 1 Issued Date 2009/02/19 Deciphered Date 2009/12/31 Title
BSS138W-7-F_SOT323-3 0_0402_5%
11 MCP79_AUX-
MCP79_AUX- 3 1 SDA_DP 1 2 DP_AUXN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI/Display Port Conn.
0.1U_0402_16V4Z C496 Size Document Number R ev
S
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Www.alliancelaptoptraining.com
Q17 Custom 1.0
2@ R479 1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4631P
0_0402_5% Date: Tuesday, February 24, 2009 Sheet 21 of 42
5 4 3 2 1
5 4 3 2 1
Www.alliancelaptoptraining.com
W=60mils
+3V_LAN
LAN_MIDI0-
CM1293A-04SO SOT23-6
1 CH1 CH4 4
1.5A +LAN_VDD
+3V_LAN_R 2 Vn Vp 5 +3VALW
+3V_LAN 1 2 +LAN_VDD12 These caps close to U64: Pin 4
1 1 1 1 1
0.1U_0402_10V7K~N C618
0.1U_0402_10V7K~N C619
0.1U_0402_10V7K~N C620
0.1U_0402_10V7K~N C621
0.1U_0402_10V7K~N C622
0.1U_0402_10V7K~N C623
C615 C616 C617 R1238 1 1 1 1 1 1 C624 C625
0_0603_5% +LAN_VDD LAN_MIDI0+ 3 6
CH2 CH3
0.1U_0402_10V7K~N
22U_1206_6.3V6M
2 2 2 2 2
0.1U_0402_10V7K~N
0.1U_0402_10V7K~N
0.1U_0402_10V7K~N
@ D25
2 2 2 2 2 2 CM1293A-04SO SOT23-6
0.1U_0402_10V7K
0.01U_0402_16V7K
D D
1 2
LAN_MIDI1- 1 4
CH1 CH4
C629
C630
2 1
@ 2 5 +3VALW
Vn Vp
These caps close to U64: Pin 44,45
These caps close to U64: Pin 44, 45 These caps close to U64: Pin 4,10,13, 30, 36,39 LAN_MIDI1+
( Should be place within 200 mils ) 3 CH2 CH3 6
@ D26
CM1293A-04SO SOT23-6
0.1U_0402_10V7K~N
22U_1206_6.3V6M
12 LAN_MIDI3- These components close to U64: Pin 48
MDI N3
2 2
1
R1255
2
2.49K_0402_1%
46 RSET FB12 4 +LAN_VDD12 ( Should be place within 200 mils )
R1256
10,23,24,28 PCIE_WAKE# PCIE_WAKE# 26 48 +LAN_SROUT12 W=60mils W=30mils R1259 W=30mils
ISOLATEB LANWAKEB SROUT12 0_0603_5%
+3VS 1 2 28 ISOLATEB
19 +LAN_EVDD12 2 1 +LAN_VDD
1K_0402_5% LAN_XTAL1 EVDD12
41 CKTAL1 DVDD12 30 +LAN_VDD12
2
LAN_XTAL2_R 42 36 1 2
R1257 CKTAL2 DVDD12 +3V_LAN_R
DVDD12 13 1 R1276 2 +3V_LAN C634 1U_0402_6.3V4Z
15K_0402_5% 10 0_0603_5% 1 2
AVDD12
10U_0603_6.3V
0.1U_0402_10V7K
1 1 C635 1U_0402_6.3V4Z
39 LED1_LED3
1
AVDD12
C643
C644
28 LAN_CABDT LAN_CABDT 23 44 These caps close to U64: Pin 19 LED2_LED3
NC VDDSR 2 2
24 NC VDDSR 45
LAN_LED0
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
7 GND VDD33 29
14 GND VDD33 37
C640
C641
C642
31 R1258
GND +LAN_AVDD33
47 GND AVDD33 1 1 2 +3V_LAN
0_0402_5% 40 0_0603_5%
LAN_LOPWEN 1 ISOLATEB AVDD33
28 LAN_LOPWEN 2 22 EGND ENSR 43 +3V_LAN_R 1 2
@ R1250 C636 0.1U_0402_16V7K~N
B B
1 2
RTL8111DL-GR_LQFP48 C637 0.1U_0402_16V7K~N
1 2
C638 0.1U_0402_16V7K~N
R230 1 @ 2 0_0402_5% LAN_XTAL1 1 2 JLAN1
11 PHY_25MHZ
C639 0.1U_0402_16V7K~N
2
LAN_LED0 1 R5 2 LED0_AD0_R 13
220_0402_5% Yellow LED-
R234 +3V_LAN 1 2 12
0_0402_5% LAN_XTAL2 1 LAN_XTAL2_R R1272 0_0402_5% Yellow LED+
0_0402_5%~D
2
R550
These caps close to U64: Pin 1, 29,37,40 RJ45_MDI3- 8
1
X5 TX3-
2 1 D21 RJ45_MDI3+ 7
LAN_LED21 LED2_LED3 TX3+
2
1 25MHZ_20P 1 RJ45_MDI1- 6
C298 C299 SDMK0340L-7-F TX1-
27P_0402_50V8J 27P_0402_50V8J RJ45_MDI2- 5
D22 TX2-
2 2 LAN_LED31 RJ45_MDI2+
2 4 TX2+
SDMK0340L-7-F RJ45_MDI1+ 3 TX1+
GND 14
T19 RJ45_MDI0- 2 15
C310 TX0- GND
GND 16
C304 1 2 0.01U_0402_16V7K 1 24 1 R236 2 CT 2 1 D23 RJ45_MDI0+ 1 17
LAN_MIDI3- TCT1 MCT1 RJ45_MDI3- 75_0402_1% LAN_LED11 LED1_LED3 TX0+ GND
2 TD1+ MX1+ 23 2 GND 18
LAN_MIDI3+ 3 22 RJ45_MDI3+ LED2_LED3 1 R22 2 LED2_RXDLY_R 11 19
TD1- MX1- 1000P_1206_2KV7K SDMK0340L-7-F 220_0402_5% Orange LED- GND
C305 1 2 0.01U_0402_16V7K 4 21 1 R239 2 LED1_LED3 1 R12 2 LED1_AD1_R 9
LAN_MIDI2- TCT2 MCT2 RJ45_MDI2- 75_0402_1% D24 220_0402_5% Green LED-
5 TD2+ MX2+ 20
LAN_MIDI2+ 6 19 RJ45_MDI2+ LAN_LED31 2 +3V_LAN 1 2 10
TD2- MX2- R1274 0_0402_5% Green-Orange LED+
A C306 0.01U_0402_16V7K A
1 2 7 TCT3 MCT3 18 1 R254 2 SDMK0340L-7-F
LAN_MIDI1- 8 17 RJ45_MDI1- 75_0402_1% TYCO_2041633-1
LAN_MIDI1+ TD3+ MX3+ RJ45_MDI1+
9 TD3- MX3- 16
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D D
1 GND
+1.5VS_CARD +3VS_CARD USB20_N3 R347 2 1 0_0402_5% USB20_N3_R 2
13 USB20_N3 USB_D-
(1A) (1.5A) 13 USB20_P3 USB20_P3 R348 2 1 0_0402_5% USB20_P3_R 3
C CPUSB# USB_D+ C
4 CPUSB#
5 RSV
6 RSV
+3VALW
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
10U_0805_4VAM~D
+3VS +1.5VS 24 SMB_CLK SMB_CLK R493 2 1 0_0402_5% SMB_CLK_R 7 SMB_CLK
10U_0805_4VAM~D
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
1 1 1 24 SMB_DATA SMB_DATA R494 2 1 0_0402_5% SMB_DATA_R 8 SMB_DATA
C523
C524
C525
1 1 1 +1.5VS_CARD 9 +1.5V
C526
C527
C528
10 +1.5V
R495 1 2 0_0402_5% 11
2 2 2 10,22,24,28 PCIE_WAKE# WAKE#
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
1 1 1 +3VS_CARD_AUX 12 +3.3VAUX
2 2 2
C529
C530
C531
PERST# 13 PERST#
U28 +3VS_CARD 14 +3.3V
15 +3.3V
2 2 2 EXP_CLKREQ# R496 1
12 1.5Vin 1.5Vout 11 10 EXP_CLKREQ# 2 0_0402_5% EXP_CLKREQ#_R 16 CLKREQ#
14 13 PEB_PRSNT# R497 1 2 0_0402_5% CPPE# 17
1.5Vin 1.5Vout 10 PEB_PRSNT# CPPE#
10 CLK_PCIE_EXPR# CLK_PCIE_EXPR# 18
CLK_PCIE_EXPR REFCLK-
10 CLK_PCIE_EXPR 19 REFCLK+
2 3 +3VS_CARD_AUX 20
3.3Vin 3.3Vout R501 1 GND
4 3.3Vin 3.3Vout 5 (0.5A) 10 PCIE_RX0_N 2 0_0402_5% PCIE_RX0_C_N 21 PERn0
10 PCIE_RX0_P R505 1 2 0_0402_5% PCIE_RX0_C_P 22 PERp0
17 AUX_IN AUX_OUT 15 23 GND
10 PCIE_TX0_N PCIE_TX0_N C47 2 1 0.1U_0402_16V7K PCIE_TX0_C_N 24 PETn0
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
10,22,24,26 PCIE_RST# PCIE_RST# 6 19 PCIE_TX0_C_P 25
SYSRST# OC# PCIE_TX0_P C46 PETp0
1 1 10 PCIE_TX0_P 2 1 0.1U_0402_16V7K 26 GND
C532
C533
20 8 PERST#
28,30,35 SYSON SHDN# PERST#
27 GND
28,30,36,37 SUSP# 1 STBY# NC 16 28 GND
2 2
29 GND GND 31
+3VALW @ R498 1 2 100K_0402_5% PEB_PRSNT# 10 7 30 32
CPPE# GND GND GND
B @ R499 1 B
2 100K_0402_5% CPUSB# 9 CPUSB#
FOX_1CX422AU1-BT_26P_RT-T
CONN@
18 RCLKEN
TPS2231MRGPR-1 QFN 20P
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Express Card
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4631P
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 23 of 42
5 4 3 2 1
A B C D E
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WLAN
W=60mils
+3VALW
Q43
+3VS
1 R308 2
+3V_WLAN
D
6 0_0805_5%
S
1 5 4
@ 330U_D2E_6.3VM_R25~D
C521 2
G
2
1 1 1
3
B+_BIAS C322 C323 C324 C535 +
@
2
2 2 2 2
1 R374 1
470K_0402_5%
@
1
EN_WLAN
2
D +1.5VS
2 Q44 R368
28 EN_WLAN#
G SSM3K7002FU_SC70-3 1.5M_0402_5%
+1.5VS +3V_WLAN S @ @
3
1 1
1
JMINI1 C320 C321
10,22,23,28 PCIE_WAKE# PCIE_WAKE# 1 2 0.01U 16V K X7R 0402 0.01U 16V K X7R 0402
WLAN_ACT R260 1 1 2
27 WLAN_ACT 2 0_0402_5% WLAN_ACT_R 3 3 4 4
BT_PRI R261 1 2 2
27 BT_PRI 2 0_0402_5% BT_PRI_R 5 5 6 6
10 WLAN_CLKREQ# W LAN_CLKREQ# R262 1 2 0_0402_5% WLAN_CLKREQ#_R 7 8 LPC_FRAME#_RR263 1 2 0_0402_5% LPC_FRAME# 12,28
7 8 LPC_AD3_R R264 0_0402_5% LPC_AD3
9 9 10 10 1 2
10 CLK_PCIE_WLAN# CLK_PCIE_WLAN# 11 12 LPC_AD2_R R265 1 2 0_0402_5% LPC_AD2
CLK_PCIE_WLAN 11 12 LPC_AD1_R R266 0_0402_5% LPC_AD1 +3VS
10 CLK_PCIE_WLAN 13 13 14 14 1 2
15 16 LPC_AD0_R R267 1 2 0_0402_5% LPC_AD0
PLT_RST# R268 1 PLT_RST#_R 15 16
12,28 PLT_RST# 2 0_0402_5% 17 17 18 18 LPC_AD[0..3] 12,28
LPC_CLK0 R282 1 2 0_0402_5% LPC_CLK0_R 19 20 WL_RADIO_OFF#
12,28 LPC_CLK0 19 20 WL_RADIO_OFF# 28
21 22 PCIE_RST_R# R37 1 2 0_0402_5%
21 22 PCIE_RST# 10,22,23,26
1
10 PCIE_RX2_N R102 1 2 0_0402_5% PCIE_RX2_C_N 23 24 R270 1 2 0_0402_5% +3VALW
R112 1 23 24
10 PCIE_RX2_P 2 0_0402_5% PCIE_RX2_C_P 25 25 26 26 SMB_CLK_WLAN R299 1 2 0_0402_5% SMB_CLK R1294 R1295
27 28 SMB_DATA_WLANR281 1 2 0_0402_5% SMB_DATA 2.2K_0402_5% 2.2K_0402_5%
27 28 R1288 1 @ 0_0402_5% MCP_SMB_CLK
29 29 30 30 2
PCIE_TX2_N C51 2 1 0.1U_0402_16V7K PCIE_TX2_C_N 31 32 R1289 1 @ 2 0_0402_5% MCP_SMB_DATA Q56
10 PCIE_TX2_N
2
PCIE_TX2_C_P 31 32 SSM3K7002FU_SC70-3
33 33 34 34
PCIE_TX2_P C50 2 1 0.1U_0402_16V7K 35 36 USB20_N7_R R273 1 2 0_0402_5% USB20_N7
10 PCIE_TX2_P 35 36 USB20_N7 13
USB20_P7_R R278 1 2 0_0402_5% USB20_P7 MCP_SMB_CLK 1 SMB_CLK
S
37 37 38 38 USB20_P7 13 14 MCP_SMB_CLK 3 SMB_CLK 23
+3V_WLAN 39 39 40 40
2 2
41 41 42 42
43 44 PCIE_RST_R#
G
2
43 44 @ @
45 45 46 46
S
14 MCP_SMB_DATA 1 3 SMB_DATA 23
2 2 1
53 GND1 GND2 54
G
2
TYCO_1775861-1~D +5VS
R1296
CONN@
2 1
2.2K_0402_5%
WWAN
+1.5VS +3VS
JMINI2
U23
1 1 2 2
3 3 4 4 1 CH1 CH4 6
3 3
5 5 6 6
7 7 8 8 +UIM_PWR 2 Vn Vp 5
9 10 UIM_DATA
9 10 UIM_CLK
11 11 12 12 3 CH2 CH3 4
13 14 UIM_RST +UIM_PWR +3VS
13 14 UIM_VPP S DIO(BR) NUP4301MR6T1 TSOP-6
15 15 16 16
17 18 D9 @
17 18 WAN_RADIO_OFF# JSIM1
19 19 20 20 WAN_RADIO_OFF# 28 3
21 22 PCIE_RST# 2 1 1
21 22 R275 1 PCIE_RST# 10,22,23,26 GND VCC
23 23 24 24 2 0_0402_5% +3VALW UIM_VPP 4 VPP RST 3 UIM_RST 2
25 26 UIM_DATA 6 5 UIM_CLK
25 26 UIM_DET I/O CLK DAN217_SC59-3
27 27 28 28 28 UIM_DET 7 DET
29 30 SMB_CLK_WWAN R276 1 2 0_0402_5% SMB_CLK 8
29 30 SMB_DATA_WWAN R277 1 DET
31 31 32 32 2 0_0402_5% SMB_DATA
33 33 34 34
35 36 USB20_N6_R R279 1 2 0_0402_5% USB20_N6 9 1 1
35 36 USB20_N6 13 GND
37 38 USB20_P6_R R280 1 2 0_0402_5% USB20_P6 C571 10 C573 C329 C330
37 38 USB20_P6 13 GND
100P_0402_25V8K
+3VS 39 39 40 40 100P_0402_25V8K
47 47 48 48 1 1
49 49 50 50
51 51 52 52
+3VS
2 2
53 GND1 GND2 54 C571 & C573 as close as JSIM1
0.01U 16V K X7R 0402
@ 330U_D2E_6.3VM_R25~D
@ 330U_D2E_6.3VM_R25~D
0.1U 16V K X7R 0402
TYCO_1775861-1~D
1 1 1 1 1 CONN@
C331 C332 C333 C575
+ C574 +
4 4
2 2 2
2 2 +1.5VS
1 1
C334 C335
0.01U 16V K X7R 0402 0.01U 16V K X7R 0402 Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 Issued Date 2009/02/19 Deciphered Date 2009/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini Card_WLAN/WWAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4631P
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 24 of 42
A B C D E
A B C D E F G H
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+DVDD_AUDIO +3VS
+AVDD_AUDIO +5VS
1 R271 2 R229 HP2_LEFT
0.1U_0402_10V6K
0.1U_0402_10V6K
0_0603_5% +AVDD_AUDIO 1 2 HP1_LEFT HP2_RIGHT
1U_0603_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
ACZ_BITCLK ACZ_SDOUT 1 1 1 0_0805_5% HP1_RIGHT
10U_0603_6.3V
10U_0603_6.3V
C338
C339
C340
1U_0603_10V6K
1U_0603_10V6K
1 1 1 1 1 1
2
C341
C342
C343
C344
C345
C346
1
R287 R306 D D
1
2 2 2 D D Q47 Q48
0_0402_5% 0_0402_5% 2 2
2 2 2 2 2 2 Q51 Q52 G G SSM3K131TU_SOT323-3
2 2 SSM3K131TU_SOT323-3
SSM3K131TU_SOT323-3 G G SSM3K131TU_SOT323-3 S S
1
3
S S C D
3
10P_0402_50V8J
10P_0402_50V8J
1 1 A B
3
S S
C572
C602
Q50
27
38
39
45
3
3
S S G G
U25 G G Q49 2 2
1 Q53 Q54 1
2 2 SSM3K131TU_SOT323-3
DVDD_IO
DVDD
DVDD_CORE
AVDD
AVDD
PVDD
PVDD
2 2 SSM3K131TU_SOT323-3
SSM3K131TU_SOT323-3
D D
1
D D SSM3K131TU_SOT323-3
1
R287 & C572 Close U25 pin6 R1290 56_0402_5% HP_MUTE
14 ACZ_BITCLK 1 R286 2 0_0402_5% 6 HDA_BITCLK HP0_PORT_A_L 28 HP1_LEFT_R 1 2 HP1_LEFT
HP1_LEFT 29
HP_MUTE
29 HP1_RIGHT_R 1 2 HP1_RIGHT
HP0_PORT_A_R HP1_RIGHT 29
14 ACZ_SDIN0 1 R288 2 33_0402_5% 8 HDA_SDI VREFOUT_A_or_F 23 R1291 56_0402_5%
R1292 56_0402_5%
1 R290 2 0_0402_5% 5 31 HP2_LEFT_R 1 2 HP2_LEFT
14 ACZ_SDOUT HDA_SDO HP1_PORT_B_L HP2_LEFT 29
32 HP2_RIGHT_R 1 2 HP2_RIGHT
HP1_PORT_B_R HP2_RIGHT 29
14 ACZ_SYNC 1 R291 2 0_0402_5% 10 HDA_SYNC
R1293 56_0402_5%
19 MIC_LEFT
PORT_C_L MIC_LEFT 29
14 ACZ_RST# 1 R293 2 0_0402_5% 11 HDA_RST# PORT_C_R 20 MIC_RIGHT
MIC_RIGHT 29
HP1_LEFT HP2_LEFT
24 +MIC1_VREFO HP1_RIGHT HP2_RIGHT
VREFOUT_C
27 DMIC_CLK 1 R294 2 33_0402_5% 2 DMIC_CLK/GPIO1
40 SPKER_L1
SPKR_PORT_D_L+
27 DMIC_DATA 1 R295 2 0_0402_5% 4 DMIC0/GPIO2 SPKR_PORT_D_L- 41 SPKER_L2
1
@ D D @ @ D D @
1 1 46 Q59 2 2 Q60 Q61 2 2 Q62
@ C593 @ C594 DMIC1/GPIO0/SPDIF_OUT_1 2N7002_SOT23 G G 2N7002_SOT23 2N7002_SOT23 G G 2N7002_SOT23
48 43 SPKER_R1 S S S S
3
100P_0402_50V 100P_0402_50V SPDIF_OUT_0 SPKR_PORT_D_R- SPKER_R2 A B C D
SPKR_PORT_D_R+ 44
2 2 EC_MUTE# 2 R297 1 EAPD 47 EAPD
@ @ @ @
3
S S S S
0_0402_5% 15 Q63 Q64 Q65 Q66
PORT_E_L 2N7002_SOT23
G G
2N7002_SOT23 2N7002_SOT23
G G
2N7002_SOT23
1 2 35 CAP- PORT_E_R 16 2 2 2 2
C352 2.2U_0603_6.3V4Z
36 17 PC_BEEP D D D D
1
CAP+ PORT_F_L
PORT_F_R 18
1 2 SENSE B 14 12 MONO_IN
2 R298 20K_0402_1% SENSE_B PC_BEEP HP_MUTE HP_MUTE 2
MONO_OUT 25
HP1_JD 2 1 SENSE A 13
29 HP1_JD SENSE_A
R300 39.2K _0402_1% 22
HP2_JD CAP2
29 HP2_JD 1 2 49 GPAD
R301 20K_0402_1% 7 21
MIC_JD DVSS VREFFILT
29 MIC_JD 1 2 42
R303 10K_0402_1% 26
PVSS
AVSS V- 34
Co-lay schematic
2.2U_0603_6.3V4Z
30 AVSS
33 AVSS VREG 37
10U_0603_6.3V
1U_0603_10V6K
1 1 1 1
C354
C355
C356
EC_MUTE# 92HD83C1X5NLGXYBX8 QFN 48P CODEC C353
28 EC_MUTE#
4.7U_0603_6.3V
2 2 2 2
C358 1U_0603_10V6K
1 2 2 1 2 R393 1 0_0402_5% PC_BEEP
EC Beep 28 BEEP#
R307 20K_0402_1% +AVDD_AUDIO +AVDD_AUDIO +DVDD_AUDIO
1
R310 20K_0402_1%
1
R272 R389
2.49K_0402_1% 2.49K_0402_1% R304
2
10K_0402_5%
R315
2
2.2K_0402_5%
2
3 SENSE A SENSE B 3
EAPD
1
1
+5VALW C313 C314
1000P_0402_50V7K~D 1000P_0402_50V7K~D
2
2
R1287
C243
10K_0402_1%
SPKER_L1 TWSPK_L1
PLACE CLOSE TO CODEC PIN 13 PLACE CLOSE TO CODEC PIN 13
1
10U_0603_6.3V6M~D
HP_MUTE
C244 If SENSE_A total length is greater If SENSE_B total length is greater
SPKER_L2 TWSPK_L2 than 6 inches, change C313 to 0.1uF. than 6 inches, change C314 to 0.1uF.
1
D
10U_0603_6.3V6M~D EC_MUTE# 2 Q55
G SSM3K7002FU_SC70-3
If ports E and F are unused,
C245 simply pull-up SENSE_B to
S
3
SPKER_R1 TWSPK_R1
TWSPK_R1 29
AVDD with a 100K-ohm resistor.
10U_0603_6.3V6M~D JSPK1
SPKER_L1 1 JTWL2
C246 1
SPKER_L2 2 TWSPK_L1 1
SPKER_R2 TWSPK_R2 SPKER_R1 2 TWSPK_L2 1
TWSPK_R2 29 3 3 2 2
SPKER_R2 4 4
100P_0402_50V
100P_0402_50V
100P_0402_50V
100P_0402_50V
10U_0603_6.3V6M~D 5 3
GND GND
PACDN042_SOT23-3~D
PACDN042_SOT23-3~D
1 1 1 1 6 GND 4 GND
3
C595
C596
C597
C598
D5 D10
2
MOLEX_53780-0470 MOLEX_53780-0270~D
Reserved for TEST @ @ @ @ CONN@ D11 CONN@
4 2 2 2 2 4
@ @
ROW PESD5V0U2BT 3P C/C SOT23 ESD
1
1
R320 1 2 0_0805_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/19 Deciphered Date 2009/12/31 Title
GND AGND THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Codec IDT 92HD83
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4631P
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 25 of 42
A B C D E F G H
5 4 3 2 1
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D D
+1.8VS_CR
W=30 mil These caps close to U26 pin5. These caps close to U26 pin10.
1 1 1 1 1
C386
C368 C367 C366 C369 10U_0805_10V4Z
@
2 2 2 2 2
1000P_0402_50V7K 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
+3VS
U26 1 1 1 W>40 mil
C388
CLK_PCIE_1394# 3 5 C373 C374 10U_0805_10V4Z
10 CLK_PCIE_1394# APCLKN APVDD
CLK_PCIE_1394 4 10 @
10 CLK_PCIE_1394 APCLKP APV18 2 2 2
C375 1 2 0.1U_0402_16V7K
10 PCIE_TX3_N
PCIE_TX3_C_N 9 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C376 1 APRXN
10 PCIE_TX3_P 2 0.1U_0402_16V7K PCIE_TX3_C_P 8 APRXP DV33 19
DV33 20
C395 1 2 0.1U_0402_16V7K PCIE_RX3_C_N 11 44
C 10 PCIE_RX3_N APTXN DV33 C
PCIE_RX3_C_P 12 18 +1.8VS_CR
C396 1 APTXP DV18
10 PCIE_RX3_P 2 0.1U_0402_16V7K DV18 37 1 1 1
R337 1 2 8.2K_0402_5% APREXT 7 C389
APREXT C377 C378 10U_0805_10V4Z
MDIO0 48
47 @
+3VS JMB_XIN MDIO1 2 2 2
W=12 mil @ JMB_XOUT
38 TXIN MDIO2 46
0.1U_0402_16V4Z 0.1U_0402_16V4Z
39 45
1 2
TXOUT JMB380 MDIO3
MDIO4 43
C387 10U_0805_10V4Z 42
MDIO5
1 2 30 TAV33 MDIO6 41
C379 0.1U_0402_16V4Z 40 MDIO7 R325 1 2 10K_0402_5% +3VS
MDIO7
MDIO8 29
PCIE_RST# R338 1 2 0_0402_5% XRSTN 1 28
10,22,23,24 PCIE_RST# XRSTN MDIO9
2 XTEST MDIO10 27
MDIO11 26
25 MDIO12 R329 1 2 200K_0402_5%
T22 MDIO12
13 SEEDAT MDIO13 23
T23 14 22 MDIO14 R327 1 2 200K_0402_5%
SEECLK MDIO14
34 IEEE_TPA1P
R342 1 TPA1P TPBIAS
+3VS 2 4.7K_0402_5% 15 CR1_CD1N TPBIAS_1 35
R343 1 2 4.7K_0402_5% 16 36 TREXT R340 1 2 12K_0402_1%
CR1_CD0N TREXT
17
APGND 6 Close to U26.
CR1_PCTLN TCPS R341 1
TCPS 24 2 10K_0402_5%
31 IEEE_TPB1N
TPB1N IEEE_TPB1P
21 CR1_LEDN TPB1P 32
IEEE_TPA1N
W=10 mil
TPA1N 33
49 IEEETP
GPAD
1
B JMB380-QGAZ0B_QFN48_7X7 R345 R538 B
1
1 56_0402_5% 56_0402_5%
C382 R344
220P_0402_50V7K 4.99K_0402_1%
2
2 IEEE_TPB1N
Close to U26 pin38, pin39. (L<500mil). IEEE_TPB1N 29
2
IEEE_TPB1P
IEEE_TPB1P 29
IEEE_TPA1N
IEEE_TPA1N 29
W=7 mil IEEE_TPA1P
C370 IEEE_TPA1P 29
2 1 JMB_XIN 1
1
22P_0402_50V8J C383 R539 R540
1
2
2
TPBIAS
C372
2
R551
2 1 1 2 JMB_XOUT W=10 mil
0_0402_5%~D
22P_0402_50V8J W=7 mil
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IEEE1394_JMB380
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4631P
Date: Tuesday, February 24, 2009 Sheet 26 of 42
5 4 3 2 1
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+5VALW +USB_AS W=80mils
L19 WCM2012F2S-900T04_0805 JUSBP1
W=80mils U32 W=80mils Close to USB Connector. USB20_N0 1 1
13 USB20_N0 2 2 USB_N0
+USB_AS 1 VBUS
1 GND OC1# 8 2 D-
2 7 USB_P0 3
IN OUT1 USB20_P0 D+
3 EN1# OUT2 6 1 13 USB20_P0 4 4 3 3 4 GND
1 28,29 USB_EN# USB_EN# 4 5
C445 EN2# OC2# + C443 C444 5 GND1
TPS2062ADR_SO8~D 6 GND2
30K_0402_5%
0.1U_0402_16V4Z
150U_B2_6.3VM_R45M
0.1U_0402_16V4Z 7
2 2 GND3
8 GND4
13 USB_OC#0 R385
SUYIN_020173MR004S52GZL
2
1
D
USB_EN# 2 Q8
G
1
SSM3K7002FU_SC70-3 change JUSBP1 connect signal (for layout)
S Bluetooth
3
R388
100K_0402_5%
@
2
+3VS
USB_N0
USB_P0
Camera Conn JBT1
L30 WCM2012F2S-900T04_0805 28 BT_DET BT_DET 1 2
1 2 BT_PRI 24
1 1 2 2 24 WLAN_ACT 3 3 4 4
28 BT_OFF# BT_OFF# 5 6 USB20_P5_R 2 R398 10_0402_5%
5 6 USB20_P5 13
2
28 BT_RADIO_OFF# BT_RADIO_OFF# 7 8 USB20_N5_R 2 R400 10_0402_5%
7 8 USB20_N5 13
4 3 9 10 D20
4 3 9 10
11 11 12 12 ROW PESD5V0U2BT 3P C/C SOT23 ESD
13 13 14 14
JCA1 15 GNDGND 16
USB20_P4 USB_P4 1
13 USB20_P4 1
USB20_N4 USB_N4 2
13 USB20_N4
1
L21 2 2 USB20_P5_R
+3VS 1 MBK1608221YZF 0603 3 3
HRS_CL537-0918-4-86
25 DMIC_CLK DMIC_CLK R74 1 2 0_0603_1% 4 CONN@ USB20_N5_R
4
5 5
25 DMIC_DATA DMIC_DATA 6 6
AS CLOSE AS JCA1
2 2
100P_0402_50V 100P_0402_50V
CLOSE TO U48
1 @ C655
1
0.1U_0402_16V4Z
R1303 R1304 D33
10K_0402_1% 100K_0402_1%~D SDMK0340L-7-F 51ON#
2 51ON# 29,32
2
C654
1
D
1
P
USB_DETECT# NC Q58
29 USB_DETECT# 2 1 2 A Y 4 2
G 2N7002_SOT23
G
2.2U_10V_K X7R_0603 S
3
U48
3
TC7SZ14FU_SSOP5~D
1
R1305
100K_0402_5%
2
2 1 USB_DET#_DELAY
USB_DET#_DELAY 28
D31
SDMK0340L-7-F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB/BlueTooth/FP/Felcia
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4631P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Www.alliancelaptoptraining.com
Date: Tuesday, February 24, 2009 Sheet 27 of 42
L17
+3VALW +EC_AVCC 2 1
+EC_AVCC +3VALW Board ID
Www.alliancelaptoptraining.com
1 2 MURATA BLM18AG601SN1D 0603 +3VALW
C397
C398
1 1 1 1 1 1 1000P_0402_50V7K~N 0.1U_0402_16V4Z~N
0.1U_0402_16V4Z~N
C399
0.1U_0402_16V4Z~N
C400
0.1U_0402_16V4Z~N
C401
0.1U_0402_16V4Z~N
C402
1000P_0402_50V7K~N
C403
1000P_0402_50V7K~N
C404
2
ECAGND2 1
2 1 Page 3 Note List
MURATA BLM18AG601SN1D 0603 L18 R350
2 2 2 2 2 2
Ra 100K_0402_5%
1
AD_BID
1
111
125
1
200K_0402_5%
22
33
96
67
9
U29 R352 C405
0.1U_0402_16V4Z
Rb
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
2
2
R559 0_0402_5%~D
EC_GA20 1 21 1 2
14 EC_GA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM 20
EC_KBRST# 2 23 BEEP# M/B rev:0.1; 0.2; 0.3; 0.4; 0.5; 1.0
14 EC_KBRST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# 25
SERIRQ 3 26 SLP_MCP79_MAC#
12 SERIRQ SERIRQ# FANPWM1/GPIO12 SLP_MCP79_MAC# 11 Voltage:0.0; 0.4; 0.8; 1.2; 1.65; 2.2
LPC_FRAME# 4 27 ACOFF
12,24 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 33
LPC_AD3 5
12,24 LPC_AD3 LAD3
LPC_CLK0 LPC_AD2 7 PWM Output C406 1 2 0.01U_0402_16V7K ECAGND
12,24 LPC_AD2 LAD2
LPC_AD1 8 63 BATT_TEMP
12,24 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 39
1
LPC_AD0 BATT_OVP
R356
12,24 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
BATT_OVP 39
ADP_I/AD2/GPIO3A 65 ADP_I 33
LPC_CLK0 12 AD Input 66 AD_BID
12,24 LPC_CLK0 PCICLK AD3/GPIO3B
@ 10_0402_5% R357 PLT_RST# 13 75 R1260 1 @ 2 0_0402_5%~D
12,24 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42 LAN_CABDT 22
1 2 EC_RST# 37 76
+3VALW LCD_DET# 20
2
USB_EN2#
R500 2
R502 2
1 4.7K_0402_5% KSO2
KSO3
KSO4
41
42
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23 SDICS#/GPXOA00 97
R361
2
STB_LAN#
0_0402_5%
1HDMI_DET_C HDMI_DET_C 21
SPI Flash (16Mb*1)
1 4.7K_0402_5% 43 KSO4/GPIO24 SDICLK/GPXOA01 98 STB_LAN# 30
@ C409
KSO5 BT_OFF# 2SPI_CLK_R
Low Enable
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 BT_OFF# 27 1
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW_D# 1 2 LID_SW# 14
KSO7 46 SPI Device Interface @ D2 0.1U_0402_16V4Z~N
KSO8 KSO7/GPIO27 SDMK0340L-7-F +3VALW
47 KSO8/GPIO28
KSO9 48 119 FRD#SPI_SO C410
KSO10 KSO9/GPIO29 SPIDI/RD# 20mils
49 KSO10/GPIO2A SPIDO/WR# 120 FWR#SPI_SI 1 2
KSO11 50 SPI Flash ROM SPICLK/GPIO58 126 SPI_CLK 2 R365 1
+3VS KSO12 KSO11/GPIO2B
51 KSO12/GPIO2C SPICS# 128 FSEL#SPICS# 0.1U_0402_16V4Z~N 10K_0402_5%
KSO13 52 U30
EC_SMB_DA2 KSO14 KSO13/GPIO2D FSEL#SPICS# 2
R362 2 1 4.7K_0402_5% 53 KSO14/GPIO2E 1SPI_CS# 1 CS# VCC 8
KSO15 54 73 USB_DET#_DELAY R367 15_0402_5% 2 7
KSO15/GPIO2F CIR_RX/GPIO40 USB_DET#_DELAY 27 SO HOLD#
EC_SMB_CK2 R363 2 1 4.7K_0402_5% KSO16 81 74 USBSW_EN# FRD#SPI_SO 1 2SPI_SO 3 SPI_CLK_R1 R370
6 2 SPI_CLK
KSO16/GPIO48 CIR_RLC_TX/GPIO41 USBSW_EN# 29 WP# SCLK
DIAG_LOOP3 82 89 FSTCHG 15_0402_5% R369 4 15_0402_5%
5
29 DIAG_LOOP3 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG 33 GND SI
90 BATT_CHG_LED# SPI_SI 1 R372 2 FWR#SPI_SI
BATT_CHGI_LED#/GPIO52 BATT_CHG_LED# 29
91 CAPSLED# MX25L1605DM2I-12G SOP 8P ROM 15_0402_5%
CAPS_LED#/GPIO53 CAPSLED#
BT_RADIO_OFF# R366 2 1 4.7K_0402_5% EC_SMB_CK1 77 GPIO BATT_LOW_LED#/GPIO54 92 BATT_LOW_LED#
39 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED# 29
EC_SMB_DA1 78 93 EN_WLAN#
39 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 EN_WLAN# 24
WAN_RADIO_OFF# R402 2 1 4.7K_0402_5% EC_SMB_CK2 79 SM Bus 95 SYSON
4 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 23,30,35
4 EC_SMB_DA2 EC_SMB_DA2 80 121 VR_ON
SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 14,38
WL_RADIO_OFF# R403 2 1 4.7K_0402_5% 127 ACIN
AC_IN/GPIO59 ACIN 14,32,33
PM_SLP_S3# EC_RSMRST# 14
14 PM_SLP_S3# 6 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 100 EC_RSMRST#
PM_SLP_S5# 14 101 EC_LID_OUT#
+5VS 14 PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 14
EC_SMI# 15 102 EC_ON @
14 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 29
R376 LCD_TST 16 103 R1251
1 20_0402_5% D13 RB751V_SOD323
20 LCD_TST LID_SW#/GPIO0A EC_SWI#/GPXO06 PCIE_WAKE# 10,22,23,24
4.7K_0402_5% BT_RADIO_OFF#17 104 MCP_PWRGD_EC 1 2 MCP_PWRGD
27 BT_RADIO_OFF# SUSP#/GPIO0B ICH_PWROK/GPXO06 MCP_PWRGD 14
TP_DATA 1 2 UIM_DET 18 GPO 105 BKOFF#
24 UIM_DET PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 20
TP_CLK 1 2 32 PS_ID PS_ID 19 GPIO 106 WAN_RADIO_OFF# 1 2 1 2 +3VS
EC_PME#/GPIO0D WL_OFF#/GPXO09 WAN_RADIO_OFF# 24
R377 29 KB_BL_PWM# KB_BL_PWM# 25 107 LCD_VCC_TEST_EN R378 0_0402_5% R379 10K_0402_5%
4.7K_0402_5% FAN_SPEED1 28 EC_THERM#/GPIO11 GPXO10 LCD_VCC_TEST_EN 20
4 FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 108 PSID_DISABLE# PSID_DISABLE# 32
@
+3VALW WL_RADIO_OFF# 29
24 WL_RADIO_OFF# FANFB2/GPIO15
E51_TXD 30 Close to U29 Close to U30
EC_MUTE# R380 1 @ EC_TX/GPIO16
2 10K_0402_5% 21 DP_HPD
0_0402_5%2 1R555 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 VGATE VGATE 14,38 SPI_CLK SPI_CLK_R
ON_OFF 32 112 EC_ENBKL
29 ON_OFF ON_OFF/GPIO18 ENBKL/GPXID2
EN_KBL# R392 1 2 10K_0402_5% PWR_BTN_LED# 34 114 MCP79_ENVDD MCP79_ENVDD 11,20 1 1
29 PWR_BTN_LED# PWR_LED#/GPIO19 GPXID3
EN_KBL# 36 GPI 115 BT_DET BT_DET 27 @ @
29 EN_KBL# NUMLED#/GPIO1A GPXID4
LID_SW_D# R397 1 2 10K_0402_5% 116 SUSP# 11 MCP79_ENBKL 2 R213 1 EC_ENBKL C645 C646
GPXID5 SUSP# 23,30,36,37
117 PWRBTN# 0_0402_5% 22P_0402_50V8J 22P_0402_50V8J
GPXID6 PWRBTN# 14
1
KSO1 R375 1 BKLT_KB_DET# 2 2
2 47K_0402_5% GPXID7 118 BKLT_KB_DET# 29
XCLKI 122 R214
KSO2 R401 1 XCLK1
2 47K_0402_5% XCLKO 1 2 123 XCLK0 V18R 124 +V18R 10K_0402_5%
R552 C411 4.7U_0603_6.3V6K
AGND
2
2 1
EC_SMB_CK1 R360 2 1 4.7K_0402_5% C412 0.1U_0402_16V4Z
KB926QFD3 LQFP 128P
11
24
35
94
113
69
22K_0402_5%
22K_0402_5%
100K_0402_5%
1K_0402_1%
R198 1
R364 2
1
+3VALW
JHS1
For ENE Debug 1 1
R1285
R1286
1 C413 C414
1
1
2 LID_SW_D#
2
2 R1270 0_0603_1% 22P_0402_50V8J X3 22P_0402_50V8J
3
IN
OUT
3 KSI4 1 @ 2 2
2 KSI5
4 R1271 0_0603_1%
GND KSI6 1
GND 5 @ 2 KSI7
NC
NC
MOLEX_53780-0370~D
R553 @ 0_0603_1%
Security Classification Compal Secret Data 0.5A perCompal
each pinElectronics, Inc.
2
1 2 E51_TXD
Issued Date 2009/02/19 Deciphered Date 2009/12/31 Title
32.768KHZ_12.5P_1TJS125BJ2A251
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4631P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Www.alliancelaptoptraining.com
Date: Tuesday, February 24, 2009 Sheet 28 of 42
A B C D E
Www.alliancelaptoptraining.com +3VALW
INT_KB_Conn.1
28 DIAG_LOOP3
DIAG_LOOP3
KSI7
JKB1
1
2
1
Power Button KSI6 3
2
3
KSI0 C542 100P_0402_25V8K KSO6 C556 100P_0402_25V8K
100K_0402_5%
KSI4 4
KSI2 4 KSI1 C543 100P_0402_25V8K KSO7 C557 100P_0402_25V8K
5 5
R382
KSI[0..7] KSI5 6
28 KSI[0..7] 6
KSI1 7 KSI2 C544 100P_0402_25V8K KSO8 C558 100P_0402_25V8K
KSO[0..16] KSI3 7
28 KSO[0..16] 8
1
D14 KSI0 8 KSI3 C545 100P_0402_25V8K KSO9 C559 100P_0402_25V8K
9 9
2 KSO5 10
ON_OFF 28 10
PWR_ON-OFF_BTN# 1 KSO4 11 KSI4 C546 100P_0402_25V8K KSO10 C560 100P_0402_25V8K
51ON# KSO7 11
3 51ON# 27,32 12 12
1 KSO6 KSI5 C547 100P_0402_25V8K KSO11 C561 100P_0402_25V8K 1
13 13
ROW BAV70W-7-F 3P C/C SOT-323 KSO8 14
KSO3 14 KSI6 C548 100P_0402_25V8K KSO12 C562 100P_0402_25V8K
15 15
KSO1 16 16
1
KSO2 17 KSI7 C549 100P_0402_25V8K KSO13 C563 100P_0402_25V8K
17
1
@ KSO0 18
C435 D15 KSO12 18 KSO0 C550 100P_0402_25V8K KSO14 C564 100P_0402_25V8K
19 19
1U_0805_25V4Z~D RLZ20A_LL34 KSO16 20
2
KSO15 20 KSO1 C551 100P_0402_25V8K KSO15 C565 100P_0402_25V8K
21
2
KSO13 21
22 22
1
D KSO14 KSO2 C552 100P_0402_25V8K KSO16 C566 100P_0402_25V8K
23 23
EC_ON 1 2 2 KSO9 24
28 EC_ON 24
R384 G Q7 KSO11 25 KSO3 C553 100P_0402_25V8K DIAG_LOOP3 C567 100P_0402_25V8K
0_0402_5% 25
S SSM3K7002FU_SC70-3 KSO10 26
3
26 KSO4 C554 100P_0402_25V8K
27 27
1
28
R383 29
30
28
29 GND 31
32
KSO5 C555 100P_0402_25V8K For EMI
10K_0402_5% 30 GND
+3VS
2
TYCO_3-2041084-0
1
+5VS Q41 R157 JBTB1
2
5 6
D
6 0.75A_24V_1812L075-24DR 7 8
S
USB20_N2 7 8
5 4 2 1 13 USB20_N2 9 9 10 10
1 2 20mil BKLT_KB_DET# USB20_P2 11 12
BKLT_KB_DET# 28 13 USB20_P2 11 12
C415 1 1 2 13 14
2 1U_0603_10V6K R305 SATA_A1_TXP 13 14 2
15 16
G
13 SATA_A1_TXP 15 16
1
0_0805_5% D SATA_A1_TXN
13 SATA_A1_TXN 17 18 +3VALW
3
1
S SATA_A1_RXP 23 24 MIC_JD
13 SATA_A1_RXP MIC_JD 25
3
23 24
2
IEEE_TPA1N 31 32 HP2_RIGHT
26 IEEE_TPA1N 33 34 HP2_RIGHT 25
1
D
2 Q40
28 KB_BL_PWM# G MMBF170-7-F NPN SOT-23 61
GND
S 62
3
GND
20mil E-T_1001-F60E-03R
CONN@
3 3
CONN@
+5VS TYCO_2041084-4
4 4 GND 6
TP_DATA 3 5
28 TP_DATA 3 GND
TP_CLK 2
28 TP_CLK 2
1 1
1
JTP1
C440
0.01U_0402_16V7K
3
2
100P_0402_25V8K C442
100P_0402_25V8K C441
1 1
D16
PESD5V0U2BT 3P C/C SOT23 ESD
2 2
1
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_OK/BTN/TP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4631P 1.0
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 29 of 42
A B C D E
A B C D E
Www.alliancelaptoptraining.com
+3VALW to +3VS Transfer +5VALW to +5VS Transfer +1.05VALW to +VCCP Transfer
+3VALW +3VS
B+_BIAS +5VALW +5VS +1.05VALW +VCCP
U42 B+_BIAS
8 1 10U_0805_10V4Z~N U43 U44
1 D S 10U_0805_10V4Z~N
7 D S 2 8 D S 1 8 D S 1
47K_0402_5%
R461 1 6 3 7 2 7 2
D S D S D S
R462
5 D G 4 1 1 1 6 D S 3 1 6 D S 3
330K_0402_5% C497 C498 C499 C500 5 4 1 1 5 4 1 1
AO4478L 1N SO8 D G C502 C503 C501 D G C504 C505
2
1
2 2 2 10U_0805_10V4Z~N 10U_0805_10V4Z~N 2 10U_0805_10V4Z~N 0.1U_0402_16V4Z~N
RUNON 3VS_GATE 2 2 2 2
1 2
R463 1 RUNON 1 2 1 5VS_GATE 0.1U_0402_16V4Z~N
100K_0402_5% 0.1U_0402_16V4Z~N R464 C507
C506 47K_0402_5%
1
1
D 0.01U_0402_25V7K~N
SUSP 2
2
G Q19
S SSM3K7002FU_SC70-3
3
+3VALW TO +3V_LAN
+3VALW +3V_LAN +1.5V to +1.5VS Transfer +3VALW to +3V_DP Transfer +3VS
U45 R1278
8 1 B+_BIAS 0_0805_5%
D S +1.5V +1.5VS +3VALW +3V_DP
7 D S 2 1 2
6 D S 3 1 1 2 U46 B+_BIAS
1
1 1 5 4 C510 C511 8 1 U47
D G D S
10U_0805_10V4Z~D
20K_0402_5%~D
C512 C513 R467 R466 7 2 8 1 10U_0805_10V4Z~N
D S D S
1
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
C514
R468
1U_0603_10V4Z 5 4 R557 1 6 3
1
2 2 2 D G @ D S 2
5 4 1 @ 1 @
2
R469 AO4478L 1N SO8 330K_0402_5% C609 D G C610 C611
1
D 2 @ AO4478L 1N SO8
1 2
2
R503 Q21 STB_LAN# 2 10U_0805_10V4Z~N
2 1
1
0_0402_5%~D G D 0_0402_5%~D C515 2 2
B+_BIAS
2 1 1 2 S 2N7002_SOT23 SUSP 2 R UN_DP 1 2 3DP_GATE
3
3
1
D C516 @ C612
1
D
332K_0402_1%
2 Q23 0.01U_0402_25V7K~N
28 STB_LAN# 2
G 0.1U_0603_25V7K SUSP 2 @
2N7002_SOT23 S 2 G Q46
3
S SSM3K7002FU_SC70-3
3
1 2 +1.8VS
+CPU_CORE
C509 0.1U_0402_16V4Z~N
+VCCP
Discharge Circuit +VCCP +1.5VS
1
3 3
1
+1.5V R476
1
R483
R485 470_0402_5%
1
470_0402_5%
2
+3VALW R531 470_0402_5%
2
1 2
1
470_0402_5% D
1
1
D D SUSP 2
2
3
1
100K_0402_5% D
S Q27 S Q33 SSM3K7002FU_SC70-3
3
3
SYSON# 2 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3
2
SYSON# G
S Q35
3
1
D SSM3K7002FU_SC70-3
SYSON 2 Q24
23,28,35 SYSON
G SSM3K7002FU_SC70-3
S
3
2
1
R473
1
R484
470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5%
+5VALW
2
2
1
1
D D D
1
3
S SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3
2
SUSP SUSP
1
D
SUSP# 2 Q25
23,28,36,37 SUSP#
G SSM3K7002FU_SC70-3
2
S
Security Classification Compal Secret Data Compal Electronics, Inc.
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4631P 1.0
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 30 of 42
A B C D E
5 4 3 2 1
Www.alliancelaptoptraining.com
D D
1
H1
@ HOLEA
H_2P2
1
H_2P8
1
1
C C
11pcs
H19 H20
H_3P0 @ HOLEA @ HOLEA
1
B B
H_4P2
1
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Screws
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4631P 1.0
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 31 of 42
5 4 3 2 1
5 4 3 2 1
@
2200P_0402_50V7K~D @ 56K_0402_5%~D
ADPIN VIN
1 2 1 2
PL1
PJPDC1 FBMJ4516HS720NT_1806~D PR2
1 1 2 @ 1M_0402_1%~N
1
2 2 1 2
3 VIN
3 VS VIN
4 4
0.01U_0402_25V7K~D
5 @
5
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1000P_0402_50V7K~D
D @ D
6 6
1
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
7 @ PR5 @ PR3
GND
1
PC3
PC5
PC7
PC8
8 PR4 10K_0402_5%~D 1K_0402_5%~D
GND
PC2
PC4
PC6
82.5K_0402_1%~D 1 2
ACES_88299-0600 ACIN 14,28,33
2
PR6
2
8
@ @ 22K_0402_1%~D @
PU1A
N41 1 2 VinDe_IN3
P
+ VinDe_Out
O 1
0.1U_0402_16V7K~D
19.6K_0402_1%~D
@ VinDe_Ref
2 -
1
@ @ @
1
PC9
PR8
@ LM393DR_SO8 PR7
4
PL2 PC10 PD1 10K_0402_5%~D
BLM18BD102SN1D_0603~D 1000P_0402_50V7K~D RLZ4.3B_LL34
2
PSID 2 1 DOCK_PSID
2
32.3
VIN @ PR9
10K_0402_5%~D
2 1
RTCVREF
2
PD2
3.3V
8
@ PU1B
5
P
RLS4148_LL34-2 +
7
1
PJP1 O
6 -
G
33_1206_5%~D
PD3 @ JUMP_43X118
1
2 1 1 1 LM393DR_SO8
2 2 Vin Detector
4
BATT+
PR10
RLS4148_LL34-2
VS
2
Max. typ. Min.
C C
PQ1
L-->H 18.234 17.841 17.449
CHGRTCP 3 S 1TR BSS84 1P SOT-23 W/D H-->L 17.597 17.210 16.813
0.22U_1206_25V7K
32.8
1
PR11
PC11
100K_0402_5%~D PC12
0.1U_0603_25V7K~D
2
PR12
2
22K_0402_5%~D
1 2 51ON#_Gate
27,29 51ON#
1
PR13
RTCVREF 200_0805_5% +5VALW +3VALW
2
PU3
DA204U_SOT323~D
1 MAX1615_IN
IN
3 OUT
2
PD4
4.7U_0805_6.3V6K~D
2.2K_0402_5%~D
@ PR15
1
PC13
5 MAX1615_#SHDN 1 2 1 2
#SHDN
1
2
B PR14 0_0402_5%~D 0_0402_5%~D B
4
GND
5/3+ PC14
2
PR16
1U_0805_25V4Z~D
2
MAX1615EUK+_SOT23-5~D PR17
2
1
33_0402_5%~D
1
DOCK_PSID
S
1 3 1 2 PS_ID 28
PQ2
SSM3K7002FU_SC70-3
G
2
15K_0402_1%~D 100K_0402_1%~D
+5VALW
2
+5VALW
PR18
DA204U_SOT323~D
PJP3
@ JUMP_43X118 PJP5
10K_0402_1%~D
1 1 @ JUMP_43X118
+5VALWP 2 2 +5VALW
2
PD6
+1.05VALWP 1 1 2 2
1
+1.05VALW
2
PR19
C
PJP4 2 PQ3
@ JUMP_43X118 PJP2 B MMST3904-7-F_SOT323~D @
2
1 1 @ JUMP_43X118 E
2 2
2
PR20
1 1 2 2
1
@
1
1
+3VALWP 1 1 2 2 +3VALW @ 10K_0402_1%~D
PJP7
PJP8 @ JUMP_43X118
@ JUMP_43X118 1 1
+1.0VSP 2 2 +1.0VS
1 1 2 2
PJP9
@ JUMP_43X118
A A
1 1 2 2
PJP10
@ JUMP_43X118
1 1 PJP11
+1.5VP 2 2 +1.5V @ JUMP_43X118
+0.75VSP 1 1 2 2 +0.75VS
PJP12
@ JUMP_43X118
1 1 PJP13 Security Classification Compal Secret Data
2 2 @ JUMP_43X118
Issued Date 2006/10/1 Deciphered Date 2007/5/01 Title
PJP14
+1.8VSP 1 1 2 2 +1.8VS DCIN / Precharge
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
@ JUMP_43X118 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1 1 Custom KCM00 1.0
2 2 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 32 of 10
5 4 3 2 1
A B C D E
0.01U_0402_25V7K~D
7 2 2 7 SUPPRE_TDK MPZ1608S300AT 0603
D S S D CHG_B+
6 D S 3 3 S D 6 1 4 1 2
1
5 D G 4 4 G D 5
2
PC22
PC18
PC19
PC20
PC23
3.3_1210_5%~D
2 3 PR23
1
PC24 100K_0402_1%~D
2
PR24
0.01U_0402_25V7K~D
1
2
CHGEN#
100K_0402_1%~D
2
1
1000P_0402_50V7K~D
1000P_0402_50V7K~D
4.7U_1206_25V6K~D
4.7U_1206_25V6K~D
4.7U_1206_25V6K~D
1 1
PVCC
PC15 PC16 PC17
1
2
5
6
7
8
1
PC21
PR26
0.01U_0603_50V7K~D 0.1U_0402_16V7K~D PU4 0.1U_0805_25V7K
1 2
1
1 2 1 28 1 2 PQ6 /BATDRV
CHGEN PVCC
3.3_1210_5%~D
2
1
4
3
2
1
PR25
PR27 FDS6690AS_NL_SO8
2
PC25 PC26 2.2_0603_5%~D PQ7
S
S
S
G
0.1U_0603_25V7K~D 0.1U_0603_25V7K~D 27 BTST 1 2 4 FDS4435BZ_SO8
2
BTST
2
2
PR28
D
D
D
D
340K_0402_1%~D ACN 2 26 DH_CHG
ACN HIDRV
2
ACP 3
3
2
1
5
6
7
8
PC27 ACP PR29
1
2.2U_0805_25V6K ACDRV 4 25 LX_CHG PL3 0.02_2512_1%
1
10U_1206_25V6M~D
10U_1206_25V6M~D
REGN
ACSET RLS4148_LL34-2 PC28 PR30 2 3
2
PR31 0.1U_0603_25V7K~D 4.7_1206_5%~D
5
6
7
8
1
PC30
PC171
PR32 124K_0402_1%
10U_1206_25V6M~D
680P_0603_50V8J~D
54.9K_0402_1% 1 2 6 PQ8 @
VREF
PC29
ACSET
2
24
2
REGN
1
1 FDS6690AS_NL_SO8
PC33
PR33 PC32
1
PC31 100K_0402_1%~D 1U_0603_10V6K~D 4
0.01U_0402_25V7K~D
2
2
2
90W adapter 1 2ACOP 7 ACOP
PR34 PC34 23 DL_CHG
3
2
1
340K_0402_1%~D 0.47U_0603_16V7K~N LODRV
Icharge=(Vsrset/Vvdac)*(0.1/PR222)=3.3A CP setting
1
Iadapter=(Vacset/Vvdac)*(0.1/PR217)=3.34A PGND 22
OVPSET 8 PC35
2 OVPSET 0.1U_0402_16V7K~D 2
Input OVP : 22.3V
1 2
Input UVP : 16.98V 9 AGND LEARN 21 ACOFF 28
2
1
Fsw : 300KHz PR35
54.9K_0402_1% VREF PC36 PC37
20 CELLS 0.1U_0603_25V7K~D @0.1U_0603_25V7K~D
2
CELLS
1
10 VREF
PQ9
3
1
SI2301BDS-T1-E3_SOT23-3 PC38
1U_0603_10V6K~D
VREF PR36 19 SRP
2
100K_0402_1%~D SRP
CELLS GND 3 Cell
1 2GATE 2 11 VDAC SRN 18 SRN
2
VREF 4 Cell
PR37 17
BAT
1
47K_0402_1%~D
1
PC40 VADJ 12
0.1U_0603_25V7K~D VADJ PC39
1
ACSET 0.1U_0603_25V7K~D
2
CELLS 29
ACGOOD# TP
13 ACGOOD ICHG setting
1
D RTCVREF VREF
2 3cell/4cell# 39 PR38
G 16 2 1 IREF 28
SRSET
2
S PQ10 /BATDRV 14 60.4K_0402_1%~D
3
BATDRV
1
2N7002 1N SOT-23
1
PR39 PR40 PR41
IADAPT PC41 100K_0402_1%~D 100K_0402_1%~D
Cells selector IADAPT 15 1 2 100K_0402_1%~D
@0.01U_0402_25V7K~D
1
BQ24751ARHDR_QFN28_5X5 PR42
2
3 10_0603_5%~D 3
ACIN 14,28,32
1
PJP16 D
+COINCELL 1 28 ADP_I ACGOOD# 2 PQ11
1 REGN G 2N7002 1N SOT-23
2 2
1
3 IREF Current S
3
3 PC42
4 100P_0402_50V8J~D
2
GND
1
5 GND 0V 0A
PR43
MOLEX_53780-0370~D @ 0_0402_5%~D
PR44 3.3V 3A
210K_0402_1%~D
2
@ VADJ
28 CHGVADJ 1 2
1
2
B+ 1 2 3 S 1TR BSS84 1P SOT-23 W/D GATE
B+_BIAS
2
PR47 PR48
470K_0402_5%~D
1
0.1U_0805_25V7M~N
2
1
+5VALW D
1
PR49
S
2
3
1
1
D D
CHGVADJ Battery Voltage/per cell
1
1
220K_0402_5%
S DIO 1SS355
0V 3V PC44 S S
3
3
0.1U_0402_16V7K~D
4 PR52 4
2
PQ16 D
2
2
0.1U_0603_25V7K~D
G SSM3K7002FU_SC70-3
220K_0402_5%
S
3
2
1
PC45
PR53
Charger
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B KCM00 1.0
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 33 of 10
A B C D E
5 4 3 2 1
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B+ ISL6237_B+
ISL6237_B+
PJP17 PR54
@ JUMP_43X118 0_0805_5%
1 1 2 2 1 2
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
2200P_0402_50V7K~D
2200P_0402_50V7K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
VL PQ18
5
6
7
8
PC46
PC47
PC48
8
7
6
5
1
PC51
FDS8884_SO8
PC49
PC50
D PQ17 D
1U_0603_10V6K~D
FDS8884_SO8
2
2
4.7U_0805_6.3V6K~D
PC52 4
1
PC53
4 0.1U_0603_25V7K~D
PC59
1
3
2
1
1
2
3
PL4 +5VALWP
7
PL5 PU5 PC54 2 1
1 2 1U_0603_10V6K~D 3.3UH +-20% FDVE1040-3R3M 11.3A
4.7_1206_5%~D
LDO
VIN
VCC
+3VALWP 3.3UH +-20% FDVE1040-3R3M 11.3A 33 19 1 2
TP PVCC
5
6
7
8
1
PQ19
8
7
6
5
680P_0603_50V8J~D 4.7_1206_5%~D
PR56
DH3 26 15 DH5
UGATE2 UGATE1
PR55
10U_1206_25V6M~D
PQ20 PR57 PR58 FDS6690AS_NL_SO8
0_0402_5%~D
10U_1206_25V6M~D
1
1 FDS6690AS_NL_SO8 2.2_0603_5%~D
2.2_0603_5%~D
2
1
61.9K_0402_1%~D
PR59
PC169
4 @
2
PC168
2
1
2
680P_0603_50V8J~D
0.1U_0603_25V7K~D 0.1U_0603_25V7K~D
2
1
1
PR60
330U_D3L_6.3VM_R25M LX3 25 16 LX5 1
1
2 PHASE2 PHASE1
PC58
PC60
3
2
1
2
+ PC61
1
2
3
DL3 23 18 DL5 330U_D3L_6.3VM_R25M
1
LGATE2 LGATE1
2
10K_0402_1%~D
2
PGND 22
2
PR61
FB3 30 OUT2
9.76K_0402_1%~D
PR62
C C
OUT1 10
VL 32
1
@ REFIN2
1
11 FB5
2VREF_ISL6237 FB1
1 2 1 REF
PC62 0.22U_0603_10V7K~D
BYP 9
8 LDOREFIN @ PR63 0_0402_5%~D
6237_SKIP2
Rds(on) = 15m ohm(max) ; Rds(on) = 12m ohm(typical) SKIP 29 1 VL
PR64 0_0402_5%~D
1 2
3.3VALWP PD9 PR65
20 NC POK2 28
VS RLZ5.1B_LL34 100K_0402_1%~D
POK
1 2 1 2 EN_LDO 4 13 PR67
EN_LDO POK1
Imax=8.5A
2
200K_0402_5%~D
267K_0402_1%~D
2
PR66
6237_EN2 27 31 ILIM2 2 1
GND
TON
1
EN2 ILIM2
NC
2
Fsw=300kHz 309K_0402_1%
2
B
0_0402_5%~D
@ PR69 ISL6237IRZ-T_QFN32_5X5 B
21
VL 0_0402_5%~D
PR70
806K_0603_1%
6237_NC
6237_TON
1
PR71
2VREF_ISL6237 1
PR73
1
@ 47K_0402_5%~D
PR72 PC64
5VALWP
1
2 1 1 2 PR74
1U_0603_10V6K~D
2
39 MAINPWON
@
2VREF_ISL6237
Imax=7.5A
0.047U_0402_16V7K~N
0_0402_5%~D
2
PC65 0_0402_5%~D
1
1
2
0.047U_0603_16V7K~D
Iocp=9.8A
PC66
2
PQ21
S TR BSS84 1P SOT-23 W/D
@
Fsw=400kHz
1 3
PD10
1 2
S DIO 1SS355
A A
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Date: Tuesday, February 24, 2009 Sheet 34 of 10
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5 4 3 2 1
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D D
PJP18
@ JUMP_43X118
1 1 6269_B+
SI4430BDY
B+ 2 2
Rds(on)=4.8mohm~6mohm
10U_1206_25V6M~D
10U_1206_25V6M~D
PHASE_1.5V
1.5VP
PC67
1
6269_1.5V UG_1.5V
PC68
PR76
1
1 2 1 2 Imax=13A
2
@ PR75
10K_0402_1%~D 2.2_0603_5%~D PC69
+5VALW
0.1U_0603_25V7K~D Iocp=16.9A
1
BOOT_1.5V
PR77
5
6
7
8
0_0603_5%~D Fsw=231kHz
17
16
15
14
13
PU6 PR78 4.7_0603_5%~D
2
1 2 6269_1.5V PQ22
PHASE
UG
BOOT
GND
PGOOD
SI4172DY-T1-GE3 1N
PC70 4
C 1 VIN PVCC 12 1 2 C
2.2U_0603_6.3V6K~D
3
2
1
6269_1.5V LG_1.5V PL6
2 VCC LG 11
1.5UH +-20% FDVE1040-H-1R5M=P3 17.1A
+1.5VP
1
PR79 1 2 +1.5VP
PC71 0_0402_5%~D
2
2.2U_0603_6.3V6K~D 1 2 3 10 1 1
2
FCCM PGND
5
6
7
8
PR80
PR81 4.7_1206_5%~D + PC72 + PC73
22K_0402_1%~D PQ23 220U_D2_4VM~D 220U_D2_4VM~D
1 2 4 9 ISEN_1.5V
1 2 SI4430BDY_SO8
2 1
23,28,30 SYSON EN ISEN 2 2
COMP
PR82 PC74
FSET
4
1
2
PC75 7.15K_0402_1%~D 680P_0603_50V8J~D
VO
FB
PR83
1
0.1U_0402_16V7K~D 2K_0402_1%~D
2
8
ISL6269ACRZ-T_QFN16_4X4
3
2
1
1
1
22P_0402_50V8J~D
1
PR84
1
PC76
2200P_0402_50V7K~D
1
2
2
49.9K_0402_1%~D PC77
PR85 0.01U_0402_25V7K~D
2
1
PC78
57.6K_0402_1%~D
1
2 PR86
1.33K_0402_1%~D
2
B B
A A
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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS KCM00 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 35 of 10
5 4 3 2 1
5 4 3 2 1
Www.alliancelaptoptraining.com PC80
1
PC79 1U_0402_6.3V6K~D
1
1U_0402_6.3V6K~D
2
2
PGOOD1 PGOOD2 串1K 電組 上@ 2
PR87
1 1
PR88
2
+5VALWP +5VALWP
PJP19 2.2_0603_1%~D 2.2_0603_1%~D
@ JUMP_43X118
B+ 1 1 2 2
ISL6228_B+ +5VALWP
470P_0402_50V8J~D
680P_0402_50K X7R~D
2200P_0402_50V7K~D
1
1
PC83 PC81 PC82
PC84
PC173
0.1U_0603_25V7K~D 0.1U_0603_25V7K~D
D D
2
2
1
PR89 ISL6228_B+ 2 PR90 1 2 PR91 1 ISL6228_B+
1K_0402_1%~D 10_0603_1% 10_0603_1%
@
2
PC86
1000P_0402_50V7K~D PR93
1
PR92 18.2K_0402_1%~D
1000P_0402_50V7K~D 681_0402_5%~D PR94 PC85 22K_0402_1%~D
86.6K_0402_1%~D 1000P_0402_50V7K~D
PR95
1
PC87
2 1 1 2
1
PR96
1
2 1
29
PGOOD1
FSET1
VIN1
VCC1
VCC2
VIN2
FSET2
68K_0402_1%~D GND_T
2
PR97 PR99 681_0402_5%~D
1 2 8 FB1 PGOOD2 28 2 PR98 1 +5VALWP 86.6K_0402_1%~D PR100 1000P_0402_50V7K~D
PC88
12.1K_0402_1%~D 1K_0402_1%~D 2 1 1 2
1
@ @ PR109
ISL6228_B+ PR101 0_0402_5%~D
9 27 FB2_+1.0VSP 1 2 1 2 +1.0VS
VO1 FB2
4.7U_1206_25V6K~D
4.7U_1206_25V6K~D
68K_0402_1%~D
1
1
PC89
PC90
8
7
6
5
PC91 PR102
.01U_0402_16V7K~D PQ24 10 26 1 2
2
2
C 4 C
PR103 1.05VALWP_EN 11 25 PR189
12.1K_0402_1%~D EN1 PU7 OCSET2 PR105 0_0402_5%~D
0_0402_5%~D
ISL6228HRTZ-T_QFN28_4X4 1 2 ISL6228_B+
1
1
2
3
1
PL7 SUSP# 23,28,30,37
4.7U_1206_25V6K~D
4.7U_1206_25V6K~D
1
5
6
7
8
1
PC94
PC95
1UH_FDV0630-1R0M-P3_10.3A_20% 1 2 PC96
8
7
6
5
220U_X_2VM_R7M~D
1 PR106 PQ26 1 2
4.7_1206_5%~D PQ25 @ 0.01U_0402_25V7K~D FDS8884_SO8
2
PC92
10U_1206_25V6M~D
10U_1206_25V6M~D
+ FDS6690AS_NL_SO8 UG_1.05VALWP
13 UGATE1 23
PHASE2
2
680P_0603_50V8J~D
PR107
2
1
4 11K_0402_1%~D
2
PC170
PC123
4
1
PC97
(0.75V~1.05V)
2
2 1 2 1BST_1.05VALWP
14 BOOT1 22 UG_1.0VP
1
UGATE2 PL8
2
3
2
1
PR108
LGATE1
LGATE2
PC98 LX_1.0VSP 1 2
PGND1
PGND2
BOOT2
PVCC1
PVCC2
+1.0VSP
1
2
3
1
0_0603_5%~D
220U_X_2VM_R7M~D
0.1U_0402_16V7K~D
PR110 0.75UH 20% FDVE0630-R75M=P3 13.4A
5
6
7
8
4.7_1206_5%~D 1
PQ27
15
16
17
18
19
20
21
PC99
680P_0603_50V8J~D
10U_1206_25V6M~D
10U_1206_25V6M~D
+ @
PC100
2
DCR 10m ohm(max)
1
PR111 SI4386DY_SO8
1
2
PC101
PC167
PC172
+5VALWP +5VALWPBST_1.0VSP
1 2 1 2 4 DCR 6.2m ohm(max)
2
2
2
2.2_0603_5%~D
+1.05VALWP
2
PC102 PC103 0.1U_0402_16V7K~D
1U_0402_6.3V6K~D 1U_0402_6.3V6K~D 1.0VSP
1
3
2
1
Imax=7A
LG_1.05VALWP LG_1.0VSP Imax=9.3A
Iocp=9.1A
B Iocp=12.1A B
Fsw=303kHz
Fsw=366kHz
+1.0VSP
PR112
0_0402_5%~D
2 1 1.05VALWP_EN
+3VALWP
0.01U_0402_25V7K~D
PC104
L L L 1.05
2
@
2
2
54.9K_0402_1%
374K_0402_1%
200K_0402_1%~D
+3VALW +3VALW +3VALW
L L H 0.98
PR113
PR114
PR115
1
1
@ PR116 @ PR117 @ PR118
L H L 0.90
1
1
10K_0402_1%~D 10K_0402_1%~D 10K_0402_1%~D
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
PR119 PR120 PR121
L H H 0.87
2
2
1
1
D 100K_0402_5%~D D 100K_0402_5%~D D 100K_0402_5%~D
2 1 2 2 1 2 2 1 2
PQ28
PQ29
PQ30
G G G
H L L 0.80 S
14 MCP_CORE_VID2
S
14 MCP_CORE_VID1
S
14 MCP_CORE_VID0
3
3
2
2
22K_0402_1%~D
22K_0402_1%~D
22K_0402_1%~D
1
1
@ PR122
@ PR123
@ PR124
H L H 0.79 PC105 PC106 PC107
0.1U_0402_16V7K~D 0.1U_0402_16V7K~D 0.1U_0402_16V7K~D
2
2
H H L 0.77
1
1
A
H H H 0.75 FB2_+1.0VSP
A
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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS KC M 00 1.0
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Date: Tuesday, February 24, 2009 Sheet 36 of 10
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D D
@
5
PJP20 JUMP_43X118 PU8 RT9025
NC
NC
+3VALW 1 1 2 2 3 VIN VOUT 6 +1.8VSP
3.01K_0402_1%~D
1
1 2 2 EN ADJ 7
1
23,28,30,36 SUSP#
PR126
PC108
PR125 0_0402_5%~D 0.1U_0402_16V7K~D PC109
4 1 @ 10U_1206_25V6M~D
GND
GND
+5VALW
2
VDD PGOOD
2
1
PC110 GND GND
0.1U_0402_16V7K~D
8
@
2.37K_0402_1%~D
PC111
1
10U_1206_25V6M~D
PR127
PC112
1U_0402_6.3V6K~D
2
+1.8VSP
C C
Imax=0.3A
4.7U_0805_6.3V6K~D
4.7U_0805_6.3V6K~D
RT9026_MSOP10
PU9
PJP21
1U_0603_10V6K~D
+1.5VP 1 1 2 2 1 VDDQSNS VIN 10 +3VALW
1
1
PC115
PC118
JUMP_43X118 2 VLDOIN
PC114
@
2
2
@ 8
GND
VTTREF 6
+0.75VSP 3 VTT
1
1
5 VTTSNS S5 9 PR128
PC117
PC116
10U_0805_10V6K~D
10U_0805_10V6K~D
PC113
PGND
7 2 1 SUSP# 23,28,30,36
0.1U_0402_16V7K~D
GND
2
2
S3
0_0402_5%~D +0.75VSP
1
4
11
PC119 Imax=1.5A
0.1U_0402_16V7K~D
2
@
B B
A A
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 37 of 10
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5 4 3 2 1
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2
CPU_VID6
CPU_VID5
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0
5
5
PC120 +CPU_B+
PR129
PL9
VR_ON
14,28
2 1 1_0603_5%~D
FBMJ4516HS720NT_1806~D
@ 1 2 B+
1
5600P_0402_25V7K
1 1
1U_0603_10V6K~D
100U_25V_M~D
100U_25V_M~D
2200P_0402_50V7K~D
2200P_0402_50V7K~D
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
D D
1
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
PC128
PC129
PC130
PC121
PC122
PR130 499_0402_1%~D @ + +
1
1U_0603_10V6K~D
PC125
PC126
PC175
PC174
14 DPRSLPVR 1 2
1
PC124
PC127
2
PR131 0_0402_5%~D 2 2
2
5,7 H_DPRSTP# 1 2
5
PR1350_0402_5%~D
PR1360_0402_5%~D
PR1370_0402_5%~D
PR1380_0402_5%~D
PR1390_0402_5%~D
PR1400_0402_5%~D
PR1410_0402_5%~D
PR132 0_0402_5%~D
1
0_0402_5%~D
CLK_EN# 1 2
PR133
PR134 0_0402_5%~D PQ31
DPRSLPVR_CPU
+3VS
DPRSTP#_CPU
SI7686DP_POWERPAK
CLK_EN#_CPU
1 2 4
VR_ON_CPU
2
2
+3VS
1U_0603_10V6K~D
3V3_CPU
1.91K_0402_1%~D
PL10 0.36UH_PCMC104T-R36MN1R17_30A_20%
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1
PC131
PR144 PC132
3
2
1
1 BOOT_CPU1 1 2 1 2 4 1 +CPU_CORE
2
4.7_1206_5%~D
PR143
PR142
5
6
7
8
5
6
7
8
1
2.2_0603_5%~D 0.22U_0603_10V7K~D 3 2
1
10K_0402_1%~D
PR145
3.65K_1206_1%
499_0402_1%~D
49
48
47
46
45
44
43
42
41
40
39
38
37
D
D
D
D
D
D
D
D
1
PR147
2
PR146
PR148
3V3
VID6
VID5
VID4
VID3
VID2
VID1
VID0
GND
CLK_EN#
DPRSTP#
DPRSLPVR
VR_ON
1
680P_0603_50V8J~D
PQ32 PQ33 1_0402_5%~D
1 2
G
G
S
S
S
S
S
S
14,28 VGATE 1 36 SI4430BDY_SO8
2
PGOOD BOOT1
PC134
5 H_PSI# PR149 @ 0_0402_5%~D
4
3
2
1
4
3
2
1
2
2 35 UGATE_CPU1 VSUM 1 2
1U_0603_10V6K~D PC133 PR150 10K_0402_1%~D PSI# UGATE1 PC135
2
POW_MON 1 2 1 2 PMON 3 34 PHASE_CPU1 1 2
PMON PHASE1 ISEN1 VCC_PRM
C PR151 147K_0402_1%~D 4 33 C
RBIAS RBIAS PGND1 SI4430BDY_SO8 0.22U_0603_16V7K~D
1 2
VR_TT# 5 32 LGATE_CPU1 +CPU_B+
VR_TT# LGATE1
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
PR152 @ 4.22K_0402_1% PH1
1
1 2 1 2 NTC 6 31 PVCC_CPU
NTC PVCC
PC137
PC138
PC139
@
@ 100K_0603_1%_TH11-4H104FT SOFT 7 30 LGATE_CPU2
2
SOFT LGATE2 PQ34
1 2
@ 0.015U_0402_16V7K PC136 OCSET 8 29 SI7686DP_POWERPAK
0.068U_0603_50V7K~N PC140 OCSET ISL6262ACRZ-T_QFN48_7X7 PGND2
4
1 2 VW 9 28 PHASE_CPU2
VW PHASE2
PR153 11.5K_0402_1%~D COMP 10 27 UGATE_CPU2 PL11 0.36UH_PCMC104T-R36MN1R17_30A_20%
COMP UGATE2 PR154 PC141
1 2
3
2
1
FB_CPU 11 26 BOOT_CPU2
1 2 1 2 4 1
PC142 FB BOOT2
1 2
5
6
7
8
5
6
7
8
1
DROOP
1000P_0402_50V7K~D 12 25 2.2_0603_5%~D
0.22U_0603_10V7K~D 3 2
FB2 NC
VDIFF
VSUM
ISEN2
ISEN1
VSEN
D
D
D
D
D
D
D
D
VDD
RTN
DFB
1
VIN
10K_0402_1%~D
3.65K_1206_1%
4.7_1206_5%~D
VO
1 2
1
PR157
PR158
PR159
1 2 PU10 PQ35 PQ36
13
14
15
16
17
18
19
20
21
1VDD_CPU 22
23
24
1 2
G
G
S
S
S
S
S
S
FB2_CPU 1_0402_5%~D
PC143 1000P_0402_50V7K~D
4
3
2
1
4
3
2
1
2
29.1
VSEN_CPU
DFB
RTN
VD IFF
Vin_CPU
2
ISEN2 680P_0603_50V8J~D 1 2
2
PR162 97.6K_0402_1%~D PC145 470P_0402_50V7K~D 1 2 +5VS
1
1 2 2 1 VSUM PC147
PR161 1_0603_5%~D 1 2
PR163 PC146
B 1K_0402_1%~D 1U_0603_10V6K~D 0.22U_0603_16V7K~D B
1 2
2
1
150K_0402_1%~D
SI4430BDY_SO8 SI4430BDY_SO8
2
PR190
255_0402_1%~D
1 2 PC150 10_0603_5%~D
Fsw=300kHz
2
PR166 1K_0402_1%~D
PC151 0.022U_0603_25V7K 0.1U_0603_25V7K~D
5 VCCSENSE 1 2 1 2
VSUM
1
PR167 0_0402_5%~D
1
2.61K_0402_1%~D
PC152 PC153
PR169
@0.022U_0603_25V7K 0.022U_0603_25V7K
2
1 2
5 VSSSENSE PR168 0_0402_5%~D
2
1
11K_0402_1%~D
PC154 180P_0402_50V8J~D
PR170
1 2
2
1 2 1 2 PH2
2
VCC_PRM 1 2
PC157 0.22U_0603_10V7K~D
A A
PC156 2 1 2 1
0.22U_0603_16V7K~D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS KCM00
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 38 of 10
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5 4 3 2 1
Www.alliancelaptoptraining.com +3VALWP
DA204U_SOT323~D
DA204U_SOT323~D
DA204U_SOT323~D
DA204U_SOT323~D
3
2
PD11
PD12
PD13
PD14
D D
@
BATT+
BATT++
1
@
@ @ Battery Connect/OTP
BATT+
PL12
FBMA-L18-453215-900LMA90T_1812~D
1 2 BATT++
+3VALWP
100P_0402_50V8J~D
1
1
100P_0402_50V8J~D
1
PC161
PC159
PC158
PC160 1000P_0402_50V7K~D
2
2
0.01U_0402_25V7K~D
2
1
PR174
PJPB1 battery connector
2
BATT_SMD
BATT_SMC
1K_0402_5%~D
BATT_B/I
PC162
0.1U_0402_16V7K~D
1
SMART
200275MR009G10PZR_9P-T
@
11 9 PR175
Batte ry: 10
GND
GND
1
2 8
7 3cell/4cell# 1K_0402_5%~D
3 3cell/4cell# 33
6 2 1
1 . B AT + @ 4
5 5 1 2 +3VALWP
2 . B AT + 6 4
3 PR176
7
C
3.ID 8 2 6.49K_0402_1%~D
C
1
4 .B/I 9
PJP22
5. TS 1 2 EC_SMB_DA1 28
6.SMD PR177
7.S MC
100_0402_5%~D
8.GND CPU
9.GND 1 2 EC_SMB_CK1 28 PH1 under CPU botten side :
PR178
100_0402_5%~D
CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C
VL VS
BATT+
1
2
PR179
1
453K_0402_1%~D PC163
0.1U_0603_25V7K~D
CPU
1
VS
2
PR180
10.7K_0402_1%~D VL
2
1
0.01U_0402_25V7K~D
PR181
B PR182 147K_0402_1%~D B
2
499K_0402_1%~D 1 2
1
PC164
PR183
205K_0402_1%~D
2
2
PR184
1
8
61.9K_0402_1%~D
1 2 OTP_IN+ 3 PD15
P
+
8
+ VL -
G
1 2 BATT_OUT7 S DIO 1SS355
0 PR186 PU11A
6
4
-
G
1
28 BATT_OVP 150K_0402_1%~D LM358ADR_SO8
1
PU11B PH3
4
1
100K_0603_1%_TH11-4H104FT
1
PR187
86.6K_0402_1%~D PC165 PR188
2
1000P_0402_50V7K~D 150K_0402_1%~D
2
2
2
PC166
1U_0603_10V6K~D
LI-3S :12.6V----BATT-OVP=1.1V
LI-4S :16.8V----BATT-OVP=1.5V
BATT-OVP=0.111*BATT+
A A
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 39 of 10
5 4 3 2 1
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Www.alliancelaptoptraining.com
Version Change List ( P. I. R. List ) Page 1/1
Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 p37 +0.75VSP/1.8VSP 08/10/15 compal source shortage pu9
9 p37 +0.75VSP/1.8VSP 08/10/15 compal adjust 1.8V output voltage PR127 PR124
11 p33 charger 08/10/15 compal adjust CP set for ICPP function PR38
12 p34 +3VALWP/+5VALWP 08/10/15 compal meet choke component current limit PL4 PL5
C C
13 p32 DCIN / Precharge 08/10/15 compal meet PSL PL1
23 ALL every power 08/10/22 compal reduce output ripple PC123 PC167 PC168 PC169 PC170
B B
24 ALL every power 08/10/22 compal sunbber for EMI request PR30 PR106 PR55 PR56 PR80 PR110 PR105 PR155
25 ALL every power 08/10/22 compal sunbber for EMI request PC33 PC58 PC60 PC74 PC97 PC101 PC134 PC144
26 P34 P35 every power 08/10/22 compal increase boost resistor value form 0 ohm to 2.2 ohm for EMI request PR57 PR58 Pr76
28 p33 charger 08/12/03 compal DFX request PQ10 PQ11 PQ13 PQ14 PQ15
29 p36 +1.05VALWP/1.0VP 08/12/03 compal adjust +1.0VSP OCP set PR102 PR107
31 p35 +1.5VSP 08/12/12 compal design change(already trail run in PT phase) PQ22
33 p33 charger 08/12/31 compal reduce AC-IN inrush current PR24 PR25
34 p34 +3VALWP/+5VALWP 08/12/31 compal adjust +5VALWP voltage PR62 change frome 10k to 9.62k
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PW PIR-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KCM00 1.0
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 24, 2009 Sheet 40 of 10
5 4 3 2 1
A
Input B+
DC IN Switch Page 32 +3VALWP: TDC:8.5A OCP:11A OVP:108%~114%
+5VALWP: TDC:7.5A OCP:9.8A OVP:108%~114%
(ISL6237) Page 34
Always
CHARGER
CC:0A~3A
CV:16.8V(4cell)
CV:12.6V(3cell)
(BQ24751) Page 33
+3VALW +1.8VSP TDC:0.24A
(RT9025-25PSP)
Page 37
SUSP#
A A
Title
<Title>
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Size Document Number Rev
Custom<Doc> 1.0
Www.alliancelaptoptraining.com
Version Change List ( P. I. R. List ) Page 1/1
Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 19 P19-DDR3_SO-DIMM SLOT 2008/09/22 nVidia can't use SO-DIMM change SO-DIMM SA0 to pull high & SA1 to pull down 0.2
D 2 D
20 P20-LCD/SATA HDD 2008/09/25 Compal can't read EDID for Panel change JLVDS1 Pin 37 from +LCDVDD TO +3VS 0.2
3 21 P21-HDMI/Display Port 2008/10/07 Compal Change DP122 to DP122A change R440 from 4.64K to 5.11K and R438 from 5.11K to 6.49K 0.2
4 12 P12-MCP79(6/10)_PCI/LPC 2008/10/13 Compal can't select on board SPD data ADD R191,R192,R193 TO SELECT ON BOARD MEMORY VENDOR 0.2
5 28 P28-EC_KB926/BIOS/Reed SW2008/10/20 Compal Change EC_SMB_DA1 and EC_SMB_CK1 from +5VALW to +3VALW 0.2
6 18 P18-1GB/2GB_DDR3_On Board2008/12/04 nVidia On board Ram unstable Add 0.1uF cap between Termination Resistor and +0.75VS 0.4
7 14 P14-MCP79(8/10)_HDA/MISC 2009/02/03 Dell saving power consumption change +3VALW to +3VS on MEM_SMBCLK & MEM_SMBDATA 1.0
10
11
12
C C
13
14
15
16
17
18
19
20
21
22
B 23 B
24
25
26
27
28
29
30
31
32
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EE PIR-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4631P 1.0
Www.alliancelaptoptraining.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 42 of 42
5 4 3 2 1