BASIC COMPUTER ORGANIZATION AND DESIGN

An instruction code is a group of bits that instruct the computer to perform a specific
operation.

Computer Instructions

Computer instructions are a set of machine language instructions that a particular

processor understands and executes. A computer performs tasks on the basis of the
instruction provided.

The operation code of an instruction is a group of bits that define operations such as
addition, subtraction, shift, complement, etc. An instruction must also include one or more
operands, which indicate the registers and/or memory addresses from which data is taken
or to which data is deposited.

An instruction comprises of groups called fields. These fields include:

 The Operation code (Opcode) field which specifies the operation to be performed.
 The Address field which contains the location of the operand, i.e., register or
memory location.
 The Mode field which specifies how the operand will be located.

A basic computer has three instruction code formats which are:

1. Memory - reference instruction

2. Register - reference instruction
3. Input-Output instruction

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Memory - reference instruction

In Memory-reference instruction, 12 bits of memory is used to specify an address and one

bit to specify the addressing mode 'I'.

Register - reference instruction

The Register-reference instructions are represented by the Opcode 111 with a 0 in the
leftmost bit (bit 15) of the instruction.

Input-Output instruction

Just like the Register-reference instruction, an Input-Output instruction does not need a
reference to memory and is recognized by the operation code 111 with a 1 in the leftmost
bit of the instruction. The remaining 12 bits are used to specify the type of the input-output
operation or test performed.

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Computer Registers

Registers are a type of computer memory used to quickly accept, store, and transfer data
and instructions that are being used immediately by the CPU. The registers used by the CPU
are often termed as Processor registers.

A processor register may hold an instruction, a storage address, or any data (such as bit
sequence or individual characters).

The computer needs processor registers for manipulating data and a register for holding a
memory address. The register holding the memory location is used to calculate the address
of the next instruction after the execution of the current instruction is completed.

Following is the list of some of the most common registers used in a basic computer s
Register Symbol Number of bits Function

Data register DR 16 Holds memory operand

Address register AR 12 Holds address for the memory

Accumulator AC 16 Processor register

Instruction register IR 16 Holds instruction code

Program counter PC 12 Holds address of the instruction

Temporary register TR 16 Holds temporary data

Input register INPR 8 Carries input character

Output register OUTR 8 Carries output character

The following image shows the register and memory configuration for a basic computer.

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 The Memory unit has a capacity of 4096 words, and each word contains 16 bits.
 The Data Register (DR) contains 16 bits which hold the operand read from the
memory location.
 The Memory Address Register (MAR) contains 12 bits which hold the address for
the memory location.
 The Program Counter (PC) also contains 12 bits which hold the address of the next
instruction to be read from memory after the current instruction is executed.
 The Accumulator (AC) register is a general purpose processing register.
 The instruction read from memory is placed in the Instruction register (IR).
 The Temporary Register (TR) is used for holding the temporary data during the
processing.
 The Input Registers (IR) holds the input characters given by the user.
 The Output Registers (OR) holds the output after processing the input data .

Instruction Cycle

A program residing in the memory unit of a computer consists of a sequence of

instructions. These instructions are executed by the processor by going through a cycle for
each instruction.

In a basic computer, each instruction cycle consists of the following phases:

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1. Fetch instruction from memory.

2. Decode the instruction.

3. Read the effective address from memory.

4. Execute the instruction.

Timing and Control

The timing for all registers in the basic computer is controlled by a master clock generator.
The clock pulses are applied to all flip-flops and registers in the system, including the flip-
flops and registers in the control unit. The clock pulses do not change the state of a register
unless the register is enabled by a control signal. The control signals are generated in the
control unit and provide control inputs for the multiplexers in the common bus, control
inputs in processor registers, and microoperations for the accumulator.

There are two major types of control organization:

1. hardwired control and

2. microprogrammed control.

In the hardwired organization, the control logic is implemented with gates, flip-flops,
decoders, and other digital circuits. It has the advantage that it can be optimized to produce
a fast mode of operation. In the microprogrammed organization, the control information is
stored in a control memory. The control memory is programmed to initiate the required
sequence of microoperations. A hardwired control, as the name implies, requires changes
in the wiring among the various components if the design has to be modified or changed.

In the microprogrammed control, any required changes or modifications can be done by

updating the microprogram in control memory.

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It consists of two decoders,

1. a sequence counter, and

2. a number of control logic gates.

An instruction read from memory is placed in the instruction register (IR). The instruction
register is divided into three parts:

1. the 1 bit,
2. the operation code, and
3. bits 0 through 11.

The operation code in bits 12 through 14 are decoded with a 3 x 8 decoder. The eight
outputs of the decoder are designated by the symbols D 0 through D 7. The subscripted
decimal number is equivalent to the binary value of the corresponding operation code. Bit
15 of the instruction is transferred to a flip-flop designated by the symbol I. Bits 0 through
11 are applied to the control logic gates. The 4-bit sequence counter can count in binary
from 0 through 15. The outputs of the counter are decoded into 16 timing signals T 0
through T15.

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The sequence counter SC can be incremented or cleared synchronously. Most of the time,
the counter is incremented to provide the sequence of timing signals out of the 4 x 16
decoder. Once in a while, the counter is cleared to 0, causing the next active timing signal to
be T0.

The timing diagram below shows the time relationship of the control signals.

The sequence counter SC responds to the positive transition of the clock. Initially, the CLR
input of SC is active. The first positive transition of the clock clears SC to 0, which in tum
activates the timing signal T0 out of the decoder. T0 is active during one clock cycle. The
positive clock transition labeled T0 in the dagram will trigger only those registers whose
control inputs are transition, to timing signal T0. SC is incremented with every positive
clock transition unless its CLR input is active. This produces the sequence of timing signals
T0, T1, T2, T3 ,T4 and so on, as shown in the dagram. (Note the the relationshuip between the
timing signal and and its corresponding positive clock transition.) If SC is not cleared, the

timing signals will continue with T5, T6 up to T15 and back to T0 .

Memory Reference Instructions

Memory reference instructions are those commands or instructions which are in the
custom to generate a reference to the memory and approval to a program to have an
approach to the commanded information and that states as to from where the data is cache
continually. These instructions are known as Memory Reference Instructions.

There are seven memory reference instructions which are as follows &

AND

The AND instruction implements the AND logic operation on the bit collection from the
register and the memory word that is determined by the effective address. The result of
this operation is moved back to the register.

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ADD

The ADD instruction adds the content of the memory word that is denoted by the effective
address to the value of the register.

LDA

The LDA instruction shares the memory word denoted by the effective address to the
register.

STA

STA saves the content of the register into the memory word that is defined by the effective
address. The output is next used to the common bus and the data input is linked to the bus.
It needed only one micro-operation.

BUN

The Branch Unconditionally (BUN) instruction can send the instruction that is determined
by the effective address. They understand that the address of the next instruction to be
performed is held by the PC and it should be incremented by one to receive the address of
the next instruction in the sequence. If the control needs to implement multiple
instructions that are not next in the sequence, it can execute the BUN instruction.

BSA

BSA stands for Branch and Save return Address. These instructions can branch a part of the
program (known as subroutine or procedure). When this instruction is performed, BSA will
store the address of the next instruction from the PC into a memory location that is
determined by the effective address.

ISZ

The Increment if Zero (ISZ) instruction increments the word determined by effective
address. If the incremented cost is zero, thus PC is incremented by 1. A negative value is
saved in the memory word through the programmer. It can influence the zero value after
getting incremented repeatedly. Thus, the PC is incremented and the next instruction is
skipped.

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INTERRUPTS IN COMPUTER ARCHITECTURE

An interrupt in computer architecture is a signal that requests the processor to suspend its
current execution and service the occurred interrupt. To service the interrupt the
processor executes the corresponding interrupt service routine (ISR). After the execution
of the interrupt service routine, the processor resumes the execution o f the suspended
program. Interrupts can be of two types of hardware interrupts and software interrupts.

Types of Interrupts in Computer Architecture

The interrupts can be various type but they are basically classified into hardware
interrupts and software interrupts.

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1. Hardware Interrupts

If a processor receives the interrupt request from an external I/O device it is termed as a
hardware interrupt. Hardware interrupts are further divided into maskable and non -
maskable interrupt.

Maskable Interrupt: The hardware interrupt that can be ignored or delayed for some time
if the processor is executing a program with higher priority are termed as maskable
interrupts.

Non-Maskable Interrupt: The hardware interrupts that can neither be ignored nor
delayed and must immediately be serviced by the processor are termed as non-maskeable
interrupts.

2. Software Interrupts

The software interrupts are the interrupts that occur when a condition is met or a system
call occurs.

STACK ORGANIZATION

Stack is also known as the Last In First Out (LIFO) list. It is the most important feature in
the CPU. It saves data such that the element stored last is retrieved first. A stack is a
memory unit with an address register. This register influence the address for the stack,
which is known as Stack Pointer (SP). The stack pointer continually influences the address
of the element that is located at the top of the stack.

It can insert an element into or delete an element from the stack. The insertion operation is
known as push operation and the deletion operation is known as pop operation. In a
computer stack, these operations are simulated by incrementing or decrementing the SP
register.

Register Stack

The stack can be arranged as a set of memory words or registers. Consider a 64-word
register stack arranged as displayed in the figure. The stack pointer register includes a
binary number, which is the address of the element present at the top of the stack. The
three-element A, B, and C are located in the stack.

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The element C is at the top of the stack and the stack pointer holds the address of C that is
3. The top element is popped from the stack through reading memory word at address 3
and decrementing the stack pointer by 1. Then, B is at the top of the stack and the SP holds
the address of B that is 2. It can insert a new word, the stack is pushed by incrementing the
stack pointer by 1 and inserting a word in that incremented location.

The stack pointer includes 6 bits, because 2 6 = 64, and the SP cannot exceed 63 (111111 in
binary). After all, if 63 is incremented by 1, therefore the result is 0(111111 + 1 =
1000000). SP holds only the six least significant bits. If 000000 is decremented by 1 thus
the result is 111111.

Therefore, when the stack is full, the one-bit register ‘FULL’ is set to 1. If the stack is null,
then the one-bit register ‘EMTY’ is set to 1. The data register DR holds the binary
information which is composed into or readout of the stack.

First, the SP is set to 0, EMTY is set to 1, and FULL is set to 0. Now, as the stack is not full
(FULL = 0), a new element is inserted using the push operation.

The push operation is executed as follows :

SP←SP + 1 It can increment stack pointer

K[SP] ← DR It can write element on top of the stack

If (SP = 0) then (FULL ← 1) Check if stack is full

EMTY ← 0 Mark the stack not empty

The stack pointer is incremented by 1 and the address of the next higher word is saved in
the SP. The word from DR is inserted into the stack using the memory write operation. The
first element is saved at address 1 and the final element is saved at address 0. If the stack
pointer is at 0, then the stack is full and ‘FULL’ is set to 1. This is the condition when the SP
was in location 63 and after incrementing SP, the final element is saved at addre ss 0.

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During an element is saved at address 0, there are no more empty registers in the stack.
The stack is full and the ‘EMTY’ is set to 0.

A new element is deleted from the stack if the stack is not empty (if EMTY = 0). The pop
operation includes the following sequence of micro-operations −

DR←K[SP] It can read an element from the top of the stack

SP ← SP – 1 It can decrement the stack pointer

If (SP = 0) then (EMTY ← 1) Check if stack is empty

FULL ← 0 Mark the stack not full

The top element from the stack is read and transfer to DR and thus the stack pointer is
decremented. If the stack pointer reaches 0, then the stack is empty and ‘EMTY’ is set to 1.
This is the condition when the element in location 1 is read out and the SP is decremented
by 1.

Instruction Formats

The instructions provided to computers help the computer perform a task. The computers
comprise instructions in groups called fields. Each field has different information and
different significance based on which the CPU decides what to perform.

The set of instructions that manages the operation codes is called the format of instruction.
The design of bits in instruction is supported by the format of instruction. The length of
instruction is generally preserved in multiples of character, which is 8bits. The instruction
format determines the behaviour and complexity of instruction. Depending upon the
number of addresses, the format of instruction is of variable length.

Types of instruction formats are :

1. Zero(0) Address Instruction format

 The instruction format in which there is no address field is called zero address
instruction

 In zero address instruction format, stacks are used

 In zero order instruction format, there is no operand

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2. One(1) Address Instruction format

 The instruction format in which the instruction uses only one address field is called
the one address instruction format
 In this type of instruction format, one operand is in the accumulator and the other is
in the memory location
 It has only one operand
 It has two special instructions LOAD and STORE

3. Two(2) Address Instruction format

 The instruction format in which the instruction uses only two address fields is called
the two address instruction format
 This type of instruction format is the most commonly used instruction format
 As in one address instruction format, the result is stored in the accumulator only,
but in two addresses instruction format the result can be stored in different
locations
 This type of instruction format has two operands
 It requires shorter assembly language instructions

4. Three(3) Address Instruction format

 The instruction format in which the instruction uses the three address fields is
called the three address instruction format
 It has three operands
 It requires shorter assembly language instructions
 It requires more bits

Example Of format Of Instruction

1. Zero Address Instruction examples

 Assembly language instruction – PUSH A, PUSH B etc.

 Stack transfer operation – TOS <- A, TOS <- B etc.

2. One Address Instruction examples

 Assembly language instruction – LOAD C, ADD B, STORE T etc.

 Operation Register instruction – AC <- M[T], AC <- M[C] etc.

3. Two Address Instruction examples

 Assembly language instruction – MOV R1, A; ADD R1, B etc.

 Operation Register instruction – R1 <- M[A], R2 <- M[C] etc.

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4. Three Address Instruction examples

 Assembly language instruction – ADD R1, A, B etc.

 Operation Register instruction – R1 <- M[A] + M[B] etc.

ADDRESSING MODES
Each instruction requires some data on which it has to operate. There are different
techniques to specify data for instructions. These techniques are called addressing modes.
Intel 8085 uses the following addressing modes:

1. Direct Addressing

In this addressing mode, the address of the operand (data) is given in the instruction itself.

Example

STA 2400H: It stores the content of the accumulator in the memory location 2400H.

In this instruction, 2400H is the memory address where data is to be stored. It is given in
the instruction itself. The 2nd and 3rd bytes of the instruction specify the address of the
memory location. Here, it is understood that the source of the data is accumulator.

2. Register Addressing

In register addressing mode, the operand is in one of the general purpose re gisters. The
opcode specifies the address of the register(s) in addition to the operation to be performed.

Example: MOV A, B: Move the content of B register to register A.

In the above example, MOV A, B is 78H. Besides the operation to be performed the opcode
also specifies source and destination registers.

The opcode 78H can be written in binary form as 01111000. The first two bits, i.e. 0 1 are
for MOV operation, the next three bits 1 1 1 are the binary code for regis ter A, and the last
three bits 000 are the binary code for register B.

3. Register Indirect Addressing

In Register Indirect mode of addressing, the address of the operand is specified by a

register pair.

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Example:

o LXI H, 2500 H - Load H-L pair with 2500H.

o MOV A, M - Move the content of the memory location, whose address is in H-L pair
(i.e. 2500 H) to the accumulator.
o HLT - Halt.

In the above program the instruction MOV A, M is an example of register indirect

addressing. For this instruction, the operand is in the memory. The address of the memory
is not directly given in the instruction. The address of the memory resides in H -L pair and
this has already been specified by an earlier instruction in the program, i.e. LXI H, 2500 H.

4. Immediate Addressing

In this addressing mode, the operand is specified within the instruction itself.

Example : LXI H, 2500 is an example of immediate addressing. 2500 is 16-bit data which is
given in the instruction itself. It is to be loaded into H-L pair.

5. Implicit Addressing

There are certain instructions which operate on the content of the accumulator. Such
instructions do not require the address of the operand.

Example : CMA, RAL, RAR, etc.

DATA TRANSFER INSTRUCTIONS:

As the name suggests data transfer instructions are meant for transfer for data from
one location to another, keeping the binary information intact. The useful transfer are
between memory and processing registers, between processor registers and input or
output, and between the processor registers themselves. Each instruction is accompanied
with the mnemonic symbol which are different in different computers for the same
instruction name. Table below gives a list of eight data transfer instructions used in many
computers.

The “load” instruction represent a transfer from memory to a processor register, usually an
“accumulator” where as the store instruction designates a transfer from a processor
register into memory.

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The move instruction is employed in computers with multiple CPU registers to designate a
transfer from one register to another. It has also been used for data transfers between CPU
registers and memory or between two memory words. Swapping of information between
to registers of a register and memory word its accomplished by using the exchange
instruction. The input and output instructions cause transfer of data among processor
registers and input or output terminals. The push and pop instructions take care of transfer
of data between processor registers and a memory stack.

To distinguish with between the various address modes, the mnemonic symbol are
modified by assembly language conventions. For instance, the mnemonic for load
immediate becomes LDI. Other assembly language conventions use a special character to
designate the addressing mode. For example, the immediate mode is recognized from a
pound sign # placed before the operand. What ever may be the case, the important thing is
to realize that each instruction can occur with a variety of addressing modes.

OPCODE OPERAND EXPLANATION EXAMPLE

MOV D, S D=S MOV AX, [SI]
PUSH D pushes D to the stack PUSH DX
POP D pops the stack to D POP AS
PUSHA none put all the registers into the stack PUSHA
POPA none gets words from the stack to all registers POPA

DATA MANIPULATION INSTRUCTIONS:

Data manipulation instructions perform operations on data and provide the

computational capabilities for the computer. The data manipulation instructions in a
typical computer usually divided into three basic types as follows.

1. Arithmetic instructions
2. Logical and bit manipulation instructions
3. Shift instructions

1. Arithmetic instructions:
The four basic arithmetic operations are addition, subtraction, multiplication, and
division. Most computers provide instructions for all four operations.

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Typical Arithmetic Instructions:

Name Mnemonic Example Explanation

It will increment the register B by 1 B<-B+1

Increment INC INC B

It will decrement the register B by 1 B<-B-1

Decrement DEC DEC B

It will add contents of register B to the contents

of the accumulator and store the result in the
accumulator AC<-AC+B
Add ADD ADD B

It will subtract the contents of register B from

the contents of the accumulator and store the
result in the accumulator AC<-AC-B
Subtract SUB SUB B

It will multiply the contents of register B with the

contents of the accumulator and store the result
in the accumulator AC<-AC*B
Multiply MUL MUL B

It will divide the contents of register B with the

contents of the accumulator and store the
quotient in the accumulator AC<-AC/B
Divide DIV DIV B

It will add the contents of register B and the

carry flag with the contents of the accumulator
and store the result in the accumulator
Add with ADDC
AC<-AC+B+Carry flag
carry ADDC B

It will subtract the contents of register B and the

carry flag from the contents of the accumulator
and store the result in the accumulator
Subtract with SUBB
AC<-AC-B-Carry flag
borrow SUBB B

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2. Logical and Bit Manipulation Instructions:

Logical instructions perform binary operations on strings of bits stored in
registers. They are useful for manipulating individual bits or a group of bits.

Typical Logical and Bit Manipulation Instructions

Name Mnemonic Example Explanation

It will set the accumulator to 0, AC<-0

Clear CLR CLR

COM
It will complement the accumulator, AC<-(AC)’
Complement COM A

It will AND the contents of register B with the

contents of accumulator and store it in the
AND
accumulator AC<-AC AND B
AND AND B

It will OR the contents of register B with the

contents of accumulator and store it in the
accumulator AC<-AC OR B
OR OR OR B

It will XOR the contents of register B with the

contents of the accumulator and store it in the
Exclusive-
accumulator AC<-AC XOR B
OR XOR XOR B

It will set the carry flag to 0, Carry flag<-0

Clear carry CLRC CLRC

3. Shift Instructions:
Shifts are operations in which the bits of a word are moved to the left or right. Shift
instructions may specify either logical shifts, arithmetic shifts, or rotate-type
operations.

Typical Shift Instructions

Name Mnemonic

Logical shift right SHR

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Logical shift left SHL

Arithmetic shift right SHRA

Arithmetic shift left SHLA

Rotate right ROR

Rotate left ROL

Rotate right through carry RORC

Rotate left through carry ROLC

Types of Processors:

RISC stands for Reduced Instruction Set Computer and CISC stands for Complex
Instruction Set Computer.

RISC PROCESSOR

RISC stands for Reduced Instruction Set Computer Processor, a microprocessor

architecture with a simple collection and highly customized set of instructions. It is built to
minimize the instruction execution time by optimizing and limiting the number of
instructions. It means each instruction cycle requires only one clock cycle, and each cycle
contains three parameters: fetch, decode and execute. The RISC processor is also used to
perform various complex instructions by combining them into simpler ones. RISC chips
require several transistors, making it cheaper to design and reduce the execution time for
instruction.

Examples of RISC processors are SUN's SPARC, PowerPC, Microchip PIC processors, RISC -V.

Advantages of RISC Processor

1. The RISC processor's performance is better due to the simple and limited number of
the instruction set.
2. It requires several transistors that make it cheaper to design.

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3. RISC allows the instruction to use free space on a microprocessor because of its
simplicity.
4. RISC processor is simpler than a CISC processor because of its simple and quick
design, and it can complete its work in one clock cycle.

Features of RISC Processor

Some important features of RISC processors are:

1. One cycle execution time: For executing each instruction in a computer, the RISC
processors require one CPI (Clock per cycle). And each CPI includes the fetch,
decode and execute method applied in computer instruction.
2. Pipelining technique: The pipelining technique is used in the RISC processors to
execute multiple parts or stages of instructions to perform more efficiently.
3. A large number of registers: RISC processors are optimized with multiple
registers that can be used to store instruction and quickly respond to the computer
and minimize interaction with computer memory.
4. It supports a simple addressing mode and fixed length of instruction for executing
the pipeline.
5. It uses LOAD and STORE instruction to access the memory location.
6. Simple and limited instruction reduces the execution time of a process in a RISC.

CISC PROCESSOR

The CISC Stands for Complex Instruction Set Computer, developed by the Intel. It has a
large collection of complex instructions that range from simple to very complex and
specialized in the assembly language level, which takes a long time to execute the
instructions. So, CISC approaches reducing the number of instruction on each program and
ignoring the number of cycles per instruction. It emphasizes to build complex instructions
directly in the hardware because the hardware is always faster than software. However,
CISC chips are relatively slower as compared to RISC chips but use little instruction than
RISC. Examples of CISC processors are VAX, AMD, Intel x86 and the System/360.

Characteristics of CISC Processor

Following are the main characteristics of the RISC processor:

1. The length of the code is shorts, so it requires very little RAM.

2. CISC or complex instructions may take longer than a single clock cycle to execute the
code.
3. Less instruction is needed to write an application.

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4. It provides easier programming in assembly language.

5. Support for complex data structure and easy compilation of high-level languages.
6. Instructions can be larger than a single word.
7. It emphasizes the building of instruction on hardware because it is faster to create
than the software.

Difference between the RISC and CISC Processors

Sl No RISC CISC

1 It is a Reduced Instruction Set Computer. It is a Complex Instruction Set Computer.

2 It emphasizes on software to optimize It emphasizes on hardware to optimize

the instruction set. the instruction set.

3 It is a hard wired unit of programming in Microprogramming unit in CISC

the RISC Processor. Processor.

4 It requires multiple register sets to store It requires a single register set to store
the instruction. the instruction.

5 CISC has complex decoding of

RISC has simple decoding of instruction.
instruction.

6 Uses of the pipeline are simple in RISC. Uses of the pipeline are difficult in CISC.

7 It uses a limited number of instruction It uses a large number of instruction that

that requires less time to execute the requires more time to execute the
instructions. instructions.

8 It uses LOAD and STORE that are It uses LOAD and STORE instruction in
independent instructions in the register- the memory-to-memory interaction of a
to-register a program's interaction. program.

10 The execution time of RISC is very short. The execution time of CISC is longer.

11 RISC architecture can be used with high- CISC architecture can be used with low-
end applications like telecommunication, end applications like home automation,
image processing, video processing, etc. security system, etc.

12 It has fixed format instruction. It has variable format instruction.

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13 The program written for RISC

Program written for CISC architecture
architecture needs to take more space in
tends to take less space in memory.
memory.

14 Example of RISC: ARM, PA-RISC, Power Examples of CISC: VAX, Motorola 68000
Architecture, Alpha, AVR, ARC and the family, System/360, AMD and the Intel
SPARC. x86 CPUs.

Dr Mahesh V, Dept. of Computer Applications, T. John College. Page 22