NOTES

ADVANCED
DIGITAL
ELECTRONICS
CONCEPTS
 FIFO DEPTH CALCULATION - MADE EASY
We need to employ an asynchronous FIFO between two modules working at
different clock domains when some amount of data has to be transmitted from one module to
the other to avoid the data loss. FIFO is required, only when you are slow at reading and fast in
writing to buffer the data which is not read by the slower module.

The depth (size) of the FIFO should be in such a way that, the FIFO can store all the
data which is not read by the slower module. FIFO will only work if the data comes in bursts;
you can't have continuous data in and out. If there is a continuous flow of data, then the size of
the FIFO required should be infinite. You need to know the burst rate, burst size, frequencies,
etc. to determine the appropriate size of FIFO.

The logic in fixing the size of the FIFO is to find the no. of data items which are not read in a
period in which writing process is done. In other words, FIFO depth will be equal to the no.
of data items that are left without reading. With this logic, I tried to fix the size of FIFO
required in different scenarios without using any standard formulas which can’t be used in
every scenario.

The following examples describe the different possible scenarios in which

Asynchronous FIFO is required. In the following examples, I considered that, the module ‘A’
wants to send some data to the module ‘B’.
Case – 1 : fA > fB with no idle cycles in both write and read.

Writing frequency = fA = 80MHz.

Reading Frequency = fB = 50MHz.
Burst Length = No. of data items to be transferred = 120.
There are no idle cycles in both reading and writing which means that, all the items
in the burst will be written and read in consecutive clock cycles.
Sol :

 Time required to write one data item = = 12.5 nSec.

 Time required to write all the data in the burst = 120 * 12.5 nSec. = 1500 nSec.
 Time required to read one data item = = 20 nSec.
 So, for every 20 nSec, the module B is going to read one data in the burst.
 So, in a period of 1500 nSec, 120 no. of data items can be written.
 And the no. of data items can be read in a duration of 1500 nSec = = 75
 The remaining no. of bytes to be stored in the FIFO = 120 – 75 = 45.
 So, the FIFO which has to be in this scenario must be capable of storing 45 data items.

So, the minimum depth of the FIFO should be 45.

Case – 2 : fA > fB with one clk cycle delay between two successive reads and
writes.

Sol :
This is just, to create some sort of confusion. This scenario is no way different from the
previous scenario (case -1), because, always, there will be one clock cycle delay between two
successive reads and writes. So, the approach is same as the earlier one.
Case – 3 : fA > fB with idle cycles in both write and read.
Writing frequency = fA = 80MHz.
Reading Frequency = fB = 50MHz.
Burst Length = No. of data items to be transferred = 120.
No. of idle cycles between two successive writes is = 1.
No. of idle cycles between two successive reads is = 3.
Sol :
 The no. of idle cycles between two successive writes is 1 clock cycle. It means that, after
writing one data, module A is waiting for one clock cycle, to initiate the next write. So, it
can be understood that for every two clock cycles, one data is written.
 The no. of idle cycles between two successive reads is 3 clock cycles. It means that, after
reading one data, module B is waiting for 3 clock cycles, to initiate the next read. So, it
can be understood that for every four clock cycles, one data is read.
1
 Time required to write one data item = 2 ∗ 80 = 25 nSec.
 Time required to write all the data in the burst = 120 * 25 nSec. = 3000 nSec.
1
 Time required to read one data item = 4 ∗ 50 = 80 nSec.
 So, for every 80 nSec, the module B is going to read one data in the burst.
 So, in a period of 3000 nSec, 120 no. of data items can be written.
 The no. of data items can be read in a period of 3000 nSec = = 37.5 − 37
 The remaining no. of bytes to be stored in the FIFO = 120 – 37 = 83.
 So, the FIFO which has to be in this scenario must be capable of storing 83 data items.
So, the minimum depth of the FIFO should be 83.

Case – 4 : fA > fB with duty cycles given for wr_enb and rd_enb.

Writing frequency = fA = 80MHz.

Reading Frequency = fB = 50MHz.
Burst Length = No. of data items to be transferred = 120.
Duty cycle of wr_enb (write enable) = 50 % = ½.
Duty cycle of wr_enb (write enable) = 25 % = ¼.

Sol :
This scenario is no way different from the previous scenario (case - 3), because, in this case
also, one data item will be written in 2 clock cycles and one data item will be read in 4 clock
cycles.

Note : Case - 2 and Case - 4 are explained to make everyone understand that
the same question can be asked in a different way.
Case – 5 : fA < fB with no idle cycles in both write and read (i.e., the delay
between two consecutive writes and reads is one clock cycle).

Writing frequency = fA = 30MHz.

Reading Frequency = fB = 50MHz.
Burst Length = No. of data items to be transferred = 120.
There are no idle cycles in both reading and writing which means that, all the items
in the burst will be written and read in consecutive clock cycles.
Sol :
 In this case, a FIFO of depth ‘1’ will be sufficient because, there will not be any data loss
since the reading is faster than writing.

Case – 6 : fA < fB with idle cycles in both write and read (duty cycles of wr_enb
and rd_enb can also be given in these type of questions).

Writing frequency = fA = 30MHz.

Reading Frequency = fB = 50MHz.
Burst Length = No. of data items to be transferred = 120.
No. of idle cycles between two successive writes is = 1.
No. of idle cycles between two successive reads is = 3.
Sol :
 The no. of idle cycles between two successive writes is 1 clock cycle. It means that, after
writing one data, module A is waiting for one clock cycle, to initiate the next write. So, it
can be understood that for every two clock cycles, one data is written.
 The no. of idle cycles between two successive reads is 3 clock cycles. It means that, after
reading one data, module B is waiting for 3 clock cycles, to initiate the next read. So, it
can be understood that for every four clock cycles, one data is read.
1
 Time required to write one data item = 2 ∗ 30 = 66.667 nSec.
 Time required to write all the data in the burst = 120 * 66.667 nSec. = 8000 nSec.
1
 Time required to read one data item = 4 ∗ 50 = 80 nSec.
 So, for every 80 nSec, the module B is going to read one data item in the burst.
 So, in a period of 8000 nSec, 120 no. of data items can be written.
 The no. of data items can be read in a period of 8000 nSec = = 100
 The remaining no. of bytes to be stored in the FIFO = 120 – 100 = 20.
 So, the FIFO which has to be in this scenario must be capable of storing 20 data items.

So, the minimum depth of the FIFO should be 20.

Case – 7 : fA = fB with no idle cycles in both write and read (i.e., the delay
between two consecutive writes and reads is one clock cycle).
Writing frequency = fA = fB = 30MHz.
Burst Length = No. of data items to be transferred = 120.
There are no idle cycles in both reading and writing which means that, all the items
in the burst will be written and read in consecutive clock cycles.
Sol :
 FIFO is not required if there is no phase difference between clkA and clkB.
 A FIFO of depth ‘1’ will be sufficient if there is some phase difference between clkA and
clkB.

Case – 8 : fA = fB with idle cycles in both write and read (duty cycles of wr_enb
and rd_enb can also be given in these type of questions).
Writing frequency = fA = 50MHz.
Reading Frequency = fB = 50MHz.
Burst Length = No. of data items to be transferred = 120.
No. of idle cycles between two successive writes is = 1.
No. of idle cycles between two successive reads is = 3.
Sol :
 The no. of idle cycles between two successive writes is 1 clock cycle. It means that, after
writing one data, module A is waiting for one clock cycle, to initiate the next write. So, it
can be understood that for every two clock cycles, one data is written.
 The no. of idle cycles between two successive reads is 3 clock cycles. It means that, after
reading one data, module B is waiting for 3 clock cycles, to initiate the next read. So, it
can be understood that for every four clock cycles, one data is read.
1
 Time required to write one data item = 2 ∗ 50 = 40 nSec.
 Time required to write all the data in the burst = 120 * 40 nSec. = 4800 nSec.
1
 Time required to read one data item = 4 ∗ 50 = 80 nSec.
 So, for every 80 nSec, the module B is going to read one data item in the burst.
 So, in a period of 4800 nSec, 120 no. of data items can be written.
 The no. of data items can be read in a period of 4800 nSec = = 60
 The remaining no. of bytes to be stored in the FIFO = 120 – 60 = 60.
 So, the FIFO which has to be in this scenario must be capable of storing 60 data items.

So, the minimum depth of the FIFO should be 60.

Case – 9 : If the data rates are given as follows.
Writing Data = 80 DATA/100 Clock (Randomization of 20 Data’s)
Outgoing Data= 8 DATA/10 Clock.
Burst size = 160
Sol :
 The given specifications indicate that the Writing Frequency is equal to reading
frequency.
 But, both reading and writing can happen at any random instants with the constraints
that “writing of 80 data items will be completed in 100 cycles” and ”reading of 8 data
items will be completed in 10 cycles”.
 The following are possibilities.

 The following are the observations from the above diagram.

Case No. of cycles taken to complete write

1 200
2 200
3 180
4 160
5 200
  To obtain safer FIFO size, we need to consider the worst case scenario for the data
transfer across the FIFO under consideration to avoid the data loss.
 For worst case scenario, the difference between the data rate between write and read
should be maximum. Hence, for write operation, maximum data rate should be
considered and for read operation, minimum data rate should be considered.
 The maximum data rate for the write is in case – 4. (Write operation is completed in
minimum no. of cycles in this case). So, consider the case - 4 for further calculations.
 So, in a period of 160 clock cycles, 160 no. of data items can be written.
 The data rate for the read is 8 data / 10 clock cycles.
∗
 The no. of data items can be read in a period of 160 clock cycles = = 128
 The remaining no. of bytes to be stored in the FIFO = 160 – 128 = 32.
 So, the FIFO which has to be in this scenario must be capable of storing 32 data items.

So, the minimum depth of the FIFO should be 32.

Case – 10 : Specifications can be given in a different way. (Understanding the

specifications is important here)
Given the following FIFO rules, how deep does the FIFO need to be to prevent underflow or
overflow?
Frequency (clk A) = frequency (clk B)/4
Period (en_B) = period (clk_A)*100
Duty cycle (en_B) = 25%
Sol :
 Assume some numerical values, if the specifications are in this way.
 Assume frequency of clk_B = 100MHz
 So, the frequency of clk_A = 100MHz /4 = 25MHz.
 In the specifications given, the burst length is specified indirectly. The burst length is 100.
 Time required to write one data item = = 40 nSec.
 Time required to write all the data in the burst = 100 * 40 nSec. = 4000 nSec.
 And the duty cycle of en_B is 25 % means that, out of 4000 nSec in which the writing
process is completed, reading is done only in a period of 1000 nSec (25% of 4000 nSec.)
 So, the FIFO should be capable of holding the data which is being written in the
remaining 3000 nSec.
 The no. of data items can be read in a period of 3000 nSec = = 75

So, the minimum depth of the FIFO should be 75.

9/14/2017 Implementing Mealy and Moore Machines

Implementing Mealy and Moore Machines

Introduction

We're going to implement Mealy and Moore machines. These are finite state machines with output.

A Mealy machine has outputs that depend on the state and input (thus, the FSM has the output written
on edges)
A Moore machine has outputs that depend on state only (thus, the FSM has the output written in the
state itself)

Most students find this material the hardest to learn, and yet learn it you must, because I always ask
questions about finite state machines and its implementation.

Never fear though. Even though it may be difficult to learn how to implement Mealy and Moore machines,
most people will tell you that it's a very mechanical process. That is, once you learn it, it's like following a
cookbook recipe.

Of course, you might ask why you should learn how to implement Mealy and Moore machines, but we'll
defer that to the next set of notes.

The Big Picture

Here's the big picture. We want to go from a finite state machine that looks like:

and eventually create a black box circuit that looks like:

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Recall that a sequential circuit stores state information. If we have k states, that state information requires
ceil( lg( k ) ) flip flops. Since each flip flop stores one bit, then the state stores ceil( lg( k ) ) bits of
information.

In fact, that information is the state label. For example, in the FSM diagram above, there's two bits used in
the state, thus you have q1q0 = 00 to mean that some state label is 00.

The Steps
It's easier to get an idea of what to do when you know the steps involved. It's really not all that difficult.

1. Create a state transition table

This is basically a truth table that records the information of the finite state machine.

2. Decide how many flip flops you need, and what kind

This is usually simple, because you have to encode each state of the finite state machine using ceil( lg(
k ) ) bits. Or even better, someone's already given you an FSM with that information encoded.

Choosing the kind of flip flop you want is usually an academic exercise. You'll often be told to use a
certain flip flop, so you need to be able to handle the kind give.

3. Use the flip flop excitation table, to fill out the rest of the chart.

We'll talk about the excitation table momentarily.

4. Implement the circuit using a ROM.

Look at the diagram of the black box in the previous section. See the box inside the black box labelled
combinational logic? We're using a ROM (read-only memory) to implement the combinational logic.

Technically, a ROM is not combinational logic. It's memory, thus, it basically has flip flops in it.
However, you could use gates to implement the equivalent behavior of a ROM, using sum-of-products
representation.

And that's it! Each step is quite easy. The real problem that most students have really lies in understanding
what they're doing.

It's like someone told you to fold a piece of paper this way, then that way, and eventually when you're done,
they say congratulations, you've made a "glurble". You're happy and proud of this paper concoction you've
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created! "A glurble!", you exclaim.

Then you realize you have absolutely no idea what you've made. You know the steps, but you don't know
why it matters.

For now, the quickest way to learn this is to follow the steps, understand how they work, and then try to get
the big picture a little later.

Step 1: Create a State Transition Table

The state transition table consists of input variables and state variables. Those serve as the "inputs" to the
truth table. We use the convention of x plus subscripts for the input variables and q plus subscripts for the
state variables.

We'll implement the Moore machine shown above. The Moore machine has two bits for the state and one bit
for the input.

Row q1 q0 x

0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

Since the input and state variables are the truth table inputs, we list out all possibilities. There are 1 input
variable plus 2 state variables = 3 truth table inputs, thus 23 rows in the truth table.

Some Intuition: Inspecting a Row

Let's look at row 0. In this row, q1q0 = 00 and x = 0. What does this mean?

It means we're current in state q1q0 = 00 and we see an input of x = 0 (at a positive edge).

Putting State Variables First

To make sure everyone is consistent on their tables, it's preferable to put state variables first, then inputs
second. As you can see above, the first two columns (after "Row") are the state, and the last column is the
inputs.

The reason for doing it in this order (as opposed to putting input variable, then state variables) is to handle
every possible input per state, before moving onto the next state.

Next Small Step: Writing the Next State

The next state uses the state variables with plus superscripts. q1+q0+ is the state we're going to go into.

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For example, look at the Moore maching above. In state 00, if we see an input of a 0, then we go to state 10.
In state 00, if we see an input of a 1, then we go to state 01. Let's put that information in the "truth table
output" section (shown in green).

Row q1 q0 x q1+ q0+

0 0 0 0 1 0
1 0 0 1 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

Now let's go to state 01. In state 01, if the input is 0, you stay in state 01. If it's 1, you go to state 10.

Row q1 q0 x q1+ q0+

0 0 0 0 1 0
1 0 0 1 0 1

2 0 1 0 0 1
3 0 1 1 1 0
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

Now we go to state 10. In state 10, if we see a 0, we head to state 01. If we see a 1, we go to state 00. We fill
that in.

Row q1 q0 x q1+ q0+

0 0 0 0 1 0
1 0 0 1 0 1
2 0 1 0 0 1
3 0 1 1 1 0

4 1 0 0 0 1
5 1 0 1 0 0
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6 1 1 0
7 1 1 1

Finally, there is no state 11. So, in that case, we don't care what happens if we are in that state. We can fill
whatever we want. However, to emphasize that we don't care, we fill in the next state with d's, which indicate
"don't care".

Row q1 q0 x q1+ q0+

0 0 0 0 1 0
1 0 0 1 0 1
2 0 1 0 0 1
3 0 1 1 1 0
4 1 0 0 0 1
5 1 0 1 0 0

6 1 1 0 d d
7 1 1 1 d d

Next Small Step: Filling the Outputs

We're almost done with filling out the state transition table.

All we need to now is fill out the outputs.

Since this is a Moore machine, here are the rules for filling out the outputs. For each state, look at the output.
Thus, state 00 has output z1z0 = 01.

State 00 is in row 0 and row 1, where q1q0 = 00.

Row q1 q0 x q1+ q0+ z1 z0

0 0 0 0 1 0 0 1
1 0 0 1 0 1 0 1
2 0 1 0 0 1
3 0 1 1 1 0
4 1 0 0 0 1
5 1 0 1 0 0
6 1 1 0 d d
7 1 1 1 d d

State 01 has output 11. State 01 is in rows 2 and 3.

State 10 has output 11. State 01 is in rows 4 and 5.

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State 11 doesn't exist, so we put "d" in rows 6 and 7 for the output columsn (in blue).

Row q1 q0 x q1+ q0+ z1 z0

0 0 0 0 1 0 0 1
1 0 0 1 0 1 0 1

2 0 1 0 0 1 1 1
3 0 1 1 1 0 1 1
4 1 0 0 0 1 1 1
5 1 0 1 0 0 1 1
6 1 1 0 d d d d
7 1 1 1 d d d d

Step 2: Picking flip flops

Step 1 was a lot of the work. However, the steps are quite easy. Step 2 is very easy. We need to choose flip
flops.

However, in a test situation, you'll be told which flip flops to use.

We need a flip flop for each bit used in a state. There are two bits, q1q0, so two flip flops are needed.

Let's implement q1 with a D flip flop, and q0 with a T flip flop. We'll label them D1 (to match up with q1)
and T0 (to match up with q0).

Step 3: Use flip flop excitation table to fill out the rest of the table.

You've read about excitation tables in the previous set of notes. This is where we're going to use excitation
tables.

We add two more columns to the table, D1 and T0.

Row q1 q0 x
q1+ q0+ z1 z0 D1 T0

0 0 0 0 1 0 0 1
1 0 0 1 0 1 0 1
2 0 1 0 0 1 1 1
3 0 1 1 1 0 1 1
4 1 0 0 0 1 1 1
5 1 0 1 0 0 1 1
6 1 1 0 d d d d
7 1 1 1 d d d d
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We now look at column q1 and q1+. They've been highlighted.

These columns refer to flip flop D1. Basically, look at each row. For example, in row 0, you see q1 = 0 and
q1+ = 1. Thus, you need to make D = 1 (based on the excitation table).

In row 1, you see q1 = 0 and q1+ = 0. Thus, you need to make D = 0 (based on the excitation table).

But recall that the D excitation table basically said D = Q+. So, all we have to do is to copy the q1+ columns
over to D1.

Row q1 q0 x
q1+ q0+ z1 z0 D1 T0

0 0 0 0 1 0 0 1 1
1 0 0 1 0 1 0 1 0
2 0 1 0 0 1 1 1 0
3 0 1 1 1 0 1 1 1
4 1 0 0 0 1 1 1 0
5 1 0 1 0 0 1 1 0
6 1 1 0 d d d d d
7 1 1 1 d d d d d

Now we focus on columns q0 and q0+.

Row q1 q0 x q1+ q0+ z1 z0 D1 T0

0 0 0 0 1 0 0 1 1
1 0 0 1 0 1 0 1 0
2 0 1 0 0 1 1 1 0
3 0 1 1 1 0 1 1 1
4 1 0 0 0 1 1 1 0
5 1 0 1 0 0 1 1 0
6 1 1 0 d d d d d
7 1 1 1 d d d d d

Now look at row 0. We have q0 = 0 and q0+ = 0. The T flip flop excitation says that T must hold (i.e., T = 0)
for that to happen.

Now look at row 1. We have q0 = 0 and q0+ = 1. The T flip flop excitation says that T must toggle (i.e., T =
1) for that to happen.

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Row q1 x q1+ z1 z0 T0
q0 q0+ D1
0 0 0 0 1 0 0 1 1 0
1 0 0 1 0 1 0 1 0 1
2 0 1 0 0 1 1 1 0
3 0 1 1 1 0 1 1 1
4 1 0 0 0 1 1 1 0
5 1 0 1 0 0 1 1 0
6 1 1 0 d d d d d
7 1 1 1 d d d d d

In fact, for each row, all you do is ask, are the values in the two columns the same? If so, set T = 0. If not, set
T = 1.

So, we fill out the rest of the column accordingly.

Row q1 q0 x q1+ q0+ z1 z0 D1 T0

0 0 0 0 1 0 0 1 1 0
1 0 0 1 0 1 0 1 0 1
2 0 1 0 0 1 1 1 0 0
3 0 1 1 1 0 1 1 1 1
4 1 0 0 0 1 1 1 0 1
5 1 0 1 0 0 1 1 0 0
6 1 1 0 d d d d d d
7 1 1 1 d d d d d d
Step 4: Implement the Circuit Using a ROM
A ROM stand for read-only memory. The inputs to a ROM are a k-bit address. The outputs to a ROM are the
contents of the address.

Thus, if we have a 3-bit ROM, then the addresses are 3 bits each. If the input is 000two, then we get the
contents of ROM at memory address M[000].
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To implement the circuit, we're going to have as many address bits in the ROM as we do truth table inputs.
The number of truth table inputs is the sum of the number of state variables and the input variables. This is
also the number of rows in our table, which is 8.

The number of bits at each memory address is the sum of the output variables, plus the number of flip flops.
So, that's 2 output variables (z1z0) and 2 flip flops (D1T0). Thus, at each address, there's 4 bits.

This is really the easy part of the circuit design. We will merely copy all columns in blue to the ROM. And
we're done.

Here's the final diagram.

A few comments about the diagram above, in particular, the ROM.

Label the address bits A2A1A0. Don't leave them out.

Make sure you hook up the wires to the address bits correctly. Order matters! q1 hooks up to A2. q0
hooks up to A1. x hooks up to A0. They are in that order, because the truth table inputs are listed in that
order.
Label addresses 000 through 111. Don't leave it blank!
Label the columns correctly: z1, z0, D0, T0.
Don't add additional bits to the ROM. In particular, don't add the next state.
Feedback D1 and T0 from the ROM output to the flip flop inputs.
Leave the don't cares as they are. Notice that we copy the d's, instead of giving them values. You
should do the same.
Circle the input, x, so I know it's coming from outside the black box.
Square the outputs, z1z0, so I know it's going outside the black box.
Add the steenkin' clock!

Does it work?

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Suppose we know the current state is q1q0 = 00, and the input is x = 0. This causes the address of the ROM
to be AA1A0 = 000. This selects the 4 bit value: z1z0D1T0 = 0110.

In particular, z1z0 = 01 which is the output you get in state 00. D1 = 1 causes q1 to be 1 at the next positive
edge. T1 = 0 causes q0 to stay at 0 at the next positive edge.

Thus, at the next positive edge, q1q0 = 10, which is the state we expect. If we're now in q1q0 = 00, on an
input of 1, then we expect to be in state q1q0 = 10, at the next positive edge.

When the next positive edge occurs, and we're in state 01, then if x is still 0, then the address bits are AA1A0
= 100, which selects address 100.

This selects the 4 bit value at adress 100: z1z0D1T0 = 1101.

Thus, the output is now 11, which is the output you expect for state 10.

Try another state and another input to convince yourself this circuit works.

Practice make perfect

Draw some more examples of Moore machines, and try it out!

Mealy Machines

The only real difference in Mealy and Moore machines is how you fill out the outputs. Other than that, it
behaves the same.

Recall from the Moore machine, you look at the current state, and then check what the output is from the
FSM, and then copy the output bits for each occurrence of that state.

Here's an example of a Mealy machine. Notice the outputs are on the edges.

Here's the table. We've filled in the don't cares for rows 4 and 5, which correspond to state 10, which doesn't
exist.

Row q1 q0 x q1+ q0+ z

0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Seq/impl.html 10/12
9/14/2017 Implementing Mealy and Moore Machines

4 1 0 0 d d d
5 1 0 1 d d d
6 1 1 0
7 1 1 1

Now, suppose you are in state 00, and see an input of a 0 (i.e., q1q0 = 00 and x = 0). At the next positive
edge, you will go transition to state 11, and output a 1 (i.e., q1q0 = 11 and z = 1).

Suppose you are in state 00, and see an input of a 1 (i.e., q1q0 = 00 and x = 1). At the next positive edge, you
will transition to state 01, and output a 1 (i.e., q1q0 = 01 and z = 1).

We can fill that information out in the table.

Row q1 q0 x q1+ q0+ z

0 0 0 0 1 1 1
1 0 0 1 0 1 1
2 0 1 0
3 0 1 1
4 1 0 0 d d d
5 1 0 1 d d d
6 1 1 0
7 1 1 1

As an exercise, you can fill out the rest of the chart yourself.

After that, the same steps are followed. Pick the flip flops, use the flip flop excitation table, and draw the
circuit.

Being Careful with Moore machines

In a Moore machine, you should fill out the output columns (those labelled with z's) first. If there are k input
variables, then every 2k rows will have the same output values. That's because Moore machines have outputs
that depend only on state.

Do we Need a ROM?

No we don't. For every column of the ROM, you can simply write a sum-of-products expression using input
and state variables, and it can be completely implemented using combinational logic.

The ROM is convenient so we can design this part in a hurry, but in principle, all it takes is writing a sum of
products expression for each of the columns.

The purpose of the ROM (or the circuit that would go in the place of the ROM) is to generate the correct
control signals to the flip flops (using feedback) to get to the next state at the next positive clock edge, as
well as to generate the output of the circuit.

https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Seq/impl.html 11/12
9/14/2017 Implementing Mealy and Moore Machines

Summary

Implementing a Moore or Mealy machine is not that hard, especially if you don't intend to minimize the
circuit (which we don't).

However, it does take practice to be able to do it reasonably fast, and is difficult to understand conceptually,
at least, at first. You should trace out a few steps just to convince yourself of how it behaves. There is a
subtle difference in the behavior of the implementation of a Mealy and Moore machine. Tracing out a few
steps can show the differences more clearly.

Usually, it's harder to understand why the circuit does the right thing (i.e., implements the FSM) than it is to
know how to build it. Certainly, you should devote time to both understanding why this technique works, as
well as mastering the technique.

https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Seq/impl.html 12/12
 Design of the 11011 Sequence Detector
A sequence detector accepts as input a string of bits: either 0 or 1.
Its output goes to 1 when a target sequence has been detected.
There are two basic types: overlap and non-overlap.
In an sequence detector that allows overlap, the final bits of one sequence can be
the start of another sequence.
11011 detector with overlap X 11011011011
Z 00001001001
11011 detector with no overlap Z 00001000001

Slide 1 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

Problem: Design a 11011 sequence detector using JK flip-flops. Allow

overlap.
Step 1 – Derive the State Diagram and State Table for the Problem
Step 1a – Determine the Number of States
We are designing a sequence detector for a 5-bit sequence, so we need 5 states.
We label these states A, B, C, D, and E. State A is the initial state.
Step 1b – Characterize Each State by What has been Input and What is Expected
State Has Awaiting
A -- 11011
B 1 1011
C 11 011
D 110 11
E 1101 1

Slide 2 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

Step 1c – Do the Transitions for the Expected Sequence

Here is a partial drawing of the state diagram. It has only the sequence
expected. Note that the diagram returns to state C after a successful detection;
the final 11 are used again.

B
1/0 Note the labeling of the transitions: X /
1/0
Z. Thus the expected transition from A
A C to B has an input of 1 and an output of
0.
1/1 0/0

E D The transition from E to C has an

1/0 output of 1 denoting that the desired
sequence has been detected.

The sequence is 1 1 0 1 1.

Slide 3 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

Step 1d – Insert the Inputs That Break the Sequence

The sequence is 1 1 0 1 1.

Each state has two lines out of it – one line for a 1 and another line for a 0.
The notes below explain how to handle the bits that break the sequence.

Slide 4 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

State A in the 11011 Sequence Detector

A State A is the initial state. It is waiting on a 1.

If it gets a 0, the machine remains in state A and continues to remain
there while 0’s are input.
If it gets a 1, the machine moves to state B, but with output 0.

Slide 5 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

State B in the 11011 Sequence Detector

B If state B gets a 0, the last two bits input were “10”.

This does not begin the sequence, so the machine goes back to state A
and waits on the next 1.
If state B gets a 1, the last two bits input were “11”. Go to state C.

Slide 6 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

State C in the 11011 Sequence Detector

C If state C gets a 1, the last three bits input were “111”.

It can use the last two to be the first two 1’s of the sequence 11011, so the
machine stays in state C awaiting a 0.
If state C gets a 0, the last three bits input were “110”. Move to state D.

Slide 7 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

State D in the 11011 Sequence Detector

D If state D gets a 0, the last four bits input were “1100”. These 4 bits are
not part of the sequence, so we start over.
If state D gets a 1, the last four bits input were “1101”. Go to state E.

Slide 8 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

State E in the 11011 Sequence Detector

E If state E gets a 0, the last five bits input were “11010”. These five bits are
not part of the sequence, so start over.
If state E gets a 1, the last five bits input were “11011”, the target sequence.
If overlap is allowed, go to state C and reuse the last two “11”.
If overlap is not allowed, go to state A, and start over.

Slide 9 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

Prefixes and Suffixes: State C

When breaking the input, we look for the largest suffix of the actual input
that is an equal–length prefix of the desired pattern.
State C, with the last input = 1.
The last three bits input were “111”.
Input Desired Sequence.
“111” “11011”
1 bit “1” “1” Good match 111 11011
2 bit “11” “11” Good match 111 11011
3 bit “111” “110” No match. 111 11011
The last two 1’s at this state can form a 2–bit prefix useable at state C.

Slide 10 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

Prefixes and Suffixes: State E

State E, with last input = 0.
The last five bits were “11010”. No suffix of this is a prefix of the target.
Input Desired Sequence.
“11010” “11011”
1 bit “0” “1” No match.
2 bit “10” “11” No match.
3 bit “010” “110” No match.
4 bit “1010” “1101” No match.
5 bit “11010” “11011” No match.

Slide 11 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

Step 1e – Generate the State Table with Output

Present State Next State / Output
X=0 X=1
A A/0 B/0
B A/0 C/0
C D/0 C/0
D A/0 E/0
E A/0 C/1

Step 2 – Determine the Number of Flip-Flops Required

We have 5 states, so N = 5. We solve the equation 2P-1 < 5  2P by inspection,
noting that it is solved by P = 3. So we need three flip-flops.

Slide 12 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

Step 3 – Assign a unique P-bit binary number (state vector) to each state.
The simplest way is to make the following assignments
A = 000
B = 001
C = 010
D = 011
E = 100
Here is a more interesting assignment.
States A and D are given even numbers. States B, C, and E are given odd
numbers. The assignment is as follows.
A = 000
B = 001
C = 011 States 010, 110, and 111 are not used.
D = 100
E = 101

Slide 13 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

Step 4 – Generate the Transition Table With Output

Present State Next State / Output

X=0 X=1
Y2Y1Y0 Y2Y1Y0 / Z Y2Y1Y0 / Z
A 0 0 0 0 0 0 / 0 0 0 1 / 0
B 0 0 1 0 0 0 / 0 0 1 1 / 0
C 0 1 1 1 0 0 / 0 0 1 1 / 0
D 1 0 0 0 0 0 / 0 1 0 1 / 0
E 1 0 1 0 0 0 / 0 0 1 1 / 1
Note that bit 0 can clearly be represented by a D flip–flop with D0 = X.

Slide 14 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

Step 4a – Generate the Output Table and Equation

The output table is generated by copying from the table just completed.

Present X= X= The output equation can be obtained from inspection.

State 0 1 As is the case with most sequence detectors, the
output Z is 1 for only one combination of present state
Y2Y1Y0 0 0
and input. Thus we get Z = X  Y2  Y1’  Y0.
0 0 0 0 0
This can be simplified by noting that the state 111 does
0 0 1 0 0
not occur, so the answer is Z = X  Y2  Y0.
0 1 1 0 0
1 0 0 0 0
1 0 1 0 1

Slide 15 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

Step 5 – Separate the Transition Table into 3 Tables, One for Each Flip-Flop
We shall generate a present state / next state table for each of the three flip-
flops; labeled Y2, Y1, and Y0. It is important to note that each of the tables must
include the complete present state, labeled by the three bit vector Y2Y1Y0.
Y2 Y1 Y0
PS Next State PS Next State PS Next State
Y2Y1Y0 X = 0 X = 1 Y2Y1Y0 X = 0 X = 1 Y2Y1Y0 X=0 X=1
000 0 0 000 0 0 000 0 1
001 0 0 001 0 1 001 0 1
011 1 0 011 0 1 011 0 1
100 0 1 100 0 0 100 0 1
101 0 0 101 0 1 101 0 1
Match Y1 Y2Y0’ 0 Y0 0 1

D2 = X’Y1 + XY2Y0’
D1 = X Y0
D0 = X

Slide 16 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

Step 6 – Decide on the type of flip-flops to be used.

The problem stipulates JK flip-flops, so we use them.
Q(T) Q(T + 1) J K
0 0 0 d
0 1 1 d
1 0 d 1
1 1 d 0
Steps 7 and 8 are skipped in this lecture.

Slide 17 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

Step 9 – Summarize the Equations

The purpose of this step is to place all of the equations into one location and
facilitate grading by the instructor. Basically we already have all of the answers.

Z = XY2Y0
J2 = X’Y1 and K2 = X’ + Y0
J1 = XY0 and K1 = X’
J0 = X and K0 = X’

Slide 18 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

Step 10 – Draw the Circuit

Slide 19 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

Here is the same design implemented with D flip-flops.

Slide 20 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

More on Overlap – What it is and What it is not

At this point, we need to focus more precisely on the idea of overlap in a
sequence detector. For an extended example here, we shall use a 1011 sequence
detector.

The next figure shows a partial state diagram for the sequence detector. The
final transitions from state D are not specified; this is intentional.

Here we focus on state C and the X=0

transition coming out of state D. By definition
of the system states,
State C – the last two bits were 10
State D – the last three bits were 101.

Slide 21 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

If the system is in state D and gets a 0 then the last four bits were 1010, not the
desired sequence. If the last four bits were 1010, the last two were 10 – go to
state C. The design must reuse as many bits as possible.

Note that this decision to go to state C when given a 0 is state D is totally

independent of whether or not we are allowing overlap. The question of
overlap concerns what to do when the sequence is detected, not what to do
when we have input that breaks the sequence.

Just to be complete, we give the state diagrams for the two implementations of
the sequence detector – one allowing overlap and one not allowing overlap.

Slide 22 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
Chapter 7 Appendix Design of a 11011 Sequence Detector

The student should note that the decision on overlap does not affect designs for
handling partial results – only what to do when the final 1 in the sequence 1011
is detected.

Slide 23 of 23 slides Revised 9/28/2009

Copyright © 2009 by Edward L. Bosworth, Ph.D. All rights reserved.
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