DA14531 Datasheet 3v1

DA14531
Ultra Low Power Bluetooth 5.1 SoC Final
General Description
The DA14531 is an ultra-low power SoC integrating a 2.4 GHz transceiver and an Arm® Cortex-M0+
microcontroller with a RAM of 48 kB and a One-Time Programmable (OTP) memory of 32 kB. It can
be used as a standalone application processor or as a data pump in hosted systems.
The radio transceiver, the baseband processor, and the qualified Bluetooth® low energy stack is fully
compliant with the Bluetooth® Low Energy 5.1 standard.
The DA14531 has dedicated hardware for the Link Layer implementation of BLE and interface
controllers for enhanced connectivity capabilities.
The BLE firmware includes the L2CAP service layer protocols, Security Manager (SM), Attribute
Protocol (ATT), the Generic Attribute Profile (GATT), and the Generic Access Profile (GAP). All
profiles published by the Bluetooth® SIG as well as custom profiles are supported.
The device is suitable for disposables, wireless sensor nodes, beacons, proximity tags and trackers,
smart HID devices (stylus, keyboards, mice, and trackpads), toys, and medical and industrial
applications.
Key Features
■ Compatible with Bluetooth v5.1, ETSI EN 300 ■ Clocks
328 and EN 300 440 Class 2 (Europe), FCC □ 32 MHz crystal and 32 MHz RC osc.
CFR47 Part 15 (US) and ARIB STD-T66
(Japan) □ 32 kHz crystal and 32/512 kHz RC osc.
■ Supports up to three BLE connections □ 15 kHz RCX as crystal replacement
■ Typical cold boot to radio active 35 ms ■ Programmable Reset Circuitry
■ Processing power ■ 2× General purpose Timers with capture and
PWM capabilities
□ 16 MHz 32-bit Arm® Cortex-M0+ with
SWD interface ■ Digital interfaces
□ 18300 EEMBC IoTMark-BLE® score □ GPIOs: 6 (WLCSP17), 12 (FCGQFN24)
□ Dedicated Link Layer and AES-128 □ 2× UARTs (one with flow control)
Encryption Processor □ SPI Master/Slave up to 32 MHz (Master)
□ Software-based True Random Number □ I2C bus at 100 kHz and 400 kHz
Generator (TRNG) □ 3-axis capable Quadrature Decoder
■ Memories □ Keyboard controller
□ 32 kB One-Time-Programmable (OTP) ■ Analog interfaces
□ 48 kB Retainable System RAM □ 4-channel 10-bit ADC
□ 144 kB ROM ■ Radio transceiver
■ Power management □ Fully integrated 2.4 GHz CMOS
□ Integrated Buck/Boost DCDC converter transceiver
□ Buck: 1.1 V ≤ VBAT_HIGH ≤ 3.3 V (min 1.8V if □ Single wire antenna
OTP read needed) □ TX: 3.5 mA, RX: 2.2 mA (system currents
□ Boost: 1.1 V ≤ VBAT_LOW ≤ 1.65 V with DC-DC, VBAT_HIGH =3 V and 0 dBm)
□ Clock-less hibernation mode: Buck 270 □ Programmable transmit output power from
nA, Boost 240 nA -19.5 dBm to +2.5 dBm
□ Built-in temperature sensor for die □ -94 dBm receiver sensitivity
temperature monitoring ■ Packages:
□ WLCSP 17 balls, 1.7 × 2.05, 0.5 mm pitch
□ FCGQFN 24 pins, 2.2 × 3, 0.4 mm pitch
Datasheet Revision 3.1 09-Jul-2020
CFR0011-120-00 1 of 374 © 2020 Dialog Semiconductor

DA14531
Applications
■ Medical applications
■ Disposables
■ Beacons
■ Proximity tags and trackers
■ Wireless sensor nodes
□ Fitness trackers
□ Consumer health
■ Smartwatches
■ Human interface devices (HID)
□ Stylus pens
□ Keyboards
□ Mouse devices
□ Trackpads
■ Toys
■ Industrial appliances
Key Benefits
■ Lowest power consumption
■ Smallest system size
■ Lowest system cost
System Diagram
Figure 1: System Diagram

DA14531
Contents
General Description ............................................................................................................................ 1
Key Features ........................................................................................................................................ 1
Applications ......................................................................................................................................... 2
Key Benefits ......................................................................................................................................... 2
System Diagram .................................................................................................................................. 2
Contents ............................................................................................................................................... 3
Figures .................................................................................................................................................. 9
Tables ................................................................................................................................................. 10
1 Block Diagram ............................................................................................................................. 19
2 Packages and Pinout .................................................................................................................. 20
2.1 WLCSP17 ........................................................................................................................... 20
2.2 FCGQFN24 ......................................................................................................................... 24
3 Specifications .............................................................................................................................. 28
3.1 Absolute Maximum Ratings ................................................................................................ 30
3.2 Recommended Operating Conditions ................................................................................. 30
3.3 DC Characteristics .............................................................................................................. 31
3.4 Timing Characteristics......................................................................................................... 33
3.5 RCX Oscillator ..................................................................................................................... 33
3.6 XTAL32MHz Oscillator ........................................................................................................ 34
3.7 XTAL32kHz Oscillator ......................................................................................................... 34
3.8 RC32MHz Oscillator ............................................................................................................ 35
3.9 DC-DC Converter ................................................................................................................ 35
3.10 LDO_LOW Characteristics .................................................................................................. 36
3.11 Digital I/O Characteristics.................................................................................................... 37
3.12 Power On Reset .................................................................................................................. 39
3.13 GP ADC .............................................................................................................................. 39
3.14 Temperature Sensor ........................................................................................................... 41
3.15 Radio ................................................................................................................................... 41
4 System Overview ......................................................................................................................... 46
4.1 Internal Blocks..................................................................................................................... 46
4.2 Power Management Unit..................................................................................................... 47
4.2.1 Introduction .......................................................................................................... 47
4.2.2 Architecture .......................................................................................................... 47
4.2.2.1 Digital Power Domains .................................................................... 49
4.2.2.2 Power Modes ................................................................................... 50
4.2.2.3 VDD Level in Hibernation ................................................................ 53
4.2.2.4 Retainable Registers ....................................................................... 53
4.2.3 Programming ....................................................................................................... 53
4.2.3.1 Buck Configuration .......................................................................... 53
4.2.3.2 Boost Configuration ......................................................................... 54
4.2.3.3 Bypass Configuration....................................................................... 55
4.3 HW FSM (Power-up, Wake-up, and Go-to-Sleep) .............................................................. 56

DA14531
4.3.1 Power-up/Wake-up in Buck Configuration........................................................... 56

4.3.2 Power-up/Wake-up in Boost Configuration ......................................................... 58
4.3.3 Go-to-Sleep and Refresh Bandgap ..................................................................... 59
4.4 OTP Memory Layout ........................................................................................................... 60
4.4.1 OTP Header ......................................................................................................... 60
4.4.2 Configuration Script ............................................................................................. 62
4.5 BootROM Sequence ........................................................................................................... 63
5 Reset ............................................................................................................................................. 67
5.1 Introduction ......................................................................................................................... 67
5.2 Architecture ......................................................................................................................... 67
5.2.1 POR, HW, and SW Reset .................................................................................... 67
5.2.2 POR Functionality ................................................................................................ 69
5.2.2.1 POR Timer Clock ............................................................................. 69
5.2.2.2 RST Pad .......................................................................................... 69
5.2.2.3 POR from GPIO ............................................................................... 69
5.2.3 POR Timing Diagram ........................................................................................... 69
5.2.4 POR Considerations ............................................................................................ 70
5.3 Programming ....................................................................................................................... 70
6 Arm Cortex-M0+........................................................................................................................... 71
6.1 Introduction ......................................................................................................................... 71
6.2 Architecture ......................................................................................................................... 72
6.2.1 Interrupts .............................................................................................................. 72
6.2.2 System Timer (systick) ........................................................................................ 74
6.2.3 Wake-Up Interrupt Controller ............................................................................... 74
6.3 Programming ....................................................................................................................... 74
7 AMBA Bus .................................................................................................................................... 75
7.1 Introduction ......................................................................................................................... 75
7.2 Architecture ......................................................................................................................... 75
7.3 Programming ....................................................................................................................... 76
8 Memory Map................................................................................................................................. 77
9 Memory Controller ...................................................................................................................... 79
9.1 Introduction ......................................................................................................................... 79
9.2 Architecture ......................................................................................................................... 79
9.2.1 Arbitration ............................................................................................................ 80
10 Clock Generation ......................................................................................................................... 81
10.1 Clock Tree ........................................................................................................................... 81
10.1.1 General Clock Constraints ................................................................................... 83
10.2 Crystal Oscillators ............................................................................................................... 83
10.2.1 Frequency Control (32 MHz Crystal) ................................................................... 83
10.2.2 Automated Trimming and Settling Notification .................................................... 84
10.3 RC Oscillators ..................................................................................................................... 85
10.3.1 Frequency Calibration .......................................................................................... 86
11 OTP Controller ............................................................................................................................. 87
11.1 Introduction ......................................................................................................................... 87
11.2 Architecture ......................................................................................................................... 87

DA14531
11.2.1 OTP Accessing Considerations ........................................................................... 89

11.3 Programming ....................................................................................................................... 89
12 DMA Controller ............................................................................................................................ 90
12.1 Introduction ......................................................................................................................... 90
12.2 Architecture ......................................................................................................................... 90
12.2.1 DMA Peripherals .................................................................................................. 90
12.2.2 Input/Output Multiplexer....................................................................................... 91
12.2.3 DMA Channel Operation...................................................................................... 91
12.2.4 DMA Arbitration ................................................................................................... 92
12.2.5 Freezing DMA Channels...................................................................................... 93
12.3 Programming ....................................................................................................................... 93
12.3.1 Memory to Memory Transfers.............................................................................. 93
12.3.2 Peripheral to Memory Transfers .......................................................................... 93
13 I2C Interface ................................................................................................................................. 95
13.1 Introduction ......................................................................................................................... 95
13.2 Architecture ......................................................................................................................... 95
13.2.1 I2C Bus Terms ..................................................................................................... 96
13.2.1.1 Bus Transfer Terms ......................................................................... 97
13.2.2 I2C Behavior ........................................................................................................ 97
13.2.2.1 START and STOP Generation ........................................................ 98
13.2.2.2 Combined Formats .......................................................................... 98
13.2.3 I2C Protocols ....................................................................................................... 98
13.2.3.1 START and STOP Conditions ......................................................... 98
13.2.3.2 Addressing Slave Protocol .............................................................. 99
13.2.3.3 Transmitting and Receiving Protocols ........................................... 100
13.2.4 Multiple Master Arbitration ................................................................................. 101
13.2.5 Clock Synchronization ....................................................................................... 102
13.3 Programming ..................................................................................................................... 103
14 UART ........................................................................................................................................... 105
14.1 Introduction ....................................................................................................................... 105
14.2 Architecture ....................................................................................................................... 106
14.2.1 UART (RS232) Serial Protocol .......................................................................... 106
14.2.2 Clock Support .................................................................................................... 107
14.2.3 Interrupts ............................................................................................................ 107
14.2.4 Programmable THRE Interrupt .......................................................................... 108
14.2.5 Shadow Registers .............................................................................................. 110
14.2.6 Direct Test Mode ............................................................................................... 110
14.3 Programming ..................................................................................................................... 110
15 SPI Interface ............................................................................................................................... 112
15.1 Introduction ....................................................................................................................... 112
15.2 Architecture ....................................................................................................................... 113
15.2.1 SPI Timing ......................................................................................................... 113
15.3 Programming ..................................................................................................................... 114
15.3.1 Master Mode ...................................................................................................... 114
15.3.2 Slave Mode ........................................................................................................ 115

DA14531
16 Quadrature Decoder .................................................................................................................. 116

16.1 Introduction ....................................................................................................................... 116
16.2 Architecture ....................................................................................................................... 116
16.3 Programming ..................................................................................................................... 118
17 Clockless Wakeup Controller................................................................................................... 119
17.1 Introduction ....................................................................................................................... 119
17.2 Architecture ....................................................................................................................... 119
17.3 Programming ..................................................................................................................... 120
18 Clocked Wakeup Controller ..................................................................................................... 121
18.1 Introduction ....................................................................................................................... 121
18.2 Architecture ....................................................................................................................... 121
18.3 Programming ..................................................................................................................... 122
19 Timer 0 ........................................................................................................................................ 124
19.1 Introduction ....................................................................................................................... 124
19.2 Architecture ....................................................................................................................... 124
19.3 Programming ..................................................................................................................... 126
19.3.1 Timer Functionality ............................................................................................ 126
19.3.2 PWM Generation ............................................................................................... 127
20 Timer 1 ........................................................................................................................................ 127
20.1 Introduction ....................................................................................................................... 127
20.2 Architecture ....................................................................................................................... 128
20.3 Programming ..................................................................................................................... 128
20.3.1 Timer Functionality ............................................................................................ 128
20.3.2 Capture Functionality ......................................................................................... 129
20.3.3 Frequency Measuring Functionality ................................................................... 129
21 Timer 2 ........................................................................................................................................ 130
21.1 Introduction ....................................................................................................................... 130
21.2 Architecture ....................................................................................................................... 131
21.3 Programming ..................................................................................................................... 132
21.3.1 PWM Generation ............................................................................................... 132
21.3.2 Freeze Functionality .......................................................................................... 132
22 Watchdog Timer ........................................................................................................................ 133
22.1 Introduction ....................................................................................................................... 133
22.2 Architecture ....................................................................................................................... 133
22.3 Programming ..................................................................................................................... 134
23 Temperature Sensor ................................................................................................................. 135
23.1 Introduction ....................................................................................................................... 135
23.2 Architecture ....................................................................................................................... 135
23.2.1 Programming ..................................................................................................... 136
23.2.1.1 Absolute Temperature ................................................................... 136
23.2.1.2 Relative Temperature .................................................................... 137
24 Keyboard Controller .................................................................................................................. 138
24.1 Introduction ....................................................................................................................... 138
24.2 Architecture ....................................................................................................................... 138

DA14531
24.2.1 Keyboard Scanner ............................................................................................. 138

24.2.2 GPIO Interrupt Generator .................................................................................. 139
24.3 Programming ..................................................................................................................... 140
24.3.1 Keyboard Scanner ............................................................................................. 140
24.3.2 GPIO Interrupts .................................................................................................. 140
25 Input/Output Ports ..................................................................................................................... 141
25.1 Introduction ....................................................................................................................... 141
25.2 Architecture ....................................................................................................................... 141
25.2.1 Programmable Pin Assignment ......................................................................... 141
25.2.1.1 Priority ............................................................................................ 142
25.2.1.2 Direction Control ............................................................................ 142
25.2.2 General Purpose Port Registers ........................................................................ 142
25.2.2.1 Port Data Register ......................................................................... 142
25.2.2.2 Port Set Data Output Register ....................................................... 142
25.2.2.3 Port Reset Data Output Register ................................................... 142
25.2.3 Fixed Assignment Functionality ......................................................................... 142
25.2.4 Types of GPIO Pads .......................................................................................... 143
25.2.5 Driving Strength ................................................................................................. 144
26 General Purpose ADC ............................................................................................................... 145
26.1 Introduction ....................................................................................................................... 145
26.2 Architecture ....................................................................................................................... 146
26.2.1 Input Channels ................................................................................................... 146
26.2.2 Operating Modes ............................................................................................... 147
26.2.2.1 Enabling the ADC .......................................................................... 148
26.2.2.2 Manual Mode ................................................................................. 148
26.2.2.3 Continuous Mode........................................................................... 148
26.2.3 Conversion Modes ............................................................................................. 148
26.2.3.1 AD Conversion ............................................................................... 148
26.2.3.2 Averaging ....................................................................................... 150
26.2.3.3 Chopper Mode ............................................................................... 150
26.2.4 Additional Settings ............................................................................................. 150
26.2.5 Non-Ideal Effects ............................................................................................... 151
26.2.6 Offset Calibration ............................................................................................... 151
26.2.7 Zero-Scale Adjustment ...................................................................................... 151
26.2.8 Common Mode Adjustment ............................................................................... 152
26.2.9 Input Impedance, Inductance, and Input Settling .............................................. 152
26.3 Programming ..................................................................................................................... 152
27 Real Time Clock (RTC) .............................................................................................................. 153
27.1 Introduction ....................................................................................................................... 153
27.2 Architecture ....................................................................................................................... 153
27.3 Programming ..................................................................................................................... 154
28 Power .......................................................................................................................................... 155
28.1 DCDC Converter ............................................................................................................... 155
28.2 LDOs ................................................................................................................................. 157
28.3 POR Circuit ....................................................................................................................... 157

DA14531
29 BLE Core .................................................................................................................................... 158

29.1 Architecture ....................................................................................................................... 158
29.1.1 Exchange Memory ............................................................................................. 158
29.2 Programming ..................................................................................................................... 159
29.2.1 Wake-Up IRQ .................................................................................................... 159
29.2.2 Switch from BLE Active Mode to BLE Deep Sleep Mode ................................. 159
29.2.3 Switch from BLE Deep Sleep Mode to BLE Active Mode ................................. 160
29.2.3.1 Switching at an Anchor Point ......................................................... 160
29.2.3.2 Switching Due to an External Event .............................................. 162
30 Radio........................................................................................................................................... 163
30.1 Introduction ....................................................................................................................... 163
30.2 Architecture ....................................................................................................................... 163
30.2.1 Receiver ............................................................................................................. 163
30.2.2 Synthesizer ........................................................................................................ 164
30.2.3 Transmitter ......................................................................................................... 164
30.2.4 RFIO .................................................................................................................. 164
30.2.5 Biasing ............................................................................................................... 164
30.2.6 RF Monitoring .................................................................................................... 164
31 Registers .................................................................................................................................... 165
31.1 Analog Miscellaneous Registers ....................................................................................... 165
31.2 BLE Core Registers .......................................................................................................... 167
31.3 Clock Generation and Reset Registers ............................................................................. 194
31.4 DCDC Converter Registers ............................................................................................... 207
31.5 DMA Controller Registers ................................................................................................. 209
31.6 General Purpose ADC Registers ...................................................................................... 224
31.7 General Purpose I/O Registers ......................................................................................... 229
31.8 General Purpose Registers ............................................................................................... 236
31.9 I2C Interface Registers ..................................................................................................... 239
31.10 Keyboard Registers ........................................................................................................... 260
31.11 Miscellaneous Registers ................................................................................................... 264
31.12 OTP Controller Registers .................................................................................................. 267
31.13 Quadrature Decoder Registers ......................................................................................... 274
31.14 Real Time Clock Registers................................................................................................ 277
31.15 SPI Interface Registers ..................................................................................................... 283
31.16 Timer and Triple PWM Registers ...................................................................................... 288
31.17 Timer1 Registers ............................................................................................................... 293
31.18 UART Interface Registers ................................................................................................. 297
31.19 Chip Version Registers ..................................................................................................... 363
31.20 Wake-Up Registers ........................................................................................................... 364
31.21 Watchdog Registers .......................................................................................................... 367
32 Ordering Information ................................................................................................................ 369
33 Package Information ................................................................................................................. 370
33.1 Moisture Sensitivity Level (MSL) ....................................................................................... 370
33.2 WLCSP Handling .............................................................................................................. 370
33.3 Soldering Information ........................................................................................................ 370

DA14531
33.4 Package Outlines .............................................................................................................. 370

Revision History .............................................................................................................................. 373
Figures
Figure 1: System Diagram ..................................................................................................................... 2
Figure 2: DA14531 Block Diagram ...................................................................................................... 19
Figure 3: WLCSP17 Ball Assignment (Top View) ............................................................................... 20
Figure 4: FCGQFN24 Pin Assignment (Top View) ............................................................................. 24
Figure 5: Boost configuration system diagram .................................................................................... 29
Figure 6: Buck configuration system diagram ..................................................................................... 29
Figure 7: Power Management Unit: Buck Configuration ..................................................................... 48
Figure 8: Power Management Unit: Boost Configuration .................................................................... 48
Figure 9: Power Management Unit: Bypass Configuration ................................................................. 49
Figure 10: Digital Power Domains ....................................................................................................... 49
Figure 11: Power-Up/Wake-Up/Sleep FSM Diagram .......................................................................... 56
Figure 12: Power-up (Buck)................................................................................................................. 57
Figure 13: Wake-Up from hibernation (Buck) ...................................................................................... 57
Figure 14: Wake-Up (Buck) ................................................................................................................. 58
Figure 15: Power-Up (Boost) ............................................................................................................... 58
Figure 16: Wake-Up from hibernation (Boost)..................................................................................... 59
Figure 17: Wake-Up from extended/deep sleep (Boost) ..................................................................... 59
Figure 18: Go-to-Sleep and Bandgap Refresh .................................................................................... 59
Figure 19: OTP Layout Scheme .......................................................................................................... 60
Figure 20: BootROM Sequence .......................................................................................................... 65
Figure 21: Reset Block Diagram ......................................................................................................... 67
Figure 22: POR Timing Diagram ......................................................................................................... 70
Figure 23: Arm Cortex-M0+ Block Diagram ........................................................................................ 71
Figure 24: AMBA Bus Architecture and Power Domains .................................................................... 75
Figure 25: Memory Controller Block Diagram ..................................................................................... 79
Figure 26: Clock Tree Diagram ........................................................................................................... 81
Figure 27: Crystal Oscillator Circuits ................................................................................................... 83
Figure 28: XTAL32MHz Oscillator Frequency Trimming ..................................................................... 84
Figure 29: Automated Mechanism for XTAL32M Trim and Settling .................................................... 85
Figure 30: OTP Controller Block Diagram ........................................................................................... 87
Figure 31: DMA Controller Block Diagram .......................................................................................... 90
Figure 32: DMA Channel Diagram ...................................................................................................... 92
Figure 33: I2C Controller Block Diagram ............................................................................................. 95
Figure 34: Master/Slave and Transmitter/Receiver Relationships ...................................................... 96
Figure 35: Data Transfer on the I2C Bus ............................................................................................ 97
Figure 36: START and STOP Conditions ............................................................................................ 98
Figure 37: 7-bit Address Format .......................................................................................................... 99
Figure 38: 10-bit Address Format ........................................................................................................ 99
Figure 39: Master-Transmitter Protocol ............................................................................................. 100
Figure 40: Master-Receiver Protocol ................................................................................................. 101
Figure 41: START BYTE Transfer ..................................................................................................... 101
Figure 42: Multiple Master Arbitration ............................................................................................... 102
Figure 43: Multiple Master Clock Synchronization ............................................................................ 103
Figure 44: UART Block Diagram ....................................................................................................... 105
Figure 45: Serial Data Format ........................................................................................................... 106
Figure 46: Receiver Serial Data Sampling Points ............................................................................. 106
Figure 47: Flowchart of Interrupt Generation for Programmable THRE Interrupt Mode ................... 109
Figure 48: Flowchart of Interrupt Generation When Not in Programmable THRE Interrupt Mode ... 110
Figure 49: SPI Block Diagram ........................................................................................................... 112
Figure 50: SPI Slave Mode Timing (CPOL = 0, CPHA = 0) .............................................................. 113
Figure 51: Quadrature Decoder Block Diagram ................................................................................ 116
Figure 52: Moving Forward on Axis X ............................................................................................... 117

DA14531
Figure 53: Moving Backwards on Axis X ........................................................................................... 117

Figure 54: Digital Filtering and Edge Detection Circuit ..................................................................... 117
Figure 55: Clockless Wakeup Controller Circuit ................................................................................ 119
Figure 56: Clocked Wakeup Controller Block Diagram ..................................................................... 121
Figure 57: Event Counter State Machine for the Wakeup Interrupt Generator ................................. 122
Figure 58: Timer 0 Block Diagram ..................................................................................................... 124
Figure 59: Timer 0 PWM Mode ......................................................................................................... 126
Figure 62: Timer 2 Timing Diagram ................................................................................................... 132
Figure 63: Watchdog Timer Block Diagram ...................................................................................... 133
Figure 64: Temperature Sensor Behavior ......................................................................................... 135
Figure 65: Keyboard Controller Block Diagram ................................................................................. 138
Figure 66: Keyboard Scanner State Machine ................................................................................... 139
Figure 67: GPIO Interrupt Generator State Machine ........................................................................ 140
Figure 68: Port P0 with Programmable Pin Assignment and driving strength .................................. 141
Figure 69: Type A GPIO Pad - GPIO with Schmitt Trigger on Input ................................................. 143
Figure 70: Type B GPIO Pad - GPIO with Schmitt Trigger and RC Filter on Input ........................... 144
Figure 71: Block Diagram of GPADC ................................................................................................ 145
Figure 72: GPADC Operation Flow Diagram .................................................................................... 147
Figure 73: Real Time Clock Block Diagram ...................................................................................... 153
Figure 74: DCDC Block Diagram - Buck Configuration ..................................................................... 155
Figure 75: DCDC Block Diagram - Boost Configuration ................................................................... 155
Figure 76: DCDC Efficiency in Buck Configuration ........................................................................... 156
Figure 77: DCDC Efficiency in Boost Configuration .......................................................................... 157
Figure 78: BLE Core Block Diagram ................................................................................................. 158
Figure 79: Entering BLE Deep Sleep mode ...................................................................................... 160
Figure 80: Exit BLE Deep Sleep Mode at Predetermined Time (Zoom In) ....................................... 161
Figure 81: Exit BLE Deep Sleep Mode after Predetermined Time (Zoom In) ................................... 161
Figure 82: Exit BLE Deep Sleep Mode at Predetermined Time (Zoom Out) .................................... 161
Figure 83: Exit BLE Deep Sleep Mode Due to External Event ......................................................... 162
Figure 84: Bluetooth Radio Block Diagram ....................................................................................... 163
Figure 85: WLCSP17 Package Outline Drawing ............................................................................... 371
Figure 86: FCGQFN24 Package Outline Drawing ............................................................................ 372
Tables
Table 1: DA14531 WLCSP17 Ball Description.................................................................................... 21
Table 2: DA14531 FCGQFN24 Pin Description .................................................................................. 24
Table 3: Absolute Maximum Ratings ................................................................................................... 30
Table 4: Recommended Operating Conditions ................................................................................... 30
Table 5: DC Characteristics................................................................................................................. 31
Table 6: Timing Characteristics ........................................................................................................... 33
Table 7: RCX Oscillator - Timing Characteristics ................................................................................ 33
Table 8: XTAL32MHz Oscillator - Recommended Operating Conditions ........................................... 34
Table 9: XTAL oscillator 32kHz - Recommended Operating Conditions ............................................ 34
Table 10: XTAL oscillator 32kHz - Timing Characteristics .................................................................. 35
Table 11: RC32MHz Oscillaor - Timing Characteristics ...................................................................... 35
Table 12: DCDC Converter - Recommended Operating Conditions................................................... 35
Table 13: DCDC Converter - DC Characteristics ................................................................................ 36
Table 14: LDO_LOW - Recommended Operating Conditions ............................................................ 36
Table 15: LDO_LOW - DC Characteristics.......................................................................................... 37
Table 16: Digital Pad - Recommended Operating Conditions ............................................................ 37
Table 17: Digital Pad - DC Characteristics .......................................................................................... 38
Table 18: Digital Pad with LPF - DC Characteristics ........................................................................... 38
Table 19: Digital Pad with LPF - Recommended Operating Conditions ............................................. 39

DA14531
Table 20: POR VBAT_LOW - DC Characteristics ............................................................................... 39

Table 21: POR VBAT_HIGH - DC Characteristics .............................................................................. 39
Table 22: GP ADC - Recommended Operating Conditions ................................................................ 39
Table 23: GP ADC - DC Characteristics ............................................................................................. 39
Table 24: GP ADC - Electrical performance........................................................................................ 40
Table 25: Temperature Sensor - DC Characteristics .......................................................................... 41
Table 26: BLE 1Mb/s specifications - Recommended Operating Conditions ..................................... 41
Table 27: BLE 1Mb/s specifications - AC Characteristics ................................................................... 41
Table 28: BLE 1Mb/s specifications - Timing Characteristics ............................................................. 44
Table 29: BLE 1Mb/s specifications - DC Characteristics ................................................................... 44
Table 30: Power Domains Description ................................................................................................ 50
Table 31: Power Modes, Digital Power Domains, Clocks, and Wake-up triggers .............................. 51
Table 32: Power Rails Drivers and Voltages ....................................................................................... 52
Table 33: VDD_Clamp recommended settings over temperature and load ....................................... 53
Table 34: Retainable Registers ........................................................................................................... 53
Table 35: OTP Header ........................................................................................................................ 60
Table 36: CS Commands and Description .......................................................................................... 62
Table 37: CS Example......................................................................................................................... 63
Table 38: Booting Sequence Steps ..................................................................................................... 66
Table 39: Reset Signals and Registers ............................................................................................... 68
Table 40: Interrupt List......................................................................................................................... 72
Table 41: Arm Documents List ............................................................................................................ 74
Table 42: Memory Map........................................................................................................................ 77
Table 43: Generated Clocks Description ............................................................................................. 82
Table 44: DMA Served Peripherals ..................................................................................................... 91
Table 45: I2C Definition of Bits in First Byte in 10-bit Address Format ............................................... 99
Table 46: UART Baud Rate Generation ............................................................................................ 107
Table 47: UART Interrupt Priorities ................................................................................................... 108
Table 48: SPI Modes Configuration and SCK States ........................................................................ 113
Table 49: SPI Timing Parameters ..................................................................................................... 114
Table 50: Fixed Assignment of Specific Signals ............................................................................... 142
Table 51: ADC Input Channels .......................................................................................................... 146
Table 52: GPADC External Input Channels and Voltage Range ...................................................... 146
Table 53: ADC_LDO Start-Up Delay ................................................................................................. 148
Table 54: ADC Sampling Time Constant (τADC_SMPL) ......................................................................... 149
Table 55: ENOB in Oversampling Mode ........................................................................................... 150
Table 56: GPADC Calibration Procedure for Single-Ended and Differential Modes......................... 151
Table 57: Common Mode Adjustment ............................................................................................... 152
Table 58: Register map anamisc2632_bif_00 ................................................................................... 165
Table 59: CLK_REF_SEL_REG (0x50001600) ................................................................................ 165
Table 60: CLK_REF_CNT_REG (0x50001602) ................................................................................ 166
Table 61: CLK_REF_VAL_L_REG (0x50001604) ............................................................................ 166
Table 62: CLK_REF_VAL_H_REG (0x50001606) ............................................................................ 166
Table 63: Register map BLE ............................................................................................................. 167
Table 64: BLE_RWBLECNTL_REG (0x40000000) .......................................................................... 169
Table 65: BLE_VERSION_REG (0x40000004) ................................................................................ 171
Table 66: BLE_RWBLECONF_REG (0x40000008) ......................................................................... 171
Table 67: BLE_INTCNTL_REG (0x4000000C) ................................................................................. 171
Table 68: BLE_INTSTAT_REG (0x40000010).................................................................................. 172
Table 69: BLE_INTRAWSTAT_REG (0x40000014) ......................................................................... 173
Table 70: BLE_INTACK_REG (0x40000018) ................................................................................... 174
Table 71: BLE_BASETIMECNT_REG (0x4000001C) ...................................................................... 175
Table 72: BLE_FINETIMECNT_REG (0x40000020) ........................................................................ 175
Table 73: BLE_BDADDRL_REG (0x40000024) ............................................................................... 176
Table 74: BLE_BDADDRU_REG (0x40000028) ............................................................................... 176
Table 75: BLE_CURRENTRXDESCPTR_REG (0x4000002C) ........................................................ 176
Table 76: BLE_DEEPSLCNTL_REG (0x40000030) ......................................................................... 176
Table 77: BLE_DEEPSLWKUP_REG (0x40000034) ....................................................................... 177

DA14531
Table 78: BLE_DEEPSLSTAT_REG (0x40000038) ......................................................................... 177

Table 79: BLE_ENBPRESET_REG (0x4000003C) .......................................................................... 177
Table 80: BLE_FINECNTCORR_REG (0x40000040) ...................................................................... 178
Table 81: BLE_BASETIMECNTCORR_REG (0x40000044) ............................................................ 178
Table 82: BLE_DIAGCNTL_REG (0x40000050) .............................................................................. 178
Table 83: BLE_DIAGSTAT_REG (0x40000054)............................................................................... 179
Table 84: BLE_DEBUGADDMAX_REG (0x40000058) .................................................................... 179
Table 85: BLE_DEBUGADDMIN_REG (0x4000005C) ..................................................................... 179
Table 86: BLE_ERRORTYPESTAT_REG (0x40000060) ................................................................. 180
Table 87: BLE_SWPROFILING_REG (0x40000064) ....................................................................... 182
Table 88: BLE_RADIOCNTL1_REG (0x40000074) .......................................................................... 182
Table 89: BLE_RADIOPWRUPDN_REG (0x40000080) .................................................................. 182
Table 90: BLE_ADVCHMAP_REG (0x40000090) ............................................................................ 183
Table 91: BLE_ADVTIM_REG (0x400000A0)................................................................................... 183
Table 92: BLE_ACTSCANSTAT_REG (0x400000A4) ...................................................................... 183
Table 93: BLE_WLPUBADDPTR_REG (0x400000B0) .................................................................... 183
Table 94: BLE_WLPRIVADDPTR_REG (0x400000B4) ................................................................... 184
Table 95: BLE_WLNBDEV_REG (0x400000B8) .............................................................................. 184
Table 96: BLE_AESCNTL_REG (0x400000C0) ............................................................................... 184
Table 97: BLE_AESKEY31_0_REG (0x400000C4) ......................................................................... 184
Table 98: BLE_AESKEY63_32_REG (0x400000C8) ....................................................................... 184
Table 99: BLE_AESKEY95_64_REG (0x400000CC) ....................................................................... 184
Table 100: BLE_AESKEY127_96_REG (0x400000D0) ................................................................... 185
Table 101: BLE_AESPTR_REG (0x400000D4) ............................................................................... 185
Table 102: BLE_TXMICVAL_REG (0x400000D8) ............................................................................ 185
Table 103: BLE_RXMICVAL_REG (0x400000DC) ........................................................................... 185
Table 104: BLE_RFTESTCNTL_REG (0x400000E0) ....................................................................... 185
Table 105: BLE_RFTESTTXSTAT_REG (0x400000E4) .................................................................. 186
Table 106: BLE_RFTESTRXSTAT_REG (0x400000E8) .................................................................. 186
Table 107: BLE_TIMGENCNTL_REG (0x400000F0) ....................................................................... 187
Table 108: BLE_GROSSTIMTGT_REG (0x400000F4) .................................................................... 187
Table 109: BLE_FINETIMTGT_REG (0x400000F8) ......................................................................... 187
Table 110: BLE_SAMPLECLK_REG (0x400000FC) ........................................................................ 187
Table 111: BLE_COEXIFCNTL0_REG (0x40000100) ...................................................................... 188
Table 112: BLE_COEXIFCNTL1_REG (0x40000104) ...................................................................... 188
Table 113: BLE_BLEMPRIO0_REG (0x40000108) .......................................................................... 189
Table 114: BLE_BLEMPRIO1_REG (0x4000010C) ......................................................................... 189
Table 115: BLE_CNTL2_REG (0x40000200) ................................................................................... 190
Table 116: BLE_EM_BASE_REG (0x40000208) ............................................................................. 192
Table 117: BLE_DIAGCNTL2_REG (0x4000020C) .......................................................................... 192
Table 118: BLE_DIAGCNTL3_REG (0x40000210) .......................................................................... 193
Table 119: Register map CRG .......................................................................................................... 194
Table 120: CLK_AMBA_REG (0x50000000) .................................................................................... 194
Table 121: CLK_FREQ_TRIM_REG (0x50000002) ......................................................................... 195
Table 122: CLK_PER_REG (0x50000004) ....................................................................................... 195
Table 123: CLK_RADIO_REG (0x50000008) ................................................................................... 196
Table 124: CLK_CTRL_REG (0x5000000A)..................................................................................... 196
Table 125: PMU_CTRL_REG (0x50000010) .................................................................................... 197
Table 126: SYS_CTRL_REG (0x50000012) ..................................................................................... 197
Table 127: SYS_STAT_REG (0x50000014) ..................................................................................... 198
Table 128: TRIM_CTRL_REG (0x50000016) ................................................................................... 199
Table 129: RAM_PWR_CTRL_REG (0x50000018) ......................................................................... 199
Table 130: CLK_RC32K_REG (0x50000020) ................................................................................... 200
Table 131: CLK_XTAL32K_REG (0x50000022) ............................................................................... 200
Table 132: CLK_RC32M_REG (0x50000024) .................................................................................. 200
Table 133: CLK_RCX_REG (0x50000026) ....................................................................................... 201
Table 134: BANDGAP_REG (0x50000028) ...................................................................................... 201
Table 135: ANA_STATUS_REG (0x5000002A) ............................................................................... 201

DA14531
Table 136: XTAL32M_START_REG (0x50000030) ......................................................................... 202

Table 137: XTALRDY_CTRL_REG (0x50000034) ........................................................................... 202
Table 138: XTAL32M_CTRL0_REG (0x50000038) .......................................................................... 203
Table 139: POR_PIN_REG (0x50000040) ........................................................................................ 203
Table 140: POR_TIMER_REG (0x50000042) .................................................................................. 203
Table 141: PMU_SLEEP_REG (0x50000050) .................................................................................. 204
Table 142: POWER_CTRL_REG (0x50000052) .............................................................................. 204
Table 143: POWER_LEVEL_REG (0x50000054) ............................................................................ 205
Table 144: XTAL32M_TRSTAT_REG (0x50000032) ....................................................................... 205
Table 145: Register map crg2632_preg_tim_00 ............................................................................... 206
Table 146: CLK_RTCDIV_REG (0x5000424C) ................................................................................ 206
Table 147: Register map crg2632_dcdc_dig_00 .............................................................................. 207
Table 148: DCDC_CTRL_REG (0x50000080).................................................................................. 207
Table 149: Register map DMA .......................................................................................................... 209
Table 150: DMA0_A_STARTL_REG (0x50003600) ......................................................................... 210
Table 151: DMA0_A_STARTH_REG (0x50003602) ........................................................................ 210
Table 152: DMA0_B_STARTL_REG (0x50003604) ......................................................................... 210
Table 153: DMA0_B_STARTH_REG (0x50003606) ........................................................................ 210
Table 154: DMA0_INT_REG (0x50003608) ...................................................................................... 211
Table 155: DMA0_LEN_REG (0x5000360A) .................................................................................... 211
Table 156: DMA0_CTRL_REG (0x5000360C) ................................................................................. 211
Table 157: DMA0_IDX_REG (0x5000360E) ..................................................................................... 213
Table 182: DMA_REQ_MUX_REG (0x50003680) ........................................................................... 221
Table 183: DMA_INT_STATUS_REG (0x50003682) ....................................................................... 222
Table 184: DMA_CLEAR_INT_REG (0x50003684) ......................................................................... 223
Table 185: Register map GPADC ..................................................................................................... 224
Table 186: GP_ADC_CTRL_REG (0x50001500) ............................................................................. 224
Table 187: GP_ADC_CTRL2_REG (0x50001502) ........................................................................... 225
Table 188: GP_ADC_CTRL3_REG (0x50001504) ........................................................................... 226
Table 189: GP_ADC_OFFP_REG (0x50001508) ............................................................................. 226
Table 190: GP_ADC_OFFN_REG (0x5000150A) ............................................................................ 226
Table 191: GP_ADC_TRIM_REG (0x5000150C) ............................................................................. 227
Table 192: GP_ADC_CLEAR_INT_REG (0x5000150E) .................................................................. 227
Table 193: GP_ADC_RESULT_REG (0x50001510) ........................................................................ 227

DA14531
Table 194: GP_ADC_SEL_REG (0x50001506) ................................................................................ 227

Table 195: Register map GPIO ......................................................................................................... 229
Table 196: P0_DATA_REG (0x50003000) ....................................................................................... 229
Table 197: P0_SET_DATA_REG (0x50003002) .............................................................................. 229
Table 198: P0_RESET_DATA_REG (0x50003004) ......................................................................... 230
Table 199: P00_MODE_REG (0x50003006) .................................................................................... 230
Table 200: P01_MODE_REG (0x50003008) .................................................................................... 231
Table 201: P02_MODE_REG (0x5000300A) .................................................................................... 232
Table 202: P03_MODE_REG (0x5000300C).................................................................................... 232
Table 203: P04_MODE_REG (0x5000300E) .................................................................................... 232
Table 204: P05_MODE_REG (0x50003010) .................................................................................... 233
Table 205: P06_MODE_REG (0x50003012) .................................................................................... 233
Table 206: P07_MODE_REG (0x50003014) .................................................................................... 233
Table 207: P08_MODE_REG (0x50003016) .................................................................................... 234
Table 208: P09_MODE_REG (0x50003018) .................................................................................... 234
Table 209: P010_MODE_REG (0x5000301A) .................................................................................. 234
Table 210: P011_MODE_REG (0x5000301C) ................................................................................. 234
Table 211: PAD_WEAK_CTRL_REG (0x5000301E) ....................................................................... 235
Table 212: Register map GPREG ..................................................................................................... 236
Table 213: SET_FREEZE_REG (0x50003300) ................................................................................ 236
Table 214: RESET_FREEZE_REG (0x50003302) ........................................................................... 236
Table 215: DEBUG_REG (0x50003304) ........................................................................................... 237
Table 216: GP_STATUS_REG (0x50003306) .................................................................................. 237
Table 217: GP_CONTROL_REG (0x50003308)............................................................................... 237
Table 218: BLE_TIMER_REG (0x5000330A) ................................................................................... 237
Table 219: Register map I2C............................................................................................................. 239
Table 220: I2C_CON_REG (0x50001300) ........................................................................................ 240
Table 221: I2C_TAR_REG (0x50001304) ......................................................................................... 241
Table 222: I2C_SAR_REG (0x50001308) ........................................................................................ 242
Table 223: I2C_DATA_CMD_REG (0x50001310) ............................................................................ 242
Table 224: I2C_SS_SCL_HCNT_REG (0x50001314) ...................................................................... 244
Table 225: I2C_SS_SCL_LCNT_REG (0x50001318) ...................................................................... 244
Table 226: I2C_FS_SCL_HCNT_REG (0x5000131C) ..................................................................... 244
Table 227: I2C_FS_SCL_LCNT_REG (0x50001320) ....................................................................... 245
Table 228: I2C_INTR_STAT_REG (0x5000132C) ........................................................................... 245
Table 229: I2C_INTR_MASK_REG (0x50001330) ........................................................................... 247
Table 230: I2C_RAW_INTR_STAT_REG (0x50001334) .................................................................. 247
Table 231: I2C_RX_TL_REG (0x50001338)..................................................................................... 249
Table 232: I2C_TX_TL_REG (0x5000133C) .................................................................................... 250
Table 233: I2C_CLR_INTR_REG (0x50001340) .............................................................................. 250
Table 234: I2C_CLR_RX_UNDER_REG (0x50001344) ................................................................... 250
Table 235: I2C_CLR_RX_OVER_REG (0x50001348) ..................................................................... 250
Table 236: I2C_CLR_TX_OVER_REG (0x5000134C) ..................................................................... 251
Table 237: I2C_CLR_RD_REQ_REG (0x50001350) ....................................................................... 251
Table 238: I2C_CLR_TX_ABRT_REG (0x50001354) ...................................................................... 251
Table 239: I2C_CLR_RX_DONE_REG (0x50001358) ..................................................................... 251
Table 240: I2C_CLR_ACTIVITY_REG (0x5000135C) ...................................................................... 251
Table 241: I2C_CLR_STOP_DET_REG (0x50001360) ................................................................... 252
Table 242: I2C_CLR_START_DET_REG (0x50001364) ................................................................. 252
Table 243: I2C_CLR_GEN_CALL_REG (0x50001368) .................................................................... 252
Table 244: I2C_ENABLE_REG (0x5000136C) ................................................................................. 252
Table 245: I2C_STATUS_REG (0x50001370).................................................................................. 253
Table 246: I2C_TXFLR_REG (0x50001374) .................................................................................... 254
Table 247: I2C_RXFLR_REG (0x50001378) .................................................................................... 254
Table 248: I2C_SDA_HOLD_REG (0x5000137C) ............................................................................ 254
Table 249: I2C_TX_ABRT_SOURCE_REG (0x50001380) .............................................................. 255
Table 250: I2C_DMA_CR_REG (0x50001388)................................................................................. 256
Table 251: I2C_DMA_TDLR_REG (0x5000138C) ............................................................................ 256

DA14531
Table 252: I2C_DMA_RDLR_REG (0x50001390) ............................................................................ 257

Table 253: I2C_SDA_SETUP_REG (0x50001394) .......................................................................... 257
Table 254: I2C_ACK_GENERAL_CALL_REG (0x50001398) .......................................................... 257
Table 255: I2C_ENABLE_STATUS_REG (0x5000139C) ................................................................. 257
Table 256: I2C_IC_FS_SPKLEN_REG (0x500013A0) ..................................................................... 259
Table 257: Register map KBRD ........................................................................................................ 260
Table 258: GPIO_IRQ0_IN_SEL_REG (0x50001400) ..................................................................... 260
Table 263: GPIO_DEBOUNCE_REG (0x5000140C) ....................................................................... 261
Table 264: GPIO_RESET_IRQ_REG (0x5000140E) ....................................................................... 262
Table 265: GPIO_INT_LEVEL_CTRL_REG (0x50001410) .............................................................. 262
Table 266: KBRD_IRQ_IN_SEL0_REG (0x50001412) .................................................................... 262
Table 267: KBRD_CTRL_REG (0x50001414) .................................................................................. 263
Table 268: Register map crg2632_preg_aon_00 .............................................................................. 264
Table 269: HWR_CTRL_REG (0x50000300) ................................................................................... 264
Table 270: RESET_STAT_REG (0x50000304) ................................................................................ 264
Table 271: RAM_LPMX_REG (0x50000308).................................................................................... 264
Table 272: PAD_LATCH_REG (0x5000030C).................................................................................. 265
Table 273: HIBERN_CTRL_REG (0x50000310) .............................................................................. 265
Table 274: POWER_AON_CTRL_REG (0x50000320) .................................................................... 265
Table 275: GP_DATA_REG (0x50000324) ....................................................................................... 266
Table 276: Register map OTPC ........................................................................................................ 267
Table 277: OTPC_MODE_REG (0x07F40000) ................................................................................ 267
Table 278: OTPC_STAT_REG (0x07F40004) .................................................................................. 268
Table 279: OTPC_PADDR_REG (0x07F40008) .............................................................................. 269
Table 280: OTPC_PWORD_REG (0x07F4000C) ............................................................................. 270
Table 281: OTPC_TIM1_REG (0x07F40010) ................................................................................... 270
Table 282: OTPC_TIM2_REG (0x07F40014) ................................................................................... 271
Table 283: OTPC_AHBADR_REG (0x07F40018) ............................................................................ 272
Table 284: OTPC_CELADR_REG (0x07F4001C) ............................................................................ 272
Table 285: OTPC_NWORDS_REG (0x07F40020) ........................................................................... 273
Table 286: Register map QDEC ........................................................................................................ 274
Table 287: QDEC_CTRL_REG (0x50000200).................................................................................. 274
Table 288: QDEC_XCNT_REG (0x50000202) ................................................................................. 274
Table 289: QDEC_YCNT_REG (0x50000204) ................................................................................. 274
Table 290: QDEC_CLOCKDIV_REG (0x50000206) ........................................................................ 275
Table 291: QDEC_CTRL2_REG (0x50000208)................................................................................ 275
Table 292: QDEC_ZCNT_REG (0x5000020A) ................................................................................. 276
Table 293: QDEC_EVENT_CNT_REG (0x5000020C) ..................................................................... 276
Table 294: Register map rtc2632_00 ................................................................................................ 277
Table 295: RTC_CONTROL_REG (0x50004100) ............................................................................ 277
Table 296: RTC_HOUR_MODE_REG (0x50004104) ...................................................................... 277
Table 297: RTC_TIME_REG (0x50004108) ..................................................................................... 278
Table 298: RTC_CALENDAR_REG (0x5000410C) .......................................................................... 278
Table 299: RTC_TIME_ALARM_REG (0x50004110) ....................................................................... 278
Table 300: RTC_CALENDAR_ALARM_REG (0x50004114) ............................................................ 279
Table 301: RTC_ALARM_ENABLE_REG (0x50004118) ................................................................. 279
Table 302: RTC_EVENT_FLAGS_REG (0x5000411C) ................................................................... 280
Table 303: RTC_INTERRUPT_ENABLE_REG (0x50004120) ......................................................... 280
Table 304: RTC_INTERRUPT_DISABLE_REG (0x50004124) ........................................................ 281
Table 305: RTC_INTERRUPT_MASK_REG (0x50004128) ............................................................. 281
Table 306: RTC_STATUS_REG (0x5000412C) ............................................................................... 282
Table 307: RTC_KEEP_RTC_REG (0x50004130) ........................................................................... 282
Table 308: Register map SPI ............................................................................................................ 283
Table 309: SPI_CTRL_REG (0x50001200) ...................................................................................... 283

DA14531
Table 310: SPI_CONFIG_REG (0x50001204).................................................................................. 284

Table 311: SPI_CLOCK_REG (0x50001208) ................................................................................... 284
Table 312: SPI_FIFO_CONFIG_REG (0x5000120C) ....................................................................... 285
Table 313: SPI_IRQ_MASK_REG (0x50001210) ............................................................................. 285
Table 314: SPI_STATUS_REG (0x50001214) ................................................................................. 285
Table 315: SPI_FIFO_STATUS_REG (0x50001218) ....................................................................... 286
Table 316: SPI_FIFO_READ_REG (0x5000121C) ........................................................................... 286
Table 317: SPI_FIFO_WRITE_REG (0x50001220) .......................................................................... 286
Table 318: SPI_CS_CONFIG_REG (0x50001224) .......................................................................... 286
Table 319: SPI_FIFO_HIGH_REG (0x50001228) ............................................................................ 287
Table 320: SPI_TXBUFFER_FORCE_L_REG (0x5000122C) ......................................................... 287
Table 321: SPI_TXBUFFER_FORCE_H_REG (0x50001230) ......................................................... 287
Table 322: Register map Timer+3PWM ............................................................................................ 288
Table 323: TIMER0_CTRL_REG (0x50003400) ............................................................................... 288
Table 324: TIMER0_ON_REG (0x50003402) ................................................................................... 289
Table 325: TIMER0_RELOAD_M_REG (0x50003404) .................................................................... 289
Table 326: TIMER0_RELOAD_N_REG (0x50003406) ..................................................................... 289
Table 327: TRIPLE_PWM_FREQUENCY (0x50003408) ................................................................. 289
Table 328: PWM2_START_CYCLE (0x5000340A) .......................................................................... 290
Table 329: PWM3_START_CYCLE (0x5000340C) .......................................................................... 290
Table 330: PWM4_START_CYCLE (0x5000340E) .......................................................................... 290
Table 331: PWM5_START_CYCLE (0x50003410) .......................................................................... 290
Table 334: PWM2_END_CYCLE (0x50003416) ............................................................................... 291
Table 336: PWM4_END_CYCLE (0x5000341A) .............................................................................. 291
Table 337: PWM5_END_CYCLE (0x5000341C) .............................................................................. 291
Table 338: PWM6_END_CYCLE (0x5000341E) .............................................................................. 291
Table 340: TRIPLE_PWM_CTRL_REG (0x50003422) .................................................................... 292
Table 341: Register map Timer1 ....................................................................................................... 293
Table 342: TIMER1_CTRL_REG (0x50004000) ............................................................................... 293
Table 343: TIMER1_CAPTURE_REG (0x50004004) ....................................................................... 293
Table 344: TIMER1_STATUS_REG (0x50004008) .......................................................................... 294
Table 345: TIMER1_CAPCNT1_VALUE_REG (0x5000400C) ......................................................... 295
Table 346: TIMER1_CAPCNT2_VALUE_REG (0x50004010) ......................................................... 295
Table 347: TIMER1_CLR_EVENT_REG (0x50004014) ................................................................... 295
Table 348: Register map UART ........................................................................................................ 297
Table 349: UART_RBR_THR_DLL_REG (0x50001000) .................................................................. 300
Table 350: UART_IER_DLH_REG (0x50001004) ............................................................................ 300
Table 351: UART_IIR_FCR_REG (0x50001008).............................................................................. 302
Table 352: UART_LCR_REG (0x5000100C) .................................................................................... 304
Table 353: UART_MCR_REG (0x50001010) ................................................................................... 305
Table 354: UART_LSR_REG (0x50001014) ..................................................................................... 306
Table 355: UART_MSR_REG (0x50001018).................................................................................... 309
Table 356: UART_SCR_REG (0x5000101C) ................................................................................... 309
Table 357: UART_SRBR_STHR0_REG (0x50001030) .................................................................... 309
Table 360: UART_SRBR_STHR3_REG (0x5000103C) ................................................................... 312
Table 364: UART_SRBR_STHR7_REG (0x5000104C) ................................................................... 316
Table 367: UART_SRBR_STHR10_REG (0x50001058) .................................................................. 319

DA14531
Table 368: UART_SRBR_STHR11_REG (0x5000105C) ................................................................. 320

Table 372: UART_SRBR_STHR15_REG (0x5000106C) ................................................................. 324
Table 373: UART_FAR_REG (0x50001070) .................................................................................... 325
Table 374: UART_USR_REG (0x5000107C) ................................................................................... 326
Table 375: UART_TFL_REG (0x50001080) ..................................................................................... 327
Table 376: UART_RFL_REG (0x50001084) ..................................................................................... 327
Table 377: UART_SRR_REG (0x50001088) .................................................................................... 327
Table 378: UART_SRTS_REG (0x5000108C) ................................................................................. 327
Table 379: UART_SBCR_REG (0x50001090).................................................................................. 328
Table 380: UART_SDMAM_REG (0x50001094) .............................................................................. 328
Table 381: UART_SFE_REG (0x50001098) ..................................................................................... 329
Table 382: UART_SRT_REG (0x5000109C) .................................................................................... 329
Table 383: UART_STET_REG (0x500010A0) .................................................................................. 330
Table 384: UART_HTX_REG (0x500010A4) .................................................................................... 330
Table 385: UART_DMASA_REG (0x500010A8) .............................................................................. 330
Table 386: UART_DLF_REG (0x500010C0) .................................................................................... 331
Table 387: UART_UCV_REG (0x500010F8) .................................................................................... 331
Table 388: UART_UCV_HIGH_REG (0x500010FA) ........................................................................ 331
Table 389: UART_CTR_REG (0x500010FC) ................................................................................... 331
Table 390: UART_CTR_HIGH_REG (0x500010FE) ........................................................................ 331
Table 391: UART2_RBR_THR_DLL_REG (0x50001100) ................................................................ 331
Table 392: UART2_IER_DLH_REG (0x50001104) .......................................................................... 332
Table 393: UART2_IIR_FCR_REG (0x50001108) ........................................................................... 334
Table 394: UART2_LCR_REG (0x5000110C) .................................................................................. 336
Table 395: UART2_MCR_REG (0x50001110) ................................................................................. 337
Table 396: UART2_LSR_REG (0x50001114)................................................................................... 338
Table 397: UART2_SCR_REG (0x5000111C) ................................................................................. 340
Table 398: UART2_SRBR_STHR0_REG (0x50001130) .................................................................. 341
Table 401: UART2_SRBR_STHR3_REG (0x5000113C) ................................................................. 343
Table 405: UART2_SRBR_STHR7_REG (0x5000114C) ................................................................. 347
Table 408: UART2_SRBR_STHR10_REG (0x50001158) ................................................................ 350
Table 409: UART2_SRBR_STHR11_REG (0x5000115C) ............................................................... 351
Table 413: UART2_SRBR_STHR15_REG (0x5000116C) ............................................................... 355
Table 414: UART2_FAR_REG (0x50001170) .................................................................................. 356
Table 415: UART2_USR_REG (0x5000117C) ................................................................................. 357
Table 416: UART2_TFL_REG (0x50001180) ................................................................................... 358
Table 417: UART2_RFL_REG (0x50001184) ................................................................................... 358
Table 418: UART2_SRR_REG (0x50001188) .................................................................................. 358
Table 419: UART2_SBCR_REG (0x50001190)................................................................................ 358
Table 420: UART2_SDMAM_REG (0x50001194) ............................................................................ 359
Table 421: UART2_SFE_REG (0x50001198)................................................................................... 359
Table 422: UART2_SRT_REG (0x5000119C) .................................................................................. 360
Table 423: UART2_STET_REG (0x500011A0) ................................................................................ 360
Table 424: UART2_HTX_REG (0x500011A4) .................................................................................. 360
Table 425: UART2_DMASA_REG (0x500011A8) ............................................................................ 361

DA14531
Table 426: UART2_DLF_REG (0x500011C0) .................................................................................. 361

Table 427: UART2_UCV_REG (0x500011F8) .................................................................................. 361
Table 428: UART2_UCV_HIGH_REG (0x500011FA) ...................................................................... 361
Table 429: UART2_CTR_REG (0x500011FC) ................................................................................. 361
Table 430: UART2_CTR_HIGH_REG (0x500011FE) ...................................................................... 362
Table 431: Register map Version ...................................................................................................... 363
Table 432: CHIP_ID1_REG (0x50003200) ....................................................................................... 363
Table 435: CHIP_ID4_REG (0x5000320C) ....................................................................................... 363
Table 436: Register map WKUP ....................................................................................................... 364
Table 437: WKUP_CTRL_REG (0x50000100) ................................................................................. 364
Table 438: WKUP_COMPARE_REG (0x50000102) ........................................................................ 365
Table 439: WKUP_IRQ_STATUS_REG (0x50000104) .................................................................... 365
Table 440: WKUP_COUNTER_REG (0x50000106) ......................................................................... 365
Table 441: WKUP_SELECT_GPIO_REG (0x50000108) ................................................................. 365
Table 442: WKUP2_SELECT_GPIO_REG (0x5000010A) ............................................................... 365
Table 443: WKUP_POL_GPIO_REG (0x5000010C) ........................................................................ 366
Table 444: WKUP2_POL_GPIO_REG (0x5000010E) ...................................................................... 366
Table 445: Register map WDOG ...................................................................................................... 367
Table 446: WATCHDOG_REG (0x50003100) .................................................................................. 367
Table 447: WATCHDOG_CTRL_REG (0x50003102) ...................................................................... 367
Table 448: Ordering Information (Samples) ...................................................................................... 369
Table 449: Ordering Information (Production) ................................................................................... 369
Table 450: MSL Classification ........................................................................................................... 370

DA14531
1 Block Diagram
24 April 2012
Arm Cortex-M0+ DCDC RC

RC RCX
Temperature
XTAL XTAL (BUCK/BOOST) 32/512
32 MHz
Sensor
32.768 kHz 32 MHz kHz
CORE LDO LDO LDO
LDO
CLAMP LDO
RET SYS SYS
SYS POR HIGH
RF
POR LOW
SWD (JTAG) Bluetooth 5.1 Core
Radio
4-CH DMA LINK LAYER
AES-128 Transceiver
HARDWARE
SysRAM1
16 KB
Memory Controller
APB bridge
SysRAM2
12 KB
SysRAM3
KEYBOARD CTRL
QUAD DECODER
20 KB TIMERS
WAKEUP CTRL
WAKEUP CTRL
Management (PMU)
CLOCK-LESS
CLOCKED
GP ADC
POWER/CLOCK
UART2
Timer 0
UART
Real Time Clock
SPI
I2C
1xPWM
OTP DMA
Timer 1
FIFO
FIFO
FIFO
FIFO
32 KB OTPC Capture
Timer 2
ROM 6xPWM GPIO MULTIPLEXING
144 KB
Figure 2: DA14531 Block Diagram


DA14531
2 Packages and Pinout

The DA14531 comes in two packages:
● A Wafer Level Chip Scale Package (WLCSP) with 17 balls
● A Quad Flat Package No Leads (FCGQFN) with 24 pins
The actual pin/ball assignment is depicted in the following sections.
2.1 WLCSP17 DA14531

1 2 3 4 5
P0_4
A RFIOP RFIOM
XTAL32km
P0_3
B XTAL32kp
C GNDRF2 GNDRF1 P0_2
D XTAL32Mp P0_5
E XTAL32Mm VSS P0_1
RST
F GND_DCDC
P0_0
G VBAT_LOW LX BAT_HIGH
(Top view)
Switching signal, Static signal, Analog signal Quiet ground

high current high current,
No connection Static signal, Digital signal Noisy ground
low current,
Figure 3: WLCSP17 Ball Assignment (Top View)

DA14531
Table 1: DA14531 WLCSP17 Ball Description

Ball Pin Name Type Reset Description
no. State
General Purpose I/Os (Note 3)
F4 P0_0 DIO (Type B) I-PD INPUT/OUTPUT with selectable pull up/down resistors.
Pull-down enabled during and after reset. General
purpose I/O port bit or alternate function nodes.
Contains state retention mechanism during power-
down.
RST DIO (Type B) RST active high hardware reset (default).
E5 P0_1 DIO (Type B) I-PD INPUT/OUTPUT with selectable pull up/down resistors.
Contains state retention mechanism during power
down.
ADC0 AI INPUT. Analog to Digital Converter input 0.
SWDIO DIO INPUT/OUTPUT. JTAG Data input/output. Bidirectional

data and control communication.
C5 P0_2 DIO (Type B) I-PD INPUT/OUTPUT with selectable pull up/down resistors.
down.
SWCLK DIO INPUT JTAG clock signal (by default).
B4 P0_3 DIO (Type B) I-PD INPUT/OUTPUT with selectable pull up/down resistors.
down. Check GP_DATA_REG[P03_P04_FILT_DIS] for
correct pad filter settings.
XTAL32kp AI INPUT. Analog input of the XTAL32K crystal oscillator.
DI INPUT. Digital input for an external clock (square

wave).
A5 P0_4 DIO (Type B) I-PD INPUT/OUTPUT with selectable pull up/down resistors.
XTAL32km AO OUTPUT. Analog output of the XTAL32K crystal

oscillator.
D4 P0_5 DIO (Type B) I-PD INPUT/OUTPUT with selectable pull up/down resistors.
down.

DA14531

no. State

data and control communication (by default).
Debug Interface
E5 SWDIO DIO I-PD INPUT/OUTPUT. JTAG Data input/output. Bidirectional

D4 data and control communication. Mapped on P0_1 or
P0_5 (P0_5 by default).
C5 SWCLK DIO I-PD INPUT JTAG clock signal. Mapped on P0_2 (by
default).
Clocks
D2 XTAL32Mp AI INPUT. Crystal input for the 32 MHz XTAL.
E1 XTAL32Mm AO OUTPUT. Crystal output for the 32 MHz XTAL.
B4 XTAL32kp AI INPUT. Crystal input for the 32.768 kHz XTAL. Mapped
on P0_3.
A5 XTAL32km AO OUTPUT. Crystal output for the 32.768 kHz XTAL.

Mapped on P0_4.
Quadrature Decoder
QD_CHA_X DI INPUT. Channel A for the X axis. Mapped on Px ports.
QD_CHB_X DI INPUT. Channel B for the X axis. Mapped on Px ports.
QD_CHA_Y DI INPUT. Channel A for the Y axis. Mapped on Px ports.
QD_CHB_Y DI INPUT. Channel B for the Y axis. Mapped on Px ports.
QD_CHA_Z DI INPUT. Channel A for the Z axis. Mapped on Px ports.
QD_CHB_Z DI INPUT. Channel B for the Z axis. Mapped on Px ports.
SPI Bus Interface
SPI_CLK DO INPUT/OUTPUT. SPI Clock. Mapped on Px ports.
SPI_DI DI INPUT. SPI Data input. Mapped on Px ports (Note 1).
SPI_DO DO OUTPUT. SPI Data output. Mapped on Px ports (Note

2).
SPI_EN DI/DO INPUT/OUTPUT. SPI Clock enable. Mapped on Px

ports.
I2C Bus Interface
SDA DIO/DIOD INPUT/OUTPUT. I2C bus data with open drain port.
Mapped on Px ports. The mapped Px pin is
automatically configured with a pull-up resistor
(25KOhm) when pin x is mapped to the I2C_SDA PID
function.
SCL DIO/DIOD INPUT/OUTPUT. I2C bus Clock with open drain port.
In open drain mode, SCL is monitored to support bit
stretching by a slave. Mapped on Px ports. The
mapped Px pin is automatically configured with a pull-
up resistor (25KOhm) when pin x is mapped to the
I2C_SCL PID function.

DA14531

no. State
UART interface
UTX DO OUTPUT. UART transmit data. Mapped on Px ports.
URX DI INPUT. UART receive data. Mapped on Px ports.
URTS DO OUTPUT. UART Request to Send. Mapped on Px

ports.
UCTS DI INPUT. UART Clear to Send. Mapped on Px ports.
UTX2 DO OUTPUT. UART2 transmit data. Mapped on Px ports.
URX2 DI INPUT. UART2 receive data. Mapped on Px ports.
ADC IO Channels
E5 ADC0 AI INPUT. Analog to Digital Converter input 0. Mapped on

P0_1.
C5 ADC1 AI INPUT. Analog to Digital Converter input 1. Mapped on

P0_2.
Radio Transceiver
A1 RFIOp AIO RF input/output. Impedance 50 Ω
A3 RFIOm AIO RF ground.
C3 GND_RF1 AIO RF ground.
C1 GND_RF2 AIO RF ground.
Miscellaneous
F4 RST DIO INPUT. Reset signal (active high). Mapped on P0_0

(by default).
G3 LX AIO INPUT/OUTPUT. Connection for the external DC-DC

converter inductor.
Power and Ground
E3 VSS AIO Digital ground.
G5 VBAT_HIGH AIO INPUT/OUTPUT. Battery connection or DCDC output

in BUCK/BOOST mode, respectively.IO-supply.
G1 VBAT_LOW AIO INPUT/OUTPUT. Battery connection or DCDC output

in BOOST/BUCK mode, respectively. System supply.
F2 GND_DCDC AIO DCDC ground
Note 1 Data input only. MOSI in SPI slave mode and MISO in SPI master mode.
Note 2 Data output only. MISO in SPI slave mode and MOSI in SPI master mode.
Note 3 The differences between Type A and Type B GPIO pads are presented in Types of GPIO Pads.

DA14531
2.2 FCGQFN24
Figure 4: FCGQFN24 Pin Assignment (Top View)
Table 2: DA14531 FCGQFN24 Pin Description

Pin Pin Name Type Reset Description
no. State
General Purpose I/Os (Note 3)
10 P0_0 DIO (Type B) I-PD INPUT/OUTPUT with selectable pull up/down resistors.
down.
RST DIO (Type B) RST active high hardware reset (default).
down.

DA14531

no. State
down.
SWCLK DIO INPUT JTAG clock signal (by default).
XTAL32kp AI INPUT. Analog input of the XTAL32K crystal oscillator.
DI INPUT. Digital input for an external clock (square

wave).
XTAL32km AO OUTPUT. Analog output of the XTAL32K crystal

oscillator.
down.
22 P0_6 DIO (Type A) I-PD INPUT/OUTPUT with selectable pull up/down resistors.
down.
down.
down.

DA14531

no. State
down.
down.

data and control communication (by default).
down.
Debug Interface
9 SWDIO DIO I-PD INPUT/OUTPUT. JTAG Data input/output. Bidirectional

data and control communication. Mapped on P0_10 (by
default).
12 SWCLK DIO I-PD INPUT JTAG clock signal. Mapped on P0_2 (by
default).
Clocks
3 XTAL32Mp AI INPUT. Crystal input for the 32 MHz XTAL.
4 XTAL32Mm AO OUTPUT. Crystal output for the 32 MHz XTAL.
13 XTAL32kp AI INPUT. Crystal input for the 32.768 kHz XTAL. Mapped
on P0_3.
14 XTAL32km AO OUTPUT. Crystal output for the 32.768 kHz XTAL.

Mapped on P0_4.
Quadrature Decoder
QD_CHA_X DI INPUT. Channel A for the X axis. Mapped on Px ports.
QD_CHB_X DI INPUT. Channel B for the X axis. Mapped on Px ports.
QD_CHA_Y DI INPUT. Channel A for the Y axis. Mapped on Px ports.
QD_CHB_Y DI INPUT. Channel B for the Y axis. Mapped on Px ports.
QD_CHA_Z DI INPUT. Channel A for the Z axis. Mapped on Px ports.
QD_CHB_Z DI INPUT. Channel B for the Z axis. Mapped on Px ports.
SPI Bus Interface
SPI_CLK DO INPUT/OUTPUT. SPI Clock. Mapped on Px ports.
SPI_DI DI INPUT. SPI Data input. Mapped on Px ports (Note 1).
SPI_DO DO OUTPUT. SPI Data output. Mapped on Px ports (Note

2).

DA14531

no. State
SPI_EN DI/DO INPUT/OUTPUT. SPI Clock enable. Mapped on Px

ports.
I2C Bus Interface
SDA DIO/DIOD INPUT/OUTPUT. I2C bus Data with open drain port.
Mapped on Px ports. The mapped Px pin is
automatically configured with a pull-up resistor
(25KOhm) when pin x is mapped to the I2C_SDA PID
function.
SCL DIO/DIOD INPUT/OUTPUT. I2C bus Clock with open drain port.
In open drain mode, SCL is monitored to support bit
stretching by a slave. Mapped on Px ports. The
mapped Px pin is automatically configured with a pull-
up resistor (25KOhm) when pin x is mapped to the
I2C_SCL PID function.
UART Interface
UTX DO OUTPUT. UART transmit data. Mapped on Px ports.
URX DI INPUT. UART receive data. Mapped on Px ports.
URTS DO OUTPUT. UART Request to Send. Mapped on Px

ports.
UCTS DI INPUT. UART Clear to Send. Mapped on Px ports.
UTX2 DO OUTPUT. UART2 transmit data. Mapped on Px ports.
URX2 DI INPUT. UART2 receive data. Mapped on Px ports.
ADC IO Channels
11 ADC0 AI INPUT. Analog to Digital Converter input 0. Mapped on

P0_1.

P0_2.

P0_6.

P0_7.
Radio Transceiver
1 RFIOp AIO RF input/output. Impedance 50 Ω
18 RFIOm AIO RF ground.
19 GND_RF1 AIO RF ground.
2 GND_RF2 AIO RF ground.
Miscellaneous
10 RST DIO INPUT. Reset signal (active high). Mapped on P0_0

(by default).
6 LX AIO INPUT/OUTPUT. Connection for the external DC-DC

converter inductor.

DA14531

no. State
Power and Ground
23 VSS AIO Digital ground.
20 GND AIO Analog ground.
7 VBAT_HIGH AIO INPUT/OUTPUT. Battery connection or DCDC output

in BUCK/BOOST mode, respectively. IO supply.
5 VBAT_LOW AIO INPUT/OUTPUT. Battery connection or DCDC output

in BOOST/BUCK mode, respectively. System supply.
21 GND_DCDC AIO DCDC ground.
Note 1 Data input only. MOSI in SPI slave mode and MISO in SPI master mode.
Note 2 Data output only. MISO in SPI slave mode and MOSI in SPI master mode.
Note 3 The differences between Type A and Type B GPIO pads are presented in Types of GPIO Pads.
3 Specifications
All MIN/MAX specification limits are guaranteed by design, production testing and/or statistical
characterization. Typical values are based on characterization results at default measurement
conditions and are informative only.
Default measurement conditions (unless otherwise specified): VBAT_HIGH = 3.0 V (buck mode),
VBAT_LOW = 1.5 V (boost mode), TA = 25 oC. All radio measurements are performed with standard RF
measurement equipment providing a source/load impedance of 50 Ω. All listed currents involving any
radio operation have been conducted without the external CLC filter.
Due to the voltage dependent capacitance of MLCC capacitors the specified capacitor values at
VBAT_HIGH and VBAT_LOW are effective capacitances.

DA14531
L1
C1 2. 2u C2 BT1
1u 10u 1. 5V
G3
G5
G1
A T1
Lx
2
VBAT I G
3. 3n
VBAT L
A1
RI p
A3 1 3
0 0 4 RI m 1. 8p 1. 8p
0 1 E5 0 0 RST
0 2 C5 0 1
0 5 D4 0 2 S CL D2
0 5 S DI TAL32 p
U1
3
2 4
1
32. 0000
E1
TAL32 m
1
DA14531
1 ball LCS
A5 0 4
0 4 TAL32km
2
32. 68
B4 0 3
0 3 TAL32kp
G D DCDC
G DR1
G DR2
VSS
wlcsp1 1. x2. 0
E3
C3
C1
Figure 5: Boost configuration system diagram
L1
C1 2. 2u C2
BT1
10u 1u
3. 0V
6
A T1
Lx
2
VBAT I G
3. 3n
VBAT L
1
RI p
18 1 3
0 0 10 RI m 1. 8p 1. 8p
0 1 11 0 0 RST
0 2 12 0 1
0 2 S CL
U1
0 5 24 3
0 5 TAL32 p
3
2 4
1
32. 0000
0 6 22
0 6
DA14531 TAL32 m
4
1
0
0 8
15
1 0 24 pin CG
0 16 0 8
0 14 0 4
0 4 TAL32km
2
0 10 32. 68
0 11 8 0 10 S DI 13 0 3
0 11 0 3 TAL32kp
G D DCDC
G DR 1
G DR 2
G D
VSS
qf n24 2. 2x3. 0
2
20
21
23
Figure 6: Buck configuration system diagram

DA14531
3.1 Absolute Maximum Ratings

Table 3: Absolute Maximum Ratings
Parameter Description Conditions Min Max Unit
VBAT_LIM_LOW limiting supply voltage Battery voltage in boost -0.2 3.6 V

configuration, supply voltage in
buck configuration
VBAT_LIM_HIG limiting supply voltage Battery voltage in buck -0.2 3.6 V

H configuration, supply voltage in
boost configuration
VPIN_LIM_defau limiting voltage on a pin -0.2 3.6 V

lt
VESD_HBM_FC electrostatic discharge voltage 4 kV

GQFN24 (Human Body Model)
VESD_HBM_WL electrostatic discharge voltage 2 kV

CSP17 (Human Body Model)
VESD_CDM_FC electrostatic discharge voltage 500 V

GQFN24 (Charged Device Model)
VESD_CDM_WL electrostatic discharge voltage 500 V

CSP17 (Charged Device Model)
TSTG storage temperature -50 150 °C
3.2 Recommended Operating Conditions

Table 4: Recommended Operating Conditions
Parameter Description Conditions Min Typ Max Unit
IL_VBAT_HIGH_ Maximum external DC load Boost mode booting 50 μA

BOOTING current on VBAT_HIGH rail sequence active
during booting in boost mode
VBAT_BYPASS Supply voltage.Battery For OTP functionality refer to 1.1 3.3 V

voltage. VBAT_HIGH_OTP_Program/Read.
Minimum boot voltage is
1.8V.
VBAT_HIGH_BO DCDC output. For OTP functionality refer to 1.8 3.3 V

OST VBAT_HIGH_OTP_Program/Read
VBAT_HIGH_BU Supply voltage.Battery For OTP functionality refer to 1.8 3.3 V

CK voltage. VBAT_HIGH_OTP_Program/Read
VBAT_LOW_BO Supply voltage.Battery 1.1 1.6 V

OST voltage.
VBAT_LOW_BU DCDC or LDO_LOW output 1.1 3.3 V

CK
VBAT_HIGH_OT Voltage range for OTP Required temperature for 2.25 3.3 V
P_Program programming. programming: -20oC to 85oC

DA14531
VBAT_HIGH_OT Voltage range for OTP 1.62 3.3 V

P_Read reading.
VPIN_default voltage on a pin -0.2 VBAT V

_HIGH
+0.2
TA ambient temperature -40 85 °C
3.3 DC Characteristics
Table 5: DC Characteristics
IBAT_HIGH_HIB battery supply current Hibernation mode, no RAM 270 nA

ERN_0kB retained, no oscillator
running
Note 1
IBAT_HIGH_HIB battery supply current Hibernation mode, 48kB 750 nA

ERN_48kB RAM retained, no oscillator
running
IBAT_LOW_HIB battery supply current Hibernation mode, no RAM 240 nA

ERN_0kB retained, no oscillator
running
Note 2
IBAT_LOW_HIB battery supply current Hibernation mode at 5 0C, 150 nA

ERN_0kB_5DEG 0kB RAM retained, no
oscillator running
IBAT_LOW_HIB battery supply current Hibernation mode, 48kB 700 nA

ERN_48kB RAM retained, no oscillator
running
IBAT_LOW_DP_ battery supply current Deep-sleep with 0 kB RAM 0.9 μA

SLP_0kB retained, running on RCX
IBAT_LOW_EX_ battery supply current Extended-sleep with 20 kB 1.2 μA

SLP_20kB RAM retained, running on
RCX
IBAT_LOW_EX_ battery supply current Extended-sleep with 48 kB 1.6 μA

SLP_48kB RAM retained, running on
RCX
IBAT_HIGH_DP_ battery supply current Deep-sleep with no RAM 1 μA

SLP_0kB retained, running on RCX
IBAT_HIGH_EX_ battery supply current Extended-sleep mode with 1.2 μA

SLP_20kB 20 kB RAM retained, running
on RCX
IBAT_HIGH_EX_ battery supply current Extended-sleep mode with 1.6 μA

SLP_48kB 48 kB RAM retained, running
on RCX

DA14531
IBAT_LOW_ACT battery supply current Application with Receiver 5 mA

_RX Active, CPU idle at 16MHz,
DCDC off
IBAT_LOW_ACT battery supply current Application with Pout = 8 mA

_TX 0dBm, Power setting 9,
Transmit continuous
unmodulated output power,
CPU idle at 16MHz, DCDC
off
IBAT_HIGH_ACT battery supply current Application with Receiver 2.2 mA

_RX Active, CPU idle at 16MHz,
DCDC on
IBAT_HIGH_ACT battery supply current Application with Pout = 3.5 mA

_TX 0dBm,Power setting 9,
Transmit continuous
unmodulated output power,
CPU idle at 16MHz, DCDC
on
IBAT_LOW_RUN battery supply current CPU executing code from 830 μA

_16MHz RAM running on XTAL32M
oscillator at 16MHz, DCDC
off
IBAT_HIGH_RU battery supply current CPU executing code from 380 μA

N_16MHz RAM running on XTAL32M
oscillator at 16MHz
IBAT_HIGH_IDL battery supply current CPU in Wait-for-Interrupt 230 μA

E_16MHz (WFI) state running on
XTAL32M oscillator at
16MHz
IBAT_LOW_IDLE battery supply current CPU in Wait-for-Interrupt 460 μA

_16MHz (WFI) state running on
XTAL32M oscillator at
16MHz, DCDC off
IBAT_HIGH_RST battery supply current Reset pin asserted, buck 200 μA

configuration, VBAT_HIGH = 3.0
V, at 25°C
IBAT_LOW_RST battery supply current Reset pin asserted, boost 200 μA

configuration, VBAT_LOW = 1.5
V, at 25°C
Note 1 IBAT_HIGH is Buck configuration at VBAT = 3 V, at 25 °C

Note 2 IBAT_LOW is Boost configuration at VBAT = 1.5 V, at 25 °C

DA14531
3.4 Timing Characteristics

Table 6: Timing Characteristics
tSTA_HIBER startup time Time from hibernation to the 0.2 0.4 ms

first executed code
instruction. Applies to both
buck or boost modes,
excludes capacitors charging
time. Assumes
VBAT_LOW=VBAT_HIGH with use
of the resistive switch so no
charging of the respective
rail is needed.
tSTA_SLP_Buck startup time Time from GPIO toggle to 0.86 1.2 ms

the first executed code
instruction. Applicable for
both deep and extended
sleep mode. Application in
buck configuration at 3V
battery voltage, excluding
capacitor charging.
tSTA_SLP_Boost startup time Time from GPIO toggle to 0.83 1.1 ms

the first executed code
instruction. Applicable for
both deep and extended
sleep mode. Application in
boost configuration at 1.5V
battery voltage, excluding
capacitor charging.
3.5 RCX Oscillator

Table 7: RCX Oscillator - Timing Characteristics
ΔfRC RCX oscillator frequency drift 100ms time slot 100 500 ppm
ΔfRC ΔV_VBA Supply voltage dependency -500 80 500 ppm/V

T_HIGH (VBAT_HIGH)
ΔfRC ΔV_VBA Supply voltage dependency -500 200 3000 ppm/V

T_LOW (VBAT_LOW)
fRCX RCX oscillator frequency at target fixed trim setting 13 15 17 kHz
ΔfRC ΔT_1 Temperature dependency temperature range -40°C to -125 125 ppm/d
85°C, RC BIAS at eg
preferred value
ΔfRC ΔT_2 Temperature dependency temperature range -40°C to -200 200 ppm/d
105°C, RC BIAS at eg
preferred value

DA14531
3.6 XTAL32MHz Oscillator

Table 8: XTAL32MHz Oscillator - Recommended Operating Conditions
PDRV_MAX maximum drive power Note 1 100 μ
VCLK_EXT external clock voltage In case of external clock 0.9 V

source on XTAL32Mp
(XTAL32Mm floating or
connected to mid-level 0.6 V)
φN_EXT_32M phase noise fC = 50 kHz; in case of -130 dBc/H

external clock source z
ΔfXTAL_TRIM crystal frequency trim 2 ppm
fXTAL_32M crystal oscillator frequency 32 MHz
ΔfXTAL crystal frequency tolerance After optional trimming; -20 20 ppm

including aging and
temperature drift
Note 2
ΔfXTAL_UNT crystal frequency tolerance Untrimmed; including aging -40 40 ppm

and temperature drift
Note 3
ESR_1pF equivalent series resistance C0<1pF 200 Ω
CL load capacitance No external capacitors are 4 6 8 pF

required
Note 1 Select a crystal which can handle a drive level of at least this specification.
Note 2 Using the internal varicaps a wide range of crystals can be trimmed to the required tolerance.
Note 3 Maximum allowed frequency tolerance for compensation by the internal varicap trimming mechanism.
3.7 XTAL32kHz Oscillator

Table 9: XTAL oscillator 32kHz - Recommended Operating Conditions
fCLK_EXT external clock frequency at pin 32KXTAL1/P0_3 in 10 100 kHz

GPIO mode
fXTAL crystal oscillator frequency 30 32.768 35 kHz
ESR equivalent series resistance 100 kΩ
CL load capacitance No external capacitors are 6 7 9 pF

required for a 6 pF or 7 pF
crystal.

DA14531
C0 shunt capacitance 1 2 pF
ΔfXTAL crystal frequency tolerance Timing accuracy is -250 250 ppm

(including aging) dominated by crystal
accuracy. A much smaller
value is preferred.
PDRV_MAX maximum drive power Note 1 0.1 μ
Note 1 Select a crystal that can handle a drive level of at least this specification.
Table 10: XTAL oscillator 32kHz - Timing Characteristics
tSTA_XTAL crystal oscillator startup time Typical application, time until 100 300 ms
1000 clocks are detected.
3.8 RC32MHz Oscillator

Table 11: RC32MHz Oscillaor - Timing Characteristics
fRC32M_TRIMM RC oscillator frequency at target trimming 29 30.5 31.5 MHz

ED
3.9 DC-DC Converter

Table 12: DCDC Converter - Recommended Operating Conditions
COUT External capacitor Effective value at DC output 1 μ

voltage
LEXT External inductor 2 2.2 2.4 μ
VBAT_HIGH Operational supply voltage, POWER_LEVEL_REG[DCD 1.8 3.3 V

applied to VBAT_HIGH C_LEVEL] = 0x0
VBAT_LOW Operational supply voltage, POWER_LEVEL_REG[DCD 1.1 1.65 V

applied to VBAT_LOW C_LEVEL] = 0x1
IL_VBAT_HIGH_ Load current on VBAT_HIGH in VOUT = 1.8 V 20 mA

1V8 BOOST mode Note 1



DA14531
Note 1 IL_VBAT_HIGH_BOOTING is applicable during booting
Table 13: DCDC Converter - DC Characteristics
VO_BUCK_1V1 DC output voltage DCDC_LEVEL = 0x0 1.075 1.1 1.125 V

DCDC_TRIM = 0x3
VO_BOOST_1V DC output voltage DCDC_LEVEL = 0x1 1.75 1.8 1.85 V

8 DCDC_TRIM = 0x3
VO_BOOST_2V DC output voltage DCDC_LEVEL = 0x2 2.425 2.5 2.575 V

5 DCDC_TRIM = 0x3
VO_BOOST_3V DC output voltage DCDC_LEVEL = 0x3 2.9 3 3.1 V

0 DCDC_TRIM = 0x3
ηCONV_BUCK Conversion efficiency VBAT = 3.0 V 80 85 90 %

VOUT = 1.1 V
ILOAD = 10 mA
ηCONV_BOOST Conversion efficiency VBAT = 1.5 V 85 90 95 %

VOUT = 1.8 V
ILOAD = 10 mA
VRPL_BUCK Ripple voltage VBAT = 3.0 V 5 15 25 mV

VOUT = 1.1 V
ILOAD = 1 - 20 mA
CEXT = 1 μ
VRPL_BOOST Ripple voltage VBAT = 1.5 V 5 20 35 mV

VOUT = 1.8 V
ILOAD = 1 - 20 mA
CEXT = 1 μ
IQ_VBAT_HIGH Quiescent current BUCK VBAT_HIGH = 3.0 V 40 μA

mode No load on VBAT_LOW
IQ_VBAT_LOW Quiescent current BOOST VBAT_LOW = 1.5 V 75 μA

mode No load on VBAT_HIGH
3.10 LDO_LOW Characteristics

Table 14: LDO_LOW - Recommended Operating Conditions
COUT output capacitance 1 10 μ

DA14531
Table 15: LDO_LOW - DC Characteristics
Active mode (high current)

POWER_LEVEL_REG[LDO
VO_ACTIVE output voltage 1.067 1.1 1.133 V
_LOW_TRIM] = 0x3 (default)
ILOAD = 1mA
Sleep mode (low current)

POWER_LEVEL_REG[LDO
VO_SLEEP output voltage 1.056 1.1 1.144 V
_LOW_TRIM] = 0x3 (default)
ILOAD = 100μA
Trim step, delta from 1.1 V POWER_LEVEL_REG[LDO

VO_TRIM_0 -75 mV
nominal value _LOW_TRIM] = 0x0

VO_TRIM_1 -50 mV

VO_TRIM_2 -25 mV

VO_TRIM_3 0 mV

VO_TRIM_4 25 mV

VO_TRIM_5 50 mV

VO_TRIM_6 75 mV

VO_TRIM_7 100 mV
IQ_ACTIVE quiescent current No load 12 μA
IQ_SLEEP quiescent current No load 40 nA
On resistance of the high

Buck mode, VBAT_HIGH = 1.62
RON_SW_HIGH Ohmic switch between 250 Ω
V, VBAT_LOW = 1.1 V
VBAT_HIGH and VBAT_LOW rail.
On resistance of the low

Buck mode, VBAT_HIGH = 1.62
RON_SW_LOW Ohmic switch between 10 Ω
V, VBAT_LOW = 1.1 V
On resistance of the low

RON_SW_LOW Boost mode, VBAT_LOW = 1.1
Ohmic switch between 10 Ω
_BOOST V
3.11 Digital I/O Characteristics

Table 16: Digital Pad - Recommended Operating Conditions
IL_HIDRV driving current - high mode 3.5 mA

DA14531
IL_LODRV driving current - low mode 0.35 mA
VIH HIGH level input voltage VDD=0.9V 0.7*V V

DD
VIL LOW level input voltage VDD=0.9V 0.3*V V

DD
Table 17: Digital Pad - DC Characteristics
IIH HIGH level input current VI=VBAT_HIGH=3.0V -10 10 μA
IIL LOW level input current VI=VSS=0V -10 10 μA
IIH_PD HIGH level input current VI=VBAT_HIGH=3.0V 60 180 μA
IIL_PU LOW level input current VI=VSS=0V, VBAT_HIGH=3.0V -180 -60 μA
VOH HIGH level output voltage IO=3.5mA, VBAT_HIGH=1.7V 0.8*VB V

AT_HI
GH
VOL LOW level output voltage IO=3.5mA, VBAT_HIGH=1.7V 0.2*VB V

AT_HI
GH
VOH_LOWDRV HIGH level output voltage IO=0.3mA, VBAT_HIGH=1.7V 0.8*VB V

AT_HI
GH
VOL_LOWDRV LOW level output voltage IO=0.3mA, VBAT_HIGH=1.7V 0.2*VB V

AT_HI
GH
CIN input capacitance 0.75 pF
Table 18: Digital Pad with LPF - DC Characteristics
CIN input capacitance Note 1 3.85 pF

Note 2
Note 1 Digital pad characteristics are equal to the standard GPIO pads unless overruled or added in this
table.
Note 2 P0_3 and P0_4 are type B pads with selectable filter via GP_DATA_REG[P03_P04_FILT_DIS], C IN is
equal to a Type A pad both with filter enabled or disabled.

DA14531
Table 19: Digital Pad with LPF - Recommended Operating Conditions
IL_HIDRV driving current - high mode 3.5 mA
IL_LODRV driving current - low mode 0.35 mA
3.12 Power On Reset

Table 20: POR VBAT_LOW - DC Characteristics
VTH_H POR VBAT_LOW reset 1.05 1.1 V

release voltage
VTH_L POR VBAT_LOW reset 0.95 1 V

activation voltage
Table 21: POR VBAT_HIGH - DC Characteristics
VTH_H POR VBAT_HIGH reset 1.75 1.8 V

release voltage
VTH_L POR VBAT_HIGH reset 1.62 1.66 V

activation voltage
3.13 GP ADC
Table 22: GP ADC - Recommended Operating Conditions
NBIT_ADC number of bits (resolution) 10 bit
Table 23: GP ADC - DC Characteristics
EG ADC gain error without Trimmed bandgap -3 3 %

software correction (single-
ended)
EG_COR ADC gain error after software Trimmed bandgap & Gain -1 1 %
correction (single-ended) Error + Offset correction
applied
EOFS ADC offset error without Trimmed bandgap, no -40 40 LSB

software correction (single- chopping
ended)

DA14531
EOFS_COR ADC offset error after Trimmed bandgap, chopping -4 4 LSB

software correction (single- enabled & Gain Error +
ended) Offset correction applied
EG_DIF ADC gain error without Trimmed bandgap -3 3 %

software correction
(differential)
EG_DIF_COR ADC gain error after software Trimmed bandgap & Gain -1 1 %
correction (differential) Error + Offset correction
applied
EOFS_DIF ADC offset error without Trimmed bandgap, no -20 20 LSB

software correction chopping
(differential)
EOFS_DIF_COR ADC offset error after Trimmed bandgap, chopping -4 4 LSB

software correction enabled & Gain Error +
(differential) Offset correction applied
EG_ATTNX ADC gain error after software Trimmed bandgap & GPADC -4 4 %
correction (including Gain Error + Offset
attenuator) correction applied
EOFS_ATTNX ADC offset error after Trimmed bandgap, chopping -16 16 LSB
software correction (including enabled & GPADC Gain
attenuator) Error + Offset correction
applied
EG_OFFSH ADC gain error after software Trimmed bandgap & Offset -1 1 %
correction (including offset Shifter Gain Error + Offset
shifter) correction applied
EOFS_OFFSH ADC offset error after Trimmed bandgap, chopping -4 4 LSB

software correction (including enabled & Offset Shifter Gain
offset shifter) Error + Offset correction
applied
INL integral non-linearity Note 1 -2 2 LSB
DNL differential non-linearity -2 2 LSB
ENOB Effective Number Of Bits no averaging, no chopping, 9 bit

Single-Ended: VIN,PP =
800mV
ENOBAVG128 Effective Number Of Bits 128x averaging, Single- 11 bit

Ended: VIN,PP = 800mV
Note 1 INL is the deviation of a code from a straight line passing through the actual endpoints of the transfer
curve.
Table 24: GP ADC - Electrical performance
tCONV_ADC Conversion time of the ADC 125 500 ns

DA14531
3.14 Temperature Sensor

Table 25: Temperature Sensor - DC Characteristics
TSENSE_RANG Temperature sensor range -40 105 °C

E
TSENSE_ACC_ Applies to the CSP package. TAMBIENT = 25°C, VBAT_LOW = TBD TBD °C
OTP_CSP Absolute accuracy of 1.1 V
temperature sensor using
calibration value from OTP
(single point calibration at
25°C) .
Formula: TX = 25°C + (ADCX
- ADCOTP_CAL_25C) / (TCSENSE
* 64) (64 is used to correct
16b to 10b ADC values)
TSENSE_ACC_ Applies to the QFN package. TAMBIENT = 25°C, VBAT_LOW = ±4 °C

OTP_QFN Absolute accuracy of 1.1 V
temperature sensor using
calibration value from OTP
(single point calibration at
25°C) .
Formula: TX = 25°C + (ADCX
- ADCOTP_CAL_25C) / (TCSENSE
* 64) (64 is used to correct
16b to 10b ADC values)
TCSENSE Temperature coefficient of reading via GP_ADC (10bit 1.15 1.45 1.75 LSB °
the internal temperature result) C
sensor
3.15 Radio
Table 26: BLE 1Mb/s specifications - Recommended Operating Conditions
fOPER operating frequency 2400 2483.5 MHz
NCH number of channels 40 1
fCH channel frequency K = 0 to 39 2402+ MHz

K*2
Table 27: BLE 1Mb/s specifications - AC Characteristics
PSENS_CLEAN sensitivity level Dirty Transmitter disabled; -94 dBm

DC-DC converter disabled;
PER = 30.8 %;
Note 1

DA14531
PSENS_EPKT sensitivity level Extended packet size (255 -90.5 dBm

octets)
Note 1
PSENS sensitivity level Normal Operating -93 dBm

Conditions; DC-DC converter
disabled; PER = 30.8 %;
Note 1
PSENS_EOC sensitivity level Extreme Operating -90 dBm

Conditions; DC-DC converter
enabled; PER = 30.8 %; -40
°C ≤ TA ≤ +85 °C
Note 1
PSENS_EPKT_ sensitivity level Dirty Transmitter disabled; -91.5 dBm

CLEAN DC-DC converter disabled;
Extended packet size (255
octets)
Note 1
PI_MAX maximum input power level DC-DC converter disabled; 0 dBm

PER = 30.8 %;
Note 1
PINT_IMD intermodulation distortion worst-case interferer level @ -35 -20.5 dBm

interferer power level f1, f2 with 2*f1 - f2 = f0, |f1 - f2|
= n MHz and n = 3, 4, 5;
PWANTED = -64 dBm @ f0;
PER = 30.8 %;
Note 1
CIR0 carrier to interferer ratio n = 0; interferer @ f1 = f0 + 7.5 21 dB

n*1 MHz;
Note 1
CIR1 carrier to interferer ratio n = ±1; interferer @ f1 = f0 + -1.5 15 dB

n*1 MHz;
Note 1
CIRP2 carrier to interferer ratio n = +2 (image frequency); -27 -9 dB

interferer @ f1 = f0 + n*1
MHz;
Note 1
CIRM2 carrier to interferer ratio n = -2; interferer @ f1 = f0 + -31 -17 dB

n*1 MHz;
Note 1
CIRP3 carrier to interferer ratio n = +3 (image frequency + 1 -37.5 -15 dB

MHz); interferer @ f1 = f0 +
n*1 MHz;
Note 1
CIRM3 carrier to interferer ratio n = -3; interferer @ f1 = f0 + -43 -27 dB

n*1 MHz;
Note 1

DA14531
CIR4 carrier to interferer ratio |n| ≥ 4 (any other BLE -41.5 -27 dB
channel); interferer @ f1 = f0
+ n*1 MHz;
Note 1
PBL_I blocker power level 30 ≤ fBL ≤ 2000 ; -17 5 dBm

PWANTED = -67 dBm;
Note 1
PBL_II blocker power level 2003 ≤ fBL ≤ 23 ; -17 0 dBm

Note 2 PWANTED = -67 dBm;
Note 1
PBL_III blocker power level 2484 ≤ fBL ≤ 2 ; -17 0 dBm

PWANTED = -67 dBm;
Note 1
PBL_IV blocker power level 3000 ≤ fBL ≤ 12. 5 G ; -17 5 dBm

PWANTED = -67 dBm;
Note 1
LACC_RSSI level accuracy tolerance at 5 % to 95 % 0 3 dB

confidence interval of PRF:
when RXRSSI[7:0] = X, 50 <
X < 175; burst mode, 1500
packets;
LRES_RSSI level resolution gradient of monotonous 0.5 dB/LS

range for RXRSSI[7:0] = X, B
50 < X < 175; burst mode,
1500 packets;
ACP2M adjacent channel power level fOFS = 2 MHz; -53 dBm

Note 1
ACP2M_EOC adjacent channel power level Extreme Operating -53 -47 dBm
Conditions; fOFS = 2 MHz; -40
°C ≤ TA ≤ +85 °C
Note 1
ACP3M adjacent channel power level fOFS ≥ 3 ; -57 dBm

Note 1
ACP3M_EOC adjacent channel power level Extreme Operating -57 -47 dBm
Conditions; fOFS ≥ 3 ; -40
°C ≤ TA ≤ +85 °C
Note 1
PO_12 output power level RF_ATTR_REG[PA_POWE 2.5 dBm

R_SETTING]= 12
PO_11 output power level RF_ATTR_REG[PA_POWE 1.5 dBm

R_SETTING]= 11
PO_10 output power level RF_ATTR_REG[PA_POWE 1 dBm

R_SETTING]= 10
PO_09 output power level RF_ATTR_REG[PA_POWE 0 dBm

R_SETTING]= 9

DA14531
PO_08 output power level RF_ATTR_REG[PA_POWE -1 dBm

R_SETTING]= 8

R_SETTING]= 7
PO_06 output power level RF_ATTR_REG[PA_POWE -3.5 dBm

R_SETTING]= 6

R_SETTING]= 5

R_SETTING]= 4

R_SETTING]= 3

R_SETTING]= 2

R_SETTING]= 1
Note 1 easured according to Bluetooth® Low Energy Test Specification R -PHY.TS/5.1.0

Note 2 Frequencies close to the ISM band can show slightly worse performance
Table 28: BLE 1Mb/s specifications - Timing Characteristics
tHOLD hold time of radio ldo's temperature from -40C to 500 ms

55C
tHOLD_EOC hold time of the radio ldo's temperature from -40C to 10 ms

85C
Table 29: BLE 1Mb/s specifications - DC Characteristics
IBAT_RF_RX Current at VBAT_LOW = 1.1V radio receiver and 4.3 mA

synthesizer active; TA = 25
°C
IBAT_RF_TX_12 Current at VBAT_LOW = 1.1V radio transmitter and 7.9 mA

synthesizer active; power
setting = 12; POUT= 2.5dBm;
TA = 25 °C

setting = 9; POUT = 0dBm; TA
= 25 °C

DA14531

setting = 6; POUT = -3.5dBm;
TA = 25 °C

DA14531
4 System Overview
4.1 Internal Blocks

The DA14531 contains the following blocks:
Arm Cortex-M0+ CPU with Wake-up Interrupt Controller (WIC). This processor provides 0.9
dMIPS/MHz and is used for assisting the BLE protocol implementation, for providing processing
power for calculations or data fetches required by applications, and for housekeeping, including
controlling the power scheme of the system.
BLE core. This is the baseband hardware accelerator for the BLE protocol.
ROM. This 144-kB ROM contains the BLE protocol stack and the boot code sequence.
OTP. This 32-kB OTP memory array is used to store application code and BLE profiles. It also
contains the system configuration and calibration data.
System SRAM (SysRAM). This 48-kB SysRAM is primarily used to mirror the program code from
the OTP when the system wakes/powers up. It also serves as a Data RAM for intermediate variables
and various data that the protocol requires. It can be used as an extra memory space for the BLE TX
and RX data structures (Exchange RAM). The SysRAM cells can not only be retained during sleep
modes but also be completely switched off during active mode if not needed.
UART and UART2. The serial interface of the UART implements hardware flow control while UART2
does not. Both UARTs feature FIFOs with depths of 16 bytes each.
SPI. This is the serial peripheral interface (SPI) with master/slave capability and it has a separate
FIFOs for RX and TX of two 16-bit words each.
I2C. This Master/Slave I2C interface is used for sensors and/or host Micro-Controllers Units (MCUs)
communication. It comprises a 32-place 9-bit deep FIFO.
General Purpose (GP) ADC. This 10-bit analog-to-digital converter (ADC) has four external input
channels (GPIOs) and internal channels for reading die temperature, the battery voltage, and other
internal analog nodes.
Radio Transceiver. This block implements the RF part of the BLE protocol.
Clock Generator. This block is responsible for clocking the system. It contains two XTAL oscillators,
one running at 32 MHz (XTAL32M) and used for the active mode of the system and the other running
at 32.768 kHz (XTAL32K) and used for the sleep modes of the system. There are also three RC
oscillators available: a 32 MHz oscillator (RC32M) with low precision (> 500 ppm), a 32 kHz oscillator
(RC32K) with low precision (> 500 ppm), and a ~15 kHz oscillator (RCX) with high precision (< 500
ppm). The RCX oscillator can be used as a sleep clock to replace the XTAL32K oscillator to further
improve the power dissipation of the system while reducing the bill of materials. The RC32M
oscillator is used to provide a clock to mirror the OTP code into the SysRAM while the XTAL32M
oscillator is settling directly after power/wake up. This clock is also used to run the Booter at power-
up. An external digital clock can be used as a sleep clock to replace the XTAL32K or the RCX
oscillator.
Timers. This block contains three timers:
● A 16-bit general purpose timer (Timer0) with two pulse width modulation (PWM) signals (PWM1
is inverted to PWM0)
● A 11-bit timer (Timer1) with two capture channels
● A 14-bit timer (Timer2) which controls six PWM signals that all have the same frequency, but
each has a configurable duty cycle
Real Time Clock (RTC). This hardware controller supports the complete time of day clock: 12/24
hours, minutes, seconds, milliseconds, and hundredths of a millisecond. It includes a configurable
alarm function and can be programmed to generate an interrupt on any event, like a rollover of
month, day, hour, minute, second, or hundredths of a millisecond.

DA14531
Wake-Up Timer. This timer captures external events and it can be used on any of the GPIO ports as
a wake-up trigger based on a programmable number of external events.
Quadrature Decoder. This block decodes the pulse trains from a rotary encoder to provide the step
and the direction of a movement of an external device. Three axes (X, Y, and Z) are supported. The
block also supports an edge counting mode which enables counting positive or negative edges on
the selected GPIOs.
Keyboard Controller. This circuit enables the reading and debouncing of a programmable number
of GPIOs and generates an interrupt upon a configurable action.
AHB/APB Bus. This block implements the AMBA Lite version of the AHB and APB specifications.
Power Management. This sophisticated power management circuit is equipped with a Buck/Boost
DC-DC converter and several low-dropout regulators (LDOs) that can be turned on/off via software.
A more detailed description of each component of the DA14531 is presented in the following
sections.
4.2 Power Management Unit
4.2.1 Introduction
The DA14531 has an integrated power management unit (PMU) which comprises a VDD_Clamp, a
POR circuitry, a DCDC convertor, and various LDOs. The system diagram of the integrated PMU is
shown in Figure 7.
Features
● Boost, Buck, and DCDC bypass configurations
● Single inductance DCDC converter configured for Boost or Buck configuration
● Programmable DCDC converter outputs
● Active and sleep mode LDOs
● Low BOM and use of small external components
4.2.2 Architecture
The PMU integrates two externally decoupled power rails: VBAT_HIGH and VBAT_LOW , and one internal
VDD power rail. There are three main power configurations: Buck, Boost, and Bypass. The integrated
PMU configures itself automatically to the appropriate mode depending on how the battery is initially
connected in the application.
● VBAT_HIGH: voltage range of 1.8 V - 3.3 V. This power rail is used for the blocks which require a
higher supply voltage. The OTP and the GPIOs are connected to this power rail. VBAT_HIGH is
protected by the POR circuit POR_HIGH, which generates a POR when the voltage drops below
the threshold voltage.
● VBAT_LOW: the main system supply and most internal blocks are powered from this rail. Its
functional range is from 1.1 V to 3.3 V. When used in Boost configuration, its default voltage
range is from 1.1 V to 1.65 V, and within this range the DCDC converter can provide a supply at
VBAT_HIGH in the range of 1.8 V to 3.0 V (see section 4.2.3.2). VBAT_LOW is protected with the POR
circuit POR_LOW which generates a HW reset when the voltage drops below the threshold
voltage.
● The internal VDD power rail supplies the digital power domains (refer to section 4.2.2.1 for the
details)
The VDD_Clamp and RC32k blocks are supplied by the highest of VBAT_HIGH and VBAT_LOW .
In Buck configuration (Figure 7), the battery is connected to VBAT_HIGH. The voltage on VBAT_LOW is
generated from VBAT_HIGH. In Boost configuration (Figure 8), the battery is connected to VBAT_LOW . The
voltage on VBAT_HIGH is generated from VBAT_LOW . The different power modes of the system are
explained in section 4.2.2.2.

DA14531
VBAT_HIGH Typ 3.0V (1.8 ... 3.3V)
BATTERY
VBAT_HL_RES
VBAT_HL_SW
Coin Cell DCDC
3V CONVERTER POR
HIGH
ret mode <1.66V
Nx GPIO
LX DCDC PORTS
OTP VDD Clamp VDD
control LDO
Memory POR_VDD LOW
>1.8V RC32kHz
FB
POR
Initial VDD
250Ω
Temp
LOW RC 32M RCX
sensor
<1.00V
VBAT_LOW Typ 1.1V (1.1 ... 3.3V)
ret mode
Decap Bandgap LDO CORE
VDD 0.75V ... 0.9V

LDO RF LDO RF LDO RF LDO GPADC LDO XTAL
32k_n 0.9V 0.9V 0.9V 0.9V 0.9V

XTAL1
PD_RAD
PD_SYS
AON incl PMU
PD_SLEEP
PD_TIM
Radio
RAM1 12KB
RAM2 20KB
RAM3 16KB
DIG
32kHz XTAL 32k RF Blocks RF Blocks RF Blocks GP ADC XTAL 32M 32MHz
32k_p XTAL2
DCORE RADIO
Always enabled Enabled by HW FSM Enabled by Software
Figure 7: Power Management Unit: Buck Configuration
VBAT_HIGH Typ 3.0V (1.8 ... 3.3V)

VBAT_HL_RES
VBAT_HL_SW
Decap DCDC
CONVERTER POR
HIGH
FB ret mode <1.66V
Nx GPIO
LX DCDC PORTS
OTP VDD Clamp VDD
control LDO
Memory POR_VDD LOW
>1.8V RC32kHz
POR
Initial VDD
250Ω
Temp
LOW RC 32M RCX
sensor
<1.00V
VBAT_LOW Typ 1.1V (1.1 ... 1.6V)
BATTERY ret mode
Silver Oxide
Bandgap LDO CORE
1.55V
VDD 0.75V ... 0.9V
LDO RF LDO RF LDO RF LDO GPADC LDO XTAL
32k_n 0.9V 0.9V 0.9V 0.9V 0.9V

XTAL1
PD_RAD
PD_SYS
AON incl PMU
PD_SLEEP
PD_TIM
Radio
RAM1 12KB
RAM2 20KB
RAM3 16KB
DIG
XTAL 32k RF Blocks RF Blocks RF Blocks GP ADC XTAL 32M 32MHz

32k_p XTAL2
DCORE RADIO
Figure 8: Power Management Unit: Boost Configuration
In bypass configuration (Figure 9), the DCDC is bypassed and the battery is connected to both
VBAT_LOW and VBAT_HIGH. In this mode an external inductor is omitted resulting to lower BOM. GPIOs
supply follows the battery voltage in this configuration. The minimum cold boot voltage is 1.8V. After
cold boot and providing that no OTP or GPIO (at a specific voltage level) is needed, POR HIGH can
be disabled and then VBAT_BYPASS can go down to 1.1V.

DA14531
VBAT_HIGH Typ 3.0V (1.8 ... 3.3V)
VBAT_HL_RES
VBAT_HL_SW
DCDC
CONVERTER POR POR
Temp
HIGH HIGH
sensor
>1.62V <1.66V
ret mode Nx GPIO
LX DCDC PORTS
VBAT_BYPASS control
OTP VDD Clamp LDO
LDO VDD
Memory POR_VDD LOW
(1.1 ... 3.3V) >1.8V RC32kHz
LOW
RET
FB
POR POR
Initial VDD
250Ω
Temp VDD
LOW RC 32M LOW RCX RC 32M RCX
sensor
>0.95V <1.00V
VBAT_LOW Typ 1.1V (1.1 ... 3.3V)

ret mode
BATTERY
Bandgap LDO VDD
3V – 1.1V Bandgap
Isupply=50uA
LDO CORE
6mA
VDD 0.75V ... 0.9V

LDO RFRF
LDO IF LDO RF LO LDO GPADC LDO XTAL
LDO RF LDO RF LDO GPADC LDO XTAL
3...8mA 2mA 1mA 1mA
0.9V 0.9V
0.9V 0.9V
0.9V 0.9V
0.9V 0.9V
32k_n XTAL1
PD_RAD
AON incl PMU
PD_SYS
PD_SLEEP
PD_TIM
ADPLL
LNA/Mix/
Radio
RAM2 20KB
RAM1 12KB
RAM3 16KB DCO/LO/ GP ADC
DIG
XTAL 32k RF Blocks RF Blocks
TIA/IFF/ RF Blocks GP ADC XTAL 32M 32MHz
32k_p DIV Isup=50uA XTAL2
ADC/DACs
DCORE RADIO
Figure 9: Power Management Unit: Bypass Configuration
4.2.2.1 Digital Power Domains

The DA14531 supports a number of digital power domains that can be turned on and off by software
(Figure 10). Some of the blocks contain registers that can retain their values even if the digital power
domain where they reside is powered off. RAM cells can retain their contents independently from the
digital power domains state.
XTAL
32 MHz
32 KHz
POR HIGH XTAL BUCK/ LDO LDO
RC
32.768 RF RC
POR LOW 32 MHz BOOST SYS RET LDO
kHz
Radio
Arm Cortex M0+
BLE TIMER
Tranceiver
CLOCK Digital
GEN
BLE 5.1 MAC PHY
RFCU
RAM AMBA AHB AMBA APB

RAM Ctrl
48 kB
OTP Ctrl TIMER0/2 UART/UART2 4-ch 10-bit ADC Temperature

CLOCK LESS
OTP
CLOCKED
sensor
WAKEUP
WAKEUP
32 kB QuadRature
TIMER1 SPI
Decoder (x3)
ROM General Purpose
ROM Ctrl RTC I2C Keyboard Scanner
144 kB Registers
DMA Engine GPIO Multiplexing
Sleep Domain (PD_SLP) Radio Domain (PD_RAD) System Domain (PD_SYS)
Always On Domain (PD_AON) Timers Domain (PD_TIM) Analog/RF
Figure 10: Digital Power Domains
The list of blocks residing in each one of the digital power domains is presented in Table 30.

DA14531
Table 30: Power Domains Description

Domain Name Description
PD_AON Always powered domain. It contains a Clock-less Wake Up controller and the pad-ring.
PD_SLP Sleep power domain. It comprises the Arm/WIC, the BLE Timer, the PMU/Clock
Generation, the Clocked Wakeup Controller, the Quadrature Decoder, and various
registers required for the Wake-Up sequence.
PD_SYS System Power Domain. It comprises the AHB bus, the OTP cell and controllers, the ROM,
the System RAM, the Watchdog, the SW Timer, and the GPIO port multiplexing.
PD_TIM Timer Power Domain. It comprises the RTC and the Timer1. These two blocks can be
active during sleep modes.
PD_RAD Radio Power Domain. It comprises the BLE Core and the digital PHY of the Radio.
4.2.2.2 Power Modes

There are five different power modes in the DA14531:
● Active mode: System is active and operates at full speed
● Sleep mode: No power gating has been programmed. The Cortex CPU is idle, waiting for an
interrupt. PD_SYS is on. PD_TIM and PD_RAD depend on the programmed enabled value
● Extended Sleep mode: PD_AON, PD_SLP, and conditionally PD_TIM are active. RAM is
expected to be retained for
○ Keeping a BLE connection alive (stack variables or BLE data)
○ Potentially keep the application code and it can be omitted if the OTP is instructed to
automatically get mirrored into RAM upon every wake up
● Deep Sleep mode: Shipping clocked mode with all domains disabled. RAM may or may not be
retained. RTC operation is programmable
● Hibernation mode: Shipping clock-less mode with all domains disabled. RAM may or may not
be retained. No clock is running
A summary of the power modes, the digital power domains, as well as the clocks and wake-up
capabilities are explained in Table 31.

DA14531
Table 31: Power Modes, Digital Power Domains, Clocks, and Wake-up triggers
Power Mode Digital Power LDOs, DCDC Converter, and Clock RAM Wake Up from
Domains VDD Level Availability
Active or Sleep PD_AON = ON VDD = 0.9 V SysRAM1 = ON (Application)
(WFI) PD_SLP = ON DCDC = ON (Buck or Boost) SysRAM2 = optionally retained
PD_SYS = ON LDO_LOW = OFF SysRAM3 = ON (Stack Data)
PD_TIM = LDO_CORE = ON, Active (0.9 All
OPTIONAL V)
PD_RAD = OPT VDD_Clamp = OFF
LDO_RADIO = Programmable
Extended Sleep PD_AON = ON VDD = 0.75 V SysRAMx =optionally retained ● RTC alarm
(with or without PD_SLP = ON DCDC = OFF (typically only SysRAM1 is ● Timer1
OTP) retained)
PD_SYS = OFF LDO_LOW = ON, in Buck mode. ● BLE sleep timer
RCX or
PD_TIM = LDO_CORE = ON, in retain XTAL32K
OPTIONAL mode (0.75 V)
PD_RAD = OFF VDD_Clamp = OFF
LDO_RADIO = OFF
Deep Sleep PD_AON = ON VDD = 0.75 V SysRAMx = optionally retained ● from any GPIOs
PD_SLP = ON DCDC = OFF (Typically OFF) ● RTC alarm
PD_SYS = OFF LDO_LOW = ON, in Buck mode. ● Timer1
RCX or
PD_TIM = LDO_CORE = ON, in retain XTAL32K
OPTIONAL mode (0.75 V)
PD_RAD = OFF VDD_Clamp = OFF
LDO_RADIO = OFF
Hibernation PD_AON = ON VDD = ~0.75 V SysRAMx =optionally retained Wake up from P0_1, P0_2,
PD_SLP = OFF DCDC = OFF P0_3, P0_4, P0_5
PD_SYS = OFF LDO_LOW = OFF
No Clocks
PD_TIM = OFF LDO_CORE = OFF
PD_RAD = OFF VDD_Clamp = ~0.75 V
LDO_RADIO = OFF

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Table 32 shows the typical rail voltages and their drivers present during various PMU modes.
Table 32: Power Rails Drivers and Voltages

Configurations Mode VBAT_HIGH VBAT_LOW VDD
Active DCDC out (1.1V) LDO_CORE (0.9V)
Buck Deep or Extended Sleep Battery (3.3V – 1.8V) LDO_LOW (1.1V) LDO_CORE in retain mode (0.75V)
Hibernation 0 V (none) VDD_Clamp (~0.75V)
Active DCDC out (3V - 1.8V) LDO_CORE 0.9V
Parasitic diodes in DCDC or
Deep or Extended Sleep LDO_CORE in retain mode (0.75V)
Boost clamp (VBAT_LOW) (Note 3) Battery (1.5V – 1.1V)
Parasitic diodes in DCDC or
Hibernation VDD_Clamp (~0.75V)
clamp (VBAT_LOW) (Note 3)
Active LDO_CORE (0.9 V)
Bypass Deep or Extended Sleep Battery (3.3V – 1.1V) Battery (3.3V – 1.1V) LDO_CORE in retain mode (0.75V)
Hibernation VDD_Clamp (~0.75V)
Note 3 Parasitic diodes in DCDC and LDO_LOW circuits prevent VBAT_HIGH from dropping to 0V. VBAT_HIGH can also be programmed to be clamped to VBAT_LOW.

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4.2.2.3 VDD Level in Hibernation

While in Hibernation, the Always On domain (PD_AON) is supplied by a clamp. Since the reference
is not enabled, the actual voltage supplied by the clamp is depending on the load and temperature.
To ensure proper operation of the PD_AON across the application operating temperature range and
load, it is recommended to configure the voltage level of the VDD_Clamp using
POWER_AON_CTRL_REG[LDO_RET_TRIM] according to the following table:
Table 33: VDD_Clamp recommended settings over temperature and load

Temperature Range 0kB retained RAM 48kB retained RAM
-40oC to +40oC 0xE 0xD
-40oC to +60oC 0xD 0xC
-40oC to +85oC 0xB 0xA
4.2.2.4 Retainable Registers

When the system enters one of the sleep modes, some registers need to retain their values even
though their power domain might be shut down. These special retainable registers and their power
domains are described in Table 34.
Table 34: Retainable Registers

Power Domains Retainable Registers
OTPC_MODE_REG
OTPC_TIM1_REG
OTPC_TIM2_REG
PD_SYS OTPC_AHBADR_REG
OTPC_CELADR_REG
OTPC_NWORDS_REG
DEBUG_REG
BLE_CNTL2_REG
RF_ADCI_DC_OFFSET_REG
RF_ADCQ_DC_OFFSET_REG
PD_RAD
RF_DC_OFFSET_RESULT_REG
RF_DC_OFFSET_FULL_RES_REG
RF_DC_OFFSET_MPAR_RES0/1/2/3_REG
4.2.3 Programming
4.2.3.1 Buck Configuration

In Buck configuration (Figure 7), the voltage on VBAT_LOW and VDD are generated from VBAT_HIGH in the
following ways:
● Hibernation Mode
In hibernation mode the VBAT_LOW rail is not powered and the digital core VDD is supplied by the VDD
clamp.

DA14531
The VDD clamp is supplied automatically by selecting the highest of VBAT_HIGH and VBAT_LOW . Since in
Buck configuration the VBAT_HIGH rail is always the highest supply on the chip, it is safe to disable this
automatic supply selection. Setting POWER_AON_CTRL_REG[CMP_VCONT_SLP_DISABLE] =
0x1 forces the clamp to use VBAT_HIGH as supply and reduces the hibernation current by approximately
40 nA.
● Extended Sleep and Deep Sleep Modes
In the extended sleep mode or deep sleep mode, the VBAT_LOW rail is supplied from LDO_LOW which
is in a retention low power mode. The digital core VDD is powered from LDO_CORE, retention mode.
To configure this mode the following settings must be applied:
○ POWER_CTRL_REG[LDO_LOW_CTRL_REG] = 0x3
○ POWER_CTRL_REG[LDO_CORE_RET_ENABLE] = 0x1
● Active and Sleep Modes
The VBAT_LOW rail is powered by LDO_LOW or by the DCDC converter. To enable the DCDC
converter the following settings must be applied:
○ POWER_LEVEL_REG[DCDC_LEVEL] = 0x0
○ DCDC_CTRL_REG[DCDC_ENABLE] = 0x1
Note that, the DCDC converter is automatically disabled and re-enabled when PD_SYS is powered
down and powered up again. Therefore, to use the DCDC converter to power V BAT_LOW rail,
LDO_LOW has to be turned off again after the system wakes up by setting the register:
● Register settings when the VBAT_LOW rail is powered by LDO_LOW:
4.2.3.2 Boost Configuration
NOTE
In Boost configuration, several diodes between VBAT_HIGH and VBAT_LOW can prevent VBAT_HIGH from dropping
more than a few hundred millivolts below VBAT_LOW.
During boot, external circuits connected to the VBAT_HIGH rail must be disabled. To guarantee a smooth startup,
a load on of VBAT_HIGH less than 50 µA is required.
In Boost configuration (Figure 8), voltages on VBAT_HIGH and VDD are generated from VBAT_LOW as
explained below:
● Hibernation Mode
Hibernation mode is generally a state in which the device stays longer. It is recommended to force
the VBAT_HL_RES switch on to reduce the power consumption from the comparator. When the
VBAT_HL_RES switch is on, VBAT_HIGH is connected to VBAT_LOW . The register setting is:
○ POWER_AON_CTRL_REG[VBAT_HL_CONNECT_RES_CTRL] = 0x1
In the hibernation mode of the Boost configuration, the digital core VDD is powered from VDD Clamp.
● Extended Sleep and Deep Sleep Modes
The digital core VDD is supplied by LDO_CORE switched to retention mode. The reference voltage
for this LDO is generated by periodically enabling and sampling the bandgap (see section 4.3.3 for
details). VBAT_HIGH rail, can be supplied by the following options:
Diodes controlled: VBAT_HIGH is connected to VBAT_LOW via diodes. This option is useful for short sleep
durations, typically below a second. When no significant load is present on VBAT_HIGH, it will not drop
below VBAT_LOW during the sleep interval. This is the reset setting.

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Software controlled: VBAT_HIGH and VBAT_LOW are connected via VBAT_HL_RES. In typical use cases
this setting is energy efficient for sleep durations longer than one second. This mode requires the
following register settings:
– POWER_CTRL_REG[LDO_CORE_RET_ENABLE] = 0x1
– POWER_AON_CTRL_REG[VBAT_HL_CONNECT_RES_CTRL] = 0x2
– HW controlled: For short sleep durations, typically under one second, in combination with
increased load conditions that can discharge VBAT_HIGH to the level of VBAT_LOW during the
sleep interval, it is recommended to use the HW-controlled VBAT_HIGH connection, in which
the two rails are connected as soon as VBAT_HIGH drops to the same level of VBAT_LOW (+/- 50
mV). This mode requires the following register settings:
– POWER_AON_CTRL_REG[LDO_CORE_RET_ENABLE] = 0x1
– POWER_CTRL_REG[CMP_VBAT_HIGH_OK_ENABLE] = 0x1
– POWER_AON_CTRL_REG[VBAT_HL_CONNECT_RES_CTRL] = 0x3
● Active and Sleep Modes
In these modes the VBAT_HIGH rail is normally powered by the DCDC converter at 1.8 V. This level can
be changed to 2.5 V or 3.0 V by configuring POWER_LEVEL_REG[DCDC_LEVEL].
Since the Boost converter is only needed to generate 1.8V allowing for accessing to the OTP call and
supply the GPIOs, it is possible to disable it when access to the OTP is required and no GPIOs are
being driven. In this mode the VBAT_HL_SW should be activated to clamp VBAT_HIGH at VBAT_LOW , allowing
some load on VBAT_HIGH and GPIO operation at a reduced speed and voltage. Note that this mode
rapidly discharges VBAT_HIGH from the boosted voltage down to VBAT_LOW level. Also, the POR_HIGH
block has to be masked or disabled to avoid resets:
if it is masked, the POR_HIGH status remains available, but it will not generate a reset;
if it is disabled, the status becomes unavailable as well.
The following settings are required to enter this mode of operation:
– POWER_CTRL_REG[POR_VBAT_HIGH_DISABLE] = 0x1 (Disable) or
– POWER_AON_CTRL_REG[POR_VBAT_HIGH_RST_MASK] = 0x1 (Mask)
– DCDC_CTRL_REG[DCDC_ENABLE] = 0x0
– POWER_CTRL_REG[VBAT_HL_CONNECT] = 0x1
4.2.3.3 Bypass Configuration

In the bypass configuration, the VBAT_HIGH and VBAT_LOW rails are shorted on the PCB. This
configuration is detected by the chip as a boost configuration, but since the boost converter is
actually not able to generate a voltage on VBAT_HIGH, the initial voltage has to be above 1.75 V to allow
the OTP to be read and mirrored.
Software can disable the DCDC converter and LDO_LOW to reduce quiescent current and avoid
unnecessary switching of the DCDC converter. The following register settings are required to
accomplish this:
– DCDC_CTRL_REG[DCDC_ENABLE] = 0x0
– POWER_CTRL_REG[LDO_LOW_CTRL_REG] = 0x1
If voltage drops below 1.75 V, POR_HIGH must be masked in order to prevent unnecessary resets.
Note that OTP reads cannot be performed after this point. Masking POR_HIGH is done by the
following setting:
– POWER_AON_CTRL_REG[POR_VBAT_HIGH_RST_MASK] = 0x1
When POR_HIGH is masked, its status remains available, but it will not generate a reset.
POR_HIGH can be also disabled by the following setting:
– POWER_CTRL_REG[POR_VBAT_HIGH_DISABLE] = 0x1

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When POR_ HIGH is disabled, its status becomes unavailable.
4.3 HW FSM (Power-up, Wake-up, and Go-to-Sleep)

The HW Finite State Machine (FSM) responsible for the power-up, wake-up, and go-to-sleep
processes of the system is presented in Figure 11.
RESET_N=0
NO YES
Charge VBAT_LOW BOOST_MODE Bandgap Enable
VBAT_LOW = OK Bandgap = OK
Bandgap Enable
Bandgap = OK
LDO_LOW_RET Enable
LDO_LOW_RET = OK
LDO_CORE Enable
LDO_CORE = OK
YES
BOOST_MODE
YES
NO
NO VBAT_LOW
Charged BootROM (SW) starts Running Charge VBAT_HIGH
Go To Sleep
Wake up Buck mode Wake up Boost mode
Sleep
Bandgap Sleep Bandgap refresh
Referent Voltage
Tracking
Figure 11: Power-Up/Wake-Up/Sleep FSM Diagram
The details of the power-up, wake-up, and sleep sequences of the FSM for the different modes are
described in the following sections.
In Boost configuration the DCDC is enabled by the Booter during power up. After waking up, if the
DCDC was left enabled, it will be started by the HW FSM. In Buck configuration, upon a wake-up, the
DCDC is enabled by programming DCDC_CTRL_REG[DCDC_ENABLE]. If DCDC_ENABLE is kept
asserted before the system goes to sleep, the DCDC will be started by the HW FSM upon waking-up.
If DCDC_ENABLE is cleared before the system goes to sleep, the DCDC can only be started by SW
asserting this bit after a wake-up. When the system is allowed to go to sleep, the HW FSM is
activated and the DCDC controller is automatically turned off.
4.3.1 Power-up/Wake-up in Buck Configuration

At the beginning of a power-up (cold boot), the PMU detects whether the system is in a Buck or a
Boost configuration, and this decision is retained from that point on. The power-up (cold boot)

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sequence of the Buck configuration is shown in Figure 12. When the system is at the start of the
Buck configuration path, then VBAT_HIGH rail has a stable supply already and "boost_mode = 0" (which
means buck is identified) has been set.
To start the system, it is required that the VBAT_LOW rail is also brought up to an acceptable level,
which is done by HW, enabling the resistive switch VBAT_HL_RES and monitoring POR_LOW. The
rising voltage of the VBAT_LOW rail will eventually trigger POR_LOW to "ok" after that, the bandgap will
be enabled. The HW FSM runs at 32 kHz from the RC32K oscillator at this time, and it will
dynamically change to 512 kHz in one clock cycle after the switch is enabled. The HW FSM will
continue working at 512 kHz. When the reference voltage from the bandgap is stable, LDO_LOW is
enabled. After a stable 1.1 V is generated, LDO_CORE is enabled to generate a stable VDD of 0.9 V.
After this, the main system clock, RC32MHz, is enabled. All conditions are now in place to release
the system reset so that the Booter can start running. An indicative time needed to power up the
system in Buck configuration up until the application SW starts running, is around 2.5 ms. The time
required to charge VBAT_LOW and VBAT_HIGH depends on the external capacitor values on these rails.
Figure 12: Power-up (Buck)
In hibernation, the resistive switch VBAT_HL_RES can be closed to pre-charge VBAT_LOW to the level
of VBAT_HIGH by programming POWER_AON_CTRL_REG[VBAT_HL_CONNECT_RES_CTRL].
Therefore, during the wake-up sequence from the hibernation mode, step "Charge VBAT_LOW " can be
omitted (Figure 13) via POWER_AON_CTRL_REG[CHARGE_VBAT_DISABLE]. All other steps are
same as in the power-up cold-boot sequence. The total time needed to wake up the system from
hibernation up until booter software starts running is around 185 µs.
Figure 13: Wake-Up from hibernation (Buck)
The wake-up sequence from the clocked, extended sleep or deep sleep mode using an external
GPIO toggle is shown in Figure 14. The difference between the power-up and wake-up sequence in
Buck configuration is that the VBAT_LOW rail is already charged via the switch VBAT_HL_RES in the
wakeup sequence as shown in Figure 11. Therefore, when the system wakes up from a deep sleep
or an extended deep sleep, the bandgap will be enabled within one 32 kHz clock cycle after the
wake-up signal is triggered. After the bandgap is enabled, LDO_LOW and LDO_CORE will be
enabled one after the other. The total time which is needed to wake up the system up until software
starts running is around 800 µs. If RAM has been retained, running software means application; if not
then the Booter will be started.

DA14531
Figure 14: Wake-Up (Buck)
A GPIO trigger will have to go through the wake up controller first, which requires 7 RCX clock cycles
before it is allowed to trigger the PMU and have the state machine running. Even after all power rails
are done, switching the system clock from RCX into RC32M (so software stars running) takes 3.5
RCX clock cycles (indicated in state=RUNNING:SWITCH) in the figure above.
If the system wakes up from an internal timer running at the RCX clock, then the WokenUp signal will
be asserted 6 RCX clock cycles after the timer generates the interrupt (i.e ~400usec).
4.3.2 Power-up/Wake-up in Boost Configuration

At the beginning of a power-up (cold boot), the PMU detects whether the system is in a Buck or a
Boost configuration, and this decision is retained in the system. The power-up (cold boot) sequence
of the Boost configuration is shown in Figure 15. When the system is at the start of the Boost
configuration path, then VBAT_LOW has a stable supply already and "boost_mode = 1" (which means
boost is identified) has been set.
Because the supply on the VBAT_LOW rail is already on an acceptable level, the bandgap will be
enabled in the first step and LDO_CORE in the second step. After this the resistive switch
VBAT_HL_RES is closed to bring VBAT_HIGH up to the same level as VBAT_LOW . This is needed for the
DCDC converter to start, since its drivers run on the VBAT_HIGH rail. When the VBAT_HIGH rail is stable,
the system reset can be released for the Booter to start running. The DCDC will be enabled during
the first actions in the Booter (section 4.5). An indicative time which is needed to power up the
system in Boost configuration up until software starts running is around 1.2 ms. The time required to
charge VBAT_HIGH depends on the external capacitor values on this rail.
Figure 15: Power-Up (Boost)
In hibernation, the resistive switch VBAT_HL_RES can be closed to pre-charge VBAT_HIGH to the level
of VBAT_LOW by programming POWER_AON_CTRL_REG[VBAT_HL_CONNECT_RES_CTRL].
Therefore, during the wake-up sequence from the hibernation mode, step "Charge VBAT_HIGH" can be
omitted (Figure 16) via POWER_AON_CTRL_REG[CHARGE_VBAT_DISABLE]. All other steps are
same as in the power-up cold-boot sequence. The total time needed to wake up the system from
hibernation up until booter software starts running is around 180 µs.

DA14531
Figure 16: Wake-Up from hibernation (Boost)
In the wake-up sequence from deep or extended sleep using a GPIO toggle, the step Charge
VBAT_HIGH lasts minimum 4 clock cycles (Figure 17). This time is sufficient to quickly re-charge
VBAT_HIGH under the condition that the leakage current and the sleep interval are sufficiently low and
the VBAT_HIGH voltage does not drop below VBAT_LOW . The state Charge VBAT_HIGH can be omitted by
using the resistive paths. The total time which is needed to power up the system up until software
starts running is around 865 µs. If RAM has been retained, running software means application; if not
then the Booter will be started.
Figure 17: Wake-Up from extended/deep sleep (Boost)
A GPIO trigger will have to go through the wake up controller first, which requires 7 RCX clock cycles
before it is allowed to trigger the PMU and have the state machine running. Even after all power rails
are done, switching the system clock from RCX into RC32M (so software stars running) takes 3.5
RCX clock cycles (indicated in state=RUNNING:SWITCH) in the figure above.
If the system wakes up from an internal timer running at the RCX clock, then the WokenUp signal will
be asserted 6 RCX clock cycles after the timer generates the interrupt (i.e ~400usec).
4.3.3 Go-to-Sleep and Refresh Bandgap

System can enter a sleep state, either sleep Buck or sleep Boost, depending on the status of the
boost_mode bit. The sleep state disables the power-consuming blocks and triggers the "hold mode"
for the bandgap referenced voltages. After a certain amount of time (sleep refresh counter), these
"hold" voltages need to be refreshed. The lower loop of the FSM in Figure 11 enables the bandgap,
refreshes the voltages, checks for BOD events via the POR circuits and if ok, resets the refresh timer
and goes back to sleep. This is an autonomous cycle led by hardware until the system is woken up
by a wake-up event. The refresh timer can be configured by setting the PMU_SLEEP_REG
[BG_REFRESH_INTERVAL] bit field (1 LSB = 64 × 32 kHz clock cycles). The go-to-sleep and the
bandgap refresh sequence is shown in Figure 18.
Figure 18: Go-to-Sleep and Bandgap Refresh


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4.4 OTP Memory Layout

The OTP memory has to be programmed according to a specific layout, which structures information
to be easily accessible from the BootROM code as well as the actual application. An overview of the
layout scheme is presented in Figure 19.
0x7F80000
Interrupt Vectors
(32 words)
CUSTOMER
CODE
(variable but known size)
OTP
0x7F87ED0
Configuration Script
(60 words)
0x7F87FC0
OTP Header
(16 words)
0x7F88000
Figure 19: OTP Layout Scheme
The OTP memory is a matrix of 8Kx32-bit words. The contents are described below:
● Interrupt Vectors: they are the vectors of the interrupt service routines and always reside at the
address 0x0. This is part of the application (customer) code. The size of this vector list is 32
words
● Customer Code: it contains the applications and the profiles that a customer has developed.
The size is known and fixed before the mass production and the programming of the OTP
● Configuration Script (section 4.4.2): it is used to program registers with values that are defined
during production testing, to store a trim value for the application software, and to define the
UART time-out timer during booting. It is executed by the Booter to prepare and initialize the
system prior to that the CPU starts running the application code. Available size is 60 words
● OTP Header: it contains various information about the configuration of the system and the BLE-
specific data. Size of the header is 16 words.
4.4.1 OTP Header

The OTP header breakdown is presented in Table 35.
Table 35: OTP Header

Programmed during
Words
Address Description Product
(32-bit) Chip Test
Manufacturing
Application Programmed Flag #1
7F87FC0 1 Yes
0x1234A5A5 = Application is in OTP
Application Programmed Flag #2
7F87FC4 1 Yes
0xA5A51234 = Application is in OTP

DA14531
Programmed during
Words
(32-bit) Chip Test
Manufacturing
Boot specific configuration:
● Bits[7:0] :
○ 0xAA = Boot from SPI port at a specific
location
○ 0xFF = Normal sequence
● Bits[15:8] = Wake up Command opcode
7F87FC8 1 ● Bits[23:16] = SPI_DIV Yes
● Bits[31:24]:
○ 0x00 = Two-wire UART (P0_0/P0_1)
○ 0x01 = One-wire UART (P0_3)
○ 0x02 = One-wire UART (P0_5)
○ Default (all other values) = Two-wire UART
(P0_0/P0_1)
Boot specific port mapping:
Bits[7:4] = SPI_CLK, Port number
Bits[3:0] = SPI_CLK, Pin number
Bits[15:12] = SPI_EN, Port number
7F87FCC 1 Bits[11:8] = SPI_EN, Pin number Yes
Bits[23:20] = SPI_DO, Port number
Bits[19:16] = SPI_DO, Pin number
Bits[31:28] = SPI_DI, Port number
Bits[27:24] = SPI_DI, Pin number
Device and Package Flag:
● Bits[7:0]:
○ 0xFF = WLCSP with P0_5
○ 0x66 = WLCSP without P0_5
7F87FD0 1 ○ 0xAA = FCGQFN24 Yes
● Bits[15:8]:
○ 0xFF = 531
○ Others = Reserved
● Bits[31:16] = Reserved
Bluetooth Device Address (64-bit word).
7F87FD4 2 Yes
It is handled as a string of bytes.
7F87FDC 1 OTP DMA length (number of 32-bit words). Yes
Position:
Bits[7:0] = X coord
7F87FE0 1 Bits[15:8] = Y coord Yes
Bits[23:16 ]= Wafer #
Bits[31:24] = LOT #
Tester:
Bits[7:0] = Tester_Site
7F87FE4 1 Bits[15:8] = Tester_ID (LSB) Yes
Bits[23:16] = Tester_ID (MSB)
Bits[31:24] = Reserved

DA14531
Programmed during
Words
(32-bit) Chip Test
Manufacturing
TimeStamp:
Bits[7:0] = TS_Byte0
7F87FE8 1 Bits[15:8] = TS_Byte1 Yes
Bits[23:16] = TS_Byte2
Bits[31:24] =TS_Byte3
7F87FEC 5 Reserved for Future Needs
The Device and Package Flag reflects what the current device (DA14531) is and which package is
used. Default (unprogrammed) values are 0xFFFFFFFF.
Boot specific mapping value is used to define a specific configuration for the SPI interface when used
for booting from an external device (either an MCU or a FLASH). Byte0 is the flag to instruct the
BootROM to use the specific SPI pin mapping and skip the rest of the serial peripheral interfaces.
The BootROM takes care of waking up an external flash when the flash memory is in deep power-
down state.
Byte1 is used for the Wake-up Command opcode that the flash memory responds to. If Byte0 is left
unprogrammed, the BootROM will send the "0xAB" opcode by default. Furthermore, the BootROM is
able to wake up the external flash by toggling the CS pin.
Two more flags indicate whether the application code has indeed been programmed (burned) into
the OTP. Both flags are read by the BootROM software designating that the system is in the Normal
mode and not in the Development mode (section 4.5).
4.4.2 Configuration Script

The Configuration Script (CS) is a table of 32-bit entries and is 60 words deep, so in total the CS can
utilize 240 bytes of space.
The CS is used to program registers with values that are defined during production testing, to store a
trim value for the application software, and to define the UART time-out timer during booting. It is
executed by the Booter to prepare and initialize the system prior to that the CPU starts running the
application code.
The format of the commands in the CS is presented in Table 36.
Table 36: CS Commands and Description

# Command Type Description
1 Start Command One 32-bit word containing 0xA5A5A5A5 to signal a valid CS is in place.
● One 32-bit word containing an address of an existing register
Register
2 ● One 32-bit word containing the data value of the register
Configuration
These are always in pairs with the address sitting in even memory addresses.
One 32-bit word which is equal to 0x9000YYXX indicating that the next word is a
value stored during production testing. More specifically:
● 9: it indicates that the following word(s) are not to be stored to registers but will be
used by the SDK SW
3 SDK Value
● YY: it indicates that YY amount of words follow
● XX: it is an increasing value and can be used for indexing by the SW application.
If YY > 1, XX will not be increased for the words that belong to the same value
One or more 32-bit words can represent one value.

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# Command Type Description

One 32-bit word which is equal to 0x70000000. It prevents the JTAG from being
4 SWD mode enabled at the end of the Booter and the Booter will not enter the endless while (1)
loop. Instead it will continue to rescan all peripherals in the development mode path.
One 32-bit word which is equal to 0x8XXXXXXX. The XXXXXXX is used to program
UART STX
5 the selected ST timeout in multiples of 100 µs. So, for example, 0x80000028 is 40 ×
timeout value
100 µS = 4 ms.
0xA0000000
6 SPI Clock value This value overwrites the default 2-MHz clock speed of the SPI boot path and sets it
to 32 MHz.
The Booter stops processing the CS once it encounters an empty OTP value (0xFFFFFFFF). This
way, no more processing time is spent to check the rest and it is possible to add new entries later, for
example, to patch/update previous entries.
An example describing the format of the configuration script is presented in Table 37.
Table 37: CS Example

Words Even Words Odd Words Description
Start command of the CS Script, followed by STX timeout value of 4
0-1 0xA5A5A5A5 0x80000028
ms (40 × 100 µs)
2-3 <Address> <Value> Booter automatically writes the <Value> to the <Address>
Three calibration values stored during production testing. SDK
4-5 0x90000301 <Value>
should know what this is for.
6-7 <Value> <Value>
8-9 <Address> <Value> Booter automatically write the <Value> to the <Address>
10-11 <Address> <Value> Booter automatically write the <Value> to <Address>
Four calibration values stored during production testing. SDK should
12-13 0x90000402 <Value1>
know what this is for.
Calibration value stored during production testing. SDK should know
14-15 <Value2> <Value3>
what this is for.
16-17 <Value4> 0x70000000 Disable SWD
Booter stops running the CS after an empty entry, so anything after
18-19 0xFFFFFFFF (don’t care)
this is "don’t care".
4.5 BootROM Sequence

The booting process of the DA14531 is presented in Figure 20. The Booter is always executed when
a POR or a HW Reset occurs, or the RESET_ON_WAKEUP feature is configured.
The booter will start executing with the RC32M clock, to speed up its execution. Then the Booter
checks whether the system is in the Boost configuration or not. The configuration (Buck or Boost)
has been already decided by the HW and should be readable by SW at the
ANA_STATUS_REG[BOOST_SELECTED] bit field. To access the OTP, VBAT_HIGH needs to be set at
≥ 1.8 V. In the Boost configuration the DCDC is enabled to boost VBAT_HIGH at 1.8 V and
BOOST_VBAT_OK = 1 confirms that the voltage at the DCDC is stable. After the OTP is operational,
the Booter initializes the UART baud rate at 115.2 kHz, and the CS (section 4.4.2) is enabled to be
executed.
After the CS has been executed, the Booter has to decide whether the device is in Development or
Normal mode by reading the two words indicated as application flags in the OTP. The OTP image is
copied into RAM starting at address 0x0 by the Booter.

DA14531
In Development mode, the "Boot from Specific" flag will be evaluated. If the flag is programmed, new
pin locations for booting from an external SPI slave to make DA14531 an SPI Master will be set. The
"Boot from Specific" flag addresses mostly the QFN package allowing for booting from a different pin
configuration than the default one, so that the system can boot from an external FLASH using the
development mode. The details of the configuration are presented in section 4.4.1. If this path is
entered, the system will always try to boot from UART so that the SPI Flash can be updated if
needed. Any of the three UART configurations specified in Table 38 can be selected by writing bits
[31:24] at the "Boot specific config" field in the OTP header. If booting from SPI Flash fails, the Booter
will jump back to the normal scan sequence of the peripheral devices.
If the "Boot from Specific" flag is not programmed, the system should continue with scanning the
different serial interfaces to identify whether a device is connected to it. After OTP is disabled, six
steps as described in Table 38 are performed. Before using the UART, the XTAL32M clock needs to
be enabled. All the boot steps are protected by a timeout.

DA14531
Default clock is
Boot Start
RC32K
Enabled already Required to be

Switch to RC32MHz
by PWR FSM able to read from
OTP
Boost
Yes Enable DCDC
mode?
No
Enable OTP
Initialize UART baudrate @ 115200
DCDC in buck
Execute Configuration Script could be enabled
here
Read OTP Application Flags
Is App Switch to
Yes programmed No XTAL32M OK Yes
XTAL32M
?
Length Register
will be Magic Number
automatically identified
read by the OTP
controller after No
wake up Read and Prog. DMA
length
NORMAL MODE
Boot specific Initialize Peripheral

Yes Yes
Start copy of OTP to flag = 0xAA? Devices All Boot Steps
SRAM protected by a
Read serial Timeout
No configuration
No Disable OTP
Copy Disable OTP
done? Boot Step 1
(ext SPIM) Switch to
ARM is polling Fail XTAL32M before
Boot from
DEVELOPMENT MODE
OTPC_STAT_REG Yes using UART
UART Success Boot Step 2
( 1w UART-1)
Disable OTP Fail
Success
Boot Step 3
Fail (1w UART-2)
Fail
Configure
SPI pins Success Boot Step 4
(2w UART)
Fail
Boot from ext
SPIS
Success Boot Step 5
(ext SPIS)
Fail
Success
Success
Boot Step 6 (I2C)
Fail, Goto Fail
Boot St ep 1
Download Code Dis_JTAG=

FALSE Flag should be
Remap SysRAM to Dis_JTAG=TRUE
Leaving Booter Enable JTAG to SRAM updated while CS
with RC32M addr 0x00 and SW
execution
always! reset Dis_JTAG=
FALSE Enable JTAG P0_5 for
WLCSP17
Dis_JTAG= P0_10 for
Boot End TRUE Switch back to Endless loop MSTQFN24
RC32M
Figure 20: BootROM Sequence
The one-wire UART boot capability is introduced due to the limited amount of the GPIOs in the
WLCSP package. The one-wire UART boot leaves four GPIOs for the application and one GPIO for
programming/debugging. Since the booting from UART protocol is a half-duplex, a single GPIO is
used in DA14531 for the external UART. The protocol is the same as for a 2-wire UART booting
except that the Booter SW need to change the pin direction before sending or receiving information.

DA14531
Table 38: Booting Sequence Steps

Step 1: Step 2: Boot Step 3: Step 4: Step 5: Step 6:
Boot from from 1-wire Boot from Boot from Boot from Boot from
external UART (first 1-wire 2-wire external I2C
SPI Master option) UART UART SPI Slave
(second
option)
P0_0/RST MISO Tx MOSI
P0_1 MOSI Rx SCS
P0_2
P0_3 SCS RxTx MISO SDA
P0_4 SCK SCK SCL
P0_5 RxTx (Default)
P0_6
P0_7
P0_8
P0_9
P0_10
P0_11
If no bootable devices are found on any of the serial interfaces, the Booter can do two things,
depending on what is stored in the CS. If the "Debugger disable" (0x70000000) command is stored
there, the Booter will start scanning for peripherals again. Otherwise it enters the endless loop with
the debugger (JTAG) being enabled. The debugger can be connected to P0_5 in the WLCSP17
package or P0_10 in the FCGQFN24 package.
After the BootROM sequence has completed, the default system clock is RC32M, regardless of
which boot path has been chosen and all GPIOs are set back to their default reset values.

DA14531
5 Reset
5.1 Introduction
The DA14531 comprises a reset (RST) pad which is active high. It contains an RC filter with a
resistor of 465 kΩ and a capacitor of 3.5 pF to suppress spikes. It also contains a 25 kΩ pull-down
resistor. This pad should be driven externally by a field-effect transistor (FET) or a single button
connected to VBAT. The typical latency of the RST pad is in the range of 2 µs.
Features
● RC spike filter on RST to suppress external spikes (465 kΩ, 3.5 pF)
● Three different reset lines (SW, HW, and POR)
● Latching the cause of a reset operation (RESET_STAT_REG)
● Configurable POR circuitry
APB16
HW_RESET
DEBUGGER_ENABLE
Debugger
SYS_CTRL_REG[SW_RESET]
SWDIO SWDAP SW_RESET

ARM
SWDCLK AIRCR[SYSRESETREQ]
0x00
WATCHDOG_CTRL_REG[NMI_RST] WATCHDOG
NMI WDOG_reset
HW_RESET
HWR_CTRL_REG[DISABLE_HWR]
Low-Pass Filter
POR Timer PWR ON

RST/P0_0 RESET
POR_TIMER_REG
P0_x
n n
POR_VDD
POR_HIGH
POR_PIN_REG[PIN_SELECT] POR_LOW
Figure 21: Reset Block Diagram
5.2 Architecture
5.2.1 POR, HW, and SW Reset

There are three main reset signals in the DA14531:
● The Power-On Reset (POR): it is optional triggered by a GPIO set as the POR source with a
selectable polarity and/or the RST pad (P0_0) after a programmable time delay
● The HW reset: it is optional triggered by the RST pad (P0_0) when it becomes active for a short
period of time (less than the programmable delay for POR)
● The SW reset: it is triggered by writing the SYS_CTRL_REG[SW_RESET] bit
The POR signal is generated:
● Internally and will release the system’s flip flops as soon as the VDD, VBAT_HIGH, and VBAT_LOW
voltages crossed the specified thresholds
● Externally by a POR source (RST pad multiplexed on a GPIO or P0_0 configured as RST pin)

DA14531
The HW reset can also be automatically activated when the system wakes up from the Extended or
Deep Sleep mode by programming the bit PMU_CTRL_REG[RESET_ON_WAKEUP]. The POR and
the HW reset basically run the cold start-up sequence and the BootROM code is executed.
The SW reset is the logical OR of a signal from the Cortex CPU (triggered by writing SCB->AIRCR =
0x05FA0004) and the SYS_CTRL_REG[SW_RESET] bit. It is mainly used to reboot the system after
the base address has been remapped.
The block diagram of the reset block is depicted in Figure 21.
Certain registers are reset by POR only, or by POR and the HW reset signal but not by the SW reset.
These registers are listed in Table 39.
Table 39: Reset Signals and Registers

Reset by POR Only Reset by POR or HW Reset Reset by POR, HW Reset, or
SW Reset
BANDGAP_REG BLE_CNTL2_REG The rest of the Register File
POR_PIN_REG CLK_AMBA_REG[OTP_ENABLE]
POR_TIMER_REG CLK_FREQ_TRIM_REG
HWR_CTRL_REG CLK_RADIO_REG
RESET_STAT_REG[PORESET_STAT] CLK_CTRL_REG
PAD_LATCH_REG PMU_CTRL_REG
POWER_AON_CTARL_REG SYS_CTRL_REG
GP_DATA_REG TRIM_CTRL_REG
TEST_VDD_REG RAM_PWR_CTRL_REG
RTC_CONTROL_REG CLK_RC32K_REG
RTC_KEEP_RTC_REG CLK_XTAL32K_REG
CLK_RC32M_REG
CLK_RCX_REG
XTALRDY_CTRL_REG
XTAL32M_CTRL0_REG
PMU_SLEEP_REG
POWER_CTRL_REG
POWER_LEVEL_REG
DCDC_CTRL_REG
RAM_LPMX_REG
HIBERN_CTRL_REG
CLK_RTCDIV_REG
RTC_CONTROL_REG
RTC_KEEP_RTC_REG
OTPC_*_REG
QDEC_*_REG
All RF calibration registers

DA14531
5.2.2 POR Functionality

The POR functionality is available by two sources:
● RST Pad: the RST pad is always capable of producing a POR
● GPIO Pin: a GPIO can be selected by the user application to act as a POR source
The time needed for a GPIO pin selected for the POR to be active is stored in the
POR_TIMER_REG. The register field POR_TIME is a 7-bit field which holds the time factor by which
the total time for POR is calculated. The maximum value of the field is 0x7F. The total time for POR
is calculated by the following formula:
Total time = POR_TIME × 4096 × RC32k clock period (1)
where RC32k clock period = 31.25 µs at 25°C.

The maximum time for which a POR can be performed is ~16.2 seconds at 25°C.
The RC32k clock frequency depends on temperature, so based on the temperature span of -10°C to
50°C, the clock frequency range is calculated to be 25 kHz to 39 kHz. Then,
TPORcold = 13 s
TPORhot = 20.8 s
5.2.2.1 POR Timer Clock

The POR timer is clocked by the RC32k clock. If a SW application disables the RC32k, the HW takes
care of enabling the RC32k clock when a POR source (the RST pad or a selected GPIO pin) is
asserted. It should be noted that if the POR is generated from the RST pad, the RC32k will operate
with the reset (default) trimming value. If a GPIO pin is used as the POR source, the RC32k clock will
be trimmed. The timing difference between both cases is expected to be minor.
5.2.2.2 RST Pad

The RST pad will produce a HW reset if the pin active time is less than the programmed value in the
POR_TIMER_REG register or a POR if the pin active time is greater than or equal to that value.
Reset pad is always Active High.
5.2.2.3 POR from GPIO

When a GPIO is used as a POR source, the selected pin retains its capability to act as GPIO. The
POR_PIN_REG[PIN_SELECT] field holds the required GPIO pin number. If the value of the
PIN_SELECT field equals to 0, the POR triggered by GPIO functionality is disabled. The polarity of
the pin can be configured by the POR_PIN_REG [POR_POLARITY] bit, where 0 means Active Low
and 1 means Active High.
5.2.3 POR Timing Diagram

The operation of the POR triggered by both the RST pad and a selected GPIO pin is depicted in
Figure 22.

DA14531
TCLK = 31.25usec
RC32k
Reset pad <POR Timer >=POR Timer
GPIO(POR) <POR Timer >=POR Timer
HW Reset
Timer value matched Timer value matched
POR Timer 0 counting 0 counting 0 counting 0 counting 0
POReset
Figure 22: POR Timing Diagram
5.2.4 POR Considerations

When a POR source (the RST pad or a selected GPIO pin) is asserted, the POR timer starts to
count. When the POR source is released before the timer has expired, the POR timer will be reset to
0. If a POR source is asserted while there is already an asserted POR, and the first POR is released
after the second POR is asserted, and the total time of the two asserted sources is larger than or
equal to the POR_TIME, POR will occur.
It should also be noted that the POR timer triggered by the RST pad can only expire once. After the
POR timer has expired, the RST pad has to be released so the timer can be reloaded. There is no
such limitation when a GPIO is used as the POR source.
The POR_PIN_REG[PIN_SELECT] field cannot survive any reset (POR, HW reset, or SW reset),
therefore, users must take special care on setting up the GPIO POR source right after a reset. This
also applies to the POR_TIMER_REG[POR_TIME] field after a POR.
Please be aware of that, if a GPIO is used as a POR source, the dynamic current of the system
increases due to the dynamic current consumed by the RC32k oscillator. This increase is calculated
to be from 100 nA to 120 nA and it is also present during sleep time period. POR from the RST pad
does not add this dynamic current consumption.
5.3 Programming
To configure the functionality of triggering a POR by a GPIO pin, follow the steps below:
1. Select a GPIO to be set as the POR source by programming
POR_PIN_REG[POR_PIN_SELECT].
2. Set up the input polarity of the GPIO that causes POR by programming
POR_PIN_REG[POR_PIN_POLARITY].
3. Configure the time for the POR to happen by programming POR_TIMER_REG[POR_TIME]. The
default time is around three seconds.
NOTE
To set up the time when the RST pad produces a POR, just set the POR_TIMER_REG register.

DA14531
6 Arm Cortex-M0+
6.1 Introduction
The Arm Cortex-M0+ processor is a 32-bit Reduced Instruction Set Computing (RISC) processor with
a von Neumann architecture (single bus interface). It uses an instruction set called Thumb, which
was first supported in the ARM7TDMI processor, but it also uses several newer instructions from the
Armv6 architecture and a few instructions from the Thumb-2 technology. Thumb-2 technology
extends the previous Thumb instruction set to allow all operations to be carried out in one CPU state.
The instruction set in Thumb-2 includes both 16-bit and 32-bit instructions; most instructions
generated by the C compiler use the 16-bit instructions, and the 32-bit instructions are used when the
16-bit version cannot carry out the required operations. This results in high code density and avoids
the overhead of switching between two instruction sets.
In total, the Cortex-M0+ processor supports only 56 base instructions, although some instructions
can have more than one form. Although the instruction set is small, the Cortex-M0+ processor is
highly capable because the Thumb instruction set is highly optimized.
Academically, the Cortex-M0+ processor is classified as load-store architecture, as it has separate
instructions for reading and writing to memory, and instructions for arithmetic or logical operations
that use registers. It has a two-stage pipeline (fetch+predecode and decode+execute) as opposed to
its predecessor (Cortex-M0) that has a three-stage pipeline (fetch, decode, and execute).
A simplified block diagram of the Cortex-M0+ is shown in Figure 23.
Figure 23: Arm Cortex-M0+ Block Diagram
Features
● Thumb instruction set: highly efficient, of high code density, and able to execute all Thumb and
Thumb-2 instructions
● High performance: up to 0.9 DMIPS/MHz (Dhrystone 2.1) with fast multiplier
● Built-in Nested Vectored Interrupt Controller (NVIC): this makes interrupt configuration and
coding of exception handlers easy. When an interrupt request is taken, the corresponding
interrupt handler is executed automatically without the need to determine the exception vector in
software

DA14531
● Interrupts can have four different programmable priority levels and the NVIC automatically
handles nested interrupts
● The design is configured to respond to exceptions (for example, interrupts) as soon as possible
(minimum 15 clock cycles)
● Non maskable interrupt (NMI) input for safety critical systems
● Easy to use and C friendly. There are only two modes, Thread mode and Handler mode. The
whole application, including exception handlers, can be written in C without any assemblers
● Built-in System Tick timer for OS support. A 24-bit timer with a dedicated exception type is
included in the architecture, which the OS can use as a tick timer or as a general timer in other
applications without an OS
● SuperVisor Call (SVC) instruction with a dedicated SVC exception and Pendable SuperVisor
service (PendSV) to support various operations in an embedded OS
● Architecturally defined sleep modes and instructions to enter sleep. The sleep features allow
power consumption to be reduced dramatically. Defining sleep modes as an architectural feature
makes porting of software easier because the sleep modes are entered by specific instructions
rather than implementation defined control registers
● Fault handling exception to catch various sources of errors in the system
● Support for 21 interrupts
● Little endian memory support
● Wake-up Interrupt Controller (WIC) to allow the processor to be powered down during sleep,
while interrupt sources are still allowed to wake up the system
● Halt mode debug allows the processor activity to stop completely so that register values can be
accessed and modified. No overhead in code size and stack memory size
● CoreSight technology allows memories and peripherals to be accessed from the debugger
without halting the processor
● Supports Serial Wire Debug (SWD) connections. The SWD protocol can handle the same debug
features as the JTAG, but it only requires two wires and is already supported by a number of
debug solutions from various tools vendors
● Four (4) hardware breakpoints and two (2) watch points
● Breakpoint instruction support for an unlimited number of software breakpoints
● rogrammer’s model similar to the AR TDMI processor. Most existing Thumb code for the
ARM7TDMI processor can be reused. This also makes it easy for ARM7TDMI users, as there is
no need to learn a new instruction set.
6.2 Architecture
6.2.1 Interrupts
This section lists all 21 interrupt lines, except the NMI interrupt, and describes their sources and
functionality. The overview of the interrupts is illustrated in Table 40.
Table 40: Interrupt List

IRQ IRQ Name Description
Number
(Inherent
Priority)
0 BLE_WAKEUP_LP_IRQn Wake up the system from Low Power (Extended Sleep) interrupt
from BLE.

DA14531
IRQ IRQ Name Description

Number
(Inherent
Priority)
1 BLE_GEN_IRQn BLE Interrupt. Sources:
● BLE_FINETGTIM_IRQn: Fine Target Timer interrupt generated
when Fine Target timer expires. The timer resolution is 625 μs
base time reference
● BLE_GROSSTGTIM_IRQn: Gross Target Timer interrupt
generated when Gross Target timer expired. The timer
resolution is 16 times 625 μs base time reference
● BLE_CSCNT_IRQn: 625 μs base time reference interrupt,
available in active modes
● BLE_SLP_IRQn: End of Sleep mode interrupt
● BLE_ERROR_IRQn: Error interrupt, generated when undesired
behavior or bad programming occurs in the BLE Core
● BLE_RX_IRQn: Receipt interrupt at the end of each received
packets
● BLE_EVENT_IRQn: End of Advertising/Scanning/Connection
events interrupt
● BLE_CRYPT_IRQn: Encryption/Decryption interrupt, generated
when AES and/or CCM processing is finished
● BLE_SW_IRQn: SW triggered interrupt, generated on SW
request
2 UART_IRQn UART interrupt.
3 UART2_IRQn UART2 interrupt.
4 I2C_IRQn I2C interrupt.
5 SPI_IRQn SPI interrupt.
6 ADC_IRQn Analog-Digital Converter interrupt.
7 KEYBRD_IRQn Keyboard interrupt.
8 BLE_RF_DIAG_IRQn Baseband or Radio Diagnostics Interrupt. Triggered by internal
events of the Radio or Baseband selected by the
BLE_RF_DIAGIRQ_REG. For Debug purposes only.
9 RF_CAL_IRQn RF Calibration Interrupt.
10 GPIO0_IRQn GPIO interrupt through debounce.
15 SWTIM_IRQn Timer0/2 interrupt.
16 WKUP_QUADEC_IRQn Combines the Wake-up Capture Timer interrupt, the GPIO
interrupt, and the QuadDecoder interrupt.
17 TIM1_IRQn Timer1 interrupt.
18 RTC_IRQn Real Time Clock interrupt.
19 DMA_IRQn DMA interrupt.
20 XTAL32RDY_IRQn XTAL32M settling ready interrupt.

DA14531
Interrupt priorities are programmable by the Arm Cortex-M0+. The lower the priority number, the
higher the priority level. The priority level is stored in a byte-wide register, which is set to 0x0 at reset.
Interrupts with the same priority level follow a fixed priority order using the interrupt number listed in
Table 40 (a lower interrupt number has a higher priority level).
To access the Cortex-M0+ NVIC registers, the Cortex Microcontroller Software Interface Standard
(CMSIS) functions can be used. The input parameter IRQn of the CMSIS NVIC access functions is
the IRQ number. This can be the IRQ number or (more conveniently) the corresponding IRQ name
listed in Table 40. For example, the corresponding interrupt handler name in the vector table for
IRQ#15 is SPI_Handler. For more information on the Arm Cortex-M0+ interrupts and the
corresponding CMSIS functions, see section 4.2 Nested Vectored Interrupt Controller in the
Cortex-M0+ Devices Generic User Guide.
The Watchdog interrupt is connected to the NMI input of the processor.
6.2.2 System Timer (systick)

The Cortex-M0+ System Timer (SysTick) can be configured for using two different clocks. The
SysTick Control & Status (STCSR) register specifies which clock should be used by the counter.
● STCSR[CLKSOURCE] = 0: use the (fixed) external reference clock STCLKEN of 1 MHz
● STCSR[CLKSOURCE] = 1: use the (HCLK_DIV dependent) processor clock SCLK (for example,
2, 4, 8, or 16 MHz)
The default SysTick Timer configuration uses the (fixed) external reference clock STCLKEN
(STCSR[CLKSOURCE] = 0). When necessary, higher clock frequencies can be used with
STCSR[CLKSOURCE] = 1, but the software should take the HCLK_DIV dependent core clock SCLK
into account about the timing.
6.2.3 Wake-Up Interrupt Controller

The Wake-up Interrupt Controller (WIC) is a peripheral that can detect an interrupt and wake the
processor from Extended Sleep mode. The WIC is enabled only when the SLEEPDEEP bit in the
system control register is set to 1 (see System Control Register in the Cortex-M0+ Technical
Reference Manual).
The WIC is not programmable and does not have any registers or user interface. It operates entirely
from hardware signals. When the WIC is enabled and the processor enters Extended Sleep mode,
the power management unit in the system can power down most of the Cortex-M0+ processor. This
has the side effect of stopping the SysTick timer. When the WIC receives an interrupt, it takes a
number of clock cycles to wake up the processor and restore its state before it can process the
interrupt. This means the interrupt latency is increased in Extended Sleep mode.
6.3 Programming
For more information on the Arm Cortex-M0+, see the documents listed in Table 41.
Table 41: Arm Documents List

Document Title Arm Document Number
1 Cortex-M0+ Devices Generic User Guide Arm DUI 0662B (available on the website)
2 Cortex-M0+ Technical Reference Manual, r0p1 Arm DDI 0484C (available on the website)
3 Armv6-M Architecture Reference Manual Arm DDI 0419C (can be downloaded by
registered customers)

DA14531
7 AMBA Bus
7.1 Introduction
The DA14531 is based on the AMBA 2.0 AHB and APB components. The AHB is an AMBA Lite
version which requires a single master on the system, but there is arbitration between the Arm
Cortex-M0+ CPU and the Direct Memory Access (DMA) engine. There are two APB bridges, one for
APB16 and the other for APB32, implementing three different decoded slaves which are grouped
according to the power domain structure of the chip.
The AMBA bus organization is presented in Figure 24.
RTC
PD_AON
PD_TIM
TIM
Clockless APB32 Timer1
AMBA APB32
Wakeup Bridge
GPIO
PMU/CRG
PD_SLP
Timer0,2
SLEEP
Quad Decoder
GPRG
BLE Timer
WatchDog
Clocked Wakeup
SYSTEM
APB16 Keyboard
ROM Bridge UART
UART2
AMBA AHB Lite
AMBA APB16
Sys Memory
RAMs Controller I2C
SPI
OTP ADC
Access from
AHB master
Controller
BLE Controller
& Memory
PD_RAD
RFCU
Arm
Remap
AHB master
Cortex- BLE Controller
M0+
Access to Memory
DMA Controller
PD_SYS
Figure 24: AMBA Bus Architecture and Power Domains
7.2 Architecture
Since the DA14531 consists of several different power domains that are digitally controlled and can
be shut down completely, various slave resources, especially on the APB bus, are grouped together
to reduce signal isolation requirements. On the AHB Lite bus, the CPU or the DMA can be the
master, while OTP, BLE Core, Memory and ROM controllers are slaves.
The Always On power domain (PD_AON) contains only the clock-less wake-up controller and the
start-up hardware FSM responsible for the activation of the power devices within the system.
The sleep power domain (PD_SLP) contains the clock tree, the BLE Timer, the Clocked Wake-up
Controller, and the Quadrature Decoder. These blocks are supposed to trigger or to capture wake-up
events while the system is in any of the clocked sleep modes.
The timers power domain (PD_TIM) contains special purpose timers that might or might not be
crucial for an application: a full featured Real Time Clock (RTC) engine and Timer1. The registers of
these blocks are 32-bit wide, hence they are connected to the APB32 bus.
The APB16 bus connects to the radio power domain (PD_RAD), which consists of the Radio control
unit and the BLE controller, and to the peripheral blocks which are all part of the same power domain
as the CPU (PD_SYS).

DA14531
7.3 Programming
Since the AMBA Bus only acknowledges a single master at a time, a programmable arbitration is
implemented to decide whether the Arm Cortex-M0+ or the DMA is the master. The priority can be
configured in the GP_CONTROL_REG[CPU_DMA_BUS_PRIO] with the CPU having the highest
priority by default.

DA14531
8 Memory Map
Table 42: Memory Map
Address Description Power Domain
0x00000000 Boot/BLE ROM/OTP/RAM
0x04000000 Remapped address space based on
SYS_CTRL_REG[REMAP_ADR0].
0x04000000 RESERVED
0x07F00000
0x07F00000 Boot/BLE ROM
0x07F24000 Contains Boot ROM code and BLE protocol related code.
0x07F24000 RESERVED
0x07F40000
0x07F40000 OTP-Regs PD_SYS
0x07F40100 Contains the control registers of the OTP Subsystem.
0x07F40100 RESERVED
0x07F80000
0x07F80000 OTP
0x07F88000 Contains the OTP cell actual memory space.
0x07F88000 RESERVED
0x07F C0000
0x07FC0000 System RAM
0x07FCC000 48 kB. Contains application code, data for the application, stack, and
heap.
SysRAM1 (16 kB): 0x07FC0000 to 0x07FC3FFF
SysRAM2 (12 kB): 0x07FC4000 to 0x07FC6FFF
SysRAM3 (20 kB): 0x07FC7000 to 0x07FCBFFF
0x07FD8000 RESERVED
0x40000000
0x40000000 AHB/BLE-Regs PD_RAD
0x40001000 Contains the control registers of the BLE Link Layer Processor.
0x40001000 AHB/Radio PD_RAD
0x40004000
0x40004000 RESERVED
0x50000000
0x50000000 APB16/PMU-CRG PD_SLP
0x50000100 Contains the control registers of the Power Management Unit and the
Clock Generator.
0x50000100 APB16/wake-up PD_SLP
0x50000200 Contains the registers of the clocked and clock-less wake up
controllers.
0x50000200 APB16/Quadrature Decoder PD_SLP
0x50000300 Contains Logic that implements a step counter for X and Y axis from a
rotary encoder.
0x50000300 RESERVED
0x50001000

DA14531
Address Description Power Domain

0x50001000 APB16/UART PD_SYS
0x50001100 Contains the control registers of the UART.
0x50001100 APB16/UART2 PD_SYS
0x50001200 Contains the control registers of the UART2.
0x50001200 APB16/SPI PD_SYS
0x50001300 Contains the control registers of the SPI interface.
0x50001300 APB16/I2C PD_SYS
0x50001400 Contains the control registers of the I2C interface.
0x50001400 APB16/Kbrd PD_SYS
0x50001500 Contains the registers of the Keyboard controller.
0x50001500 APB16/ADC PD_SYS
0x50001600 Contains the registers of the 4-channel ADC.
0x50001600 APB16/AnaMisc PD_SYS
0x50001700 Contains registers for various analog blocks.
0x50001700 RESERVED
0x50003000
0x50003000 APB16/Ports PD_SYS
0x50003100 Contains the mode and direction registers of the GPIOs.
0x50003100 APB16/Watchdog PD_SYS
0x50003200 Contains the control registers of the Watchdog timer.
0x50003200 APB16/Version PD_SYS
0x50003300 Contains the version/revision of the chip.
0x50003300 APB16/Gen Purpose PD_SYS
0x50003400 Contains general purpose control registers.
0x50003400 APB16/Timer PD_SYS
0x50003500 Contains the control registers of Timer0 and Timer2.
0x50003500 APB16/RF Monitor PD_SYS
0x50003600 Contains the control registers of the RFMON.
0x50003600 APB16/DMA PD_SYS
0x50003700 Contains the control registers of the DMA.
0x50003700 RESERVED
0x50004000
0x50004000 APB32/Timer1 PD_TIM
0x50004100 Contains the control registers of Timer1.
0x50004100 APB32/RTC PD_TIM
0x50004200 Contains the control registers of the Real Time Clock.
0x50004200 RESERVED
0xE0000000
0xE0000000 Internal Private Bus PD_SYS
0xE0100000 Contains various registers of the Arm Cortex-M0+.

DA14531
9 Memory Controller
9.1 Introduction
The Memory Controller of DA14531 is responsible for the interface between the memory cells and
the masters of the system that request access. It comprises two arbiters which use a fixed priority
level scheme to allow parallelization between the three main masters of the RAM. The memory
controller also provides the actual physical sequence of the RAM cells in a continuous memory
space to enable the activation of the required amount of SysRAM only in order to save power.
The block diagram is presented in Figure 25.
Features
● Three different capacities for the RAM cells with retention capability (12 kB, 16 kB, and 20 kB)
● Arbitration among the AHB masters (CPU or DMAs), OTP, and the BLE core
● Transparently interfaces the AHB busses to memory signaling
● Fixed arbitration algorithm with time sharing
System AHB bus
BLE memory bus
Memory bus
MUX-DEMUX
Arbiter Arbiter
SysRAM3 20KB
SysRAM1 16KB
SysRAM2 12KB
Memory
Controller
Figure 25: Memory Controller Block Diagram
9.2 Architecture
The Memory Controller contains two Arbiters which connect to the following busses via a Mux-
Demux:
● BLE Mem I/F: this is a memory interface directly from the Bluetooth 5.1 Core to the RAM used as
an exchange memory (TX/RX descriptors and others). This interface always operates at 16 MHz
● System Mem I/F: This is a memory interface directly from the OTP memory to the RAM used for
copying data after power-up/wake-up

DA14531
9.2.1 Arbitration
The arbitration is a mixture of the highest priority and a fair use policy. If more than one master
request access to cells which reside under the same arbiter, time division is employed. This is to
make sure none of the busses can stall the others for a long period. The OTP and BLE accesses are
handled as very critical and therefore they have the highest priority.

DA14531
10 Clock Generation
10.1 Clock Tree

The generation of the system's clocks is described in detail in Figure 26.
LDO_CORE CP (512KHz)
Analog startup FSM

gen_por_timer
CLK_AMBA_REG[OTP_ENABLE]
otp_clk
CLK_PER_REG[WAKEUPCT_ENABLE]
CLK_CTRL_REG[SYS_CLK_SEL]==0x0
wakeupct_clk
System
XTAL32M DIV Divide by Clocks
1 apb_clk
2 PCLK_DIV
OSC sys_clk
wokenup & !(CLK_CTRL_REG[SYS_CLK_SEL]&0x2) 0 hclk
Divide by
RC32M DIV ble_hclk
1 HCLK_DIV
OSC 2
arb_clk
0 wakeup_clk CLK_PER_REG[SPI_ENABLE]
spi_clk
CLK_PER_REG[I2C_ENABLE]
i2c_clk
CLK_PER_REG[UART1_ENABLE]
uart_clk
CLK_PER_REG[UART2_ENABLE]
uart2_clk
CLK_PER_REG[QUAD_ENABLE]
quad_clk
CLK_PER_REG[TMR_ENABLE] 0
tmr2_clk
Divide by 1
TMR_DIV
TRIPLE_PWM_CTRL_REG[TRIPLE_PWM_CLK_SEL]
Peripheral
0 Clocks
CLK_CTRL_REG[LP_CLK_SEL] tmr0_clk
1
1
TIMER0_CTRL_REG[TIM0_CLK_SEL] tmr0_on_clk
RC OSC Divide by 0
32K/512K 0 10
TIMER0_CTRL_REG[TIM0_CLK_SEL]
RCX
OSC 1 lp_clk 0
tmr1_clk
1
XTAL32K 2
OSC Divide by TIMER1_CTRL_REG[TIM1_CLK_SEL]
rtc_clk
RTC_DIV
3
P0[3] GP_ADC_CTRL_REG[GP_ADC_EN]
gp_adc_clk
DIV=>10,24ms wdog_clk
CLK_RADIO_REG[RFCU_ENABLE]
Divide by
2 rfcu_clk
CLK_RADIO_REG[BLE_ENABLE]
Divide by
BLE_DIV ble_master1_clk
ble_master2_clk BLE & Radio

Clocks
ble_crypt_clk
ble_lp_clk
PLL
RC32M 0
spi_fast_clk
XTAL32M 1
CLK_CTRL_REG[SYS_CLK_SEL]=0x0
Figure 26: Clock Tree Diagram

DA14531
Figure 26 depicts the possible clock sources as well as all different divisions and multiplexing paths
towards the generation of each block's clock. Furthermore, the required registers that have to be
programmed are also shown in Figure 26.
Internal clock sources of DA14531 are the RC32M, RC32K/512K, and RCX oscillators. External
clock sources of DA14531 are the 32 MHz crystal oscillator (the pins XTAL32Mp and XTAL32Mm),
the 32.768 kHz crystal oscillator (the pins XTAL32kp and XTAL32km mapped on P0_3 and P0_4,
respectively), or an external digital clock (the pin P0_3).
There are two main clock lines which are of interest:
● lp_clk: this is the low power clock used for the sleep modes and can only be either the RCX, the
RC32K, the XTAL32K, or an externally supplied digital clock
● sys_clk: this is the system clock used for the AMBA clock (hclk), which runs the CPU, the
memories, and the bus. This clock source can be one of the oscillators or an externally supplied
digital clock
The clock names depicted in Figure 26 are explained in Table 43.
Table 43: Generated Clocks Description

Clock Name Description
wakeupct_clk Clocked wake-up controller clock.
apb_clk AMBA APB interface clock.
otp_clk OTP controller clock.
hclk AMBA AHB interface clock.
ble_hclk AMBA AHB clock for the BLE core.
wdog_clk Watchdog clock.
pmu_rc_clk Clock for the PMU and analog start-up FSM.
icp_clk_512_c (512KHz) Clock for the Charge pump in the LDO_CORE.
gen_por_timer Clock for the POR_FORCE Timer.
spi_clk Clock for the SPI controller. This clock is further divided by 2, 4, 8, or 14
as defined by SPI_CTRL_REG[SPI_CLK].
spi_fast_clk Fast 32 MHz clock for the SPI controller.
i2c_clk Clock for the I2C controller. This clock is further divided to provide 100
kHz or 400 kHz as defined by I2C_CON_REG[I2C_SPEED].
uart_clk Clock for the UART.
uart2_clk Clock for the UART2.
quad_clk Clock for the quadrature decoders.
rfcu_clk Clock for the RF control unit of the Radio.
tmr0_clk, tmr2_clk Timer0/2 clocks.
tmr1_clk Timer1 clock.
tmr0_on_clk Timer0 ON counter clock.
rtc_clk Clock for Real Time Clock (RTC).
gp_adc_clk General Purpose ADC conversion clock.
ble_crypt_clk Clock for the Crypto block of the BLE core.
ble_master1_clk Internal clock for the BLE core.
ble_master2_clk Internal clock for the BLE core.

DA14531
Clock Name Description

arb_clk Clock for the memory controller arbiter.
ble_lp_clk BLE core low power clock.
pll PLL clock.
10.1.1 General Clock Constraints

There are certain constraints on various clocks regarding their frequency relations or the
effectiveness. This section summarizes these rules:
● The minimum of the AMBA clock (hclk) has to be 8 MHz when BLE is utilized. This is also the
clock of the Cortex CPU and ensures the required MIPS for handling the BLE Protocol
● The AMBA clock (hclk) should always be greater or equal to the ble_*_clks. This is required for
the proper operation of the BLE protocol. For example, hclk at 16 MHz and BLE clocks at 8 MHz
is an acceptable combination but not the other way around
10.2 Crystal Oscillators

The Digital Controlled XTAL Oscillators (DXCO) are designed for low power consumption and high
stability. There are two such crystal oscillators in the system, one at 32 MHz (XTAL32M) and the
other at 32.768 kHz (XTAL32K). The XTAL32K has no trimming capabilities and is used as the clock
of the Deep Sleep/Extended Sleep modes. The XTAL32M can be trimmed.
The principle schematic of the two oscillators is shown in Figure 27. No external components to the
DA14531 are required other than the crystal itself. If the crystal has a case connection, it is advised
to connect the case to ground.
XTAL 32Mm
XTAL 32Km
XTAL 32Mp
XTAL 32Kp
32 MHz 32.768 kHz
CL = 4pF - 8 pF
clock32MHz clock32KHz
Figure 27: Crystal Oscillator Circuits
10.2.1 Frequency Control (32 MHz Crystal)

The 8-bit register CLK_FREQ_TRIM_REG controls the trimming of the 32 MHz crystal oscillator. The
frequency is trimmed by two on-chip variable capacitor banks. Both capacitor banks are controlled by
the same register.
The capacitance of both variable capacitor banks varies from the minimum to the maximum value in
256 equal steps. With CLK_FREQ_TRIM_REG[XTAL32M_TRIM] = 0x00, the minimum capacitance
and thus the maximum frequency are selected. With CLK_FREQ_TRIM_REG[XTAL32M_TRIM] =
0xFF, the maximum capacitance and thus the minimum frequency are selected.
The five least significant bits of CLK_FREQ_TRIM_REG register (XTAL32M_TRIM<4:0>) directly
control five binary weighted capacitors (Figure 28). The three most significant bits of
CLK_FREQ_TRIM_REG register (XTAL32M_TRIM<7:5>) are binary to the thermometer decoded.
Each of the seven outputs of the decoder controls a capacitor, of which the value is 32 times the
value of the smallest capacitor.

DA14531
CLK_FREQ_TRIM_REG[XTAL32M_TRIM]
7 6 5 4 3 2 1 0
Decoding
3 -> 7
...
...
2.25pF 2.25pF 1.2pF ... 150fF 75fF

Figure 28: XTAL32MHz Oscillator Frequency Trimming
10.2.2 Automated Trimming and Settling Notification

There is provision in the DA14531 for automating the actual trimming of the 32 MHz crystal oscillator.
This is a special hardware block that realizes the XTAL trimming in a single step. Notification about
the XTAL oscillator being settled after applying the trim value is also provided in form of an interrupt,
namely, the XTAL32RDY_IRQn line. The automated mechanism for applying the trim value and
signaling that the oscillator is settled is described in Figure 29.
The XTAL32RDY_IRQn is always triggered as soon as an internal counter reaches the value
programmed at XTALRDY_CTRL_REG. This counter runs on the RC32M clock if the system is
powering up, or on a selected low power clock if the system is waking up. The enabling of the
XTAL32M is always done by HW. There are two sections until the interrupt notifies the software that
the XTAL32M can be used:
● The start-up section, where the XTAL32M oscillator is slowly converging towards the initial
frequency of the crystal. This section ends with the application of the trim value to achieve a <50
ppm, 32 MHz clock
● The settling section, where the XTAL32M oscillator settles to the preferred frequency after the
application of the trim value which is done automatically by HW
There are two ways of deciding when the start-up section ends and when the trim values are
supposed to be applied. This decision is controlled by TRIM_CTRL_REG[XTAL_TRIM_SELECT] bit
field:
● Counter Mode: trim value stored in the CLK_FREQ_REG is applied as soon as an internal
counter reaches the value XTAL_COUNT_N-1. This is the default mode
● Current Mode: trim value is applied as soon as the current drops
The different modes are illustrated in Figure 29.

DA14531
LP_CLK
Loads from
XTAL32M_EN XTALRDY_CTRL_REG and
counting down...
XTALRDY_CNT 0 2 1 0
(8 bits)
XTAL32RDY_IRQn is always
asserted when XTALRDY_CNT
reaches 1
XTAL32RDY_IRQn
XTAL32MHz
XTAL32_CLK_CNT
Counting ... 0x11FF
(10 bits)
XTAL32_CLK_CNT= XTAL32_CLK_CNT=
XTAL_CO UNT_N XTAL_SETTLE_N
XTAL32_SETTLE_READY
XTAL32M_TRIM_READY asserted when current drops

XTAL32M_TRIM_READY
On FR EQ_TRIM_SW2 rising edge,

XTAL_RDY_CNT value is stored here!
XTALRDY_STAT_REG XTAL_RDY_CN T old value XTAL_RDY_CN T curren t valu e
(8 bits)
TRIM VALUE Performed only during power up

XTAL_TRIM_SELECT=0 XTAL32M_START_REG CLK_FREQ_TRIM_REG
TRIM VALUE
XTAL_TRIM_SELECT=1 XTAL32M_START_REG CLK_FREQ_TRIM_REG
Figure 29: Automated Mechanism for XTAL32M Trim and Settling
In both modes mentioned above, trimming is done by HW. In the current mode, upon assertion of
XTAL32M_TRIM_READY, the interrupt counter value is stored in a shadow register
XTALRDY_STAT_REG to enable SW understanding when the start-up section is finished.
The settling section usually takes no more than five to 10 clock cycles. Using the explanation above,
fine tuning and reducing the XTAL32M latency is feasible. One feature of the XTAL32_CLK_CNT is
that it asserts an observable signal (SYS_STAT_REG[XTAL32_SETTLE_READY]) as soon as the
counter reaches a pre-defined threshold programmed at TRIM_CTRL_REG[XTAL_SETTLE_N]. This
allows the SW to have an indication of the status of the clock by adjusting the threshold accordingly.
10.3 RC Oscillators
There are three RC oscillators in the DA14531:
● One providing 32 MHz (RC32M)
● One providing 32 kHz and 512 kHz (RC32K/512K)
● One providing a frequency of 15 kHz (RCX)
The RC32M is powered by VBAT_LOW which is available during Active or Sleep mode. The output clock
is slower than 32 MHz if untrimmed and it is used to clock the CPU and the digital part of the chip
during power-up or wake-up, while the XTAL32M oscillator is settling.
The simple RC oscillator (RC32K/512K) operates on VDD and provides 32 kHz or 512 kHz. The
main usage of the RC32K/512K oscillator is for internal clocking during power-up or start-up. It clocks
the HW FSM which brings up the power management system of the chip. In the power-up or start-up
sequence, the clock dynamically changes from 32 kHz to 512 kHz in order to speed up the

DA14531
sequence. The enhanced RC oscillator (RCX) provides a stable 15 kHz frequency and operates on
VBAT_LOW which is available during Active or Sleep mode.
The RCX oscillator can be used to replace the 32.768 kHz crystal, since it has a precision of < 500
ppm, while its output frequency needs to be recalibrated over temperature.
Using the RCX requires the following registers to be set:
● Set GP_DATA_REG = 0x20 after the system wakes up
● RCX calibration (the calibration is optional, please see section 10.3.1 for the RCX calibration)
● Go to sleep: set GP_DATA_REG = 0x40 after the sleep procedure is handled
The procedure is also implemented as a part of the SDK.
10.3.1 Frequency Calibration

The output frequency of the 32 kHz crystal oscillator and the three RC-oscillators can be measured
relative to the 32/2 (16) MHz crystal oscillator using the on-chip reference counter.
The measurement procedure is as follows:
1. REF_CNT_VAL = N (the larger number N is, the more accurate and longer the calibration will be)
2. CLK_REF_SEL_REG = 0x0000 (RC32K) or
CLK_REF_SEL_REG = 0x0001 (RC32M) or
CLK_REF_SEL_REG = 0x0002 (XTAL32K) or
CLK_REF_SEL_REG = 0x0003 (RCX)
3. Start the calibration: CLK_REF_SEL_REG[REF_CAL_START] = 1
4. Wait until CLK_REF_SEL_REG[REF_CAL_START] = 0
5. Read CLK_REF_VAL_H_REG and CLK_REF_VAL_L_REG = M (32-bit values)
6. Frequency = (N/M) × 32/2 MHz
If the RCX is used as a sleep clock, the frequency calibration should be implemented on each active
time of a connection interval to guarantee a correct operation.

DA14531
11 OTP Controller
11.1 Introduction
The OTP controller realizes all functions of the OTP macro cell in an automated and transparent way.
The controller facilitates all data transfers (reading and programming), comprises a DMA engine
which connects to the AHB bus as a master, and has the highest priority to copy code from OTP into
SysRAM in mirrored mode. The block diagram is presented in Figure 30.
Features
● Implements all timing constraints for any access to the physical OTP cell
● Automatic single Error Code Correction (ECC) - 6 bits (implemented in the OTP cell)
● 32-bit read in a single read access from the OTP cell
● Single word buffer for programming. No burst programming supported
● Empty words are 0xFFFFFFFF. Zeros are programmed per 32-bit word
● Embedded DMA engine for fast mirroring of the OTP contents into the SysRAM
● Embedded DMA supports reading in bursts of 4 × 32-bit words
● Transparent random address access to the OTP memory cells via the AHB slave memory
interface
● Hardwired handshaking with the PMU to realize the mirroring procedure
AHB Lite
AHB Slave AHB Slave AHB Master

Registers Memory
Copy
Req/Ack Slave DMA
FIFO
IF Ctrl Controller
OTP Memory
(32+6)bits x 8192
Figure 30: OTP Controller Block Diagram
11.2 Architecture
The OTP controller block includes the OTP macro cell and pure digital logic implementing the
controlling functions. The OTP memory communicates with the controller through a proprietary
interface.
The internal organization of the OTP cell is 32-bit data and 6-bit ECC for each of the 8192
addressable positions. The six bits of the ECC are only accessible within the OTP cell. The ECC is
generated by the OTP cell during the programming and is used again by the OTP cell in a
transparent way during reading.
The AHB master interface is controlled by a DMA engine with an internal FIFO of eight 32-bit words.
The DMA engine supports AHB reads and writes. The AHB address where memory access should
begin is programmed into the DMA engine at OTPC_AHBADR_REG[OTPC_AHBADR]. The number

DA14531
of the 32-bit words of a transfer minus 1 must be specified in

OTPC_NWORDS_REG[OTP_NWORDS].
The DMA engine internally supports the following burst types:
● Eight words incremental burst (INCR8)
● Four words incremental burst (INCR4)
● Unspecified incremental burst (INCR) with a length different from 1, 4, or 8
● Single word access (SINGLE)
The slave block combines two AHB slave interfaces: one is for the registers and can be read
from/written to, and the other is for the contents of the OTP memory and is read-only.
The OTP controller configures the OTP cell to be in one of the following modes:
● Deep Stand-by Mode (DSTBY). In this mode the required power supplies are applied to the
OTP cell, while the internal LDO of the OTP cell is inactive.
● Stand-by Mode (STBY). In this mode, the OTP cell is disabled by deactivating the chip select
signal. The OTP cell is powered and the internal LDO is enabled. The power consumption of the
OTP cell in this mode is not the minimum possible but is less than in an active mode (RD, PROG,
PVFY, RINI, AREAD). This is the state from which any active mode of operation can be
transitioned into with the least delay.
● Read Mode (RD). When this mode is used, the contents of the OTP cell can be read at the
respective AHB address space. This mode can also be used to execute software in place (XIP).
A read request is translated by the OTP controller into the corresponding control sequence for
the OTP cell in order to retrieve the requested data.
● Programming Mode (PROG). The PROG mode provides the functionality to program a 32-bit
word into an OTP position. The OTP cell expands the 32-bit word by calculating and
automatically appending a 6-bit checksum (ECC). Please note that there is no way to access
these extra six bits of the ECC information. Programming is performed only for bits equal to 0.
Bits equal to 1 are bypassed to save programming time. Because the ECC value is unknown to
the controller, there are always six extra programming pulses applied to the ECC bits.
Programming is done by issuing a programming request stored in the Programming Buffer
(PBUF). PBUF consists of two configuration registers storing the 32-bit data value and the 13-bit
address in the OTP cell where the value should be programmed. A new request can only be
stored in PBUF when the previous is served. A status bit indicates whether this has already been
done, therefore programming should be monitored by SW before a new programming request is
issued.
● Programming Verification Mode (PVFY). The PVFY mode forces the OTP cell to enter a
special margin read mode. This mode is used to verify the content of the OTP positions that have
been programmed using the PROG mode and to verify that the programmed data is retrieved
correctly under all corner cases. When this mode is used, the contents of the OTP cell can be
read at the respective AHB address space. The CPU must read all OTP positions that have been
programmed by accessing the corresponding addresses and verify that all the retrieved words
are equal to the expected values.
● Read Initial State Mode (RINI). The RINI mode implements a production test of the initial margin
read, which should be performed in the OTP cell, before the first programming is applied. This
test verifies that the OTP cell is empty (all the bits are equal to 1). The OTP controller will send
the required control sequence to the OTP cell to enables the test mode. Then the CPU should
read all the content of the OTP cell at the respective AHB address space and verify that all the
retrieved words are equal to 0xFFFFFFFF. The RINI mode should be used after the PROG mode
in order to verify the content of the OTP positions that have been programmed and specify the
bits that remain un-programmed. This verification is required to ensure that the programming
process has not affected the un-programmed bits. This specific read mode is a margin read,
which means that it is not an equivalent to the normal read and should only be used for the
purpose of verification.

DA14531
● Automatic Read Mode (AREAD). This mode is used to mirror large parts of the OTP cell into
RAM through the AHB master interface and the integrated DMA controller.
Transitioning from one mode to another automatically steps through the STBY mode.
11.2.1 OTP Accessing Considerations

Accesses to the OTP memory (read/write) can only be performed at certain voltage ranges. Users
are responsible for meeting these conditions while accessing the OTP. The recommended operation
conditions of the OTP memory can be found under Recommended Operating Conditions section.
11.3 Programming
To configure the OTP controller, following the sequence of steps below:
1. Enable clock for OTP controller by setting the CLK_AMBA_REG[OTP_ENABLE] bit.
2. Put the OTP in STBY mode (OTPC_MODE_REG[OTPC_MODE_MODE] = 0x2).
3. Wait for OTP mode to change (OTPC_STAT_REG[OTPC_STAT_MRDY] = 1).
4. Set OTP speed by writing OTPC_TIM1_REG and OTPC_TIM2_REG if system clock speed is to
be reduced. These numbers basically generate asynchronous timing signals towards the OTP
cell that comply to the default internal 16 MHz bus speed.
5. Perform an OTP access:
a. Programming:
i. Set up OTP write mode (OTPC_MODE_REG[OTPC_MODE_MODE] = 0x3).
ii. Wait for OTP mode to change (OTPC_STAT_REG[OTPC_STAT_MRDY] = 1).
iii. Check OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY] = 1
iv. Write the data to be programmed to OTPC_PWORD_REG.
v. Write the address to which the data to be programed to OTPC_PADDR_REG.
vi. Wait until the programming is finished (OTPC_STAT_REG[OTPC_STAT_PRDY] = 1).
vii. Switch to OTP verify mode (OTPC_MODE_REG[OTPC_MODE_MODE] = 0x4).
viii. Wait for OTP mode to change (OTPC_STAT_REG[OTPC_STAT_MRDY] = 1).
ix. Read back and compare the data written.
x. Put the OTP in STBY mode (OTPC_MODE_REG[OTPC_MODE_MODE] = 0x1).
xi. Wait for OTP mode to change (OTPC_STAT_REG[OTPC_STAT_MRDY] = 1).
b. Reading:
i. Set up OTP read mode (OTPC_MODE_REG[OTPC_MODE_MODE] = 0x2).
ii. Wait for OTP mode to change (OTPC_STAT_REG[OTPC_STAT_MRDY] = 1).
iii. Read OTP word.
iv. Put the OTP in STBY mode (OTPC_MODE_REG[OTPC_MODE_MODE] = 0x1).
v. Wait for OTP mode to change (OTPC_STAT_REG[OTPC_STAT_MRDY] = 1).

DA14531
12 DMA Controller
12.1 Introduction
The 4-channel direct memory access (DMA) controller transfers data of eight bits, 16 bits, or 32 bits
between the on-chip supported peripherals (SPI, UART, UART2, I2C, and ADC) and the on-chip
RAM and supports regular memory-to-memory transfers. The DMA also supports a programmable
interrupt generation to generate an interrupt after a certain number of transfers in order to off load the
Cortex interrupt rate. The on-chip peripheral requests are multiplexed on the two available channel
pairs to increase the DMA utilization. A block diagram of the controller is depicted on Figure 27.
Features
● Four channels with an optional peripheral trigger
● Full 32-bit source and destination pointers
● Flexible interrupt generation
● Programmable length
● Flexible peripheral request per channel
● Option to initialize memory (DMA_INIT)
● Programmable edge-sensitive request support (recommended when writing to UART/UART2 and
I2C)
AHB Lite
SPI RX/TX req

MUX
I2C RX/TX req SPI RX/TX ack

DMA Channel 0
DEMUX
... I2C RX/TX ack

other req DMA Channel 1 ...
other ack
SPI RX/TX req
MUX
I2C RX/TX req SPI RX/TX ack

DMA Channel 2
DEMUX
... I2C RX/TX ack

other req DMA Channel 3 ...
other ack
DMA01_REQ_MUX
DMA03_REQ_MUX
DMA IRQ lines
IRQ lines
Block IRQ lines
APB16
Control
Figure 31: DMA Controller Block Diagram
12.2 Architecture
12.2.1 DMA Peripherals

By default, the DMA assumes memory-to-memory transactions. Each DMA channel can also be
connected with the hand-shaking signals or other request signals of the corresponding peripherals
(Table 44).

DA14531
Table 44: DMA Served Peripherals

Name Direction
SPI RX/TX
UART RX/TX
UART2 RX/TX
I2C RX/TX
GP-ADC RX
12.2.2 Input/Output Multiplexer

The multiplexing of peripheral requests is controlled by DMA_REQ_MUX_REG. Thus, if
DMA_REQ_MUX_REG[DMAxy_SEL] is set to a certain (non-reserved) value, the TX/RX request
from the corresponding peripheral will be routed to DMA channels y (TX request) and x (RX request),
respectively. Similarly, an acknowledging de-multiplexing mechanism is applied.
When two or more bit-fields (peripheral selectors) of DMA_REQ_MUX_REG have the same value,
the lesser significant selector will be given priority (see also the register's description).
12.2.3 DMA Channel Operation

A DMA channel is switched on with bit DMA_ON. This bit is automatically reset if the DMA channel's
transfer is finished. The DMA channels can either be triggered by SW or by a peripheral DMA
request. If DREQ_MODE is 0, a DMA channel is immediately triggered.
If DREQ_MODE is 1, a DMA channel can be triggered by a HW request coming from a selected
peripheral. All DMA channels support either level (default) or edge-sensitive requests via the bit-field
REQ_SENSE of DMAx_CTRL_REG (x = 0, 1, 2, 3). If this bit-field is set (recommended for Memory-
to-UART/UART2 and Memory-to-I2C transfers), the channel detects a positive edge on the request
signal of the selected peripheral in order to start up a new transfer cycle. The edge-sensitive
requests can be used globally, if desired, for all the peripherals interfacing with the DMA.
When DMA starts, data is transferred from address DMAx_A_START_REG to address
DMAx_B_START_REG for a length of DMAx_LEN_REG, which can be eight, 16, or 32 bits wide.
The address increment is realized with an internal 16-bit counter DMAx_IDX_REG, which is set to 0
when the DMA transfer starts and is compared with the DMAx_LEN_REG after each transfer. The
register value is multiplied by the values of the automatic increment of source address (AINC), the
automatic increment of destination address (BINC), and bus transfer width (BW) before it is added to
DMAx_A_START_REG and DMAx_B_START_REG. AINC or BINC must be 0 for register access.
If at the end of a DMA cycle, the DMA start condition is still true, the DMA continues. The DMA stops
if DREQ_MODE is low or if DMAx_LEN_REG is equal to the internal index register. This condition
also clears the DMA_ON bit if DREQ_MODE is 0 or if DREQ_MODE is set to 1 and CIRCULAR bit is
not set.
If a hand shaking is attached to the specific DMA channel at the end of a DMA cycle, the channel will
be blocked for as long as the peripheral is not ready for the next transaction.
If the bit CIRCULAR is set to 1, the DMA controller automatically resets the internal index registers
and continues from its starting address without intervention of the Arm Cortex-M0+. If the DMA
controller is started with DREQ_MODE = 0, the DMA will always stop, regardless of the state of
CIRCULAR.

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31 0
DMAx_A_START_REG
15 0 AINCx AD[31-0]
DMAx_IDX_REG
+1 BINCx
31
+ IRQ_ENABLE
0
DMAx_B_START_REG
15 0
=
DMAx_INT_REG
DMA_IRQ_CHx
STOP/
RELOAD
15 0 =
DMAx_LEN_REG
13 0
DMAx_CTRL_REG Bus request
Bus Grant
DMA_REQ DMA_INT
DMA_ACK
Figure 32: DMA Channel Diagram
Each DMA channel can generate an interrupt if the index counter DMAx_IDX_REG reaches the
value of the channel's interrupt transfer length register, DMAx_INT_REG. After the transfer and
before DMAx_IDX_REG is incremented, the interrupt is generated.
For example, if DMA_x_INT_REG = 0 and DMA_x_LEN_REG = 0, there will be one transfer and an
interrupt.
12.2.4 DMA Arbitration

The priority level of a DMA channel can be set with bits DMA_PRIO[2-0]. These bits determine which
DMA channel will be activated if more than one DMA channel requests DMA. If two or more channels
have the same priority, an inherent priority applies (see register description).
With DREQ_MODE = 0, a DMA can be interrupted by a channel with a higher priority if the
DMA_IDLE bit is set.
When DMA_INIT is set, however, the DMA channel currently performing the transfer locks the bus
and cannot be interrupted by any other channels until the transfer is completed, regardless of
whether DMA_IDLE is set. The purpose of DMA_INIT is to initialize a specific memory block with a
certain value without any interruption from other active DMA channels that may request the bus at
the same time. Consequently, DMA_INIT should be used only for memory initialization. When the
DMA transfers data to/from peripherals, DMA_INIT should be set to 0.

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NOTE
When DMA_INIT is enabled, AINC must be set to 0 and BINC to 1.
Memory initialization could also be performed by simply setting AINC to 0 and BINC to 1 without enabling the
DMA_INIT, provided that the source address of the memory will not change during the transfer. However, it is
not guaranteed that the DMA transfer will not be interrupted by other channels of a higher priority, when they
request access to the bus at the same time.
12.2.5 Freezing DMA Channels

Each channel of the DMA controller can be temporarily disabled by writing a 1 to bit 4
SET_FREEZE_REG[FRZ_DMA] to freeze all channels.
To enable a frozen channel again, write a 1 to bit 4 RESET_FREEZE_REG[FRZ_DMA].
There is no HW protection from erroneous programming of the DMA registers.
The on-going Memory-to-Memory transfers (DREQ_MODE = 0) cannot be interrupted, therefore the
corresponding DMA channels are frozen after a Memory-to-Memory transfer is completed.
12.3 Programming
12.3.1 Memory to Memory Transfers

1. Set the length of data to be transferred (DMAx_LEN_REG).
2. Set the source address (DMAx_A_START_REG).
3. Set the destination address (DMAx_B_START_REG).
4. Configure the number of transfers until an interrupt is generated (DMAx_INT_REG).
5. Configure transfer options:
a. DMAx_CTRL_REG[AINC]: Automatic increment of source address.
b. DMAx_CTRL_REG[BINC]: Automatic increment of destination address.
c. DMAx_CTRL_REG[BW]: Bus transfer width.
d. DMAx_CTRL_REG[IRQ_ENABLE]: Enable the DMA interrupt generation for this channel.
6. Start the DMA transfer by setting the DMAx_CTRL_REG[DMA_ON] bit.
7. Wait until the transfer is finished (DMAx_CTRL_REG[DMA_ON] = 0).
8. Clear the IRQ status bit for channel x in DMA_INT_STATUS_REG.
12.3.2 Peripheral to Memory Transfers

1. Set the length of data to be transferred (DMAx_LEN_REG).
2. Set the source address (DMAx_A_START_REG) to the peripheral Rx register (for example,
I2C_DATA_CMD_REG).
3. Set the destination address (DMAx_B_START_REG). This should point to a buffer in memory
(for example, SYSRAM).
4. Configure the number of transfers until an interrupt is generated (DMAx_INT_REG).
5. Map the peripheral to the selected channels pair (DMA_REQ_MUX_REG[DMAxy_SEL]).
6. Configure transfer options:
a. DMAx_CTRL_REG[AINC]: Disable automatic increment of source address.
b. DMAx_CTRL_REG[BINC]: Automatic increment of destination address.
c. DMAx_CTRL_REG[BW]: Bus transfer width.
d. DMAx_CTRL_REG[DREQ_MODE]: Enable triggering by peripheral DMA request.
e. DMAx_CTRL_REG[DMA_PRIO]: Set the channel's priority.
f. DMAx_CTRL_REG[IRQ_ENABLE]: Enable the DMA interrupt generation for this channel.

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g. DMAx_CTRL_REG[REQ_SENSE]: Enable edge-sensitive requests for this channel. This is

recommended for Memory-to-UART/UART2/I2C transfers but can also be used globally for
all the supported peripherals and for both directions (TX/RX).
7. Start the DMA transfer by setting the DMAx_CTRL_REG[DMA_ON] bit.
8. Enable peripheral’s D A request (for example, I2C_DMA_CR_REG[TDMAE]).
9. Clear the IRQ status bit for channel x in DMA_INT_STATUS_REG.

DA14531
13 I2C Interface
13.1 Introduction
The I2C Interface is a programmable control bus that provides support for the communications link
between Integrated Circuits in a system. It is a simple two-wire bus with a software-defined protocol
for system control, which is used in temperature sensors and voltage level translators to EEPROMs,
general-purpose I/O, and A/D and D/A converters.
Features
● Two-wire I2C serial interface consisting of a serial data line (SDA) and a serial clock (SCL)
● Two speeds are supported:
○ Standard mode (0 to 100 kbit/s)
○ Fast mode (≤ 400 kbit/s)
● Clock synchronization
● 32 locations deep transmit/receive FIFOs (32× 8-bit Rx and 32× 10-bit Tx)
● Master transmit and Master receive operation
● Slave transmit and Slave receive operation
● 7-bit or 10-bit addressing
● 7-bit or 10-bit combined format transfers
● Bulk transmit mode
● Default slave address of 0x055
● Interrupt or polled-mode operation
● Handles bit and byte waiting at both bus speeds
● Programmable SDA hold time
● DMA support
Figure 33: I2C Controller Block Diagram
13.2 Architecture
The I2C Controller block diagram is shown in Figure 33. It contains the following sub-blocks:
● AMBA Bus Interface Unit: it accesses the register file via the APB interface
● Register File: it contains configuration registers and is the interface with SW
● Master State Machine: it generates the I2C protocol for the master transfers

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● Slave State Machine: it generates the I2C protocol for the slave transfers
● Clock Generator: it calculates the required time to do the following:
○ Generate the SCL clock when configured as a master
○ Check for bus idle
○ Generate a START and a STOP
○ Set up the data and hold the data
● Rx Shift: it takes data into the design and extracts it in byte format
● Tx Shift: it presents data supplied by CPU for transfer on the I2C bus
● Rx Filter: it detects the events in the bus, for example, start, stop, and arbitration lost
● Toggle: it generates pulses on both sides and toggles to transfer signals across clock domains
● Synchronizer: it transfers signals from one clock domain to another
● Interrupt Controller: it generates the raw interrupt and interrupt flags, allowing them to be set
and cleared.
● RX FIFO/TX FIFO: it holds the RX FIFO and TX FIFO register banks and controllers along with
their status levels.
13.2.1 I2C Bus Terms

The following terms relate to what the role of a I2C device is and how it interacts with other I2C
devices on the bus.
● Transmitter is the device that sends data to the bus. A transmitter can either initiate the data
transmission to the bus (a master-transmitter) or respond to a request from the master to send
data back (a slave-transmitter)
● Receiver is the device that receives data from the bus. A receiver can either receive data on its
own request (a master-receiver) or respond to a request from the master to receive data (a slave-
receiver)
● Master is the component that initializes a transfer (START command), generates the clock (SCL)
signal, and terminates the transfer (STOP command). A master can be either a transmitter or a
receiver
● Slave is the device addressed by the master. A slave can be either a receiver or a transmitter
These concepts are illustrated in Figure 34.
Figure 34: Master/Slave and Transmitter/Receiver Relationships
● Multi-master means the ability for more than one master to co-exist on the bus at the same time
without collision or data loss
● Arbitration is the predefined procedure that authorizes only one master at a time to take control of
the bus. For more information, refer to section 13.2.4
● Synchronization is the predefined procedure that synchronizes the clock signals provided by two
or more masters. For more information, refer to section 13.2.5

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● SDA is the data signal line (Serial Data)

● SCL is the clock signal line (Serial Clock)
13.2.1.1 Bus Transfer Terms

The following terms are specific to data transfers that occur to/from the I2C bus.
● START (RESTART). Data transfer begins with a START or RESTART condition. The level of the
SDA data line changes from high to low, while the SCL clock line remains high. When this
occurs, the bus becomes busy
● STOP. Data transfer is terminated by a STOP condition. This occurs when the level of the SDA
data line changes from low to high, while the SCL clock line remains high. When the data transfer
has been terminated, the bus is free or idle again. The bus stays busy if a RESTART is
generated instead of a STOP condition
NOTE
START and RESTART conditions are functionally identical.
13.2.2 I2C Behavior

The I2C can be only be controlled via SW to be an I2C master, communicating with other I2C slaves.
The master is responsible for generating the clock and controlling the transfer of data. The I2C
protocol also allows multiple masters to reside on the I2C bus and uses an arbitration procedure to
determine the bus ownership. A slave is responsible for either transmitting or receiving data to/from
the master. The acknowledgement of data is sent by the device that is receiving data, which can be
either a master or a slave.
Each slave has a unique address that is determined by the system designer. When a master wants
to communicate with a slave, the master transmits a START/RESTART condition that is then
followed by the slave’s address and a control bit (R ) to determine whether the master wants to
transmit data or receive data from the slave. The slave then sends an acknowledge pulse (ACK) after
the address.
If a master-transmitter writes to a slave-receiver, the receiver gets one byte of data. This transaction
continues until the master terminates the transmission with a STOP condition. If a master-receiver
reads from a slave-transmitter, the slave transmits a byte of data to the master, and the master then
acknowledges the transaction with an ACK pulse. This transaction continues until the master
terminates the transmission by not acknowledging (NACK) the transaction after the last byte is
received, and then the master issues a STOP condition or addresses another slave after issuing a
RESTART condition. This behavior is illustrated in Figure 35.
Figure 35: Data Transfer on the I2C Bus
The I2C is a synchronous serial interface. The SDA line is a bidirectional signal and changes only
when the SCL line is low, except for STOP, START, and RESTART conditions. The output drivers
are open-drain or open-collector to perform wire-AND functions on the bus. The maximum number of
devices on the bus is limited only by the maximum capacitance specification of 400 pF. Data is
transmitted in byte packages.

DA14531
13.2.2.1 START and STOP Generation

When operating as an I2C master, putting data into the transmit FIFO causes the I2C Controller to
generate a START condition on the I2C bus. Allowing the transmit FIFO to empty causes the I2C
Controller to generate a STOP condition on the I2C bus.
When operating as a slave, the I2C Controller does not generate START or STOP conditions, as per
the protocol. However, if a read request is made to the I2C Controller, it holds the SCL line low until
read data has been supplied to it. This stalls the I2C bus until read data is provided to the slave I2C
Controller, or the I2C Controller slave is disabled by writing a 0 to I2C_ENABLE.
13.2.2.2 Combined Formats

The I2C Controller supports transactions in a read and write combined format in both 7-bit and 10-bit
addressing modes.
The I2C Controller does not support mixed address and mixed address format, that is, a 7-bit
address transaction followed by a 10-bit address transaction or vice versa.
To initiate combined format transfers, I2C_CON_REG[I2C_RESTART_EN] should be set to 1. With
this value set and the I2C Controller operating as a master, when an I2C transfer is completed, the
I2C Controller checks the transmit FIFO and executes the next transfer. If the direction of the new
transfer differs from the previous one, the combined format is used to issue the transfer. If the
transmit FIFO is empty when the current I2C transfer completes, a STOP is issued, and the next
transfer is issued after a START condition.
13.2.3 I2C Protocols

The I2C Controller has the following protocols:
● START and STOP Conditions
● Addressing Slave Protocol
● Transmitting and Receiving Protocols
● START BYTE Transfer Protocol
13.2.3.1 START and STOP Conditions

When the bus is idle, both SCL and SDA signals are pulled high through external pull-up resistors on
the bus. When a master wants to start a transmission on the bus, it issues a START condition. This
is defined to be a high-to-low transition of the SDA signal while SCL is 1. When the master wants to
terminate the transmission, it issues a STOP condition. This is defined to be a low-to-high transition
of the SDA line while SCL is 1. Figure 36 shows the timing of the START and STOP conditions.
When data is being transmitted on the bus, the SDA line must be stable when SCL is 1.
Figure 36: START and STOP Conditions
NOTE
The signal transitions for the START/STOP conditions (Figure 36) reflect those observed at the output signals
of the master driving the I2C bus. Be careful with observing the SDA/SCL signals at the input signals of the
slave(s), because unequal line delays may result in an incorrect SDA/SCL timing relationship.

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13.2.3.2 Addressing Slave Protocol

There are two address formats: 7-bit address format and 10-bit address format.
7-bit Address Format

In the 7-bit address format, the first seven bits (bits 7:1) of the first byte set the slave address and the
LSB bit (bit 0) is the R/W bit (Figure 37). When bit 0 (R/W) is set to 0, the master writes to the slave.
When bit 0 (R/W) is set to 1, the master reads from the slave.
Figure 37: 7-bit Address Format
10-bit Address Format

In the 10-bit address format, two bytes are transferred to set the 10-bit address. The transfer of the
first byte contains the following bit definition: the first five bits (bits 7:3) notify the slaves that this is a
10-bit transfer, the next two bits (bits 2:1) set the slaves address bits 9:8, and the LSB bit (bit 0) is the
R/W bit. The second byte transferred sets bits 7:0 of the slave address. Figure 38 shows the 10-bit
address format and Table 45 defines the special purpose and the reserved first byte addresses.
Figure 38: 10-bit Address Format
Table 45: I2C Definition of Bits in First Byte in 10-bit Address Format
Slave Address R/W Bits Description
0000 000 0 General Call Address. I2C Controller places the data in the receive buffer
and issues a General Call interrupt.
0000 000 1 START byte. For more details, refer to "START BYTE Transfer Protocol".
0000 001 X CBUS address. I2C Controller ignores these accesses.
0000 010 X Reserved.
0000 011 X Reserved.
0000 1XX X High-speed master code (for more information, refer to section 13.2.4)
1111 1XX X Reserved.
1111 0XX X 10-bit slave addressing.
The I2C Controller does not restrict users from using these reserved addresses. However, if these
reserved addresses are used, incompatibilities with other I2C components may occur.

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13.2.3.3 Transmitting and Receiving Protocols

A master can initiate data transmission and reception to/from the bus, acting as either a master-
transmitter or master-receiver. A slave responds to requests from a master to either transmit data or
receive data to/from the bus, acting as either a slave-transmitter or slave-receiver.
Master-Transmitter and Slave-Receiver

All data is transmitted in byte format with no limit on the number of bytes transferred per data
transfer. After a master sends a slave address and a R/W bit or a master transmits a byte of data to a
slave, the slave-receiver must respond with an acknowledge signal (ACK). When a slave-receiver
does not respond with an ACK signal, the master aborts the transfer by issuing a STOP condition.
The slave must leave the SDA line high so that the master can abort the transfer.
If a master-transmitter is transmitting data as shown in Figure 39, the slave-receiver responds to the
master-transmitter with an ACK signal after every byte of data is received.
Figure 39: Master-Transmitter Protocol
Master-Receiver and Slave-Transmitter

If a master is receiving data as shown in Figure 40, the master responds to the slave-transmitter with
an ACK signal after a byte of data has been received except for the last byte. This is the way the
master-receiver notifies the slave-transmitter that this is the last byte. The slave-transmitter
relinquishes the SDA line after detecting the No Acknowledge (NACK) so that the master can issue a
STOP condition.
When a master does not want to relinquish the bus with a STOP condition, the master can issue a
RESTART condition. This is identical to a START condition except it occurs after the ACK signal.
The master can then communicate with the same slave or a different slave.

DA14531
Figure 40: Master-Receiver Protocol
START BYTE Transfer Protocol

The START BYTE transfer protocol is set up for systems that do not have an on-board dedicated I2C
hardware module. When the I2C Controller is addressed as a slave, it always samples the I2C bus at
the highest speed supported so that it never requires a START BYTE transfer. However, when I2C
Controller is a master, it supports the generation of START BYTE transfers at the beginning of every
transfer in case a slave device requires it. This protocol consists of seven zeros followed by a 1 being
transmitted (Figure 41). This allows the processor that is polling the bus to under-sample the address
phase until 0 is detected. Once the microcontroller detects a 0, it switches from the under-sampling
rate to the correct rate of the master.
Figure 41: START BYTE Transfer
The START BYTE procedure is as follows:

1. Master generates a START condition.
2. Master transmits the START byte (0000 0001).
3. Master transmits the ACK clock pulse. (Present only to conform with the byte handling format
used on the bus)
4. No slave sets the ACK signal to 0.
5. Master generates a RESTART (R) condition.
A hardware receiver does not respond to the START BYTE because it is a reserved address and
gets reset after the RESTART condition is generated.
13.2.4 Multiple Master Arbitration

The I2C Controller allows multiple masters to reside on the same bus. There is an arbitration
procedure if two masters on the same I2C bus try to control the bus at the same time by generating a
START condition simultaneously. Once a master (for example, a microcontroller) has control of the
bus, no other master can take control until the first master sends a STOP condition and places the
bus in an idle state.

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Arbitration takes place on the SDA line while the SCL line is 1. The master which transmits a 1 while
the other master transmits a 0 loses the arbitration and turns off its data output stage. The master
that has lost the arbitration can continue to generate clocks until the end of the byte transfer. If both
masters are addressing the same slave device, the arbitration could go into the data phase. Figure
42 illustrates the timing of an arbitration between two masters on the bus.
For the high-speed mode, an arbitration cannot go into the data phase because each master is
programmed with a unique high-speed master code. This 8-bit code is defined by the system
designer and is set by writing to I2C_HS_MADDR, the High-Speed Master Mode Code Address
Register. Because the codes are unique, only one master can win an arbitration, which occurs by the
end of the transmission of the high-speed master code.
Control of the bus is determined by the address or master code and data sent by the competing
masters, so there is no central master or any order of priority on the bus.
Arbitration is not allowed between the following conditions:
● A RESTART condition and a data bit
● A STOP condition and a data bit
● A RESTART condition and a STOP condition
Slaves are not involved in the arbitration process.
Figure 42: Multiple Master Arbitration
13.2.5 Clock Synchronization

All masters generate their own clock to transfer messages. Data is only valid during the HIGH period
of the SCL clock. When two or more masters try to transfer information on the bus at the same time,
they must synchronize the SCL clock. Clock synchronization is performed using the wired-AND
connection to the SCL signal. When the master transitions the SCL clock to 0, the master starts
counting the LOW period of the SCL clock and transitions the SCL clock signal to 1 at the beginning
of the next clock period. However, if another master is holding the SCL line to 0, the first master goes
into a HIGH wait state until the SCL clock line transitions to 1.
All masters then count out their HIGH time and the master with the shortest HIGH time transitions the
SCL line to 0. The masters then count out their LOW time and the one with the longest LOW time
forces the other master into a HIGH wait state. Therefore, a synchronized SCL clock is generated,

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which is illustrated in Figure 43. Optionally, slaves may hold the SCL line LOW to slow down the
timing on the I2C bus.
Figure 43: Multiple Master Clock Synchronization
13.3 Programming
To configure and use the I2C Controller, follow the simple sequence of steps below:
1. Set up the GPIOs to be used for the I2C interface (P0x_MODE_REG[PID] = 9 or 10).
2. Enable the clock for the I2C Controller (CLK_PER_REG[I2C_ENABLE] = 0x1).
3. Disable the I2C Controller (I2C_ENABLE_REG = 0).
4. Configure the I2C clock frequency:
a. Standard mode (100 kbit/s) : I2C_CON_REG[I2C_SPEED] = 1.
b. Full speed mode (400 kbit/s) : I2C_CON_REG[I2C_SPEED] = 2.
5. Setup the I2C Controller as:
a. Master: I2C_CON_REG[I2C_MASTER_MODE] = 1 and
I2C_CON_REG[I2C_SLAVE_DISABLE] = 1.
b. Slave: I2C_CON_REG[I2C_MASTER_MODE] = 0 and
I2C_CON_REG[I2C_SLAVE_DISABLE] = 0.
6. Choose whether the controller starts its transfers in the 7-bit or 10-bit addressing format when
acting as a master (I2C_CON_REG[I2C_10BITADDR_MASTER]) or whether the controller
responds to the 7-bit or 10-bit addresses when acting as a slave
(I2C_CON_REG[I2C_10BITADDR_SLAVE]).
7. Set target slave address in:
a. Master mode (I2C_TAR_REG[IC_TAR] = 0x55 (default)).
b. Slave mode (I2C_SAR_REG[IC_SAR] = 0x55 (default)).
8. Set the threshold levels on RX and TX FIFO (I2C_RX_TL_REG and I2C_TX_TL_REG).
9. Enable the required interrupts (I2C_INTR_MASK_REG).
10. Enable the I2C Controller (I2C_ENABLE_REG = 0x1).
11. Read a byte:
a. Prepare to transmit the read command byte (I2C_DATA_CMD_REG[I2C_CMD] = 1).
b. Wait until TX FIFO is empty (I2C_STATUS_REG[TFE] = 1).
c. Wait until master has finished reading the byte from slave device
(I2C_STATUS_REG[MST_ACTIVITY] = 0).
12. Write a byte:
a. Prepare to transmit the write command byte (I2C_DATA_CMD_REG[I2C_CMD] = 0 and
I2C_DATA_CMD_REG[I2C_DAT] = command byte).
b. Wait until TX FIFO is empty (I2C_STATUS_REG[TFE] = 1).

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c. Wait until master has finished reading the response byte from slave device
(I2C_STATUS_REG[MST_ACTIVITY] = 0).

DA14531
14 UART
14.1 Introduction
The DA14531 contains two instances of the UART block, that is, UART and UART2.
The UART is compliant to the industry-standard 16550 and is used for serial communication with a
peripheral. Data is written from a master (CPU) over the APB bus to the UART and it is converted to
the serial form and transmitted to the destination device. Serial data is also received by the UART
and stored for the master (CPU) to read back.
There is also DMA support on the UART block, thus the internal FIFOs can be used. Only UART
supports the hardware flow control signals (RTS and CTS) and the 9-bit mode.
UART
pclk UART2
FIFO
Block
APB
APB Bus
Interface
Register uart_int
Block
cts_n
rts_n } UART only
Sync
Block Timeout
Detector
Baud
Clock
uart_clk Generator
uart_rx Serial Receiver Serial Transmitter uart_tx
Figure 44: UART Block Diagram
Features
● 16-byte transmit and receive FIFOs
● Hardware flow control (CTS/RTS) (UART only)
● Shadow registers to reduce software overhead and a software programmable reset is included
● Transmitter Holding Register Empty (THRE) interrupt mode

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● Functionality based on the 16550 industry standard:

○ Programmable character properties, such as number of data bits per character (5-8)
(optional)
○ Parity bit (with odd or even select) and number of stop bits (1, 1.5, or 2)
○ Line break generation and detection
○ Prioritized interrupt identification
● Programmable serial data baud rate
14.2 Architecture
14.2.1 UART (RS232) Serial Protocol

Because the serial communication between the UART and the selected device is asynchronous,
additional bits (start and stop) are added to the serial data to indicate the beginning and end. Utilizing
these bits allows two devices to be synchronized. This structure of serial data accompanied by the
start and stop bits is referred to as a character (Figure 45).
Bit Time
ʃʃ ʃʃ
Serial Data Start Data bits 5-8 Parity Stop 1, 1.5, 2
ʃʃ
One Character
Start
Figure 45: Serial Data Format
An additional parity bit may be added to the serial character. This bit appears after the last data bit
and before the stop bit(s) in the character structure to provide the UART with the ability to perform
simple error checking on the received data.
The UART Line Control Register (UART_LCR_REG) is used to control the serial character
characteristics. The individual bits of the data word are sent after the start bit, starting with the least-
significant bit (LSB). These are followed by the optional parity bit and then by the stop bit(s), which
can be of 1, 1.5, or 2 bits.
All the bits in the transmission (except the half stop bit when the 1.5 stop bits are used) are
transmitted for exactly the same time duration. This is referred to as a Bit Period or Bit Time. One Bit
Time equals to 16 baud clocks. To ensure stability on the line, the receiver samples the serial input
data at approximately the mid-point of the Bit Time, once the start bit has been detected. As the
exact number of baud clocks that each bit has been transmitted for is known, the mid-point for
sampling is every 16 baud clocks after the mid-point sample of the start bit. Figure 46 shows the
sampling points of the first couple of bits in a serial character.
Serial Data In Start Data Bit 0 (LSB) Data Bit 1
8 16 16
Figure 46: Receiver Serial Data Sampling Points
As part of the 16550 standard, an optional baud clock reference output signal (baudout_n) is
supplied to provide timing information to the receiving devices that require it. The baud rate of the
UART is controlled by the serial clock (sclk or pclk in a single clock implementation) and the Divisor
Latch Register (DLH and DLL) in the following equation:
baud rate = (serial clock frequency)/(16 × divisor) (2)

DA14531
where the divisor is a 16-bit integer value plus 4-bit fractional value. The divisor range is 0 to
65535,9375 with steps of 1/16. Divisor High 8-bit integer part is in the DLH register. Divisor Low 8-bit
integer part is in the DLL register. Divisor 4-bit fractional port is in the DLF register.
The registers settings for the common baud rate values are presented in Table 46.
Table 46: UART Baud Rate Generation

Divisor
Baud Rate Divider DLH Reg DLL Reg DLF Reg Actual BR Error (%)
Latch
1200 833,333 833,3125 3 65 5 1200,03 0,00
2400 416,667 416,6875 1 160 11 2399,88 0,00
4800 208,333 208,3125 0 208 5 4800,48 0,01
9600 104,167 104,1875 0 104 3 9598,08 0,02
19200 52,083 52,0625 0 52 1 19207,68 0,04
38400 26,042 26,0625 0 26 1 38369,30 0,08
57600 17,361 17,375 0 17 6 57553,96 0,08
115200 8,681 8,6875 0 8 11 115107,91 0,08
230400 4,340 4,3125 0 4 5 231884,06 0,64
460800 2,170 2,1875 0 2 3 457142,86 0,79
921600 1,085 1,0625 0 1 1 941176,47 2,12
1000000 1 1 0 1 0 1000000 0,00
14.2.2 Clock Support

The UART has two system clocks (pclk and sclk). Having a second asynchronous serial clock (sclk)
allows for accurate serial baud rate settings and meeting APB bus interface requirements.
With the two-clock design, a synchronization module is implemented to synchronize all controls and
data across the two system clock boundaries.
Although a serial clock faster than four-times the pclk does not leave enough time for a complete
incoming character to be received and pushed into the receiver FIFO, in most cases the pclk signal is
faster than the serial clock and this should never be an issue.
The serial clock modules must have time to see new register values and reset their respective state
machines. This total time is guaranteed to be no more than eight clock cycles of the slower of the two
system clocks. Therefore, no data should be transmitted or received before this maximum time
expires after the initial configuration of the UART.
14.2.3 Interrupts
The assertion of the UART interrupt (UART_INT) occurs whenever one of the several prioritized
interrupt types are enabled and active. The following interrupt types can be enabled with the IER
register:
● Receiver Error
● Receiver Data Available
● Character Timeout (in FIFO mode only)
● Transmitter Holding Register Empty at/below threshold (in Programmable THRE interrupt mode)
When an interrupt occurs, the master accesses the UART_IIR_REG to determine the source of the
interrupt before dealing with it accordingly. These interrupt types are described in more detail in
Table 47.

DA14531
Table 47: UART Interrupt Priorities

Interrupt ID Interrupt Set and Reset Functions
Bits [3-0] Priority Interrupt Type Interrupt Source Interrupt Reset Control
0001 - None
0110 Highest Receiver Line status Overrun/parity/framing errors Reading the line status
or break interrupt register
0100 1 Receiver Data Receiver data available (non- Reading the receiver
Available FIFO mode or FIFOs buffer register (non-FIFO
disabled) or RCVR FIFO mode or FIFOs disabled)
trigger level reached (FIFO or the FIFO drops below
mode and FIFOs enabled) the trigger level (FIFO
mode and FIFOs
enabled)
1100 2 Character timeout No characters in or out of the Reading the receiver
indication RCVR FIFO during the last buffer register
four character times and there
is at least one character in it
during this time.
0010 3 Transmitter holding Transmitter holding register Reading the IIR register
register empty empty (Prog. THRE Mode to check whether there is
disabled) or XMIT FIFO at or an interrupt and what its
below threshold (Prog. THRE source is; or, writing into
Mode enabled). THR (FIFOs or THRE
Mode not selected or
disabled) or XMIT FIFO
above threshold (FIFOs
and THRE Mode
selected and enabled).
0000 4 Reserved
0111 Lowest Reserved - -
14.2.4 Programmable THRE Interrupt

The UART can be configured to have a Programmable THRE Interrupt mode available to increase
system performance.
When Programmable THRE Interrupt mode is selected, it can be enabled via the Interrupt Enable
Register (IER[7]). When FIFOs and the THRE Mode are implemented and enabled, THRE Interrupts
are active at and below a programmed transmitter FIFO empty threshold level, as shown in the
flowchart in Figure 47. Figure 48 shows the programmed transmitter FIFO empty threshold level,
where THRE Interrupts are active when the FIFO is empty. In this case the programmable THRE
interrupt mode is disabled.
This threshold level is programmed into CR[5:4]. The available empty thresholds are: empty, 2, ¼,
and ½. See UART CR REG for threshold setting details. Selection of the best threshold value
depends on the system's ability to begin a new transmission sequence in a timely manner. However,
one of these thresholds should prove optimum in increasing system performance by preventing the
transmitter FIFO from running empty.
In addition to the interrupt change, Line Status Register (LSR[5]) also switches its function from
indicating transmitter FIFO empty to FIFO full. This allows software to fill the FIFO in each transmit
sequence by polling LSR[5] before writing another character. Instead of waiting until the FIFO is
completely empty, the flow becomes "fill transmitter FIFO whenever an interrupt occurs and there is
data to transmit". Waiting until the FIFO is empty causes a performance hit whenever the system is
too busy to respond immediately.

DA14531
Even if everything else is selected and enabled, if the FIFOs are disabled via FCR[0], the
Programmable THRE Interrupt mode is also disabled. When not selected or disabled, THRE
interrupts and LSR[5] function normally (both reflecting an empty THR or FIFO). The flowchart of
THRE interrupt generation when not in programmable THRE interrupt mode is shown in Figure 48.
For the THRE interrupt to be controlled as

shown here, the following must be true:
- FIFO_MODE!=NONE CLEAR INTR
- THRE_MODE==Enabled
- FIFOs enabled (FCR[0]==1)
- THRE mode enabled (IER[7]==1)
FIFO LEVEL > TX
Y
Empty Trigger?
N
N
THRE Interrupt
Enabled?
Y
N
SET INTR
Under the condition that

there are no other pending
FIFO LEVEL > TX
interrupts, the interrupt
signal (intr) is asserted Empty Trigger?
Figure 47: Flowchart of Interrupt Generation for Programmable THRE Interrupt Mode

DA14531
For the THRE interrupt to be controlled as CLEAR INTR

shown here, the following must be true:
- FIFO_MODE!=NONE
- THRE_MODE==Disabled
- FIFOs disabled (FCR[0]==0) TX FIFO EMPTY? N
- THRE mode disabled (IER[7]==0)
Y
N
THRE Interrupt
Enabled?
Y
Under the condition that N
there are no other pending SET INTR
interrupts, the interrupt
signal (intr) is asserted
TX FIFO Not Empty

or IIR Read?
Figure 48: Flowchart of Interrupt Generation When Not in Programmable THRE Interrupt Mode
14.2.5 Shadow Registers

The shadow registers shadow some of the existing register bits that are regularly modified by
software. These can be used to reduce the software overhead that is introduced by having to perform
read-modify-writes.
● UART_SRBR_REG support a host burst mode where the host increments its address but still
accesses the same receive buffer register
● UART_STHR support a host burst mode where the host increments its address but still accesses
the same transmit holding register
● UART_SFE_REG accesses the FCR[0] register without accessing the other UART_FCR_REG
bits
● UART_SRT_REG accesses the FCR[7-6] register without accessing the other UART_FCR_REG
bits
● UART_STER_REG accesses the FCR[5-4] register without accessing the other
UART_FCR_REG bits
14.2.6 Direct Test Mode

The on-chip UARTs can be used for the Direct Test Mode required for the final product PHY layer
testing. It can be done either over the HCI layer, which engages a full CTS/RTS UART, or by using a
2-wire UART directly as described in the Bluetooth Low Energy Specification (Volume 6, Part F).
14.3 Programming
To configure and use the UART controllers, follow the simple sequence of steps below:
1. Set up the GPIOs to be used for the UART interface (P0x_MODE_REG[PID] = 1 to 4 and/or 19-
20).
2. Enable the selected UART by setting the CLK_PER_REG[UARTx_ENABLE] bit.

DA14531
3. Enable access to Divisor Latch Registers (DLL and DLH) by setting the
UARTx_LCR_REG[UART_DLAB] bit.
4. Set the desired baud rate. To calculate the registers values for the desired baud rate, use the
following equation:
Divisor = UART CLK/(16 × Baud rate) (3)
a. UARTx_IER_DLH_REG: High byte of the Divisor integer part.

b. UARTx_RBR_THR_DLL_REG: Low byte of the Divisor integer part.
c. UARTx_DLF_REG: The fractional part of the Divisor.
5. Configure the break control bit, parity, number of stop bits, and data length (UARTx_LCR_REG).
6. Enable and configure the FIFO (UARTx_IIR_FCR_REG).
7. Configure the generated interrupts, if needed (UARTx_IER_DLH_REG).
8. Send a byte:
a. Check if Transmit Hold Register (THR) is empty (UARTx_LSR_REG[UART_THRE]).
b. Load the byte to THR (UARTx_RBR_THR_DLL_REG).
c. Check if the byte has been transmitted (UARTx_LSR_REG[UART_TEMT]).
9. Receive a byte:
a. Wait until serial data is ready (UARTx_LSR_REG[UART_DR]).
b. Read the incoming byte from the THR (UARTx_RBR_THR_DLL_REG).

DA14531
15 SPI Interface
15.1 Introduction
This controller implements the Serial Peripheral Interface (SPI™)1 for master and slave modes. The
serial interface can transmit and receive from four bits to up to 32 bits in master/slave mode. The
controller comprises separate TX and RX FIFOs and DMA handshake support. Slave mode clock
speed is independent from the system clock speed. Moreover, master's clock speed can be as fast
as the system's clock speed. The controller can generate an interrupt upon data threshold reached in
the TX or RX FIFOs.
Features
● Slave and master mode
● From 4-bit to up to 32-bit operation
● SPI Master clock line speed up to 32 MHz, SPI Slave clock line speed up to 16 MHz
● SPI mode 0, 1, 2, and 3 support (clock edge and phase)
● Built-in separate 8-bit wide and 4-byte deep RX/TX FIFOs for continuous SPI bursts
● Maskable interrupt generation based on TX or RX FIFO thresholds
● DMA support
APB
INTERRUPT
DMA_TX_REQ
DMA_RX_REQ TX fifo RX fifo Configuration
8bits width 8bits width registers
DMA_TX_ACK X depth Y depth
DMA_RX_ACK
TX buffer RX buffer
Spi core
TX shift RX shift
register register
DO enable
CS0
DO
CS1
DI
Figure 49: SPI Block Diagram
1 SPI is a trademark of Motorola, Inc.

DA14531
15.2 Architecture
The SPI controller is an APB peripheral operating on the apb_clk clock. It contains a front end which
is clocked by the spi_clk clock and is responsible for the serialization/deserialization of the data in the
RX and TX streams.
Two separate FIFOs, each of eight bits wide and four bytes deep, are used to store data for RX and
TX streams. Since a SPI word can be configured to be from four bits to up to 32 bits, one to four
FIFO positions can be written/read at the same time. FIFOs contain logic implementing
programmable thresholds comparison.
The SPI controller supports DMA requests and interrupt generation based on the FIFO thresholds. If
enabled, a DMA request and/or interrupt will be asserted with whether TX_FIFO level is low or
RX_FIFO level is high.
The SPI interface supports all four modes of operation and the corresponding polarity (CPOL) and
phase (CPHA) of the SPI clock (SPI_CLK) are defined in Table 48.
Table 48: SPI Modes Configuration and SCK States

SPI Mode CPOL CHPA TX SPI_CLK RX SPI_CLK Idle SPI_CLK
0 0 0 Falling edge Rising edge Low
1 0 1 Rising edge Falling edge Low
2 1 0 Rising edge Falling edge High
3 1 1 Falling edge Rising edge High
To read from or to write to an external single byte FLASH device in the SPI master mode, a byte
swap mechanism is implemented to allow for a proper placement of the bytes in a 16-bit word for the
DMA to write to/read from the internal RAM. More specifically, when the SPI controller is configured
as a master with DMA support and a 16-bit word width so that the bus utilization is increased
compared to reading from an 8-bit device, the byte swap mechanism brings the least significant byte
read and place it in the most significant byte in the 16-bit word. The controller automatically swaps
the bytes to allow for placing the first byte read in the least significant byte of the 16-bit word. This
feature is programmable via SPI_CTRL_REG[SPI_SWAP_BYTES].
The SPI controller can operate at the highest speed (32 MHz on the SPI_CLK line) in a special
master mode. The clock of the controller is then either the XTAL32M or the RC32M and can be used
for fast booting from external FLASH devices that support this frequency.
15.2.1 SPI Timing

The timing of the SPI interface when the SPI controller is in slave mode is presented in Figure 50.
Figure 50: SPI Slave Mode Timing (CPOL = 0, CPHA = 0)

DA14531
Table 49: SPI Timing Parameters

Parameter Description Typ Unit
tCKPER spi_clk clock period 60 ns
tCSST CS active time before the first edge of spi_clk 1 spi_clk cycle
tCSHOLD CS non-active time after the last edge of spi_clk 1 spi_clk cycle
tMOST Master input data latching setup time (spi_clk/2) - 5 ns
tMOHOLD Master input data hold time 0 ns
tSODEL Slave output data delay 25 ns
15.3 Programming
15.3.1 Master Mode

To configure the SPI controller in master mode, follow the steps below:
1. Set the appropriate GPIO ports in SPI clock mode (output), SPI Chip Select mode (output), SPI
Data Out mode (output), and SPI Data In mode (input).
2. Enable SPI clock by setting CLK_PER_REG[SPI_ENABLE] = 1.
3. Reset SPI FIFO by setting SPI_CTRL_REG[SPI_FIFO_RESET] = 1.
4. Set the SPI clock mode (synchronous or asynchronous with APB clock) by programming
SPI_CLOCK_REG[SPI_MASTER_CLK_MODE].
5. Set the SPI clock frequency by programming SPI_CLOCK_REG[SPI_CLK_DIV]. If SPI_CLK_DIV
is not 0x7F, SPI_CLK = module_clk/2 × (SPI_CLK_DIV + 1). If SPI_CLK_DIV = 0x7F, SPI_CLK =
module_clk.
6. Set the SPI mode (CPOL or CPHA) by programming SPI_CONFIG_REG[SPI_MODE].
7. Set the SPI controller in master mode by setting SPI_CONFIG_REG[SPI_SLAVE_EN] = 0.
8. Define the SPI word length (from 4-bit to 32-bit) by programming
SPI_CONFIG_REG[SPI_WORD_LENGTH]. SPI_WORD_LENGTH = word length - 1.
To read/write the following sequence has to be performed:
1. If a slave device is slow and does not give the data at the correct clock edge, configure the SPI
module to capture data at the next clock edge by setting
SPI_CTRL_REG[SPI_CAPTURE_AT_NEXT_EDGE] = 1. Otherwise, set
SPI_CTRL_REG[SPI_CAPTURE_AT_NEXT_EDGE] = 0.
2. Release FIFO reset by setting SPI_CTRL_REG[SPI_FIFO_RESET] = 0.
3. Enable SPI TX path by setting SPI_CTRL_REG[SPI_TX_EN] = 1.
4. Enable SPI RX path by setting SPI_CTRL_REG[SPI_RX_EN] = 1.
5. Enable the SPI chip select by programming the SPI_CS_CONFIG_REG[SPI_CS_SELECT] = 1
or 2. This option allows the master to select the slave that is connected to the GPIO that has the
function of SPI_CS0 or SPI_CS1.
6. Enable the SPI controller by setting SPI_CTRL_REG[SPI_EN] = 1.
7. Write to TX FIFO by programming SPI_FIFO_WRITE_REG[SPI_FIFO_WRITE]. Write access is
permitted only when SPI_FIFO_STATUS_REG[SPI_TX_FIFO_FULL] = 0.
8. Read from RX FIFO by programming SPI_FIFO_READ_REG[SPI_FIFO_READ]. Read is
permitted only when SPI_FIFO_STATUS_REG[SPI_RX_FIFO_EMPTY] = 0.
9. To disable the SPI chip select, set SPI_CS_CONFIG_REG[SPI_CS_SELECT] = 0 to deselect
the slave and set SPI_CTRL_REG[SPI_FIFO_RESET] = 1 to reset the SPI FIFO.

DA14531
15.3.2 Slave Mode

1. Set the appropriate GPIO ports in SPI clock mode (input), SPI Chip Select mode (input), SPI
Data Out mode (output), and SPI Data In mode (input).
2. Enable SPI clock by setting CLK_PER_REG[SPI_ENABLE] = 1.
3. Reset SPI FIFO by setting SPI_CTRL_REG[SPI_FIFO_RESET] = 1.
4. Set the SPI mode (CPOL or CPHA) by programming SPI_CONFIG_REG[SPI_MODE].
5. Set the SPI module in slave controller by setting SPI_CONFIG_REG[SPI_SLAVE_EN] = 1.
6. Define the SPI word length (from 4-bit to 32-bit) by programming
SPI_CONFIG_REG[SPI_WORD_LENGTH]. SPI_WORD_LENGTH = word length - 1.
To read/write the following sequence has to be performed:
1. Set SPI FIFO in normal operation by setting SPI_CTRL_REG[SPI_FIFO_RESET] = 0.
2. Enable SPI TX path by setting SPI_CTRL_REG[SPI_TX_EN] = 1.
3. Enable SPI RX path by setting SPI_CTRL_REG[SPI_RX_EN] = 1.
4. Enable the SPI controller by setting SPI_CTRL_REG[SPI_EN] = 1.
5. Write the first data byte directly to TX buffer by programming the
SPI_TXBUFFER_FORCE_L_REG[SPI_TXBUFFER_FORCE_L].
6. Write the rest of the data to TX FIFO by programming
SPI_FIFO_WRITE_REG[SPI_FIFO_WRITE]. Write access is permitted only if
SPI_FIFO_STATUS_REG[SPI_TX_FIFO_FULL] = 0.
7. Read from RX FIFO by programming SPI_FIFO_READ_REG[SPI_FIFO_READ]. Read is
permitted only if SPI_FIFO_STATUS_REG[SPI_RX_FIFO_EMPTY] = 0.

DA14531
16 Quadrature Decoder
16.1 Introduction
The DA14531 has an integrated Quadrature decoder that can automatically decode the signals for
the X, Y, and Z axes of a HID input device, reporting step count and direction. It can also be
programmed to simply count rising/falling edges on any of the channel pairs. This block can be used
to wake up the chip as soon as there is a movement from the connected external device. The block
diagram of the quadrature decoder is presented in Figure 51.
Features
● Three 16-bit signed counters that provide the step count and direction on each of the axes (X, Y,
and Z) and one 8-bit counter counting the overall edges from all the three counters
● Programmable system clock sampling at a maximum of 16 MHz
● APB interface for control and programming
● Programmable source from the GPIOs
● Digital filter on the channel inputs to avoid spikes
APB Interface
Register File
QD_CHA_X
Digital
16-bit Counter
Filter
QD_CHB_X (X Axis)
QD_CHA_Y
Digital
16-bit Counter
Filter
QD_CHB_Y (Y Axis)
QD_CHA_Z
Digital
16-bit Counter
Filter
QD_CHB_Z (Z Axis)
Quad_Dec_IRQn
Interrupt Generator
Figure 51: Quadrature Decoder Block Diagram
16.2 Architecture
Channels are expected to provide a pulse train with 90 degrees rotation as displayed in Figure 52
and Figure 53.

DA14531
QD_CHA_X
QD_CHB_X
Figure 52: Moving Forward on Axis X
QD_CHA_X
QD_CHB_X
Figure 53: Moving Backwards on Axis X
Depending on whether channel A or channel B is leading in phase, the quadrature decoding block
calculates the direction on the related axis. Furthermore, the signed counter value represents the
number of steps moved.
Users can choose which GPIOs to use for the channels by programming the QDEC_CTRL2_REG
register. The block supports two modes of operation: quadrature counting and edges counting. The
quadrature counting mode reads the patterns of successive pulses as in Figure 52 and Figure 53,
while the edges counting mode simply counts all positive and negative edges on any of the two
channels of a pair.
NOTE
If two edges happen at the same time, the counter will only count one.
The digital filter eliminates the spikes shorter than three clock periods. It is followed by an edge
detection circuitry and they are shown in Figure 54.
QDEC_CHx_EVENT_MODE
J Q
D Q
Cnt_dir 16bit Counter
K
ChA_x D Q D Q D Q D Q X-Axis
J Q
D Q
Cnt_en
K 8bit Counter
ChB_x D Q D Q D Q D Q QDEC_EVENT_CNT
QDEC_CHy_EVENT_MODE
J Q
D Q
Cnt_dir
K 16bit Counter
ChA_y D Q D Q D Q D Q
Y-Axis
J Q
D Q
Cnt_en
K
ChB_y D Q D Q D Q D Q
Digital Filtering & Edge Detection Quadrature decoders
Figure 54: Digital Filtering and Edge Detection Circuit
A counter for its dedicated axis holds the movement events of the channels. When a channel is
disabled, the counter is reset. The counters are accessible via the APB bus.
The QDEC_EVENT_CNT gathers all edges on all channels regardless of the mode of operation. If
two edges happen at the same time, this counter will only be increased by one.

DA14531
The quadrature decoder operates on the system clock. The QDEC_CLOCKDIV register defines the
number of clock cycles during which the decoding logic samples the data on the channel inputs. The
division is automatically disabled when the lp_clk is used as the system clock.
16.3 Programming
To program the quadrature decoder for actual quadrature counting or edge counting, follow the
simple sequence of steps below:
1. Configure the clock frequency by configuring the QDEC_CLOCKDIV register. The value in this
register will be dividing the sys_clk. However, if sys_clk = lp_clk, this divider is completely
bypassed.
2. Define which pin pairs represent the different channels for the X, Y, and Z axes or the GPIOs
from which the edges are counted. Configure such information at QDEC_CHX_PORT_SEL,
QDEC_CHY_PORT_SEL, and QDEC_CHZ_PORT_SEL registers.
3. Configure the interrupt threshold upon which an interrupt will be generated at
QDEC_CTRL_REG[QDEC_IRQ_THRES]. Note that the interrupt threshold is based on the value
of QDEC_EVENT_CNT_REG which keeps on counting after the interrupt is generated.
4. Define the mode of operation by configuring the respective QDEC_CHx_EVENT_MODE field in
the QDEC_CTRL2_REG.
5. Enable the clock of the block by writing at CLK_PER_REG[QUAD_ENABLE].
6. Wait for the interrupt and then read X, Y, and Z values at QDEC_XCNT_REG,
QDEC_YCNT_REG, and QDEC_ZCNT_REG (in the quadrature counting case) or the
QDEC_EVENT_CNT_REG (in the edges counting case).
7. Clear the interrupt (by writing at QDEC_CTRL_REG[QDEC_IRQ_STATUS]) and the edge
counter (by writing at QDEC_CTRL_REG[QDEC_EVENT_CNT_CLR) if needed.

DA14531
17 Clockless Wakeup Controller
17.1 Introduction
The Clockless Wakeup Controller implements a circuit that enables the RC32K clock which in turn
triggers the HW Startup FSM to allow the system to be woken up by an external event (a GPIO
toggle). This controller is only used when the system is in hibernation mode, that is, when all clocks
are stopped.
Features
● Wake up the system from specific GPIOs (P0_1, P0_2, P0_3, P0_4, and P0_5)
● Configurable polarity of the GPIO signals (single configuration for all GPIOs)
● Special RC filtered inputs feeding the wakeup control circuit (Type B pads)
● Always powered
RC Filtered Non-Filtered
Outputs Outputs => to PPA
P0_1
P0_2
Enable clock
P0_3 FF RC32KHz
Fast_mode
P0_4
Start Up
HIBERN_WKUP_POLARITY FSM
P0_5
HIBERN_WKUP_MASK
Figure 55: Clockless Wakeup Controller Circuit
17.2 Architecture
The Clockless Wakeup Controller automatically enables the RC32K oscillator when a toggle is
identified in one of the five specific GPIOs (P0_1, P0_2, P0_3, P0_4, and P0_5). These GPIO
signals are connected to the Type B pads, which provide two outputs to the digital domain. One
output goes through a Schmitt trigger and the other one goes through an RC filter with a cutoff
frequency of 100 kHz and a Schmitt trigger. The output going through the RC filter and a Schmitt
trigger feeds the clockless wakeup controller circuitry. Hence, any spikes larger than 100 kHz will be
filtered out without waking up the system.
The triggering GPIO can be defined by means of a masking register. If no GPIO is masked out, any
toggle in any of these GPIOs will create an edge which serves as a clock for a Flip-Flop to lock and
enable the oscillator. The polarity of the edge is also programmable, but it is common for the GPIOs
and not a dedicated bit per GPIO.
Note that, if two opposite edges occur exactly at the same time on two GPIOs that are allowed to
wake up the system, the XOR output will not change its value and no wake up occurs. However,
even if the GPIO signal events have a couple of ns difference, the circuit will still understand it and
the clock will be started.

DA14531
17.3 Programming
To program the clockless wakeup controller before setting the system into hibernation mode, follow
the simple sequence of steps below:
1. Define which pins are allowed to wake up the system from hibernation by configuring the
HIBERN_CTRL_REG[HIBERN_WKUP_MASK].
2. Define the polarity of the waking up events at
HIBERN_CTRL_REG[HIBERN_WKUP_POLARITY]. This should be done by reading the value of
the unmasked G I s and programming the polarity register with their R’ed state.
3. Enable the hibernation mode by programming the
HIBERN_CTRL_REG[HIBERNATION_ENABLE] bit field. Note that this action stops all clocks
when the system drops to sleep.
4. Allow RAM to be retained by programming the RAM_PWR_CTRL_REG accordingly.
5. Define where address 0 is to be mapped at SYS_CTRL_REG[REMAP_ADR0] so that the CPU
can execute code right after waking up. If RAM is retained, REMAP_ADR0 should point to 0x2 or
0x3.
6. Clear RESET_STAT_REG. Clear this register means that the system wakes up from the
hibernation mode.
7. Put the system to sleep by executing the WFI command with the SCR bit set.

DA14531
18 Clocked Wakeup Controller
18.1 Introduction
The Clocked Wakeup Controller can be programmed to wake up the DA14531 from deep sleep
mode and extended sleep mode upon a pre-programmed number of GPIO events on a maximum of
two pins in parallel. This wakeup controller resides in the PD_SLP power domain and operates on
the LP_CLK.
The block diagram illustrating the wakeup function is shown in Figure 56.
Features
● Monitors GPIO state changes
● Implements debouncing time from 0 ms up to 63 ms on two GPIOs in parallel
● Accumulates external events and compares the number to a programmed value
● Generates an interrupt to the CPU's WIC
P0_0 WKUP_COMPARE_REG
wkup_pol_gpio_reg[0]
wkup_select_gpio_reg[0] Key_hit
.
. D Q D Q
Debounce Events
. Counter Counter
P0_x
WKUP_ENABLE_IRQ
wkup_pol_gpio_reg[x]
wkup_select_gpio_reg[x]
WKUPCT_IRQ
P0_0
wkup2_pol_gpio_reg[0]
WKUP2_ENABLE_IRQ
wkup2_select_gpio_reg[0]
. Key_hit
. D Q D Q
Debounce Events
. Counter Counter
P0_x
wkup2_pol_gpio_reg[x]
wkup2_select_gpio_reg[x] WKUP_COMPARE_REG
Figure 56: Clocked Wakeup Controller Block Diagram
18.2 Architecture
The controller comprises two identical circuits that implement the edge detection, debouncing, and
event counting before generating a wakeup interrupt towards the CPU.
A LOW to HIGH level transition on the selected input port sets internal signal "key_hit" to 1, while
WKUP_POL_GPIO_REG[y] = 0. This signal triggers the event counter state machine as shown in
Figure 57. The debounce counter is loaded with the value of
WKUP_CTRL_REG[WKUP_DEB_VALUE]. The timer counts down every 1 ms. The signal state is
constantly monitored. If the debounce counter reaches 0, it means that the key_hit signal state has
been stable over the amount of clock cycles counted by the debounce counter.

DA14531
RST
IDLE
key_hit = 1
timer = DEBOUNCE
key_hit = 0 key_hit = 0
timer not 0
KEY_PRESSED
key_hit = 1
KEY_RELEASE key_hit = 1 and
timer = 0
event_count = event_count + 1
Figure 57: Event Counter State Machine for the Wakeup Interrupt Generator
The event counter is edge sensitive. After an active edge is detected, a reverse edge must be
detected first before the event counter goes back to the IDLE state and from there starts waiting for a
new active edge.
If the event counter is equal to the value set in the WKUP_COMPARE_REG register, the counter will
be reset and an interrupt will be generated, if the interrupt generation has been enabled by
WKUP_ENABLE_IRQ and WKUP2_ENABLE_IRQ in the WKUP_CTRL_REG.
NOTE
There is only one register for both circuits that contains the number of events before an interrupt is issued.
The interrupt can be cleared by writing a value to the register WKUP_RESET_IRQ_REG. The event
counter can be reset by writing a value to the register WKUP_RESET_CNTR_REG. The value of the
event counter can be read at any time by reading register WKUP_COUNTER_REG.
Any of the GPIO inputs can be selected to generate an event by programming the corresponding
WKUP/WKUP2_SELECT_GPIO_REG register. When both WKUP/WKUP2_SELECT_GPIO_REG
registers are configured to generate a wakeup interrupt, a toggle on any GPIO will wake up the
system.
The input signal edge can be selected by programming the WKUP/WKUP2_POL_GPIO_REG
registers.
NOTE
A minimum of 2 low power clocks pulse is required on a GPIO in order to be correctly identified as a wake up
edge trigger
18.3 Programming
To configure the clocked wakeup controller, follow the simple sequence of steps below:
1. Define the polarity of the triggering GPIOs at WKUP/WKUP2_POL_GPIO_REG.
2. Configure the debouncing counters by programming WKUP_CTRL_REG[WKUP_DEB_VALUE]
with the amount of time (ms) during which the signal should be re-sampled before its state is
decided. Note that there is a single bit field for both debouncing counters.
3. Define the number of events that are needed to trigger the wakeup interrupt by programming the
WKUP_COMPARE_REG. Note there is only one register for both circuits.
4. Allow the interrupt generation by configuring the WKUP_ENABLE_IRQ and
WKUP2_ENABLE_IRQ bit fields, respectively, in the WKUP_CTRL_REG.
5. Define which GPIOs are allowed to trigger a wakeup event at
WKUP/WKUP2_SELECT_GPIO_REG.

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6. Set the system to deep sleep mode or extended sleep mode by executing the WFI command with
the SCR bit set.

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19 Timer 0
19.1 Introduction
Timer 0 is a 16-bit general purpose software programmable timer, which has the ability of generating
Pulse Width Modulated (PWM) signals PWM0 and PWM1. It also generates the SWTIM_IRQ
interrupt to the Arm Cortex-M0+. It can be configured in various modes regarding output frequency,
duty cycle, and the modulation of the PWM signals. Figure 58 shows the block diagram of Timer 0.
Features
● 16-bit general purpose timer
● Ability to generate two PWM signals (PWM0 and PWM1)
● Programmable output frequency (f) with N = 0 to (216-1) and M = 0 to (216-1)
f = (------------------------------------------------------------------
16, 8, 4, 2 MHz or 32 kHz)
------
( M + 1 ) + (N + 1)
● Programmable duty cycle (δ):

M+1
 = --------------------------------------------  100 %
( M + 1) + (N + 1 )
● Separately programmable interrupt timer:
T = (----------------------------------------------------------------
16, 8, 4, 2 MHz or 32 kHz)
--------
( ON + 1 )
Figure 58: Timer 0 Block Diagram
19.2 Architecture
The 16-bit Timer 0 consists of two counters, that is, T0-counter and ON-counter, and three registers,
that is, TIMER0_RELOAD_M_REG, TIMER0_RELOAD_N_REG, and TIMER0_ON_REG. Upon

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reset, the counter and register values are 0x0000. Timer 0 generates a PWM signal PWM0, of which
the frequency and duty cycle are determined by the contents of the TIMER0_RELOAD_N_REG and
the TIMER0_RELOAD_M_REG registers. The PWM1 signal is the inverted version of PWM0.
Timer 0 can run at five different clocks: 16 MHz, 8 MHz, 4 MHz, 2 MHz, or 32 kHz. The 32 kHz clock
is selected by default with bit TIM0_CLK_SEL in the TIMER0_CTRL_REG register. This slow clock
has no enabling bit. The other four options can be selected by setting the TIM0_CLK_SEL bit and the
TMR_ENABLE bit in the CLK_PER_REG (by default the TMR_ENABLE bit is disabled). This register
also controls the four higher clock frequency on which Timer 0 runs via the TMR_DIV bits. An extra
clock divider is available and can be activated via bit TIM0_CLK_DIV of the timer control register
TIMER0_CTRL_REG. This clock divider is only used for the ON-counter and always divides the
clock for the ON-counter by 10.
NOTE
If the LP clock is selected as system clock, the CLK_AMBA_REG[HCLK] bit field should always be 0 to
ensure the proper operation of the timer.
Timer 0 operates in PWM mode. The signals PWM0 and PWM1 can be mapped to any GPIOs.
Timer 0 PWM Mode
If bit TIM0_CTRL in the TIMER0_CTRL_REG is set, Timer 0 will start running. SWTIM_IRQ will be
generated and the T0-counter will load its start value from the TIMER0_RELOAD_M_REG register
and will decrement on each clock cycle. The ON-counter also loads its start value from the
TIMER0_ON_REG register and decrements with the selected clock.
When the T0-counter reaches zero, the internal signal T0-toggle will be toggled to select the
TIMER0_RELOAD_N_REG whose value will be loaded in the T0-counter. Each time the T0-counter
reaches zero, it will alternately be reloaded with the values of the M0- and N0-shadow registers.
PWM0 will be high when the M0-value decrements and low when the N0-value decrements. For
PWM1 the opposite is applicable since it is inverted. If bit PWM_MODE in the TIMER0_CTRL_REG
register is set, the PWM signals are not HIGH during the "high time" but output a clock in that stage.
The frequency is based on the clock settings defined in the CLK_PER_REG register (also when the
32-kHz clock is used), but the selected clock frequency is divided by two to get a 50 % duty cycle.
If the ON-counter reaches zero, it will remain zero until the T0-counter also reaches zero, while
decrementing the value loaded from the TIMER0_RELOAD_N_REG register (PWM0 is low). The
counter will then generate an interrupt (SWTIM_IRQ). The ON-counter will be reloaded with the value
of the TIMER0_ON_REG register. The T0-counter as well as the M0-shadow register will be loaded
with the value of the TIMER0_RELOAD_M_REG register. At the same time, the N0-shadow register
will be loaded with the value of TIMER0_RELOAD_N_REG register. Both counters will be
decremented on the next clock again and the sequence will be repeated.
NOTE
It is possible to generate interrupts at a high rate by selecting a high clock frequency and low counter values.
This could result in missed interrupt events.
During the time when the ON-counter is non-zero, new values for the ON-register, M0-register, and
N0-register can be written, but they are not used by the T0-counter until a full cycle is finished. More
specifically, the newly written values in the TIMER0_RELOAD_M_REG and
TIMER0_RELOAD_N_REG registers are only stored into the shadow registers when the ON-counter
and the T0-counter have both reached zero and the T0-counter is decrementing the value loaded
from the TIMER0_RELOAD_N_REG register (Figure 59).

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clk
TIM0_CTRL
M N M N M N
T0-counter 0 1 0 1 0 1 0 1 0 1 0 1
ON-counter 0 4 3 2 1 0 4 3 2
PWM0 pin
PWM1 pin
SWTIM_IRQ
M0=1 N0=1 ON=4
TIM0580-01
Figure 59: Timer 0 PWM Mode
At start-up both counters and the PWM0 signal are LOW, so at start-up an interrupt is also
generated. If Timer 0 is disabled, all flip-flops, counters, and outputs are in reset state except the ON-
register, the TIMER0_RELOAD_N_REG register, and the TIMER0_RELOAD_M_REG register.
The timer input registers, that is, ON-register, TIMER0_RELOAD_N_REG, and
TIMER0_RELOAD_M_REG can be written, and the counter registers ON-counter and T0-counter
can be read. When reading from the address of the ON-register, the value of the ON-counter is
returned. Reading from the address of either the TIMER0_RELOAD_N_REG or the
TIMER0_RELOAD_M_REG register returns the value of the T0-counter.
It is possible to freeze Timer 0 with bit FRZ_SWTIM of the register SET_FREEZE_REG. When the
timer is frozen, the timer counters are not decremented. This will freeze all the timer registers at their
last value. The timer will continue its operation again when bit FRZ_SWTIM is cleared via register
RESET_FREEZE_REG.
19.3 Programming
When LP clock is selected as system clock, CLK_AMBA_REG[HCLK_DIV] should be set to 0.
When LP clock is selected as Timer clock, CLK_PER_REG[TMR_DIV] should be set to 0
19.3.1 Timer Functionality

Timer 0 supports the functionality of a timer for generating interrupts after specific time intervals. To
configure the timer operation, follow the steps below:
1. Select the timer clock by programming TIMER0_CTRL_REG[TIM0_CLK_SEL]. The system or
the LP clock can be selected using this option.
2. Select the clock division scaler by programming CLK_PER_REG[TMR_DIV]. Note that this
setting only applies to the system clock.
3. Define whether Timer 0 will use the clock frequency as is or divided by 10 by programming
TIMER0_CLK_REG[TIM0_CLK_DIV].
4. Enable Timer 0 clock by programming CLK_PER_REG[TMR_ENABLE].
5. For 16-bit counting, program TIMER0_ON_REG with the expired time in timer 0 clock cycles
TIMER0_RELOAD_M_REG and TIMER0_RELOAD_N_REG must be set to 0.
6. For 17-bit counting, load 65535 to TIMER0_RELOAD_M_REG and the rest to
TIMER0_RELOAD_N_REG. TIMER0_ON_REG must be set to 0.
7. Enable Timer 0 by programming TIMER0_CTRL_REG[TIM0_CTRL].

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19.3.2 PWM Generation

Timer 0 also supports PWM generation. To configure the PWM generation functionality, follow the
steps below:
1. Select the timer clock by programming TIMER0_CTRL_REG[TIM0_CLK_SEL]. The system or
the LP clock can be selected by this option.
2. Select the clock division scaler by programming CLK_PER_REG[TMR_DIV]. Note that this
setting only applies to the system clock.
3. Select the PWM mode by programming the TIMER0_CTRL_REG[PWM_MODE]. There are two
modes supported. In the first one, the PWM signals are '1' during high time. In the second one,
the PWM signals send out the (fast) clock divided by two during high time, so the clock frequency
will be in the range of 1 to 8 MHz.
4. Enable Timer 0 clock by programming CLK_PER_REG[TMR_ENABLE].
5. Load the "high" value of the duty cycle in TIMER0_RELOAD_M_REG and the "low" value of the
duty cycle in TIMER0_RELOAD_N_REG.
6. Set the desired GPIOs in PWM0/PWM1 and output mode.
7. Enable Timer 0 by programming TIMER0_CTRL_REG[TIM0_CTRL].
20 Timer 1
20.1 Introduction
Timer 1 is an 11-bit timer that can count up or down. It supports a free-running mode with an interrupt
generated when zero is reached (also by wrapping around). It can be configured to use the system
clock (sys_clk) or the LP clock (lp_clk) as the clock source. It supports capturing events on two GPIO
channels when the number of clock cycles between these events is known. It can also generate an
interrupt after a programmable number of clock cycles after an event. Figure 60 shows the block
diagram of Timer 1.
Features
● 11-bit up/down counter with free running mode
● Selectable system or LP clock as source
● Two channels for capture input triggered by GPIOs
● Capture capability from two GPIO events with programmable polarity
● Programmable number of events between the two GPIOs for capturing
● Timer 1 or RTC snapshot on capture events
● Interrupt generation

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RTC_Timer_Value
22
sys_clk
COUNTER (Up/Down)
Lp_clk
CAPCNT1_VALUE
TIMER_VALUE TIM_RELOAD GPIO_IN1
TIMER_CTRL
Capture Event
TIMER1_STATUS_REG CAPCNT2_VALUE
GPIOx_CONF IN1_PERIOD_MAX GPIO_IN2
CLEAR_GPIO_EVENT IN2_PERIOD_MAX
TIM1_IRQn
IRQ
CLEAR_IRQ IN1_OVRFLW IN2_OVRFLW
Generator
20.2 Architecture
Timer 1 is placed in the PD_TIM power domain which can be kept powered even when the system
power domain (containing the CPU) is shut down.
The main operation of Timer 1 is to count up or down, generating an interrupt when it reaches the
maximum/minimum value or the threshold that has been programed as the reload value.
Moreover, Timer 1 comes with a sense block that allows for sensing positive or negative edges on
two GPIOs (configurable). The sense block operates in two modes:
● Counting mode: Timer1 will generate an interrupt upon a configurable amount of edges on a
GPIO has been detected. The number of clock cycles was counted between timer start and
captured the N - events is stored to CAPCNTx_VALUE register. When timer detects the first N-
events, automatically starts to detect the next N-events until timer is disabled
● Capture mode: Timer 1 saves a snapshot of either its own counter (11 bits) or the RTC port (22
bits) after an edge on a GPIO has been detected. If there is a pending interrupt, a new snapshot
is not saved and the TIMER1_STATUS_REG[TIMER1_INx_OVRFLW] bit is set. This bit is
cleared together with the TIMER1_STATUS_REG[TIMER1_Inx_EVENT] bit
The same GPIO can be used for both modes.
If Timer 1 is used in the counting mode, it can measure the frequency applied to a GPIO port (see
section 20.3.3).
20.3 Programming
20.3.1 Timer Functionality

Timer 1 supports the functionality of a timer for generating interrupts after specific time intervals. To
configure the timer functionality, follow the steps below:
1. Select the timer clock by programming TIMER1_CTRL_REG[TIMER1_USE_SYS_CLK]. The
system or the LP clock can be selected by this option.
NOTE
If the LP clock is selected as system clock, the CLK_AMBA_REG[HCLK] bit field should always be 0 to
ensure the proper operation of the timer.

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2. Enable or disable the free run mode by programming

TIMER1_CTRL_REG[TIMER1_FREE_RUN_MODE_EN]. The free run mode can only be used
when Timer 1 counts up.
3. Enable Timer 1 interrupt by programming TIMER1_CTRL_REG[TIMER1_IRQ_EN].
4. Set Timer 1 to count up or down by programming
TIMER1_CTRL_REG[TIMER1_COUNT_DOWN_EN].
5. Specify the reload value by programming TIMER1_CTRL_REG[TIMER1_RELOAD].
6. Enable the Timer 1 clock by programming TIMER1_CTRL_REG[TIMER1_CLK_EN].
7. Enable Timer 1 by programming TIMER1_CTRL_REG[TIMER1_ENABLE].
20.3.2 Capture Functionality

Timer 1 can capture a snapshot of the value of RTC or Timer1 counts after a GPIO edge is detected.
To configure the capture functionality, follow the steps below:
1. Depending on the source of the snapshot value, configure and enable RTC or Timer 1 or both in
the capture mode.
2. Set the edge type (rising or falling edge) by programming
TIMER1_CAPTURE_REG[TIMER1_IN1_EVENT_FALL_EN] or
TIMER1_CAPTURE_REG[TIMER1_IN2_EVENT_FALL_EN], depending on the channel that is
used.
3. Set the timer in capture mode by setting
TIMER1_CAPTURE_REG[TIMER1_IN1_COUNT_EN]=0 or
TIMER1_CAPTURE_REG[TIMER1_IN2_COUNT_EN]=0, depending on the channel that is used.
4. Enable capture interrupt by setting TIMER1_CAPTURE_REG[TIMER1_IN1_IRQ_EN] = 1 or
TIMER1_CAPTURE_REG[TIMER1_IN2_IRQ_EN] = 1, depending on the channel that is used.
5. Set the source of the snapshot value (RTC or Timer 1 count) by setting
TIMER1_CAPTURE_REG[TIMER1_IN1_STAMP_TYPE] or
TIMER1_CAPTURE_REG[TIMER1_IN2_STAMP_TYPE], depending on the channel that is used.
6. Set the GPIO that will be used to trigger the capture by setting
TIMER1_CAPTURE_REG[TIMER1_GPIO1_CONF] or
TIMER1_CAPTURE_REG[TIMER1_GPIO1_CONF], depending on the channel that is used.
Note that the values from 1 to 12 define the P0 pins from 0 to 11.
7. When an interrupt is generated, the capture value will be saved in
TIMER1_CAPCNT1_VALUE_REG[TIMER1_CAPCNT1_VALUE] or
TIMER1_CAPCNT2_VALUE_REG[TIMER1_CAPCNT2_VALUE], depending on the channel that
is used.
8. Write 1 to TIMER1_CLR_EVENT_REG[TIMER_CLR_Inx_EVENT] to clear the event.
20.3.3 Frequency Measuring Functionality

Timer 1 can measure the frequency applied to a GPIO port. To configure the frequency measure
functionality, follow the steps below:
1. Configure and enable Timer 1 in count up free mode using the system clock.
2. Set Timer 1 in count mode by setting TIMER1_CAPTURE_REG[TIMER1_IN1_COUNT_EN] = 1
or TIMER1_CAPTURE_REG[TIMER1_IN2_COUNT_EN] = 1, depending on the channel that is
used.
3. Enable capture interrupt by setting TIMER1_CAPTURE_REG[TIMER1_IN1_IRQ_EN] = 1 or
TIMER1_CAPTURE_REG[TIMER1_IN2_IRQ_EN] = 1, depending on the channel that is used.
4. Set the rising edge by programming TIMER1_CAPTURE_REG[TIMER1_IN1_EVENT_FALL_EN]
= 0 or TIMER1_CAPTURE_REG[TIMER1_IN2_EVENT_FALL_EN] = 0, depending on the
channel that is used.

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5. Set the number of periods plus one, in which Timer 1 counts, by setting
TIMER1_CAPTURE_REG[TIMER1_IN1_PERIOD_MAX] or
TIMER1_CAPTURE_REG[TIMER1_IN2_PERIOD_MAX], depending on the channel that is used.
6. Set the GPIO that will be used to trigger the capture by setting
TIMER1_CAPTURE_REG[TIMER1_GPIO1_CONF] or
TIMER1_CAPTURE_REG[TIMER1_GPIO1_CONF], depending on the channel that is used.
Note that the values from 1 to 12 define the P0 pins from 0 to 11.
7. After the interrupt is triggered, read the value in
TIMER1_CAPCNT1_VALUE_REG[TIMER1_CAPCNT1_VALUE] or
TIMER1_CAPCNT2_VALUE_REG[TIMER1_CAPCNT2_VALUE], depending on the channel that
is used. This value indicates the number of cycles that has passed during the period defined in
step 5.
8. To calculate the frequency applied to the GPIO, divide the number of periods (step 5) by the
cycles (step 7) and multiply the result with the frequency of Timer 1 clock.
9. Write 1 to TIMER1_CLR_EVENT_REG[TIMER_CLR_Inx_EVENT] to clear the event.
21 Timer 2
21.1 Introduction
Timer 2 is basically a PWM generator. It has six PWM outputs. The block diagram is shown in Figure
61.
Timer 2 System bus
13 0 13 0
13 0
PWM2_START_CYCLE ... PWM7_START_CYCLE
TRIPLE_PWM_FREQ PWM2_END_CYCLE PWM7_END_CYCLE
6 x 14 bits T2_PWM1
Comparators
14 bits
sys_clk DIV
...
1/2/4/8 DUTY_CNTR
reset T2_PWM6
Hold
+1
/Reset block
TRIPLE_PWM_ENABLE
TRIPLE_PWM_CTRL_REG
SW_PAUSE_EN
RX_EN HW_PAUSE_EN
TRIPLE_PWM_CTRL_REG
TX_EN
Features

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● 14-bit general purpose timer

● Ability to generate six PWM signals (PWM2, PWM3, PWM4, PWM5, PWM6, and PWM7,)
● Input clock frequency (fIN) with N = 1, 2, 4, or 8 and sys_clk = 16 MHz or 32 kHz:
fIN = sys_clk
-------------------
N
● Programmable output frequency (fOUT):
f IN  fIN 
fOUT =  ------ to  -----------------
-
2  2 14 – 1
● Six outputs with a programmable duty cycle from 0 % to 100 %

● Used for white LED intensity (on/off) control or motor control
21.2 Architecture
Timer 2 is clocked with the system clock divided by TMR_DIV (1, 2, 4, or 8) and can be enabled with
TRIPLE_PWM_CTRL_REG[TRIPLE_PWM_ENABLE].
TRIPLE_PWM_FREQUENCY determines the output frequency of the PWM outputs.
NOTE
There is a single frequency register for all six PWM outputs.
DUTY_CNTR is an up-counter counting from 0 up to TRIPLE_PWM_FREQUENCY.

If DUTY_CNTR is equal to the value stored in the respective PWMn_END_CYCLE register, it resets
the PWMn output to 0.
If DUTY_CNTR is equal to the value stored in the respective PWMn_START_CYCLE register, it sets
the PWMn output to 1.
Note that the value of PWMn_END_CYCLE and PWMn_START_CYCLE must be less than or equal
to TRIPLE_PWM_FREQUENCY.
The Timer 2 is enabled/disabled by programming the
TRIPLE_PWM_CTRL_REG[TRIPLE_PWM_EN] bit.
The timing diagram of Timer 2 is shown in Figure 62.
Freeze function
During RF activity it may be desirable to temporarily suppress the PWM switching noise. This can be
done by setting TRIPLE_PWM_CTRL_REG[HW_PAUSE_EN] = 1. The effect is that whenever there
is a transmission or a reception process from the Radio, DUTY_CNTR is frozen and PWMx output is
switched to 0 to disable the selected PWMn. As soon as the Radio is idle, that is, RX_EN or TX_EN
signals are zero, DUTY_CNTR resumes counting and finalizes the remaining part of the PWM duty
cycle.
TRIPLE_PWM_CTRL_REG[SW_PAUSE_EN] can be set to 0 to disable the automatic, hardware
driven freeze function of the duty counter and keep the duty cycle constant.
Note that the RX_EN and TX_EN signals are not software driven but controlled by the BLE core
hardware.

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TMR2_CLK
TRIPLE_PWN_ENABLED
DUTY_CNTR 0 0 1 2 3 8 9 ... 0 1 2 3
T2_PWMn
Figure 62: Timer 2 Timing Diagram
21.3 Programming
When LP clock is selected as Timer clock, CLK_PER_REG[TMR_DIV] should be set to 0
21.3.1 PWM Generation

Timer 2 only supports PWM generation and does not support a normal, interrupt generating, timer
functionality as the previous timers do. To configure the PWM generation functionality, follow the
steps below:
1. Select the clock source for Timer 2 by programming
TRIPLE_PWM_CTRL_REG[TRIPLE_PWM_CLK_SEL]. System clock or LP clock can be
selected. Please note that if the (fast) system clock is selected, the division scaler is the same as
the one for Timer 0.
2. Define the GPIOs to which the PWM signals are mapped by programming the respective PID
number.
3. Define the frequency of Timer 2 that feeds the PWM waveforms by programming the
TRIPLE_PWM_FREQUENCY with a value that conforms to the following equation. For example,
if Timer 2 clock is 32000 Hz (lp_clk) and the required frequency for the PWM is 16 kHz, this
register should be written with 0x1.
Timer2_clk_freq_Hz/Required_freq_Hz − 1 (4)
NOTE
There is a single frequency register for all six PWM outputs.
4. Define the duty cycle of each PWM signal. Program the start and end cycle of the pulse at
PWMx_START_CYCLE and PWMx_END_CYCLE, respectively. The available amount of cycles
is depicted in the contents of TRIPLE_PWM_FREQUENCY register. For example, if the
TRIPLE_PWM_FREQUENCY has a value of 0x8 and the START/END_CYCLE bit fields have a
value of 3 and 5, respectively, the PWM signals will rise after three Timer 2 clock cycles and fall
after five clock cycles. Every PWM signal has its own register to configure its duty cycle.
5. Enable the PWM signals by programming TRIPLE_PWM_CTRL_REG[TRIPLE_PWM_ENABLE]
= 1.
21.3.2 Freeze Functionality

There is provision to allow hardware to pause PWM signals while RF is active. This can be done by
programming TRIPLE_PWM_CTRL_REG[HW_PAUSE_EN] = 1. It can also be done via SW control
by programming TRIPLE_PWM_CTRL_REG[SW_PAUSE_EN] = 1.

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22 Watchdog Timer
22.1 Introduction
The Watchdog Timer is an 8-bit timer with a sign bit that can be used to detect an unexpected
execution sequence caused by a software run-away and can generate a full system reset (WDOG
reset) or a Non-Maskable Interrupt (NMI). Figure 63 shows the block diagram of the Watchdog
Timer.
Features
● 8-bit down counter with a sign bit, clocked with a 10.24 ms clock for a maximum 2.6 s time-out
● Non-Maskable Interrupt (NMI) or WDOG reset
● Optional automatic WDOG reset if NMI handler fails to update the Watchdog register
● Non-maskable Watchdog freeze of the Cortex-M0+ Debug module when the Cortex-M0+ is
halted in Debug state. Maskable Watchdog freeze by user program
Figure 63: Watchdog Timer Block Diagram
22.2 Architecture
The 8-bit watchdog timer is decremented by 1 every 10.24 ms. The timer value can be accessed
through the WATCHDOG_REG register which is set to 255 (FF16) at reset. This results in a
maximum watchdog time-out of ~2.6 s. During write access, the WATCHDOG_REG[WDOG_WEN]
bit must be 0. This provides extra filtering for a software run-away by writing ones to all the bits in the
WATCHDOG_REG. If the watchdog timer reaches 0, its value will get a negative value by setting bit
8. The counter sequence becomes 1, 0, 1FF16 (-1), 1FE16(-2), till 1F016 (-16).
If WATCHDOG_CTRL_REG[NMI_RST] = 0, the watchdog timer will generate an NMI when it
reaches 0 and a WDOG reset when it becomes less or equal to -16 (1F016). The NMI handler must
write a value that is larger than -16 to the WATCHDOG_REG to prevent the generation of a WDOG
reset when the watchdog timer reaches the value -16 after 16 × 10.24 = 163.8 ms.
If WATCHDOG_CTRL_REG[NMI_RST] = 1, the watchdog timer generates a WDOG reset when it
becomes less than or equal to 0.
The WDOG reset is one of the system (SYS) reset sources and resets almost the whole device,
including resetting the WATCHDOG_REG register to 255. Refer to the POR, HW, and SW Reset
section for an overview of the complete reset circuit and conditions.
For debugging purposes, the Cortex-M0+ Debug module can always freeze the watchdog by setting
the DHCSR[DBGKEY | C_HALT | C_DEBUGEN] control bits (reflected by the status bit S_HALT, see

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Table 42). This is automatically done by the debugging tool, for example, during step-by-step
debugging. Note that this bit also freezes the Wake-up Timer, the Software Timer, and the BLE
master clock. For additional information see the DEBUG_REG[DEBUGS_FREEZE_EN] mask
register. The C_DEBUGEN bit cannot be accessed by the user software so that freezing the
watchdog is prevented.
In addition to the S_HALT bit, the watchdog timer can also be frozen if NMI_RST = 0 and
SET_FREEZE_REG[FRZ_WDOG] is set to 1. The watchdog timer resumes counting when
RESET_FREEZE_REG[FRZ_WDOG] is set to 1. The WATCHDOG_CTRL_REG[NMI_RST] bit can
only be set by software and will only be reset on a SYS reset. Note that if the system is not
remapped, that is, the SysRAM is at address 0x07FC0000, a watchdog fire will trigger the BootROM
code to be executed again.
22.3 Programming
To program the Watchdog Timer, follow the simple sequence of steps below:
1. Freeze watchdog by setting the SET_FREEZE_REG[FRZ_WDOG] bit (optional).
2. Select NMI and reset events (WATCHDOG_CTRL_REG[NMI_RST]).
3. Enable writing of the watchdog timer (WATCHDOG_REG[WDOG_WEN] = 0]).
4. Write the reload value of the watchdog timer (WATCHDOG_REG[WDOG_VAL], see the register
description).
5. Resume watchdog (RESET_FREEZE_REG[FRZ _WDOG] = 1), if frozen.

DA14531
23 Temperature Sensor
23.1 Introduction
The DA14531 features a built-in temperature sensor.
Features
● Temperature range -40°C to 105°C
● Absolute accuracy after one-point calibration +/- 4°C (assuming 25°C reference temperature)
● 25°C single point calibration reference value provided in T memory
23.2 Architecture
The temperature sensor can be read out via the GP_ADC.
Figure 64 illustrates the relationship between the actual ambient temperature and the calculated
temperature from the GP_ADC readout, including possible inaccuracies in T SENSE_ACC_OTP (offset) and
TCSENSE (angle).
Figure 64: Temperature Sensor Behavior

DA14531
The recommended formula for single point calibrated temperature reading is as follows:
Tx = 25 + (ADCx - ADCOTP_CAL_25C)/(TCSENSE × 64)
Where:
● Tx = calculated single point calibrated die temperature in [°C]
● ADCx = 16-bit GP_ADC_VAL readout (converted to decimal) at temperature Tx
● ADCOTP_CAL_25C = 25°C T calibration value recorded during production testing (based on the
16-bit readout)
● TCSENSE = temperature coefficient in [LSB °C], typical value is 1.45 LSB °C
● 25 = reference base value in [°C]
● 64 = correction for 16-bit to 10-bit ADC values
For uncalibrated temperature sensor measurements, ADCOTP_CAL25C can be replaced by the default
value using the formula below:
Tx = 25 + (ADCx - 30272)/(TCSENSE × 64)
Note that this is not recommended since it can result in large offsets.
NOTE
While measuring and/or calibration, the system's power dissipation should be kept the same, otherwise the
measurement is affected by the internal thermal gradient.
23.2.1 Programming
There is a certain programming sequence required to read the temperature sensor. There are two
reading options available:
absolute temperature (single-point calibration)
relative temperature
23.2.1.1 Absolute Temperature

A calibration value at 25°C is stored in OTP for absolute temperature measurements. When the
calibration value from OTP is used, the default GP_ADC offset calibration settings should be used.
● To enable OTP in normal read mode:
○ CLK_AMBA_REG[OTP_ENABLE] = 1
○ OTPC_MODE_REG[OTPC_MODE_MODE] = 2
● To read the calibration value at 25°C:
○ Read ADCOTP_CAL_25C: the content of ADCOTP_CAL_25C is at the address 0x7F87F28 of the OTP
● To disable OTP:
○ OTPC_MODE_REG[OTPC_MODE_MODE] = 0
○ CLK_AMBA_REG[OTP_ENABLE] = 0
● To read back the offset calibration:
○ Offp = GP_ADC_OFFP_REG[GP_ADC_OFFP]
○ Offn = GP_ADC_OFFN_REG[GP_ADC_OFFN]
(Store the data if the original values are need later for the application)
● To overwrite the defaults (the settings during factory calibration) with the ADC offset values
○ GP_ADC_OFFP_REG[GP_ADC_OFFP] = 200
○ GP_ADC_OFFN_REG[GP_ADC_OFFN] = 200
● To enable the temperature sensor:

DA14531
○ GP_ADC_CTRL_REG[DIE_TEMP_EN] = 1
● Wait 25 µs for the temperature sensor to start up
● To set the advised ADC settings:
○ GP_ADC_TRIM_REG[GP_ADC_LDO_LEVEL] = 4
○ GP_ADC_CTRL_REG[GP_ADC_CHOP] = 1
○ GP_ADC_CTRL_REG[GP_ADC_SE] = 1
○ GP_ADC_CTRL_REG[GP_ADC_EN] = 1
○ GP_ADC_CTRL2_REG[GP_ADC_I20U] = 1
○ GP_ADC_SEL_REG[GP_ADC_SEL_P] = 4
○ GP_ADC_CTRL2_REG[GP_ADC_STORE_DEL] = 0
● To set sample time and averaging of the ADC sampling
○ GP_ADC_CTRL2_REG[GP_ADC_SMPL_TIME] = F
○ GP_ADC_CTRL2_REG[GP_ADC_CONV_NRS] = 6
● To perform ADC conversion:
○ GP_ADC_CTRL_REG[GP_ADC_START] = 1
● To wait for the conversion to finish, read the register
○ GP_ADC_RESULT_REG[GP_ADC_VAL]
● To write back the original offset values
○ GP_ADC_OFFP_REG[GP_ADC_OFFP] = Offp
○ GP_ADC_OFFN_REG[GP_ADC_OFFN] = Offn
(Restore the original data if need by the application)
23.2.1.2 Relative Temperature

For relative temperature measurements, the single-point calibration is not needed. The programming
sequence is presented below.
● To enable GP_ADC:
○ GP_ADC_CTRL_REG[DIE_TEMP_EN] = 1
● Wait 25 µs for the temperature sensor to start up
● To set the advised ADC settings:
○ GP_ADC_TRIM_REG[GP_ADC_LDO_LEVEL] = 4
○ GP_ADC_CTRL_REG[GP_ADC_CHOP] = 1
○ GP_ADC_CTRL_REG[GP_ADC_SE] = 1
○ GP_ADC_CTRL_REG[GP_ADC_EN] = 1
○ GP_ADC_CTRL2_REG[GP_ADC_I20U] = 1
○ GP_ADC_SEL_REG[GP_ADC_SEL_P] = 4
○ GP_ADC_CTRL2_REG[GP_ADC_STORE_DEL] = 0
● To set sample time and averaging of the ADC sampling
○ GP_ADC_CTRL2_REG[GP_ADC_SMPL_TIME] = F
○ GP_ADC_CTRL2_REG[GP_ADC_CONV_NRS] = 6
● To perform ADC conversion:
○ GP_ADC_CTRL_REG[GP_ADC_START] = 1
● To wait for the conversion to finish, read the register
○ GP_ADC_RESULT_REG[GP_ADC_VAL]

DA14531
24 Keyboard Controller
24.1 Introduction
The Keyboard controller can be used for debouncing the incoming GPIO signals when implementing
a keyboard scanning engine. It generates an interrupt to the CPU (KEYBR_IRQ).
In parallel, five extra interrupt lines can be triggered by a state change on up to 12 selectable GPIOs
(GPIO_IRQx).
Features
● Monitors the 12 available GPIOs (6 in the WLCSP17 package and 12 in the FCGQFN24
package)
● Generates a keyboard interrupt on key press or key release
● Implements debouncing time from 0 up to 63 ms.
● Supports five separate interrupt generation lines from GPIO toggling
The block diagram of the Keyboard Controller is presented in the Figure 65.
Figure 65: Keyboard Controller Block Diagram
24.2 Architecture
24.2.1 Keyboard Scanner

A HIGH-to-LOW transition on one of the GPIO inputs sets the internal signal "key_hit" to 1, while
KBRD_IRQ_IN_SEL0_REG[KBRD_LEVEL] = 0 and KBRD_IRQ_IN_SELx_REG[KBRD_Pyy_EN] =
1. This signal triggers the state machine of the keyboard interface shown in Figure 66. The debounce
timer is loaded with the value of GPIO_DEBOUNCE_REG[DEB_VALUE]. The timer counts down
every 1 ms. When the timer reaches 0 and the "key_hit" signal is still 1, the timer is loaded with the
value of KBRD_IRQ_IN_SEL0_REG[KEY_REPEAT], generating a repeating sequence of interrupts
every time when the timer reaches 0.
When the key is released (key_hit = 0) and the bit KBRD_REL (key release) is set to 1, a new
debounce sequence is started and a KEYBR_IRQ interrupt is generated after the debounce time.

DA14531
The debounce timer can be disabled with GPIO_DEBOUNCE_REG[DEB_ENABLE_KBRD] = 0. The

key repeat function can be disabled by setting KEY_REPEAT to 0.
The level for generating an interrupt is programmable via bit
KBRD_IRQ_IN_SEL0_REG[KBRD_LEVEL]. The key release function can be disabled by setting bit
KBRD_IRQ_IN_SEL0_REG[KBRD_REL] to 0. The inputs for the keyboard interface can be selected
by setting the corresponding bits KBRD_IRQ_IN_SEL0_REG[KBRD_Pxx_EN] to 1.
The keyboard interrupt service routine can distinguish which input has caused the interrupt by
reading the Px_DATA_REG registers.
RST KEYBR_IRQ = 0
key_hit = 1
IDLE debounce = 0
key _hit = 1
key_hit = 0 and timer = DEBOUNCE
KEYBR_IRQ = 1 timer = 0
KEY_RELEASED KEY_PRESSED timer not 0
key _hit = 1 and
timer = 0 key_hit = 0 and key_hit = 1 and
key_hit = 0 and K EY_ REL = 0 timer = 0
timer = 0
key_hit = 0 KEYB_INT = 0
and KEY_REL = 1
KEY_RELEASING KEY_VALID KEYBR_IRQ
key_hit = 0 and
timer not 0 t im er = DE B OUNCE
KEY_REL = 0 KEYBR_IRQ = 1
key_hit = 0 and key_hit = 1 and
KEY_REPEAT != 0 key_hit = 1 and
KEY_REL = 1 and timer = 0
debounce > 0
key_hit = 0 and KEY_REPEAT timer = KEY_REPEAT
KEY_REL = 1 and
debounce = 0 timer not 0
Figure 66: Keyboard Scanner State Machine
24.2.2 GPIO Interrupt Generator

Five identical GPIO interrupt generators support the generation of up to five interrupts (GPIO0_IRQ
to GPIO4_IRQ). One of the GPIO inputs can be selected to generate an interrupt by programming
the corresponding GPIO_IRQx_IN_SEL_REG register. The input level can be selected by
GPIO_INT_LEVEL_CTRL_REG[INPUT_LEVELx].
A LOW-to-HIGH level transition on one of the GPIO inputs sets the internal signal "key_hit" to 1,
while the bit INPUT_LEVELx = 0. This signal triggers the state machine of the GPIO Interrupt
Generator shown in Figure 67. The debounce timer is loaded with the value of
GPIO_DEBOUNCE_REG[DEB_VALUE]. The timer counts down every 1 ms. If the timer reaches 0
and the "key_hit" signal is still 1, an interrupt will be generated. The debounce timer for each interrupt
can be disabled with GPIO_DEBOUNCE_REG[DEB_ENABLEx].
The interrupt flag will remain set until it is reset by writing to the corresponding bit in the
GPIO_RESET_IRQ_REG register. If the GPIO interrupt is edge sensitive selected with bit
GPIO_INT_LEVEL_CTRL_REG[EDGE_LEVELNx], the state machine will progress to the state
WAIT_FOR_RELEASE when the interrupt is reset. It will progress to the IDLE state only after the
non-active edge is detected.
To detect both signal edges, the edge polarity INPUT_LEVELx must be inverted in the
WAIT_FOR_RELEASE state. This will result in "key_hit" = 0 and will advance the state machine to
the IDLE state, allowing the next inverted edge to be detected.

DA14531
RST GPIOx_IRQ = 0
IDLE key _hit = 1 and DEB_ENABLE_KBRD = 1

key _hit = 0 timer = DEBOUNCE
key_hit = 1
key_hit = 0 and
timer = 0
WAIT_FOR_RELEASE
KEY_PRESSED timer not 0
key_hit = 1 and
GPIOx_IRQ = 0
DEB_ENABLE_KBRD = 0 GPIOx_IRQ = 0
reset_interrupt = 1 and
edge_leveln = 0 key_hit = 1 and
timer = 0
reset_interrupt = 1 and
edge_leveln = 1
KEY_VALID reset_int = 0
GPIOx _IRQ = 1
Figure 67: GPIO Interrupt Generator State Machine
24.3 Programming
To configure and use the Keyboard controller, follow the steps under each subsection.
24.3.1 Keyboard Scanner

1. Enable a keyboard interrupt for the P0_x by setting the
KBRD_IRQ_IN_SEL0_REG[KBRD_Px_EN] bit.
2. Select the logic level by which the interrupt is generated (KBRD_CTRL_REG[KBRD_LEVEL]).
3. Select whether a key release also generates an interrupt (KBRD_CTRL_REG[KBRD_REL]).
4. Select whether repeated interrupts will be generated when a key is held pressed
(KBRD_CTRL_REG[KEY_REPEAT]).
5. Set up the debounce time for each key stroke (GPIO_DEBOUNCE_REG[DEB_VALUE]).
6. Enable the debounce timer (GPIO_DEBOUNCE_REG[DEB_ENABLE_KBRD]).
24.3.2 GPIO Interrupts

1. Enable a GPIO interrupt for the P0_x by setting the
GPIO_IRQx_IN_SEL_REG[KBRD_IRQ0_SEL] bit.
2. Select the logic level by which the interrupt is generated
(GPIO_INT_LEVEL_CTRL_REG[INPUT_LEVELx]).
3. Select whether a key release is needed for an interrupt to be generated after a generated IRQ is
cleared (GPIO_INT_LEVEL_CTRL_REG[EDGE_LEVELNx]).
4. Set up the debounce time for GPIO trigger (GPIO_DEBOUNCE_REG[DEB_VALUE]).
5. Enable the debounce timer for the selected IRQ (GPIO_DEBOUNCE_REG[DEB_ENABLEx]).

DA14531
25 Input/Output Ports
25.1 Introduction
The DA14531 has an I/O pin assignment that can be configured by the SW and is organized into the
Port 0. Pins from P0_0 to P0_5 are available for input/output on the WLCSP17 package, whereas the
full Port 0 (P0_0 to P0_11) is available on the FCGQFN24 package. Figure 68 shows the block
diagram of the IO and its programmability options.
Features
● Six GPIOs on WLCSP17 and 12 GPIOs on FCGQFN24 (including RST, SW_CLK, SWDIO,
XTAL32Km, and XTAL32Kp)
● Fully programmable pin assignment
● Selectable 25 kΩ pull-up and pull-down resistors per pin
● Programmable driving strength outputs
● Fixed assignment for analog pin ADC[3:0]
● Pins can retain their last state when system enters a Sleep mode
Px[y]
Peripheral X input
Px_DATA_REG (input)
VBAT_HIGH
PUPD
25 kΩ Px_MODE_REG
PID
Peripheral X output
Px[y] Peripheral Y output
Px_RESET_OUTPUT_DATA_REG
Px_DATA_REG (output)
Px_SET_OUTPUT_DATA_REG
25 kΩ
PAD_LOW_DRVx
Figure 68: Port P0 with Programmable Pin Assignment and driving strength
25.2 Architecture
25.2.1 Programmable Pin Assignment

The Programmable Pin Assignment (PPA) provides a multiplexing function to the I/O pins of on-chip
peripherals. Any peripheral input or output signal can be freely mapped to any I/O port bit by setting
Pxy_MODE_REG[4-0]:
0x00 to 0x1F: Peripheral IO ID (PID)
Refer to the registers of Px_MODE_REG (x = 00, 01, 02, to 11) for an overview of the available PIDs.
The analog ADC has a fixed pin assignment so that the interference with the digital domain is limited.
The SWD interface (JTAG) is mapped on P0_5 (or P0_1 or P0_10, see chapter 2 Pinout) for the
SWDIO and on P0_2 for the SWCLK.

DA14531
25.2.1.1 Priority
The firmware can assign the same peripheral output to more than one pin. It is the users'
responsibility to make a unique assignment.
If more than one input signal is assigned to a peripheral input, the left most pin in the lowest port pin
number has priority.
25.2.1.2 Direction Control

The port direction is controlled by setting Pxy_MODE_REG[9-8] to:
● 00 = Input, no resistors selected
● 01 = Input, pull-up resistors selected
● 10 = Input, pull-down resistors selected
● 11 = Output, no resistors selected
In output mode and analog mode, the pull-up/down resistors are automatically disabled.
25.2.2 General Purpose Port Registers

The general-purpose ports are selected with PID = 0. The port function is accessible through
registers:
● Px_DATA_REG: Port data input/output register
● Px_SET_OUTPUT_DATA_REG: Port set output register
● Px_RESET_OUTPUT_DATA_REG: Port reset output register
25.2.2.1 Port Data Register

The registers input Px_DATA_REG and output Px_DATA_REG are mapped on the same address.
The data input register (Px_DATA_REG) is a read-only register that returns the current state on each
port pin, even if the output direction is selected, regardless of the programmed PID, unless the
analog function is selected (in this case it reads 0). The Cortex CPU can read this register at any
time, even when the pin is configured as an output.
The data output register (Px_DATA_REG) holds the data to be driven on the output port pins. In this
configuration, writing to this register changes the output value.
25.2.2.2 Port Set Data Output Register

Writing a 1 in the set data output register (Px_SET_DATA_REG) sets the corresponding output pin.
Writing a 0 is ignored.
25.2.2.3 Port Reset Data Output Register

Writing a 1 in the reset data output register (Px_RESET_DATA_REG) resets the corresponding
output pin. Writing a 0 is ignored.
25.2.3 Fixed Assignment Functionality

Certain signals have a fixed mapping on specific general purpose IOs. This assignment is illustrated
in Table 50.
Table 50: Fixed Assignment of Specific Signals

GPIO Reset/SWD (Note 1) QUADRATURE DECODER ADC (Note 3)
(Note 2)
P0_0 RST CH6_A
P0_1 SWDIO (alternative) CH1_A ADC_0

DA14531
GPIO Reset/SWD (Note 1) QUADRATURE DECODER ADC (Note 3)

(Note 2)
P0_2 SWCLK CH1_B ADC_1
P0_3 CH2_A
P0_4 CH2_B
P0_5 SWDIO CH3_A
P0_6 CH3_B ADC_2
P0_7 CH4_A ADC_3
P0_8 CH6_B
P0_9 CH5_A
P0_10 SWDIO (alternative) CH5_B
P0_11 CH4_B
Note 1 The SWD signal mapping is defined by SYS_CTRL_REG[DEBUGGER_ENABLE]. However, these
signals are mapped on the ports by default. The alternative SWD mapping is selected by the
SYS_CTRL_REG[DEBUGGER_ENABLE] bit field. The RST default functionality can be disable by the
HWR_CTRL_REG[DISABLE_HWR] bit.
Note 2 The mapping of the quadrature decoder signals on the respective pins is overruled by the
QDEC_CTRL2_REG[CHx_PORT_SEL] register.
Note 3 The ADC function can be selected by the PID bit field on the respective Px port.
25.2.4 Types of GPIO Pads

There are two different types for the GPIO pads, namely, type A and type B. Their block diagrams
are presented in Figure 69 and Figure 70.
VDD Px_MODE_REG
VBAT_HIGH
Input
Enable* 25k
VSS
VDD VBAT_HIGH
Pullup
Data* Enable*
Output Enable*
PIN
Pulldown
Low Drive* Enable*
VSS
Analog ESD active ESD

protection 25k protection
GND
Digital PADs for GPIO w Schmitt Trigger
Figure 69: Type A GPIO Pad - GPIO with Schmitt Trigger on Input

DA14531
VDD Px_MODE_REG
filtered
100kHz
VSS
VDD
VBAT_HIGH
Input
Enable* 25k
VSS
VDD VBAT_HIGH
Pullup
Data* Enable*
Output Enable*
PIN
Pulldown
Low Drive* Enable*
VSS
Analog ESD active ESD

protection 25k protection
GND
Digital PADs for GPIO w Schmitt Trigger & RC

filter
Figure 70: Type B GPIO Pad - GPIO with Schmitt Trigger and RC Filter on Input
Red signals are latched when the system enters a Sleep mode.
25.2.5 Driving Strength

Pads can be configured regarding their driving capability using PAD_WEAK_CTRL_REG. There are
only 2 levels available for the load that the pad can support, namely normal=3.5mA typical, and
reduced=0.35mA typical.

DA14531
26 General Purpose ADC
26.1 Introduction
The DA14531 is equipped with a high-speed ultra-low-power 10-bit general purpose Analog-to-Digital
Converter (GPADC). It can operate in unipolar (single ended) mode as well as in bipolar (differential)
mode. The ADC has its own voltage regulator (LDO) of 0.9 V, which represents the full-scale
reference voltage. Figure 71 shows the block diagram of the GPADC.
Features
● 10-bit dynamic ADC with 125 ns typical conversion time
● Maximum sampling rate 1 Msample/s
● 128× averaging; conversion time 1 ms, up to 11b ENOB
● Ultra-low power (20 µA typical supply current at 100 ksample/s)
● Four single-ended or two differential external input channels (GPIOs)
● Battery, DCDC outputs, and the internal VDD monitoring channels
● Chopper function
● Offset adjust
● Common-mode input level adjust
● Configurable attenuator: 1×, 2×, 3× and 4×
● Input shifter
GP_ADC_OFFS_SH_EN
General Purpose ADC

GP_ADC_OFFS_CM
GP_ADC_SEL_P
GP_ADC_OFFS_SH_EN
P0 _1 0
P0 _2 1 Shifter
P0 _6 2 (1.8-0.9V -> 0.9-0V) VBAT _L OW
GP_ADC_ATTN
P0 _7 3
Temp Sens or 4
VBAT _H IG H 5
VBAT _L OW 6 120 kOhm 0.9V GP_ADC_EN
VDD 7 GP_ADC_I20U
1 LDO
40 kOhm GP_ADC_MINT
0 Vref=0.9V
20 kOhm ADC_IRQ
GP_ADC_INT
60 kOhm ADC_DMA_REQ
ADC
GP_ADC_SE
GP_ADC_RESULT_REG
16bit
60 kOhm
GP_ADC_SIGN
GP_ADC_START
GP_ADC_EN
GP_ADC_SMPL_TIME
GP_ADC_CHOP
GP_ADC_MUTE
GP_ADC_CONV_NRS
GP_ADC_OFFx
GP_ADC_SEL_N 20 kOhm
40 kOhm
0
GP_ADC_ATTN
P0 _1 120 kOhm
P0 _2 1
P0 _6 2
P0 _7 3
Figure 71: Block Diagram of GPADC

DA14531
26.2 Architecture
The ADC architecture shown in Figure 71 has the following sub-blocks:
● Analog to Digital converter (ADC)
○ ADC analog part internally clocked with 100 MHz
○ ADC logic part clocked with the ADC_CLK which is the 16 MHz system clock (sys_clk)
● 0.9 V LDO for the ADC supply with a high PSRR enabled with
GP_ADC_CTRL_REG[GP_ADC_EN]
● Configurable attenuator with 1×, 2×, 3×, and 4× attenuation controlled by
GP_ADC_CTRL2_REG[GP_ADC_ATTN]
● Input shifter which shifts the battery voltage range from 0.85 V to 1.75 V (with a common mode
adjustment) to the ADC input range from 0 V to 0.9 V controlled by
GP_ADC_CTRL2_REG[GP_ADC_OFFS_SH_EN] and
GP_ADC_CTRL2_REG[GP_ADC_OFFS_CM]
● APB Bus interface clocked with the APB clock. Control and status registers are available through
registers GP_ADC_*
● Maskable Interrupt (ADC_IRQ) and DMA request (ADC_DMA_REQ)
● ADC input channel selector. Up to four GPIO ports, the battery and DCDC output (VBAT_HIGH and
VBAT_LOW ), the internal VDD, and the analog ground level (AVS) can be measured.
26.2.1 Input Channels

Table 51 summarizes the ADC input channels. The GPIO signals at the channels [3:0] can be
monitored both single-ended and differentially. The signals at the 4-7 inputs can be monitored single-
ended or differentially with respect to the GPIOs.
Table 51: ADC Input Channels

Channel Signal Description
3:0 GPIO [P0_1, P0_,2, P0_6, P0_7] General Purpose Inputs
4 Temperature Sensor Temperature Sensor
5 VBAT_HIGH VBAT_HIGH rail
6 VBAT_LOW VBAT_LOW rail
7 VDD VDD rail for the digital power domain
Table 52 summarizes the voltage ranges which can be handled with the single-ended or differential
operation for different attenuation values. The single-ended/differential mode is controlled by the bit
GP_ADC_CTRL_REG[GP_ADC_SE], and the attenuation is handled by the bit
GP_ADC_CTRL2_REG[GP_ADC_ATTN].
Table 52: GPADC External Input Channels and Voltage Range

GP_ADC_ATTN GP_ADC_SE Input Scale Input Limits
0 -0.9 V to +0.9 V -1 V to +1 V
0 (1 ×)
1 0 V to +0.9 V -0.1 V to 1V
0 -1.8 V to +1.8 V -1.9 V to +1.9 V
1 (2 ×)
1 0 V to +1.8 V -0.1 V to 1.9 V
0 -2.7 V to +2.7 V -2.8 V to +2.8 V
2 (3 ×)
1 0 V to +2.7 V -0.1 V to 2.8 V
0 -3.6 V to +3.6 V -3.45 V to +3.45 V
3 (4 ×)
1 0 V to +3.6 V -0.1 V to 3.45 V

DA14531
26.2.2 Operating Modes

The GPADC operation flow diagram is shown in Figure 72.
START
GP_ADC_EN=1
cntr = 4*GP_ADC_EN_DEL
Yes
No cntr--
cntr ==0
ADC_LDO_0V9
start-up
No
GP_ADC_START==1
Wait for initual

conv_nr = 2*GP_ADC_CONV_NRS Star
cntr = 8*GP_ADC_SMPL_TIME
Yes
ADC
No Sample time
cntr ==0 cntr--
ADC Conversion
ADC
Conversion
cntr = GP_ADC_STORE_DEL
Yes No
cntr ==0
No No ADC
ADC_READY cntr ==0 cntr--
Store delay
tmp_result += ADC value
Oversampling
No Mode
conv_nr-- conv_nr==0
Delay = Yes
GP_ADC_INTERVAL*1.024 ms GP_ADC_RESULT=
average(tmp_result)
No
ADC_IRQ_EN=1
Yes DMA Request =1
GP_ADC_INTERVAL==0
Continuous
Mode
No
GP_ADC_CONT==0
Yes
GP_ADC_START=0
STOP
Figure 72: GPADC Operation Flow Diagram

DA14531
26.2.2.1 Enabling the ADC

Enabling/disabling of the ADC is triggered by configuring bit GP_ADC_CTRL_REG[GP_ADC_EN].
When the bit is set to 1, first the LDO is enabled. Then after the delay value set in
GP_ADC_CTRL3_REG[GP_ADC_EN_DEL] (typically 16 µs to account for the LDO settling time),
the ADC will be enabled, and an AD conversion can be started. See Table 53 for recommended
values.
Table 53: ADC_LDO Start-Up Delay

fADC_CLK GP_ADC_EN_DEL τADC_EN_DEL
16 MHz 0x40 16 µs
Formula:
G ADC E DEL = τADC_EN_DEL × fADC_CLK / 4
This value must be rounded up to the nearest integer.
The GPADC is a dynamic ADC and consumes no static power, except for the ADC_LDO which
consumes approximately 20 µA. Therefore, GP_ADC_EN must be set to 0 if the ADC is not used.
26.2.2.2 Manual Mode

An AD conversion can be started by setting GP_ADC_START to 1. While a conversion is active,
GP_ADC_START remains 1. When a conversion is finished, the hardware sets GP_ADC_START to
0 and GP_ADC_INT to 1 (interrupt), and GP_ADC_RESULT_REG contains the valid ADC value.
While a conversion is active, writing 1 to GP_ADC_START will not start a new conversion. SW
should always check that bit GP_ADC_START = 0 before starting a new conversion.
26.2.2.3 Continuous Mode

Setting GP_ADC_CTRL_REG[GP_ADC_CONT] to 1 enables the continuous mode, which
automatically starts a new AD conversion when the current conversion has been completed. The
GP_ADC_START bit is only needed once to trigger the first conversion. As long as the continuous
mode is active, GP_ADC_RESULT_REG always contains the latest ADC value.
To correctly terminate the continuous mode, it is required to disable the GP_ADC_CONT bit first and
then wait until the GP_ADC_START bit is cleared to 0, so the ADC is in a defined state.
NOTE
Before making any changes to the ADC settings, users must disable the continuous mode by setting bit
GP_ADC_CONT to 0 and waiting until bit GP_ADC_START = 0.
At full speed the ADC consumes approximately 50 to 60 µA. If the data rate is less than 100
ksample/s, the current consumption will be in the order of 25 µA.
The time interval between two successive AD conversions is programmable with
GP_ADC_CTRL3_REG[GP_ADC_INTERVAL] in steps of 1.024 ms. If GP_ADC_INTERVAL = 0, the
conversion will restart immediately. If GP_ADC_INTERVAL is not zero, the ADC first synchronizes to
the delay clock before starting the conversion. This can take up to 1 ms.
26.2.3 Conversion Modes
26.2.3.1 AD Conversion
Each AD conversion has three phases:
● Sampling
● Conversion
● Storage

DA14531
The AD conversion starts with the sampling phase. This phase ends after the time set in
GP_ADC_CTRL2_REG[GP_ADC_SMPL_TIME] and triggers the conversion phase. If
GP_ADC_CTRL2_REG[GP_ADC_STORE_DEL] = 0, handshaking is used, that is, the ADC result is
stored when a conversion is finished. Otherwise, a fixed (programmable) delay is used, and the
result is stored regardless of whether the conversion is finished or not.
The total conversion time of an AD conversion depends on various settings. In short, it is as follows.
𝑁𝐶𝑂𝑁𝑉 ∙ (𝑁𝐶𝑌𝐶𝐿_𝑆𝑀𝑃𝐿 + 𝑁𝐶𝑌𝐿𝐶_𝑆𝑇𝑂𝑅𝐸 )
𝑇𝐴𝐷𝐶 = (5)
𝑓𝐴𝐷𝐶_𝐶𝐿𝐾
Where
● NCONV = the number of conversions. This is related to the value programmed in
GP_ADC_CTRL2_REG[GP_ADC_CONV_NRS], following 2GP_ADC_CONV_NRS. When
GP_ADC_CTRL_REG[GP_ADC_CHOP] is set, the minimum value for NCONV is always 2.
● NCYLC_SMPL = the number of ADC_CLK cycles used for sampling, which is 8 ×
GP_ADC_CTRL2_REG[GP_ADC_SMPL_TIME].
● NCYCL_STORE = the number of ADC_CLK cycles until the result is stored. When
GP_ADC_CTRL2_REG[GP_ADC_STORE_DEL] = 0, handshaking is used. With handshaking,
the number of ADC_CLK cycles is typically three. This value may spread from sample to sample
and over temperature, otherwise the number of ADC_CLK cycles is
GP_ADC_CTRL2_REG[GP_ADC_STORE_DEL] + 1.
Sampling Phase
The sampling time can be programmed via GP_ADC_CTRL2_REG[GP_ADC_SMPL_TIME] and
depends on the sampling time constant in combination with the desired sampling accuracy. This
sampling time constant, τADC_SMPL (Table 54), then depends on the output impedance of the source,
the internal resistive dividers, and the internal sampling capacitor. And the number of required time
constants is given by the natural logarithm of the desired accuracy, that is, ln(2^NBIT). For NBIT =
10-bit accuracy, 7 time constants are required.
Table 54: ADC Sampling Time Constant (τADC_SMPL)

ADC Input τADC_SMPL
ROUT × 0.5 p (Differential Input)
GPADC0, GPADC1 (GP_ADC_ATTN = 0)
ROUT × 1 p (Single-Ended Input)
(ROUT + 120 kΩ) × 0.5 p (Differential Input)
GPADC0, GPADC1 (GP_ADC_ATTN = 1)
(ROUT + 120 kΩ) × 1 p (Single-Ended Input)
Formula:
GP_ADC_SMPL_TIME = ln(2^NBIT) × τADC_SMPL × fADC_CLK / 8
This value must be rounded up to the nearest integer.
Conversion and Storage Phase

One AD conversion typically takes around 125 ns with a 100 MHz clock. The result can be
stored either by handshaking or after a fixed number of cycles (programmable).
● Handshake mode (GP_ADC_STORE_DEL = 0):
In handshake mode the conversion result is available in GP_ADC_RESULT_REG after two sampling
ADC_CLK cycles plus two conversion ADC_CLK cycles plus two ADC_CLK cycles for
synchronization.
● Fixed delay mode (GP_ADC_STORE_DEL > 0):
In fixed delay mode the conversion result is available in GP_ADC_RESULT_REG after the
programmed storage delay, regardless of whether the conversion is ready or not. Note that when the

DA14531
delay is too short (that is, the conversion is not finished in the allocated time), the old (previous) ADC
result is stored.
26.2.3.2 Averaging
In order to reduce noise and improve performance, multiple samples can be averaged out (assuming
the time average of noise equals zero). This is handled by HW and can be controlled by setting
GP_ADC_CTRL2_REG[GP_ADC_CONV_NRS] to a non-zero value. The actual number of the
consecutive samples taken is by 2GP_ADC_CONV_NRS.
Because the internal noise also acts as a form of dither, the actual accuracy can be improved.
Therefore, the ADC result is not truncated to 10-bit but stored as 16-bit left aligned, and truncation is
left for the user. The expected Effective Number of Bits (ENOB) is shown in Table 55.
Table 55: ENOB in Oversampling Mode

GP_ADC_CONV_NRS ENOB (Left Aligned) in GP_ADC_RESULT_REG
0 >9
1 >9
2 >9
3 > 10
4 > 10
5 > 10
6 > 11
7 > 11
26.2.3.3 Chopper Mode

Inherently, the ADC has a DC offset (EOFS). When GP_ADC_CTRL_REG[GP_ADC_CHOP] is set
to 1, the hardware triggers two consecutive AD conversions and flips the sign of the offset in-
between. Summing the two samples effectively cancels out the inherent ADC offset. This method
also smooths other non-ideal effects and is recommended for DC and the slowly changing signals.
When combined with averaging, every other AD conversion is taken with opposite sign. Without
averaging two AD conversions are always triggered.
Note that a DC offset causes saturation effects at zero scale or full scale. When chopping is used
without offset calibration, non-linear behavior is introduced towards zero scale and full scale.
26.2.4 Additional Settings

The hardware also supports pre-ADC attenuation via GP_ADC_CTRL2_REG[GP_ADC_ATTN]:
● Setting 0 disables the attenuator
● Setting 1 scales the input range by a factor of two
● Setting 2 scales the input range by a factor of three
● Setting 3 scales the input range by a factor of four
With bit GP_ADC_CTRL_REG[GP_ADC_MUTE] = 1, the input is connected to 0.5 × ADC reference.
So, the ideal ADC result should be 511.5. Any deviation from this is the ADC offset.
With bit GP_ADC_CTRL_REG[GP_ADC_SIGN] = 1, the sign of the offset is inverted. When chopper
is used, the hardware alternates GP_ADC_SIGN = 0 and 1. This bit is typically only used for the
offset calibration routine described in section 26.2.6 and has no specific use to the end user.

DA14531
26.2.5 Non-Ideal Effects

Besides Differential Non-Linearity (DNL) and Integral Non-Linearity (INL), each ADC has a gain error
(linear) and an offset error (linear). The gain error (EG) of the GPADC affects the effective input
range. The offset error (EOFS) causes the effective input scale to become non-centered. The offset
error can be reduced by chopping and/or by offset calibration.
The ADC result will also include some noise. If the input signal itself is noise free (inductive effects
included), the average noise level will be ±1 LSB. Reducing noise effects can be done by taking
more samples and calculating the average value. This can be done by programming
GP_ADC_CTRL2_REG[GP_ADC_CONV_NRS] to a non-zero value.
ith a “perfect” input signal (for example, if a filter capacitor is placed close to the input pin), most of
the noise comes from the low-power voltage regulator (LDO) of the ADC. Since the DA14531 is
targeted for ultra-compact applications, there is no pin available to add a capacitor at this voltage
regulator output.
The dynamic current of the ADC causes extra noise at the regulator output. This noise can be
reduced by setting bits GP_ADC_CTRL2_REG[GP_ADC_I20U]. Bit GP_ADC_I20U enables a
constant 20 µA load current at the regulator output so that the current will not drop to zero. This,
obviously, increases power consumption by 20 µA.
26.2.6 Offset Calibration

A relative high offset error (EOFS, up to 30 mV, so approximately 30 LSB) is caused by a very small
dynamic comparator. This offset error can be cancelled with the chopping function, but it still causes
unwanted saturation effects at zero scale or full scale. With GP_ADC_OFFP_REG and
GP_ADC_OFFN_REG, the offset error can be compensated in the ADC network itself. To calibrate
the ADC, follow the steps in Table 56. In this routine, 0x200 is the target mid-scale of the ADC.
Table 56: GPADC Calibration Procedure for Single-Ended and Differential Modes
Step Single-Ended Mode (GP_ADC_SE = 1) Differential Mode (GP_ADC_SE = 0)
1 Set GP_ADC_OFFP = GP_ADC_OFFN = 0x200; Set GP_ADC_OFFP = GP_ADC_OFFN = 0x200;
GP_ADC_MUTE = 0x1; GP_ADC_SIGN = 0x0. GP_ADC_MUTE = 0x1; GP_ADC_SIGN = 0x0.
2 Start conversion. Start conversion.
3 adc_off_p = GP_ADC_RESULT - 0x200 adc_off_p = GP_ADC_RESULT - 0x200
4 Set GP_ADC_SIGN = 0x1. Set GP_ADC_SIGN = 0x1.
5 Start conversion. Start conversion.
6 adc_off_n = GP_ADC_RESULT - 0x200 adc_off_n = GP_ADC_RESULT - 0x200
7 GP_ADC_OFFP = 0x200 - 2 × adc off p GP_ADC_OFFP = 0x200 - adc_off_p
GP_ADC_OFFN = 0x200 - 2 × adc off n GP_ADC_OFFN = 0x200 - adc_off_n
In order to increase the accuracy, it is recommended to set the

GP_ADC_CTRL2_REG[GP_ADC_SMPL_TIME] = 2 or 3 and
GP_ADC_CTRL2_REG[GP_ADC_CONV_NRS] = 3 or 4 prior to this routine.
It is recommended to implement the above calibration routine during the initialization phase of
DA14531. To verify the calibration results, check whether the GP_ADC_RESULT value is close to
0x200 while bit GP_ADC_CTRL_REG[GP_ADC_MUTE] = 1.
26.2.7 Zero-Scale Adjustment

The GP_ADC_OFFP and GP_ADC_OFFN registers can also be used to set the zero-scale or full-
scale input level at a certain target value. For instance, they can be used to calibrate
GP_ADC_RESULT to 0x000 at an input voltage of exactly 0.0 V, or to calibrate the zero scale of a
sensor.

DA14531
26.2.8 Common Mode Adjustment

The common mode level of the differential signal must be 0.45 V = Full Scale/2 (or 1.35 V with
GP_ADC_ATTN = 2, that is, 3× attenuation). If the common mode input level of 0.45 V cannot be
achieved, the common mode level of the GPADC can be adjusted via GP_ADC_OFFP_REG and
GP_ADC_OFFN_REG according to Table 57. The GPADC can tolerate a common mode margin of
up to 50 mV.
Table 57: Common Mode Adjustment

CM Voltage (Vccm) GP_ADC_OFFP = GP_ADC_OFFN
0.225 V 0x300
0.450 V 0x200
0.675 V 0x100
Any other common mode levels between 0.0 V and 0.9 V can be calculated from Table 57. Offset
calibration can be combined with common mode adjustment by replacing the 0x200 value in the
offset calibration routine with the value required to get the appropriate common mode level.
26.2.9 Input Impedance, Inductance, and Input Settling

The GPADC has no input buffer stage. During the sampling phase, a capacitor of 0.5 pF in
differential mode or 1 pF in single-ended mode is switched to the input line(s). The pre-charge of this
capacitor is at midscale level, so the input impedance is infinite.
During the sampling phase, a certain settling time is required. A 10-bit accuracy requires at least
seven time constants τADC_SMPL, determined by the output impedance of the input signal source, the
internal resistive dividers, and the 0.5 pF or 1 pF sampling capacitor. See Table 54.
The inductance from the signal source to the ADC input pin must be very small. Otherwise filter
capacitors are required from the input pins to ground (single-ended mode) or from pin to pin
(differential mode).
26.3 Programming
To program and use the GPADC, follow the simple sequence of steps below:
1. Enable the GPADC by setting the GP_ADC_CTRL_REG[GP_ADC_EN] bit.
2. Set up the GPIO input (P0_x_MODE_REG[PID] = 15).
3. Select the input channel (GP_ADC_SEL_REG).
4. Select the sampling mode (differential or single ended) by writing the
GP_ADC_CTRL_REG[GP_ADC_SE] bit.
5. Select between the manual mode and the continuous mode of sampling
(GP_ADC_CTRL_REG[GP_ADC_CONT].
6. Set up extra options (see GP_ADC_CTRLx_REG description)
7. Start the conversion by setting GP_ADC_CTRL_REG[GP_ADC_START] bit.
8. Wait for GP_ADC_CTRL_REG[GP_ADC_START] to become 0 or interrupt being triggered (when
used).
9. Clear the ADC interrupt by writing any value to GP_ADC_CLEAR_INT_REG.
10. Get the ADC result from the GP_ADC_RESULT_REG.

DA14531
27 Real Time Clock (RTC)
27.1 Introduction
The DA14531 is equipped with a Real Time Clock (RTC) which provides the complete clock and
calendar information with automatic time units adjustment and easy configuration.
Features
● Complete time of day clock: 12/24 hour, hours, minutes, seconds, and hundredths of a second
● Calendar function: day of week, date of month, month, year, century, leap year compensation,
and year 2000 compliant
● Alarm function: month, date, hour, minute, second, and hundredths of a second
● Event interrupt on any calendar or time unit
● Available during sleep if the power domain PD_TIM is kept alive
● Granularity of 10 ms (RTC_CLK)
● Provides 22 LSB to Timer 1 upon a capture trigger
Counters
APB32 Bus
1/100th
Register File
Timer 1
second 22
time_o
minute
Synchronizer
hour
date day
month
RTC_CLK (10ms)
AON_PCLK
year
RTC_IRQn
century
Figure 73: Real Time Clock Block Diagram
27.2 Architecture
The architecture of the RTC is depicted in Figure 73.
The RTC supports a year range from 1900 to 2999 as well as full month, date, minute, second, and
hundredth of second ranges. It also supports hour ranges of 0 to 23 (24-hour format) or 1 to 12 with
a.m./p.m. flag (12-hour format).
Alarms can be generated in two ways, as a one-time alarm or as a recurring alarm. In addition to
alarms, the RTC can detect when a particular event occurs. Each field of the calendar and time
counter can generate an event when it rolls over. For example, an event can be generated every new
month, new week, new day, new half day (12-hour mode), new minute, or new second. Both alarms

DA14531
and events can generate an interrupt. All the interrupts can be set, enabled, disabled, or masked at
any time.
The LSB (22) of the port showing a full of 32-bit information on the current time is latched by Timer 1
(TIMER1_CAPCNT1/2_VALUE_REG) if instructed by Timer 1 configuration. This allows for storing
an RTC based snapshot upon an event on a GPIO.
27.3 Programming
To configure the RTC, follow the simple sequence of steps below:
1. Configure the 100 Hz RTC granularity if needed:
a. Based on the selected LP clock (for example, 32768 kHz), set the
CLK_RTCDIV_REG[RTC_DIV_INT] = 327 (= 0x147).
This values should be equal to the integer divisor part of the formula
FLP_CLK/100 = 327.680.
b. Based on the selected LP clock (for example, 32768 kHz), set the
CLK_RTCDIV_REG[RTC_DIV_FRAC] = 680 (= 0x2A8).
This values should be equal to the fractional divisor part of the formula
FLP_CLK/100 = 327.680.
c. To achieve a better accuracy of the divisor, configure the denominator for the fractional
division accordingly (CLK_RTCDIV_REG[RTC_DIV_DENOM]).
d. Enable the 100 Hz RTC granularity by setting the CLK_RTCDIV_REG [RTC_DIV_ENABLE]
bit.
2. Enable the time functionality by clearing the RTC_CONTROL_REG[RTC_TIME_DISABLE].
3. Enable the calendar functionality by clearing the RTC_CONTROL_REG[RTC_CAL_DISABLE].
4. Choose between 12-hour or 24-hour mode (RTC_HOUR_MODE_REG[RTC_HMS]).
5. Configure the time (RTC_TIME_REG).
6. Configure the date (RTC_CALENDAR_REG).
7. Set up a time alarm if needed (RTC_ALARM_ENABLE_REG).
8. Set up a calendar alarm if needed (RTC_CALENDAR_ALARM_REG).
9. Enable the configured alarms (RTC_ALARM_ENABLE_REG[RTC_ALARM_xxxx_EN]).
10. Configure the interrupt generation when an alarm happens (RTC_INTERRUPT_ENABLE_REG).
Disable the interrupt generation with RTC_INTERRUPT_DISABLE_REG.
11. Configure the event flag generation when an alarm happens (RTC_EVENT_FLAGS_REG).
12. Define whether a SW reset resets the RTC (RTC_KEEP_RTC_REG[RTC_KEEP]).

DA14531
28 Power
As discussed in section 4.2, the integrated power management unit (PMU) comprises the DCDC
converter and various LDOs, the VDD Clamp, and the POR circuitry. The details of these blocks are
discussed in the following sections.
28.1 DCDC Converter

The DA14531 can be configured in three configurations: buck, boost, and DCDC bypass. The
integrated part of the DCDC is the same for all three configurations, that is, the black building blocks
in Figure 74 and Figure 75. The buck configuration and the boost configuration are configured on the
PCB, distinguished with the red external components in Figure 74 and Figure 75, respectively. In the
bypass configuration the VBAT_HIGH and VBAT_LOW rails are connected together, so the DCDC is
bypassed.
VBAT_HIGH
Battery
CBAT
FSM Controller
LEXT
LX VBAT_LOW
VREF
CEXT
VSSA_DCDC
Figure 74: DCDC Block Diagram - Buck Configuration
VBAT_HIGH
CEXT
FSM Controller
LEXT
LX VBAT_LOW
Battery VREF
CBAT
VSSA_DCDC
Figure 75: DCDC Block Diagram - Boost Configuration
● In buck configuration the battery is connected to VBAT_HIGH, and DCDC supplies power to VBAT_LOW
rail
● In boost configuration the battery is connected to VBAT_LOW , and DCDC supplies power to
VBAT_HIGH rail
● In DCDC bypass configuration VBAT_HIGH is connected to VBAT_LOW and the battery is connected to
both rails.

DA14531
The DCDC level can be programmed by POWER_LEVEL_REG[DCDC_LEVEL] and a fine trimming

is available by POWER_LEVEL_REG[DCDC_TRIM].
When the system is allowed to go to sleep, the HW FSM is activated and the DCDC controller is
automatically turned off. Upon a wakeup, the DCDC will be enabled by programming
DCDC_CTRL_REG[DCDC_ENABLE]. If DCDC_ENABLE is kept set before the system goes to
sleep, the DCDC will be started by the HW FSM while waking up. If DCDC_ENABLE is reset before
the system goes to sleep, the DCDC can only be started by SW setting this bit after wakeup.
or Buck configuration, a typical DCDC efficiency at 25°C as a function of the load current for
different battery voltages (VBAT = VBAT_HIGH) is shown in Figure 76.
Figure 76: DCDC Efficiency in Buck Configuration
For Boost configuration, a typical DCDC efficiency at 25°C as a function of the load current for
different battery voltages (VBAT = VBAT_LOW ) is shown in Figure 77.

DA14531
Figure 77: DCDC Efficiency in Boost Configuration
28.2 LDOs
Several LDOs are used in the DA14531 to provide a stable power supply to the rails and the building
blocks.
● VDD_Clamp generates a trimmable ~0.75 V VDD supply voltage for the AON (always on) DCORE
power domain from VBAT_HIGH or VBAT_LOW when the system is in the hibernation mode
● LDO_LOW provides power to the VBAT_LOW rail in the buck configuration with a typical output
voltage of 1.1 V. This LDO is used during start-up and can also be used after start-up.
Alternatively, it can be disabled and the VBAT_LOW rail can be supplied by the DCDC converter.
The LDO has a low power setting which is used to maintain the VBAT_LOW rail during sleep mode.
See section 4.2.3 for more details.
● LDO_CORE supplies the internal VDD from VBAT_LOW . In the active mode it generates 0.9 V and in
the sleep mode 0.75 V
● LDOs for the RF and the analog building blocks generate 0.9 V when the particular blocks are
active. When the blocks are switched off, the LDOs are disabled.
28.3 POR Circuit

The POR_LOW circuit issues a POR when the VBAT_LOW voltage is below the threshold voltage VIL
for more than 50 µs. The POR is cleared when the battery voltage is above VIH for at least 25 µs. The
threshold levels of the POR circuit are summarized in section 3.12.
The POR_HIGH circuit issues a POR when the VBAT_HIGH voltage is below the VIL for more than
50 µs. The POR is cleared when the battery voltage is above VIH for at least 25 µs. The threshold
levels of the POR circuit are summarized in section 3.12.

DA14531
29 BLE Core
The Bluetooth Low Energy (BLE) core used in the DA14531 is a qualified Bluetooth 5.1 baseband
controller compatible with the BLE specification and it is in charge of packet encoding/decoding and
frame scheduling.
The block diagram of BLE core is presented in Figure 78.
Features
● Compliant with Bluetooth Core Specification, v5.1, Bluetooth SIG
○ Dual topology
○ Low duty cycle advertising
○ L2CAP connection-oriented channels
● All device classes support (Broadcaster, Central, Observer, and Peripheral)
● All packet types (Advertising, Data, and Control)
● Dedicated Encryption (AES/CCM)
● Bit stream processing (CRC and Whitening)
● FDMA/TDMA/events formatting and synchronization
● Frequency hopping calculation
● Operating clock 16 MHz or 8 MHz
● Low power modes supporting 32.0 kHz, 32.768 kHz, or 15 kHz
● Supports powerdown of the baseband during the protocol’s idle periods
BLE Timer AHB AHB

Slave Master
Radio BLE Core
Test MUXes Registers Bus Interface
Control
BLE_EM
Radio Frequency Interrupt AES
Memory Controller _BASE_
Controller Selection Generator CCM
REG
Data
Packet Event White List Event
Whitening CRC
Controller Controller Search Scheduler
Figure 78: BLE Core Block Diagram
29.1 Architecture
29.1.1 Exchange Memory

The BLE Core requires access to a memory space named "Exchange Memory" to store control
structures and frame buffers. The access to Exchange Memory is performed via the AHB Master
interface. The base address of the Exchange Memory is programmable by means of the
BLE_EM_BASE register.

DA14531
29.2 Programming
29.2.1 Wake-Up IRQ

Once the BLE core switches to "BLE Deep Sleep mode", the only way to correctly exit from this state
is by generating initially the BLE_WAKEUP_LP_IRQ and consecutively the BLE_SLP_IRQ. This
sequence must be followed regardless of the cause of the termination of the "BLE Deep Sleep
mode", that is, regardless of whether the BLE Timer has expired or BLE Timer has been stopped due
to the assertion of BLE_WAKEUP_REQ.
The assertion and de-assertion of BLE_WAKEUP_LP_IRQ is fully controlled via the
BLE_ENBPRESET_REG bit fields. A detailed description is as follows:
● TWIRQ_SET: it defines the number of "ble_lp_clk" cycles before the expiration of the BLE Timer
when the BLE_WAKEUP_LP_IRQ must be asserted. It is recommended to select a TWIRQ_SET
value larger than the amount of time that is required to finish trimming the XTAL 32 MHz (refer to
XTAL32M_TRIM_READY) plus the execution time of the IRQ Handler. If the programmed value
of TWIRQ_SET is less than the minimum recommended value, the system will wake up but the
actual BLE sleep duration (refer to BLE_DEEPSLSTAT_REG) will be larger than the
programmed sleep duration (refer to BLE_DEEPSLWKUP_REG)
● TWIRQ_RESET: it defines the number of "ble_lp_clk" cycles before the expiration of the sleep
period when the BLE_WAKEUP_LP_IRQ will be de-asserted. It is recommended to always set its
value to "1"
● TWEXT: it determines the high period of BLE_WAKEUP_LP_IRQ, if an external wake-up event
(refer to GP_CONTROL_REG[BLE_WAKEUP_REQ]) occurs. Its minimum value is
"TWIRQ_RESET + X", where X is the number of "ble_lp_clk" clock cycles that
BLE_WAKEUP_LP_IRQ will be held high. The recommended value is "TWIRQ_RESET + 1".
Note that as soon as GP_CONTROL_REG[BLE_WAKEUP_REQ] is set to "1", the
BLE_WAKEUP_LP_IRQ will be asserted
● Minimum BLE Sleep Duration: The minimum value of
BLE_DEEPSLWKUP_REG[DEEPSLTIME] bit, measured in "ble_lp_clk" cycles, is the higher
value between (a) "TWIRQ_SET + 1" and (b) the SW execution time from setting
BLE_DEEPSLCNTL_REG[DEEP_SLEEP_ON] up to preparing CPU to accept the
BLE_WAKEUP_LP_IRQ (for example, to call the Cortex instruction WFI). If the programmed
DEEPSLTIME is less than the minimum value of BLE_DEEPSLWKUP_REG[DEEPSLTIME], the
BLE_WAKEUP_LP_IRQ Handler may execute sooner than the call of the Cortex WFI instruction
in the example and cause SW instability
29.2.2 Switch from BLE Active Mode to BLE Deep Sleep Mode
Software can set the BLE core into the "BLE Deep Sleep mode" by first programming the timing of
BLE_WAKEUP_LP_IRQ generation, then programming the desired sleep duration at
BLE_DEEPSLWKUP_REG, and finally set the register bit
BLE_DEEPSLCNTL_REG[DEEP_SLEEP_ON].
During the "BLE Deep Sleep mode", the BLE Core will switch to the "ble_lp_clk" (15kHz, 32.0 kHz, or
32. 68 k ) in order to maintain its internal 625 μs timing reference. SW must poll the state of
BLE_CNTL2_REG[RADIO_PWRDN_ALLOW] to detect the completion of this mode transition. Once
the "ble_lp_clk" is used for base time reference, SW must disable the BLE clocks ("ble_master1_clk",
"ble_master2_clk", and "ble_crypt_clk") by setting the CLK_RADIO_REG[BLE_ENABLE] register bit
to "0".
Finally, SW can optionally power down the Radio Subsystem by using the
PMU_CTRL_REG[RADIO_SLEEP] and the Peripheral and System power domains as well.
Figure 79 presents the waveforms when the BLE Deep Sleep mode is entered. In this case, as soon
as the SW detects that RADIO_PWRDOWN_ALLOW is "1", it sets the
PMU_CTRL_REG[RADIO_SLEEP] to power down the Radio Subsystem. In Figure 79, Figure 80,
Figure 81, Figure 82, and Figure 83, the corresponding BLE Core signals are marked with red while

DA14531
Radio Subsystem is in power-down state and they remain red-marked during the period when
RADIO_SLEEP is set.
Figure 79: Entering BLE Deep Sleep mode
29.2.3 Switch from BLE Deep Sleep Mode to BLE Active Mode
There are two possibilities for the BLE Core to terminate the BLE Deep Sleep mode:
● Termination at the end of a predetermined time
● Termination on SW wake-up request due to an external event
29.2.3.1 Switching at an Anchor Point

Figure 82 shows a typical BLE deep sleep phase that is terminated at a predetermined time. After a
configurable time before the scheduled wake-up time (configured via BLE_ENBPRESET_REG
register bit fields), the BLE Timer asserts the BLE_WAKEUP_LP_IRQ in order to wake up the CPU
(powering up the System Power Domain). The BLE_WAKEUP_LP_IRQ Interrupt Handler will
prepare the code environment and the XTAL32M oscillator stabilization (refer to
SYS_STAT_REG[XTAL32_SETTLED]) and will decide when the BLE Core is ready to exit the BLE
Deep Sleep mode.
Once the SW decides that the BLE Core can wake up, it must enable the BLE clocks (via
CLK_RADIO_REG[BLE_ENABLE]) and power up the Radio Power Domain (refer to
PMU_CTRL_REG[RADIO_SLEEP] and SYS_STAT_REG[RAD_IS_UP]).
After the sleep period is expired (as specified in BLE_DEEPSLWKUP_REG[DEEPSLTIME]), the BLE
Timer will not exit the BLE Deep Sleep mode until it detects that the BLE Core is powered up. That
means, if the SW requires more time to power up the BLE Core, the final sleep duration (provided by
BLE_DEEPSLSTAT_REG) will be longer than the preprogrammed value.
When the BLE Timer is expired, BLE clocks are enabled, and the BLE Core (Radio Subsystem) is
powered up, the BLE Core exists the "BLE Core Deep Sleep mode" and asserts the BLE_SLP_IRQ.

DA14531
Figure 80: Exit BLE Deep Sleep Mode at Predetermined Time (Zoom In)
Figure 81: Exit BLE Deep Sleep Mode after Predetermined Time (Zoom In)
Figure 82: Exit BLE Deep Sleep Mode at Predetermined Time (Zoom Out)

DA14531
29.2.3.2 Switching Due to an External Event

Figure 83 shows a wakeup from a BLE deep sleep period forced by the assertion of register bit
GP_CONTROL_REG[BLE_WAKEUP_REQ].
Assume that the system is in Extended Sleep state with all power domains switched off and both the
wake-up timer and wake-up controller programmed appropriately. Then assume that an event is
detected at one of the GPIOs, causing the System Power Domain to wake up due to
WKUP_QUADDEC_IRQ. In that case, the SW will decide to wake up the BLE core, then it sets the
GP_CONTROL_REG[BLE_WAKEUP_REQ] to 1 in order to force the wake-up sequence.
In Figure 83 the BLE_WAKEUP_REQ is raised by the SW as soon as possible, causing
BLE_WAKEUP_LP_IRQ Handler to be executed as soon as possible. It is also possible to raise
BLE_WAKEUP_REQ after the detection of XTAL32_TRIM_READY, causing both
BLE_WAKEUP_LP_IRQ and BLE_SLP_IRQ Handlers to be executed sequentially. The decision
depends on the SW structure and the application.
Figure 83: Exit BLE Deep Sleep Mode Due to External Event
As soon as the bit field BLE_WAKEUP_REQ is set to 1, the BLE_WAKEUP_LP_IRQ will be

asserted. In that case, the high period of BLE_WAKEUP_LP_IRQ is controlled via TWEXT. The
recommended value of TWEXT is "TWIRQ_RESET + 1", meaning that BLE_WAKEUP_LP_IRQ will
remain high for one "ble_lp_clk" period.
As long as the BLE_WAKEUP_REQ is high, entering the sleep mode is prohibited. Please note that
BLE_WAKEUP_REQ event can be disabled by setting BLE_DEEPSLCNTL_REG[EXTWKUPDSB].

DA14531
30 Radio
30.1 Introduction
The Radio Transceiver implements the RF part of the BLE protocol. Together with the Bluetooth 5.1
PHY layer, it provides up to 93 dB RF link budget for a reliable wireless communication. All RF
blocks are supplied by on-chip low-drop out-regulators (LDOs). The bias scheme is programmable
per block and optimized for minimum power consumption. The radio block diagram is given in Figure
84. It comprises the Receiver, Transmitter, Synthesizer, Rx/Tx combiner block, and Biasing LDOs.
Features
● Single ended RFIO interface, 50 Ω matched
● Alignment free operation
● -90 dBm receiver sensitivity
● Configurable transmit output power from -19.5 dBm up to +2.5 dBm
● Ultra-low power consumption
● Fast frequency tuning minimizes overhead
I-ADC
LNA
IF
DEM
Filter
Q-ADC
RFIO LLH
SYNTH
32 MHz
PA MOD
XO
Figure 84: Bluetooth Radio Block Diagram
30.2 Architecture
30.2.1 Receiver
The RX frontend consists of a selective matching network, a low noise amplifier (LNA), and an image
rejection down conversion mixer. The intermediate frequency (IF) part of the receiver comprises a
filter with a programmable gain. The LNA and IF Filter gains are controlled by the Automatic Gain
Control (AGC). This provides the necessary signal conditioning prior to digitalization. The digital
demodulator block (DEM) provides a synchronous bit stream.

DA14531
30.2.2 Synthesizer
The RF Synthesizer generates the quadrature LO signal for the mixer, but also generates the
modulated TX output signal. The Digitally Controlled Oscillator (DCO) runs at twice the required
frequency and a dedicated divide-by-2 circuit generates the 2.4 GHz signals in the required phase
relations. The reference frequency is the 32 MHz crystal clock. The modulation of the TX frequency
is performed by 2-point modulation.
30.2.3 Transmitter
The RF power amplifier (RFPA) is an extremely efficient Class-D structure, providing typically the
power ranging from -1 .5 dBm to +2.5 dBm to the antenna. It is fed by the DC ’s divide-by-2 circuit
and delivers its TX power to the antenna pin through the combined RX/TX matching circuit.
30.2.4 RFIO
The RX/TX combiner block is a unique feature of the DA14531. It makes sure that the received
power is applied to the LNA with minimum losses towards the RFPA. In TX mode, the LNA poses a
minimal load for the RFPA and its input pins are protected from the RFPA. In both modes, the single
ended RFIO port is matched to a resistor of 50 Ω in order to provide the simplest possible interfacing
to the antenna on the printed circuit board.
30.2.5 Biasing
All RF blocks are supplied by on-chip LDOs. The bias scheme is programmable and optimized for
minimum power consumption.
30.2.6 RF Monitoring
The Radio is equipped with a monitoring block whose responsibility is to acquire the data provided by
the RF Unit and other analog resources, to combine them in words of 32 bits (when necessary), and
to store them in system’s memory. Data can be the output of the Demodulator (I and Q) or be
provided by the GPADC. With the monitoring block, production tests of the corresponding block can
be achieved.

DA14531
31 Registers
This section contains a detailed view of the DA14531 registers. It is organized as follows: an
overview table is presented initially, which depicts all register names, addresses, and descriptions. A
detailed bit level description of each register follows.
The register file of the Arm Cortex-M0+ can be found in the following documents available on the
website:
Devices Generic User Guide:
https://developer.arm.com/docs/238818831/10/getting-started-with-cortex-m0-cortex-m0-cortex-m3-
and-cortex-m4-full-licensee-bundles
Technical Reference Manual:
https://developer.arm.com/docs/ddi0484/c/preface
These documents contain the register descriptions for the Nested Vectored Interrupt Controller
(NVIC), the System Control Block (SCB), and the System Timer (SysTick).
31.1 Analog Miscellaneous Registers
Table 58: Register map anamisc2632_bif_00

Address Register Description
0x50001600 CLK_REF_SEL_REG Select clock for oscillator calibration
0x50001602 CLK_REF_CNT_REG Count value for oscillator calibration
0x50001604 CLK_REF_VAL_L_RE XTAL32M reference cycles, lower 16 bits
G
0x50001606 CLK_REF_VAL_H_RE XTAL32M reference cycles, higher 16 bits
G
Table 59: CLK_REF_SEL_REG (0x50001600)

Bit Mode Symbol Description Reset
3 R/W EXT_CNT_EN_SEL 0 : Enable XTAL_CNT counter by the REF_CLK 0x0
selected by REF_CLK_SEL.
1 : Enable XTAL_CNT counter from an external
input.
2 R/W REF_CAL_START Writing a '1' starts a calibration of the clock 0x0
selected by
CLK_REF_SEL_REG[REF_CLK_SEL]. This bit is
cleared when calibration is finished, and
CLK_REF_VAL is ready.
1:0 R/W REF_CLK_SEL Select clock input for calibration: 0x0
0x0 : RC32K
0x1 : RC32M
0x2 : XTAL32K
0x3 : RCX

DA14531
Table 60: CLK_REF_CNT_REG (0x50001602)

15:0 R/W REF_CNT_VAL Indicates the calibration time, with a decrement 0x0
counter to 1.
Table 61: CLK_REF_VAL_L_REG (0x50001604)

15:0 R XTAL_CNT_VAL Returns the number of DIVN clock cycles counted 0x0
during the calibration time, defined with
REF_CNT_VAL
Table 62: CLK_REF_VAL_H_REG (0x50001606)

15:0 R XTAL_CNT_VAL Returns the number of DIVN clock cycles counted 0x0
during the calibration time, defined with
REF_CNT_VAL

DA14531
31.2 BLE Core Registers
Table 63: Register map BLE

0x40000000 BLE_RWBLECNTL_R BLE Control register
EG
0x40000004 BLE_VERSION_REG Version register
0x40000008 BLE_RWBLECONF_R Configuration register
EG
0x4000000C BLE_INTCNTL_REG Interrupt controller register
0x40000010 BLE_INTSTAT_REG Interrupt status register
0x40000014 BLE_INTRAWSTAT_R Interrupt raw status register
EG
0x40000018 BLE_INTACK_REG Interrupt acknowledge register
0x4000001C BLE_BASETIMECNT_ Base time reference counter
REG
0x40000020 BLE_FINETIMECNT_ Fine time reference counter
REG
0x40000024 BLE_BDADDRL_REG BLE device address LSB register
0x40000028 BLE_BDADDRU_REG BLE device address MSB register
0x4000002C BLE_CURRENTRXDE Rx Descriptor Pointer for the Receive Buffer Chained List
SCPTR_REG
0x40000030 BLE_DEEPSLCNTL_R Deep-Sleep control register
EG
0x40000034 BLE_DEEPSLWKUP_ Time (measured in Low Power clock cycles) in Deep Sleep
REG Mode before waking-up the device
0x40000038 BLE_DEEPSLSTAT_R Duration of the last deep sleep phase register
EG
0x4000003C BLE_ENBPRESET_R Time in low power oscillator cycles register
EG
0x40000040 BLE_FINECNTCORR_ Phase correction value register
REG
0x40000044 BLE_BASETIMECNTC Base Time Counter
ORR_REG
0x40000050 BLE_DIAGCNTL_REG Diagnostics Register
0x40000054 BLE_DIAGSTAT_REG Debug use only
0x40000058 BLE_DEBUGADDMAX Upper limit for the memory zone
_REG
0x4000005C BLE_DEBUGADDMIN Lower limit for the memory zone
_REG
0x40000060 BLE_ERRORTYPEST Error Type Status registers
AT_REG
0x40000064 BLE_SWPROFILING_ Software Profiling register
REG

DA14531

0x40000074 BLE_RADIOCNTL1_R Radio interface control register
EG
0x40000080 BLE_RADIOPWRUPD RX/TX power up/down phase register
N_REG
0x40000090 BLE_ADVCHMAP_RE Advertising Channel Map
G
0x400000A0 BLE_ADVTIM_REG Advertising Packet Interval
0x400000A4 BLE_ACTSCANSTAT Active scan register
_REG
0x400000B0 BLE_WLPUBADDPTR Start address of public devices list
_REG
0x400000B4 BLE_WLPRIVADDPT Start address of private devices list
R_REG
0x400000B8 BLE_WLNBDEV_REG Devices in white list
0x400000C0 BLE_AESCNTL_REG Start AES register
0x400000C4 BLE_AESKEY31_0_R AES encryption key
EG
0x400000C8 BLE_AESKEY63_32_ AES encryption key
REG
0x400000CC BLE_AESKEY95_64_ AES encryption key
REG
0x400000D0 BLE_AESKEY127_96 AES encryption key
_REG
0x400000D4 BLE_AESPTR_REG Pointer to the block to encrypt/decrypt
0x400000D8 BLE_TXMICVAL_REG AES / CCM plain MIC value
0x400000DC BLE_RXMICVAL_REG AES / CCM plain MIC value
0x400000E0 BLE_RFTESTCNTL_R RF Testing Register
EG
0x400000E4 BLE_RFTESTTXSTAT RF Testing Register
_REG
0x400000E8 BLE_RFTESTRXSTAT RF Testing Register
_REG
0x400000F0 BLE_TIMGENCNTL_R Timing Generator Register
EG
0x400000F4 BLE_GROSSTIMTGT Gross Timer Target value
_REG
0x400000F8 BLE_FINETIMTGT_R Fine Timer Target value
EG
0x400000FC BLE_SAMPLECLK_R Samples the Base Time Counter
EG
0x40000100 BLE_COEXIFCNTL0_ Coexistence interface Control 0 Register
REG
0x40000104 BLE_COEXIFCNTL1_ Coexistence interface Control 1 Register
REG
0x40000108 BLE_BLEMPRIO0_RE Coexistence interface Priority 0 Register
G

DA14531

0x4000010C BLE_BLEMPRIO1_RE Coexistence interface Priority 1 Register
G
0x40000200 BLE_CNTL2_REG BLE Control Register 2
0x40000208 BLE_EM_BASE_REG Exchange Memory Base Register
0x4000020C BLE_DIAGCNTL2_RE Debug use only
G
0x40000210 BLE_DIAGCNTL3_RE Debug use only
G
Table 64: BLE_RWBLECNTL_REG (0x40000000)

31 R0/W MASTER_SOFT_R Reset the complete BLE Core except registers 0x0
ST and timing generator, when written with a 1.
Resets at 0 when action is performed. No action
happens if it is written with 0.
30 R0/W MASTER_TGSOFT Reset the timing generator, when written with a 1. 0x0
_RST Resets at 0 when action is performed. No action
29 R/W REG_SOFT_RST Reset the complete register block, when written 0x0
with a 1. Resets at 0 when action is performed. No
action happens if it is written with 0.
Note that INT STAT will not be cleared, so the
user should also write to BLE_INTACK_REG after
the SW Reset
28 R0/W SWINT_REQ Forces the generation of ble_sw_irq when written 0x0
with a 1, and proper masking is set. Resets at 0
when action is performed. No action happens if it
is written with 0.
26 R0/W RFTEST_ABORT Abort the current RF Testing defined as per CS- 0x0
FORMAT when written with a 1. Resets at 0 when
action is performed. No action happens if it is
written with 0.
Note that when RFTEST_ABORT is requested:
1) In case of infinite Tx, the Packet Controller FSM
stops at the end of the current byte in process,
and processes accordingly the packet CRC.
2) In case of Infinite Rx, the Packet Controller
FSM either stops as the end of the current Packet
reception (if Access address has been detected),
or simply stop the processing switching off the RF.
25 R0/W ADVERT_ABORT Abort the current Advertising event when written 0x0
with a 1. Resets at 0 when action is performed. No
24 R0/W SCAN_ABORT Abort the current scan window when written with a 0x0
1. Resets at 0 when action is performed. No action

DA14531

22 R/W MD_DSB 0: Normal operation of MD bits management 0x0
1: Allow a single Tx/Rx exchange whatever the
MD bits are.
value forced by SW from Tx Descriptor
value just saved in Rx Descriptor during reception
21 R/W SN_DSB 0: Normal operation of Sequence number 0x0

1: Sequence Number Management disabled:
value ignored in Rx, where no SN error reported.
20 R/W NESN_DSB 0: Normal operation of Acknowledge 0x0

1: Acknowledge scheme disabled:
value ignored in Rx, where no NESN error
reported.
19 R/W CRYPT_DSB 0: Normal operation. Encryption / Decryption 0x0

enabled.
1: Encryption / Decryption disabled.
Note that if CS-CRYPT_EN is set, then MIC is
generated, and only data encryption is disabled,
meaning data sent are plain data.
18 R/W WHIT_DSB 0: Normal operation. Whitening enabled. 0x0
1: Whitening disabled.
17 R/W CRC_DSB 0: Normal operation. CRC removed from data 0x0
stream.
1: CRC stripping disabled on Rx packets, CRC
replaced by 0x000 in Tx.
16 R/W HOP_REMAP_DSB 0: Normal operation. Frequency Hopping 0x0
Remapping algorithm enabled.
1: Frequency Hopping Remapping algorithm
disabled
13:12 R/W - 0x0
9 R/W ADVERTFILT_EN Advertising Channels Error Filtering Enable 0x0
control
0: BLE Core reports all errors to RW-BLE
Software
1: BLE Core reports only correctly received
packet, without error to RW-BLE Software
8 R/W RWBLE_EN 0: Disable BLE Core Exchange Table pre-fetch 0x0
mechanism.
1: Enable BLE Core Exchange table pre-fetch
mechanism.
7:4 R/W RXWINSZDEF Default Rx Window size in us. Used when device: 0x0
is master connected
performs its second receipt.
0 is not a valid value. Recommended value is 10
(in decimal).

DA14531

2:0 R/W SYNCERR Indicates the maximum number of errors allowed 0x0
to recognize the synchronization word.
Table 65: BLE_VERSION_REG (0x40000004)

31:24 R TYP BLE Core Type 0x7
23:16 R REL BLE Core version Major release number. 0x1
15:8 R UPG BLE Core upgrade Upgrade number. 0x0
7:0 R BUILD BLE Core Build Build number. 0x0
Table 66: BLE_RWBLECONF_REG (0x40000008)

29:24 R ADD_WIDTH Value of the RW_BLE_ADDRESS_WIDTH 0xF
parameter concerted into binary.
22:16 R RFIF Radio Interface ID 0x2
13:8 R CLK_SEL Operating Frequency (in MHz) 0x0
6 R DECIPHER 0: AES deciphering not present 0x0
5 R DMMODE 0: BLE Core is used as a standalone BLE device 0x0
4 R INTMODE 1: Interrupts are trigger level generated, i.e. stays 0x1
active at 1 till acknowledgement
3 R COEX 1: WLAN Coexistence mechanism present 0x1
2 R USEDBG 1: Diagnostic port instantiated 0x1
1 R USECRYPT 1: AES-CCM Encryption block present 0x1
0 R BUSWIDTH Processor bus width: 0x1
1: 32 bits
Table 67: BLE_INTCNTL_REG (0x4000000C)

15 R/W CSCNTDEVMSK CSCNT interrupt mask during event. This bit 0x1
allows to enable CSCNT interrupt generation
during events (i.e. advertising, scanning, initiating,
and connection)
0: CSCNT Interrupt not generated during events.
1: CSCNT Interrupt generated during events.
14:10 R - 0x0
9 R/W SWINTMSK SW triggered interrupt Mask 0x0
0: Interrupt not generated
1: Interrupt generated

DA14531

8 R/W EVENTAPFAINTMS End of event / anticipated pre-fetch abort interrupt 0x1
K Mask
7 R/W FINETGTIMINTMSK Fine Target Timer Mask 0x0
6 R/W GROSSTGTIMINTM Gross Target Timer Mask 0x0
SK 0: Interrupt not generated
5 R/W ERRORINTMSK Error Interrupt Mask 0x0
4 R/W CRYPTINTMSK Encryption engine Interrupt Mask 0x1
3 R/W EVENTINTMSK End of event Interrupt Mask 0x1
2 R/W SLPINTMSK Sleep Mode Interrupt Mask 0x1
1 R/W RXINTMSK Rx Interrupt Mask 0x1
0 R/W CSCNTINTMSK 625us Base Time Interrupt Mask 0x1
Table 68: BLE_INTSTAT_REG (0x40000010)

9 R SWINTSTAT SW triggered interrupt status 0x0
0: No SW triggered interrupt.
1: A SW triggered interrupt is pending
8 R EVENTAPFAINTST End of event / Anticipated Pre-Fetch Abort 0x0
AT interrupt status
0: No End of Event interrupt.
1: An End of Event interrupt is pending.
7 R FINETGTIMINTSTA Masked Fine Target Timer Error interrupt status 0x0
T 0: No Fine Target Timer interrupt.
1: A Fine Target Timer interrupt is pending.

DA14531

6 R GROSSTGTIMINTS Masked Gross Target Timer interrupt status 0x0
TAT 0: No Gross Target Timer interrupt.
1: A Gross Target Timer interrupt is pending.
5 R ERRORINTSTAT Masked Error interrupt status 0x0
0: No Error interrupt.
1: An Error interrupt is pending.
4 R CRYPTINTSTAT Masked Encryption engine interrupt status 0x0
0: No Encryption / Decryption interrupt.
1: An Encryption / Decryption interrupt is pending.
3 R EVENTINTSTAT Masked End of Event interrupt status 0x0
0: No End of Advertising / Scanning / Connection
interrupt.
1: An End of Advertising / Scanning / Connection
interrupt is pending.
2 R SLPINTSTAT Masked Sleep interrupt status 0x0
0: No End of Sleep Mode interrupt.
1: An End of Sleep Mode interrupt is pending.
1 R RXINTSTAT Masked Packet Reception interrupt status 0x0
0: No Rx interrupt.
1: An Rx interrupt is pending.
0 R CSCNTINTSTAT Masked 625us base time reference interrupt 0x0
status
0: No 625us Base Time interrupt.
1: A 625us Base Time interrupt is pending.
Table 69: BLE_INTRAWSTAT_REG (0x40000014)

9 R SWINTRAWSTAT SW triggered interrupt raw status 0x0
0: No SW triggered interrupt.
1: A SW triggered interrupt is pending.
8 R EVENTAPFAINTRA End of event / Anticipated Pre-Fetch Abort 0x0
WSTAT interrupt raw status
0: No End of Event interrupt.
1: An End of Event interrupt is pending.
7 R FINETGTIMINTRA Fine Target Timer Error interrupt raw status 0x0
WSTAT 0: No Fine Target Timer interrupt.
1: A Fine Target Timer interrupt is pending.
6 R GROSSTGTIMINTR Gross Target Timer interrupt raw status 0x0
AWSTAT 0: No Gross Target Timer interrupt.
1: A Gross Target Timer interrupt is pending.
5 R ERRORINTRAWST Error interrupt raw status 0x0
AT 0: No Error interrupt.
1: An Error interrupt is pending.

DA14531

4 R CRYPTINTRAWST Encryption engine interrupt raw status 0x0
AT 0: No Encryption / Decryption interrupt.
1: An Encryption / Decryption interrupt is pending.
3 R EVENTINTRAWST End of Event interrupt raw status 0x0
AT 0: No End of Advertising / Scanning / Connection
interrupt.
1: An End of Advertising / Scanning / Connection
interrupt is pending.
2 R SLPINTRAWSTAT Sleep interrupt raw status 0x0
0: No End of Sleep Mode interrupt.
1: An End of Sleep Mode interrupt is pending.
1 R RXINTRAWSTAT Packet Reception interrupt raw status 0x0
0: No Rx interrupt.
1: An Rx interrupt is pending.
0 R CSCNTINTRAWST 625us base time reference interrupt raw status 0x0
AT 0: No 625us Base Time interrupt.
1: A 625us Base Time interrupt is pending.
Table 70: BLE_INTACK_REG (0x40000018)

9 R0/W SWINTACK SW triggered interrupt acknowledgement bit 0x0
Software writing 1 acknowledges the SW triggered
interrupt. This bit resets SWINTSTAT and
SWINTRAWSTAT flags.
Resets at 0 when action is performed
8 R0/W EVENTAPFAINTAC End of event / Anticipated Pre-Fetch Abort 0x0
K interrupt acknowledgement bit
Software writing 1 acknowledges the End of event
/ Anticipated Pre-Fetch Abort interrupt. This bit
resets EVENTAPFAINTSTAT and
EVENTAPFAINTRAWSTAT flags.
7 R0/W FINETGTIMINTACK Fine Target Timer interrupt acknowledgement bit 0x0
Software writing 1 acknowledges the Fine Timer
interrupt. This bit resets FINETGTIMINTSTAT and
FINETGTIMINTRAWSTAT flags.
6 R0/W GROSSTGTIMINTA Gross Target Timer interrupt acknowledgement bit 0x0
CK Software writing 1 acknowledges the Gross Timer
interrupt. This bit resets GROSSTGTIMINTSTAT
and GROSSTGTIMINTRAWSTAT flags.
5 R0/W ERRORINTACK Error interrupt acknowledgement bit 0x0
Software writing 1 acknowledges the Error
interrupt. This bit resets ERRORINTSTAT and
ERRORINTRAWSTAT flags.

DA14531

4 R0/W CRYPTINTACK Encryption engine interrupt acknowledgement bit 0x0
Software writing 1 acknowledges the Encryption
engine interrupt. This bit resets CRYPTINTSTAT
and CRYPTINTRAWSTAT flags.
3 R0/W EVENTINTACK End of Event interrupt acknowledgment bit 0x0
Software writing 1 acknowledges the End of
Advertising / Scanning / Connection interrupt. This
bit resets SLPINTSTAT and SLPINTRAWSTAT
flags.
2 R0/W SLPINTACK End of Deep Sleep interrupt acknowledgment bit 0x0
Software writing 1 acknowledges the End of Sleep
Mode interrupt. This bit resets SLPINTSTAT and
SLPINTRAWSTAT flags.
1 R0/W RXINTACK Packet Reception interrupt acknowledgment bit 0x0
Software writing 1 acknowledges the Rx interrupt.
This bit resets RXINTSTAT and RXINTRAWSTAT
flags.
0 R0/W CSCNTINTACK 625us base time reference interrupt 0x0
acknowledgment bit
Software writing 1 acknowledges the CLKN
interrupt. This bit resets CLKINTSTAT and
CLKINTRAWSTAT flags.
Table 71: BLE_BASETIMECNT_REG (0x4000001C)

26:0 R BASETIMECNT Value of the 625us base time reference counter. 0x0
Updated each time SAMPCLK is written. Used by
the SW in order to synchronize with the HW
Table 72: BLE_FINETIMECNT_REG (0x40000020)

9:0 R FINECNT Value of the current s fine time reference counter. 0x0
Updated each time SAMPCLK is written. Used by
the SW in order to synchronize with the HW, and
obtain a more precise sleep duration

DA14531
Table 73: BLE_BDADDRL_REG (0x40000024)

31:0 R/W BDADDRL Bluetooth Low Energy Device Address. LSB part. 0x0
Table 74: BLE_BDADDRU_REG (0x40000028)

16 R/W PRIV_NPUB Bluetooth Low Energy Device Address privacy 0x0
indicator
0: Public Bluetooth Device Address
1: Private Bluetooth Device Address
15:0 R/W BDADDRU Bluetooth Low Energy Device Address. MSB part. 0x0
Table 75: BLE_CURRENTRXDESCPTR_REG (0x4000002C)

31:16 R/W ETPTR Exchange Table Pointer that determines the 0x0
starting point of the Exchange Table
14:0 R/W CURRENTRXDESC Rx Descriptor Pointer that determines the starting 0x0
PTR point of the Receive Buffer Chained List
Table 76: BLE_DEEPSLCNTL_REG (0x40000030)

31 R/W EXTWKUPDSB External Wake-Up disable 0x0
0: RW-BLE Core can be woken by external wake-
up
1: RW-BLE Core cannot be woken up by external
wake-up
15 R DEEP_SLEEP_STA Indicator of current Deep Sleep clock mux status: 0x0
T 0: RW-BLE Core is not yet in Deep Sleep Mode
1: RW-BLE Core is in Deep Sleep Mode (only
low_power_clk is running)
4 R/W SOFT_WAKEUP_R Wake Up Request from BLE Software. Applies 0x0
EQ when system is in Deep Sleep Mode. It wakes up
the BLE Core when written with a 1. Resets at 0
when action is performed. No action happens if it
is written with 0.
3 R0/W DEEP_SLEEP_CO 625us base time reference integer and fractional 0x0
RR_EN part correction. Applies when system has been
woken-up from Deep Sleep Mode. It enables Fine
Counter and Base Time counter when written with
a 1. Resets at 0 when action is performed. No

DA14531

2 R0/W DEEP_SLEEP_ON 0: BLE Core in normal active mode 0x0
1: Request RW-BLE Core to switch in deep sleep
mode.
This bit is reset on DEEP_SLEEP_STAT falling
edge.
1:0 R/W DEEP_SLEEP_IRQ Always set to "3" when DEEP_SLEEP_ON is set 0x0
_EN to "1".
It controls the generation of
BLE_WAKEUP_LP_IRQ.
Table 77: BLE_DEEPSLWKUP_REG (0x40000034)

31:0 R/W DEEPSLTIME Determines the time in low_power_clk clock 0x0
cycles to spend in Deep Sleep Mode before
waking-up the device. This ensures a maximum of
37 hours and 16mn sleep mode capabilities at
32kHz. This ensures a maximum of 36 hours and
16mn sleep mode capabilities at 32.768kHz
Table 78: BLE_DEEPSLSTAT_REG (0x40000038)

31:0 R DEEPSLDUR Actual duration of the last deep sleep phase 0x0
measured in low_power_clk clock cycle.
DEEPSLDUR is set to zero at the beginning of the
deep sleep phase, and is incremented at each
low_power_clk clock cycle until the end of the
deep sleep phase.
Table 79: BLE_ENBPRESET_REG (0x4000003C)

31:21 R/W TWEXT Minimum and recommended value is 0x0
"TWIRQ_RESET + 1".
In the case of wake-up due to an external wake-up
request, TWEXT specifies the time delay in low
power oscillator cycles to deassert
BLE_WAKEUP_LP_IRQ.
Refer also to
GP_CONTROL_REG[BLE_WAKEUP_REQ].
Range is [0...64 ms] for 32kHz; [0...62.5 ms] for
32.768kHz

DA14531

20:10 R/W TWIRQ_SET Minimum value is "TWIRQ_RESET + 1". 0x0
Time in low power oscillator cycles to set
BLE_WAKEUP_LP_IRQ before the BLE sleep
timer expiration.
Refer also to
BLE_DEEPSLWKUP_REG[DEEPSLTIME].
32.768kHz
9:0 R/W TWIRQ_RESET Recommended value is 1. 0x0
Time in low power oscillator cycles to reset
BLE_WAKEUP_LP_IRQ before the BLE sleep
timer expiration.
Refer also to
BLE_DEEPSLWKUP_REG[DEEPSLTIME].
32.768kHz.
Table 80: BLE_FINECNTCORR_REG (0x40000040)

9:0 R/W FINECNTCORR Phase correction value for the 625us reference 0x0
counter (i.e. Fine Counter) in us.
Table 81: BLE_BASETIMECNTCORR_REG (0x40000044)

26:0 R/W BASETIMECNTCO Base Time Counter correction value. 0x0
RR
Table 82: BLE_DIAGCNTL_REG (0x40000050)

31 R/W DIAG3_EN 0: Disable diagnostic port 0 output. All outputs are 0x0
set to 0x0.
1: Enable diagnostic port 0 output.
29:24 R/W DIAG3 Only relevant when DIAG3_EN = 1. 0x0
Selection of the outputs that must be driven to the
diagnostic port BLE_DIAG3.
set to 0x0.

DA14531

set to 0x0.
set to 0x0.
Table 83: BLE_DIAGSTAT_REG (0x40000054)

31:24 R DIAG3STAT Directly connected to ble_dbg3[7:0] output. Debug 0x0
use only.
use only.
use only.
use only.
Table 84: BLE_DEBUGADDMAX_REG (0x40000058)

31:16 R/W REG_ADDMAX Upper limit for the Register zone indicated by the 0x0
reg_inzone flag
15:0 R/W EM_ADDMAX Upper limit for the Exchange Memory zone 0x0
indicated by the em_inzone flag
Table 85: BLE_DEBUGADDMIN_REG (0x4000005C)

31:16 R/W REG_ADDMIN Lower limit for the Register zone indicated by the 0x0
reg_inzone flag
15:0 R/W EM_ADDMIN Lower limit for the Exchange Memory zone 0x0
indicated by the em_inzone flag

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Table 86: BLE_ERRORTYPESTAT_REG (0x40000060)

17 R CONCEVTIRQ_ER Indicates whether two consecutive and concurrent 0x0
ROR ble_event_irq have been generated, and not
acknowledged in time by the BLE Software.
0: No error
1: Error occurred
16 R RXDATA_PTR_ER Indicates whether Rx data buffer pointer value 0x0
ROR programmed is null: this is a major programming
failure.
0: No error
1: Error occurred
15 R TXDATA_PTR_ERR Indicates whether Tx data buffer pointer value 0x0
OR programmed is null during Advertising / Scanning /
Initiating events, or during Master / Slave
connections with non-null packet length: this is a
major programming failure.
0: No error
1: Error occurred
14 R RXDESC_EMPTY_ Indicates whether Rx Descriptor pointer value 0x0
ERROR programmed in register is null: this is a major
programming failure.
0: No error
1: Error occurred
13 R TXDESC_EMPTY_ Indicates whether Tx Descriptor pointer value 0x0
ERROR programmed in Control Structure is null during
Advertising / Scanning / Initiating events: this is a
major programming failure.
0: No error
1: Error occurred
12 R CSFORMAT_ERRO Indicates whether CS-FORMAT has been 0x0
R programmed with an invalid value: this is a major
software programming failure.
0: No error
1: Error occurred
11 R LLCHMAP_ERROR Indicates Link Layer Channel Map error, happens 0x0
when actual number of CS-LLCHMAP bit set to
one is different from CS-NBCHGOOD at the
beginning of Frequency Hopping process
0: No error
1: Error occurred
10 R ADV_UNDERRUN Indicates Advertising Interval Under run, occurs if 0x0
time between two consecutive Advertising packet
(in Advertising mode) is lower than the expected
value.
0: No error
1: Error occurred

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9 R IFS_UNDERRUN Indicates Inter Frame Space Under run, occurs if 0x0
IFS time is not enough to update and read Control
Structure/Descriptors, and/or White List parsing is
not finished and/or Decryption time is too long to
be finished on time
0: No error
1: Error occurred
8 R WHITELIST_ERRO Indicates White List Timeout error, occurs if White 0x0
R List parsing is not finished on time
0: No error
1: Error occurred
7 R EVT_CNTL_APFM_ Indicates Anticipated Pre-Fetch Mechanism error: 0x0
ERROR happens when 2 consecutive events are
programmed, and when the first event is not
completely finished while second pre-fetch instant
is reached.
0: No error
1: Error occured
6 R EVT_SCHDL_APF Indicates Anticipated Pre-Fetch Mechanism error: 0x0
M_ERROR happens when 2 consecutive events are
programmed, and when the first event is not
completely finished while second pre-fetch instant
is reached.
0: No error
1: Error occured
5 R EVT_SCHDL_ENTR Indicates Event Scheduler faced Invalid timing 0x0
Y_ERROR programing on two consecutive ET entries (e.g
first one with 624s offset and second one with no
offset)
0: No error
1: Error occurred
4 R EVT_SCHDL_EMA Indicates Event Scheduler Exchange Memory 0x0
CC_ERROR access error, happens when Exchange Memory
accesses are not served in time, and blocks the
Exchange Table entry read
0: No error
1: Error occurred
3 R RADIO_EMACC_E Indicates Radio Controller Exchange Memory 0x0
RROR access error, happens when Exchange Memory
accesses are not served in time and data are
corrupted.
0: No error
1: Error occurred
2 R PKTCNTL_EMACC Indicates Packet Controller Exchange Memory 0x0
_ERROR access error, happens when Exchange Memory
accesses are not served in time and Tx/Rx data
are corrupted
0: No error
1: Error occurred

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1 R RXCRYPT_ERROR Indicates real time decryption error, happens 0x0
when AES-CCM decryption is too slow compared
to Packet Controller requests. A 16-bytes block
has to be decrypted prior the next block is
received by the Packet Controller
0: No error
1: Error occurred
0 R TXCRYPT_ERROR Indicates Real Time encryption error, happens 0x0
when AES-CCM encryption is too slow compared
to Packet Controller requests. A 16-bytes block
has to be encrypted and prepared on Packet
Controller request, and needs to be ready before
the Packet Controller has to send ti
0: No error
1: Error occurred
Table 87: BLE_SWPROFILING_REG (0x40000064)

31:0 R/W SWPROFVAL Software Profiling register: used by BLE Software 0x0
for profiling purpose: this value is copied on
Diagnostic port
Table 88: BLE_RADIOCNTL1_REG (0x40000074)

31:21 - - 0x0
20:16 R/W XRFSEL Extended radio selection field, Must be set to "2". 0x0
Table 89: BLE_RADIOPWRUPDN_REG (0x40000080)

30:24 R/W RTRIP_DELAY Defines round trip delay value. This value 0x0
correspond to the addition of data latency in Tx
and data latency in Rx. Value is in usec.
23:16 R/W RXPWRUP This register holds the length in s of the RX power 0xD2
up phase for the current radio device. Default
value is 210 usec (reset value). Operating range
depends on the selected radio.

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11:8 R/W TXPWRDN This register extends the length in s of the TX 0x3
power down phase for the current radio device.
Default value is 3 usec (reset value). Operating
range depends on the selected radio.
7:0 R/W TXPWRUP This register holds the length in s of the TX power 0xD2
up phase for the current radio device. Default
value is 210 usec (reset value). Operating range
depends on the selected radio.
Table 90: BLE_ADVCHMAP_REG (0x40000090)

2:0 R/W ADVCHMAP Advertising Channel Map, defined as per the 0x7
advertising connection settings. Contains
advertising channels index 37 to 39. If
ADVCHMAP[i] equals:
0: Do not use data channel i+37.
1: Use data channel i+37.
Table 91: BLE_ADVTIM_REG (0x400000A0)

13:0 R/W ADVINT Advertising Packet Interval defines the time 0x0
interval in between two ADV_xxx packet sent.
Value is in us.
Value to program depends on the used
Advertising Packet type and the device filtering
policy.
Table 92: BLE_ACTSCANSTAT_REG (0x400000A4)

24:16 R BACKOFF Active scan mode back-off counter initialization 0x1
value.
8:0 R UPPERLIMIT Active scan mode upper limit counter value. 0x1
Table 93: BLE_WLPUBADDPTR_REG (0x400000B0)

15:0 R/W WLPUBADDPTR Start address pointer of the public devices white 0x0
list.

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Table 94: BLE_WLPRIVADDPTR_REG (0x400000B4)

15:0 R/W WLPRIVADDPTR Start address pointer of the private devices white 0x0
list.
Table 95: BLE_WLNBDEV_REG (0x400000B8)

15:8 R/W NBPRIVDEV Number of private devices in the white list. 0x0
7:0 R/W NBPUBDEV Number of public devices in the white list. 0x0
Table 96: BLE_AESCNTL_REG (0x400000C0)

1 R/W AES_MODE 0: Cipher mode 0x0
1: Decipher mode
0 R0/W AES_START Writing a 1 starts AES-128 ciphering/deciphering 0x0
process.
This bit is reset once the process is finished (i.e.
ble_crypt_irq interrupt occurs, even masked)
Table 97: BLE_AESKEY31_0_REG (0x400000C4)

31:0 R/W AESKEY31_0 AES encryption 128-bit key. Bit 31 down to 0 0x0
Table 98: BLE_AESKEY63_32_REG (0x400000C8)

Table 99: BLE_AESKEY95_64_REG (0x400000CC)


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Table 100: BLE_AESKEY127_96_REG (0x400000D0)

Table 101: BLE_AESPTR_REG (0x400000D4)

15:0 R/W AESPTR Pointer to the memory zone where the block to 0x0
cipher/decipher using AES-128 is stored.
Table 102: BLE_TXMICVAL_REG (0x400000D8)

31:0 R TXMICVAL AES-CCM plain MIC value. Valid on when MIC 0x0
has been calculated (in Tx)
Table 103: BLE_RXMICVAL_REG (0x400000DC)

31:0 R RXMICVAL AES-CCM plain MIC value. Valid on once MIC has 0x0
been extracted from Rx packet.
Table 104: BLE_RFTESTCNTL_REG (0x400000E0)

31 R/W INFINITERX Applicable in RF Test Mode only 0x0
0: Normal mode of operation
1: Infinite Rx window
27 R/W RXPKTCNTEN Applicable in RF Test Mode only 0x0
0: Rx packet count disabled
1: Rx packet count enabled, and reported in CS-
RXCCMPKTCNT and
BLE_RFTESTRXSTAT_REG[RXPKTCNT] on RF
abort command
15 R/W INFINITETX Applicable in RF Test Mode only 0x0
0: Normal mode of operation.
1: Infinite Tx packet / Normal start of a packet but
endless payload

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14 R/W TXLENGTHSRC Applicable only in Tx/Rx RF Test mode 0x0
0: Normal mode of operation: TxDESC-
TXADVLEN controls the Tx packet payload size
1: Uses BLE_RFTESTCNTL_REG[TXLENGTH]
packet length (can support up to 512 bytes
transmit)
13 R/W PRBSTYPE Applicable only in Tx/Rx RF Test mode 0x0
0: Tx Packet Payload are PRBS9 type
1: Tx Packet Payload are PRBS15 type
12 R/W TXPLDSRC Applicable only in Tx/Rx RF Test mode 0x0
0: Tx Packet Payload source is the Control
Structure
1: Tx Packet Payload are PRBS generator
11 R/W TXPKTCNTEN Applicable in RF Test Mode only 0x0
0: Tx packet count disabled
1: Tx packet count enabled, and reported in CS-
TXCCMPKTCNT and
BLE_RFTESTTXSTAT_REG[TXPKTCNT] on RF
abort command
8:0 R/W TXLENGTH Applicable only for Tx/Rx RF Test mode, and valid 0x0
when BLE_RFTESTCNTL_REG[TXLENGTHSRC]
=1
Tx packet length in number of byte
Table 105: BLE_RFTESTTXSTAT_REG (0x400000E4)

31:0 R TXPKTCNT Reports number of transmitted packet during Test 0x0
Modes.
Value is valid if
BLE_RFTESTCNTL_REG[TXPKTCNTEN] is set
Table 106: BLE_RFTESTRXSTAT_REG (0x400000E8)

31:0 R RXPKTCNT Reports number of correctly received packet 0x0
during Test Modes (no sync error, no CRC error).
Value is valid if
BLE_RFTESTCNTL_REG[RXPKTCNTEN] is set

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Table 107: BLE_TIMGENCNTL_REG (0x400000F0)

31 R/W APFM_EN Controls the Anticipated pre-Fetch Abort 0x1
mechanism
0: Disabled
1: Enabled
25:16 R/W PREFETCHABORT Defines the instant in usec at which immediate 0x1FE
_TIME abort is required after anticipated pre-fetch abort.
8:0 R/W PREFETCH_TIME Defines Exchange Table pre-fetch instant in us 0x96
Table 108: BLE_GROSSTIMTGT_REG (0x400000F4)

22:0 R/W GROSSTARGET Gross Timer Target value on which a 0x0
ble_grosstgtim_irq must be generated. This timer
has a precision of 10ms: interrupt is generated
only when GROSSTARGET[22:0] =
BASETIMECNT[26:4] and BASETIMECNT[3:0] =
0.
Table 109: BLE_FINETIMTGT_REG (0x400000F8)

26:0 R/W FINETARGET Fine Timer Target value on which a 0x0
ble_finetgtim_irq must be generated. This timer
has a precision of 625 usec: interrupt is generated
only when FINETARGET = BASETIMECNT
Table 110: BLE_SAMPLECLK_REG (0x400000FC)

31:1 - - 0x0
0 R0/W SAMP Writing a 1 samples the Base Time Counter value 0x0
in BASETIMECNT register. Resets at 0 when
action is performed.

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Table 111: BLE_COEXIFCNTL0_REG (0x40000100)

21:20 R/W WLCRXPRIOMODE Defines Bluetooth Low Energy packet ble_rx 0x0
mode behavior.
00: Rx indication excluding Rx Power up delay
(starts when correlator is enabled)
01: Rx indication including Rx Power up delay
10: Rx High priority indicator
11: n/a
17:16 R/W WLCTXPRIOMODE Defines Bluetooth Low Energy packet ble_tx mode 0x0
behavior
00: Tx indication excluding Tx Power up delay
01: Tx indication including Tx Power up delay
10: Tx High priority indicator
11: n/a
7:6 R/W WLANTXMSK Determines how wlan_tx impact BLE Tx and Rx 0x0
00: wlan_tx has no impact (default mode)
01: wlan_tx can stop BLE Tx, no impact on BLE
Rx
10: wlan_tx can stop BLE Rx, no impact on BLE
Tx
11: wlan_tx can stop both BLE Tx and BLE Rx
5:4 R/W WLANRXMSK Determines how wlan_rx impact BLE Tx and Rx 0x1
00: wlan_rx has no impact
01: wlan_rx can stop BLE Tx, no impact on BLE
Rx (default mode)
10: wlan_rx can stop BLE Rx, no impact on BLE
Tx
11: wlan_rx can stop both BLE Tx and BLE Rx
1 R/W SYNCGEN_EN Determines whether ble_sync is generated or not. 0x0
0: ble_sync pulse not generated
1: ble_sync pulse generated
0 R/W COEX_EN Enable / Disable control of the MWS/WLAN 0x0
Coexistence control
0: Coexistence interface disabled
1: Coexistence interface enabled
Table 112: BLE_COEXIFCNTL1_REG (0x40000104)

28:24 R/W WLCPRXTHR Applies on ble_rx if WLCRXPRIOMODE equals 10 0x0
Determines the threshold for Rx priority setting.
If ble_pti[3:0] output value is greater than
WLCPRXTHR, then Rx Bluetooth Low Energy
priority is considered as high, and must be
provided to the WLAN coexistence interface

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20:16 R/W WLCPTXTHR Applies on ble_tx if WLCTXPRIOMODE equals 10 0x0
Determines the threshold for priority setting.
If ble_pti[3:0] output value is greater than
WLCPTXTHR, then Tx Bluetooth Low Energy
priority is considered as high, and must be
provided to the WLAN coexistence interface
14:8 R/W WLCPDURATION Applies on ble_tx if WLCTXPRIOMODE equals 10 0x0
Applies on ble_rx if WLCRXPRIOMODE equals 10
Determines how many s the priority information
must be maintained
Note that if WLCPDURATION = 0x00, then Tx/Rx
priority levels are maintained till Tx/Rx EN are de-
asserted.
6:0 R/W WLCPDELAY Applies on ble_tx if WLCTXPRIOMODE equals 0x0
10.
Applies on ble_rx if WLCRXPRIOMODE equals
10.
Determines the delay (in us) in Tx/Rx enables
rises the time Bluetooth Low energy Tx/Rx priority
has to be provided .
Table 113: BLE_BLEMPRIO0_REG (0x40000108)

31:28 R/W BLEM7 Set Priority value for Passive Scanning 0x3
27:24 R/W BLEM6 Set Priority value for Non-Connectable Advertising 0x4
23:20 R/W BLEM5 Set Priority value for Connectable Advertising BLE 0x8
message
19:16 R/W BLEM4 Set Priority value for Active Scanning BLE 0x9
message
15:12 R/W BLEM3 Set Priority value for Initiating (Scanning) BLE 0xA
message
11:8 R/W BLEM2 Set Priority value for Data Channel transmission 0xD
BLE message
7:4 R/W BLEM1 Set Priority value for LLCP BLE message 0xE
3:0 R/W BLEM0 Set Priority value for Initiating (Connection 0xF
Request Response) BLE message
Table 114: BLE_BLEMPRIO1_REG (0x4000010C)

31:28 R/W BLEMDEFAULT Set default priority value for other BLE message 0x3
than those defined above

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Table 115: BLE_CNTL2_REG (0x40000200)

31:25 R - 0x0
24 R/W BLE_PHY_ERR_M 0x0
SK_N
23 R/W BLE_ARP_ERR_M When cleared to "0" then it masks the 0x0
SK_N BLE_ARP_ERR_STAT in order to not trigger a
BLE_ERROR_IRQ.
22 RW1C BLE_ARP_PHY_ER When set to "1" then an error occured in BLE ARP 0x0
R_STAT sub-block and the BLE_GEN_IRQ will be aserted.
It will be set if the ARP_ERROR or PHY_ERROR
will be asserted and if the BLE_ARP_ERR_MSK
is set to "1".
Writing the value "1" will acknowledge and clear
this field.
21 R/W BLE_RSSI_SEL 0: (default) Select Peak-hold RSSI value during 0x0
the SYNC_FOUND event:
CS->RXRSSI[7:0] = RF_RSSI_RESULT_REG-
>RSSI_LATCHED_RD[9:2].
1: Select the Average RSSI value during the
SYNC_FOUND event:
CS->RXRSSI[7:0] = RF_RSSI_RESULT_REG-
>RSSI_AVG_RD[9:2].
20 R WAKEUPLPSTAT The status of the BLE_WAKEUP_LP_IRQ. The 0x0
Interrupt Service Routine of
BLE_WAKEUP_LP_IRQ should return only when
the WAKEUPLPSTAT is cleared.
Note that BLE_WAKEUP_LP_IRQ is automatically
acknowledged after the power up of the Radio
Subsystem, plus one Low Power Clock period.
19 R/W SW_RPL_SPI Keep to 0. 0x0
18 R/W BB_ONLY Keep to 0. 0x0
17 R/W BLE_PTI_SOURCE 0: Provide to COEX block the PTI value indicated 0x0
_SEL by the Control Structure. Recommended value is
"0".
1: Provide to COEX block the PTI value generated
dynamically by the BLE core, which is based on
the PTI of the Control Structure.
16:15 R - 0x0

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14:9 R/W BLE_CLK_SEL BLE Clock Select. 0x0
Specifies the BLE master clock absolute
frequency in MHz.
Typical values are 16 and 8.
Value depends on the selected XTAL frequency
and the value of CLK_RADIO_REG[BLE_DIV]
bitfield. For example, if XTAL oscillates at 16MHz
and CLK_RADIO_REG[BLE_DIV] = 1 (divide by
2), then BLE master clock frequency is 8MHz and
BLE_CLK_SEL should be set to value 8.
The selected BLE master clock frequency
(affected by BLE_DIV and BLE_CLK_SEL) must
be modified and set only during the initialization
time, i.e. before setting
BLE_RWBLECNTL_REG[RWBLE_EN] to 1.
Refer also to
BLE_RWBLECONF_REG[CLK_SEL].
8 R RADIO_PWRDN_A This active high signal indicates when it is allowed 0x0
LLOW for the BLE core (embedded in the Radio sub-
System power domain) to be powered down.
After the assertion of the
BLE_DEEPSLCNTL_REG[DEEP_SLEEP_ON] a
hardware sequence based on the Low Power
clock will cause the assertion of
RADIO_PWRDN_ALLOW. The
RADIO_PWRDN_ALLOW will be cleared to "0"
when the BLE core exits from the sleep state, i.e.
when the BLE_SLP_IRQ will be asserted.
7 R MON_LP_CLK The SW can only write a "0" to this bit. 0x0
Whenever a positive edge of the low power clock
used by the BLE Timers is detected, then the HW
will automatically set this bit to "1". This
functionality will not work if BLE Timer is in reset
state (refer to
CLK_RADIO_REG[BLE_LP_RESET]).
This bit can be used for SW synchronization, to
debug the low power clock, etc.
6 R BLE_CLK_STAT 0: BLE uses low power clock 0x0
1: BLE uses master clock
5:4 R/W - 0x0
3 R/W BLE_DIAG_OVR 1: Overrule BLE_DIAG. 0x0
0: BLE_DIAG is not overruled.
2 R/W EMACCERRMSK Exchange Memory Access Error Mask: 0x1
When cleared to "0" the EM_ACC_ERR will not
cause an BLE_ERROR_IRQ interrupt.
When set to "1" an BLE_ERROR_IRQ will be
generated as long as EM_ACC_ERR is "1".
1 R0/W EMACCERRACK Exchange Memory Access Error Acknowledge. 0x0
When the SW writes a "1" to this bit then the
EMACCERRSTAT bit will be cleared.
When the SW writes "0" it will have no affect.
The read value is always "0".

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0 R EMACCERRSTAT Exchange Memory Access Error Status: 0x0
The bit is read-only and can be cleared only by
writing a "1" at EMACCERRACK bitfield.
This bit will be set to "1" by the hardware when the
controller will access an EM page that is not
mapped according to the EM_MAPPING value.
When this bit is "1" then the BLE_ERROR_IRQ
will be asserted as long as EMACCERRMSK is
"1".
Table 116: BLE_EM_BASE_REG (0x40000208)

31:17 R - 0x0
16:10 R/W BLE_EM_BASE_16 The physical address on the system memory map 0x0
_10 of the base of the Exchange Memory.
9:0 R - 0x0
Table 117: BLE_DIAGCNTL2_REG (0x4000020C)

set to 0x0.
30 R - 0x0
set to 0x0.
22 R - 0x0
set to 0x0.
14 R - 0x0
13:8 R/W DIAG5 Only relevant when DIAG5_EN= 1. 0x0
set to 0x0.

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6 R - 0x0
Table 118: BLE_DIAGCNTL3_REG (0x40000210)

31 R/W DIAG7_INV If set, then the specific diagnostic bit will be 0x0
inverted.
30:28 R/W DIAG7_BIT Selects which bit from the DIAG7 word will be 0x0
forwarded to bit 7 of the BLE DIagnostic Port.
inverted.
inverted.
inverted.
inverted.
inverted.
inverted.
inverted.

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31.3 Clock Generation and Reset Registers
Table 119: Register map CRG

0x50000000 CLK_AMBA_REG HCLK, PCLK, divider and clock gates
0x50000002 CLK_FREQ_TRIM_RE Xtal frequency trimming register
G
0x50000004 CLK_PER_REG Peripheral divider register
0x50000008 CLK_RADIO_REG Radio PLL control register
0x5000000A CLK_CTRL_REG Clock control register
0x50000010 PMU_CTRL_REG Power Management Unit control register
0x50000012 SYS_CTRL_REG System Control register
0x50000014 SYS_STAT_REG System status register
0x50000016 TRIM_CTRL_REG Control trimming of the XTAL32M
0x50000018 RAM_PWR_CTRL_RE Control power state of System RAMS
G
0x50000020 CLK_RC32K_REG 32 kHz RC oscillator register
0x50000022 CLK_XTAL32K_REG 32 kHz XTAL oscillator register
0x50000024 CLK_RC32M_REG Fast RC control register
0x50000026 CLK_RCX_REG RCX-oscillator control register
0x50000028 BANDGAP_REG Bandgap trimming
0x5000002A ANA_STATUS_REG Status bit of analog (power management) circuits
0x50000030 XTAL32M_START_RE Trim values for XTAL32M
G
0x50000032 XTAL32M_TRSTAT_R Read back value of current XTAL trimming
EG
0x50000034 XTALRDY_CTRL_RE Control register for XTALRDY IRQ
G
0x50000038 XTAL32M_CTRL0_RE Control bits for XTAL32M
G
0x50000040 POR_PIN_REG Selects a GPIO pin for POR generation
0x50000042 POR_TIMER_REG Time for POR to happen
0x50000050 PMU_SLEEP_REG Bandgap refresh interval during sleep
0x50000052 POWER_CTRL_REG Power management control
0x50000054 POWER_LEVEL_REG Power management level and trim settings
Table 120: CLK_AMBA_REG (0x50000000)

7 R/W OTP_ENABLE Clock enable for OTP controller 0x0
6 R/W - 0x0

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5:4 R/W PCLK_DIV APB interface clock (PCLK). Divider is cascaded 0x0
with HCLK_DIV. PCLK is HCLK divided by:
0x0: divide by 1
0x1: divide by 2
0x2: divide by 4
0x3: divide by 8
3:2 R/W - 0x0
1:0 R/W HCLK_DIV AHB interface and microprocessor clock (HCLK). 0x0
HCLK is source clock divided by:
0x0: divide by 1
0x1: divide by 2
0x2: divide by 4
0x3: divide by 8
Table 121: CLK_FREQ_TRIM_REG (0x50000002)

7:0 R/W XTAL32M_TRIM Xtal frequency fine trimming register. 0x80
0x00: highest frequency
0xFF: lowest frequency
Table 122: CLK_PER_REG (0x50000004)

11 R/W QUAD_ENABLE Enable the Quadrature clock 0x1
10 R/W SPI_ENABLE Enable SPI clock 0x0
9:8 R/W - 0x0
7 R/W UART1_ENABLE Enable UART1 clock 0x0
6 R/W UART2_ENABLE Enable UART2 clock 0x0
5 R/W I2C_ENABLE Enable I2C clock 0x0
4 R/W WAKEUPCT_ENAB Enable Wakeup CaptureTimer clock 0x0
LE
3 R/W TMR_ENABLE Enable TIMER0 and TIMER2 clock 0x0
2 R/W - 0x0
1:0 R/W TMR_DIV Division factor for TIMER0 0x0
0x0: divide by 1
0x1: divide by 2
0x2: divide by 4
0x3: divide by 8

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Table 123: CLK_RADIO_REG (0x50000008)

15:8 - - 0x0
7 R/W BLE_ENABLE Enable the BLE core clocks 0x0
6 R/W BLE_LP_RESET Reset for the BLE LP timer 0x1
5:4 R/W BLE_DIV Division factor for BLE core blocks 0x0
0x0: divide by 1
0x1: divide by 2
0x2: divide by 4
0x3: divide by 8
The programmed frequency should not be lower
than 8 MHz and not faster than the programmed
CPU clock frequency. Refer also to
BLE_CNTL2_REG[BLE_CLK_SEL].
3 R/W RFCU_ENABLE Enable the RF control Unit clock 0x0
2 R/W - 0x0
1:0 R/W - 0x0
Table 124: CLK_CTRL_REG (0x5000000A)

7 R RUNNING_AT_XTA Indicates that the XTAL32M clock is used as 0x0
L32M clock, and may not be switched off
6 R RUNNING_AT_RC3 Indicates that the RC32M clock is used as clock 0x1
2M
5 R RUNNING_AT_LP_ Indicates that either the LP_CLK is being used as 0x0
CLK system clock
4:3 R/W LP_CLK_SEL Sets the clock source of the LowerPower clock 0x0
0x0: RC32K
0x1: RCX
0x2: XTAL32K through the oscillator with an
external Crystal.
0x3: XTAL32K through an external square wave
generator (set PID of P0[3] to FUNC_GPIO)
Change this setting before using this clock, and
while RUNNING_AT_LP_CLK == 0.
2 R/W XTAL32M_DISABL Setting this bit instantaneously disables the 32 0x0
E MHz crystal oscillator. Also, after sleep/wakeup
cycle, the oscillator will not be enabled. This bit
may not be set to '1'when
"RUNNING_AT_XTAL32M is '1' to prevent
deadlock. After resetting this bit, wait for
XTAL32M_SETTLED or XTAL32M_TRIM_READY
to become '1' before switching to XTAL32M clock
source.

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1:0 R/W SYS_CLK_SEL Selects the clock source. 0x1
0x0: XTAL32M (check the XTAL32M_SETTLED
and XTAL32M_TRIM_READY bits!!)
0x1: RC32M
0x2/0x3: LP_CLK
Table 125: PMU_CTRL_REG (0x50000010)

6 R/W MAP_BANDGAP_E Enable wakeup diagnostics mapping. When set, 0x0
N these functions are mapped (please set direction
to output)
P0[2]: BANDGAP_ENABLE
P0[1]: Power WOKENUP
Note: P0[2] assigned also to SWD_CLK, thus the
debugger must be detached before entering into
sleep mode with MAP_BANDGAP_EN=1. Refer
also to SYS_STAT_REG->DBG_IS_UP.
5:4 R/W OTP_COPY_DIV Sets the HCLK division during OTP mirroring 0x0
3 R/W - 0x0
2 R/W RADIO_SLEEP Put the digital part of the radio in powerdown 0x1
1 R/W TIM_SLEEP Put PD_TIM in powerdown 0x1
0 R/W RESET_ON_WAKE Perform a Hardware Reset after waking up. 0x0
UP Booter will be started.
Table 126: SYS_CTRL_REG (0x50000012)

15 W SW_RESET Writing a '1' to this bit will reset the device, except 0x0
for:
SYS_CTRL_REG
CLK_FREQ_TRIM_REG
...
10 R/W TIMEOUT_DISABL Disables timeout in Power statemachine. By 0x0
E default, the statemachine continues if after 2 ms
the blocks are not started up. This can be read
back from
ANA_STATUS_REG.
9 R/W - 0x0
8:7 R/W DEBUGGER_ENAB Enable the debugger. This bit is set by the booter 0x0
LE according to the OTP header. If not set, the
SWDIO and SW_CLK can be used as gpio ports.
0x0: no debugger enabled.
0x1: SW_CLK = P0[2], SW_DIO=P0[5]
0x2: SW_CLK = P0[2], SW_DIO=P0[1]
0x3: SW_CLK = P0[2], SW_DIO=P0[10]

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6 R/W OTPC_RESET_RE Reset request for the OTP controller. 0x0
Q
5 R/W - 0x1
4 R/W OTP_COPY Enables OTP to SysRAM copy action after waking 0x0
up PD_SYS
3 R/W - 0x0
2 R/W DEV_PHASE Sets the development phase mode. 0x0
If this bit is set, in combination with the

OTP_COPY bit, the OTP DMA will emulate the
OTP mirroring to System RAM.
No actual writing to RAM is done, but the exact
same amount of time is spend as if the mirroring
would take place. This is to mimic the behavior as
if the System Code is already in OTP, and the
mirroring takes place after waking up, but the
(development) code still resides in an external
source.
If this bit is set to '0' and OTP_COPY='1', then the
OTP DMA will actually do the OTP mirroring at
wakeup.
1:0 R/W REMAP_ADR0 Controls which memory is located at address 0x0
0x0000 for execution.
0x0: ROM
0x1: OTP
0x2: RAM (SysRAM1)
0x3: RAM (SysRAM3, 28 kBytes offset)
This bitfield only takes affect after a Software
Reset.
Table 127: SYS_STAT_REG (0x50000014)

7 R XTAL32M_SETTLE Indicates that XTAL32M has had its settle time, as 0x0
D defined by TRIM_CTRL_REG[XTAL_SETTLE_N]
6 R XTAL32M_TRIM_R Indicates that XTAL trimming mechanism is ready, 0x1
EADY i.e. the trimming equals CLK_FREQ_TRIM_REG.
5 R - 0x0
4 R DBG_IS_UP Indicates that the SW debugger is attached and in 0x0
connection with the Cortex.
3 R TIM_IS_UP Indicates that PD_TIM is functional 0x0
2 R TIM_IS_DOWN Indicates that PD_TIM is in power down 0x1
1 R RAD_IS_UP Indicates that PD_RAD is functional 0x0
0 R RAD_IS_DOWN Indicates that PD_RAD is in power down 0x1

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Table 128: TRIM_CTRL_REG (0x50000016)

13:8 R/W XTAL_SETTLE_N Designates that the XTAL can be safely used as 0x3F
the CPU clock. When XTAL_CLK_CNT reases
this value, the signal XTAL32M_SETTLED bit in
the SYS_STAT_REG will be set. Counts in steps
of 64 xtal clock-cycles.
7:6 R/W XTAL_TRIM_SELE Select which source controls the XTAL trimming 0x0
CT 0b00: xtal counter. Starts
XTAL32M_START_REG[XTAL32M_START] after
COUNT_N * 32 xtal pulses trim is changed to
CLK_FREQ_TRIM_REG[XTAL32M_TRIM].
0b01: xtal OK filter. Starts with
CLK_FREQ_TRIM_REG[XTAL32M_START],
when xtal amplitude is ramping is changed to
0b10: statically forced off. Only uses
0b11: xtal OK filter, 2 stage. Starts with
CLK_FREQ_TRIM_REG[XTAL32M_START]
switches to
CLK_FREQ_TRIM_REG[XTAL32M_RAMP] after
timeout (32us), and switches to
CLK_FREQ_TRIM_REG[XTAL32M_TRIM] when
xtal amplitude is ramping up.
5:0 R/W XTAL_COUNT_N Defines the number of XTAL cycles to be counted, 0x22
before the xtal trimming is applied, in steps of 64
cycles.
0x01: 64
0x02: 128
0x3f: 4032
Table 129: RAM_PWR_CTRL_REG (0x50000018)

5:4 R/W RAM3_PWR_CTRL See description of RAM1_PWR_CTRL. 0x0
3:2 R/W RAM2_PWR_CTRL See description of RAM1_PWR_CTRL. 0x0
1:0 R/W RAM1_PWR_CTRL Power state control of the individual RAMs. May 0x0
only change when the memory isn't accessed.
When in Active or Sleep mode:
0x0: Normal operation
0x1: Normal operation
0x2: Retained (no access possible)
0x3: Off (memory content corrupted)
When in Extended Sleep, Deep Sleep or
Hibernation mode
0x0: Retained
0x2: Retained

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Table 130: CLK_RC32K_REG (0x50000020)

4:1 R/W RC32K_TRIM 0000 = lowest frequency 0x7
0111 = default
1111 = highest frequency
0 R/W RC32K_DISABLE Instantly disables the 32kHz RC oscillator 0x0
Sleep cycles cannot happen with this clock
disabled.
Table 131: CLK_XTAL32K_REG (0x50000022)

8 - - 0x0
7 R/W XTAL32K_DISABLE Setting this bit disables the amplitude regulation of 0x0
_AMPREG the XTAL32kHz oscillator.
Set this bit to '1' for an external clock to
XTAL32Kp
Keep this bit '0' with a crystal between XTAL32Kp
and XTAL32Km
6:3 R/W XTAL32K_CUR Bias current for the 32kHz XTAL oscillator. 0000 is 0x5
minimum, 1111 is maximum, 0011 is default. For
each application there is an optimal setting for
which the start-up behavior is optimal
2:1 R/W XTAL32K_RBIAS Setting for the bias resistor. 00 is maximum, 11 is 0x3
minimum. Prefered setting will be provided by
Dialog
0 R/W XTAL32K_ENABLE Enables the 32kHz XTAL oscillator. 0x0
Also set GP_DATA_REG[P03_P04_FILT_DIS] = 1
for lowest current consumption.
Table 132: CLK_RC32M_REG (0x50000024)

10:7 R/W RC32M_COSC C-adjust of RC-oscillator 0xF
A higher value of COSC results in a lower
frequency
6:5 R/W RC32M_RANGE Coarse adjust 0x0
A higher value of RANGE results in a higher
frequency, values 2 and 3 are equal
4:1 R/W RC32M_BIAS Bias adjustment 0x7
0 R/W RC32M_DISABLE Instantly disables the 32MHz RC oscillator 0x0
Disabling of the oscillator during sleep happens
automatically.

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Table 133: CLK_RCX_REG (0x50000026)

11:8 R/W RCX_BIAS LDO bias current. 0xA
0x0: minimum
0xF: maximum
7 R/W RCX_C0 Add unit capacitance to RC-time delay. 0x1
6:2 R/W RCX_CADJUST Adjust capacitance part of RC-time delay. 0x1F
0x00: minimum capacitance
0x1F: maximum capacitance
1 R/W RCX_RADJUST Adjust resistance part of RC-time delay. Lower 0x0
resistance increases power consumption.
0x0: maximum resistance
0x1: minimum resistance
0 R/W RCX_ENABLE Enable the RCX oscillator 0x0
Table 134: BANDGAP_REG (0x50000028)

9:5 R/W BGR_ITRIM Trim setting for bandgap bias current 0x0
10000 -> -25%
....
11111 -> ~0%
00000 -> ~0% (typ)
...
01111 -> +32%
4:0 R/W BGR_TRIM Trim setting for bandgap voltage 0x0
10000 -> -6.4%
....
11111 -> ~0%
00000 -> ~0% (typ)
...
01111 -> +5.8%
Table 135: ANA_STATUS_REG (0x5000002A)

12 R CLKLESS_WAKEU Indicates the output of the Clockless wakeup XOR 0x0
P_STAT tree. If this signal is '0', the chip will wake up.
Use the HIBERN_WKUP_POLARITY bit to set the
value to '1' before going into hibernation mode.
11 - - 0x0
10 R LDO_GPADC_OK Indicates that LDO_GPADC output is OK 0x0
9 R LDO_XTAL_OK Indicates that LDO_XTAL output is OK 0x0

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8 R BOOST_SELECTE 0: Buck mode detected 0x0
D 1: Boost mode detected
7 R POR_VBAT_HIGH Output of VBAT_HIGH supply rail voltage monitoring 0x0
circuit.
0: Voltage level on VBAT_HIGH is lower than POR
VBAT_HIGH threshold VTH_L (rail not ok, will result
in reset if not masked)
1: Voltage level on VBAT_HIGH is higher than POR
VBAT_HIGH threshold VTH_H (rail ok, reset
released)
6 R POR_VBAT_LOW Output of VBAT_LOW supply rail voltage monitoring 0x0
circuit.
0: Voltage level on VBAT_LOW is lower than POR
VBAT_LOW threshold VTH_L (rail not ok, will result
in reset if not masked)
1: Voltage level on VBAT_LOW is higher than POR
VBAT_LOW threshold VTH_H (rail ok, reset
released)
5 R BANDGAP_OK Indicates that BANDGAP is OK 0x0
4 R COMP_VBAT_HIG Indicates that VBAT_HIGH < VBAT_LOW -50 mV 0x0
H_NOK
3 R COMP_VBAT_HIG Indicates that VBAT_HIGH > VBAT_LOW +50 mV 0x0
H_OK
2 R DCDC_OK Indicates that VBAT_LOW (buck mode) or VBAT_HIGH 0x0
(boost mode) is OK
1 R LDO_LOW_OK Indicates that LDO_LOW output is OK 0x0
(only valid for high current mode)
0 R LDO_CORE_OK Indicates that LDO_CORE output is OK 0x0
Table 136: XTAL32M_START_REG (0x50000030)

15:8 R/W XTAL32M_RAMP Xtal frequency trimming register. 0x0
0x00 : highest frequency
0xFF :lowest frequency
7:0 R/W XTAL32M_START Xtal frequency trimming register. 0xAA
0x0 = highest frequency
0xF = lowest frequency.
Table 137: XTALRDY_CTRL_REG (0x50000034)

7:0 R/W XTALRDY_CNT Number of 32kHz cycles between the crystal is 0x0
enabled, and the XTALRDY_IRQ is fired. 0x00: no
interrupt

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Table 138: XTAL32M_CTRL0_REG (0x50000038)

9:8 - - 0x0
7:5 R/W CORE_AMPL_TRIM Core amplitude trimming 0x0
4:2 R/W CORE_CUR_SET Core current trim setting 0x5
1 R/W CORE_AMPL_REG Keep bias in ampl detector alive, even when there 0x0
_NULLBIAS is a large drive
0 R/W DCBLOCK_ENABL Enable dcblock/high pass filter circuit 0x1
E
Table 139: POR_PIN_REG (0x50000040)

7 R/W POR_PIN_POLARI 0: Active Low 0x0
TY 1: Active High
Note: This applies only for the GPIO pin. Reset
pad has a fixed polarity
6:4 R/W - 0x0

3:0 R/W POR_PIN_SELECT Selects the GPIO which is used for POR 0x0
generation.
0x0: GPIO pin POReset disabled
0x1: P0_0
0x2: P0_1
...
0xB: P0_10
0xC: P0_11
0xD - 0xF: reserved
Table 140: POR_TIMER_REG (0x50000042)

6:0 R/W POR_TIME Time for the POReset to happen. 0x18
Formula:
Time = POR_TIME x 4096 x RC32k clock period
Default value: ~3 seconds
When set to 0x00, the POR TIMER is disabled.

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Table 141: PMU_SLEEP_REG (0x50000050)

11:0 R/W BG_REFRESH_INT Defines the refresh interval of reference voltages 0x80
ERVAL (bandgap activation and sampling), in units of
2ms.
Table 142: POWER_CTRL_REG (0x50000052)

15 R/W VBAT_HL_CONNE Sets the control mode fo the switch between 0x0
CT_MODE VBAT_HIGH and VBAT_LOW
0: Manual (default)
1: Automatic (boost mode only)
14 R/W POR_VBAT_HIGH_ 0: Hysteresis enabled 0x1
HYST_DIS 1: Hysteresis disabled
13 R/W POR_VBAT_HIGH_ 0: Low level selected 0x0
HYST_SEL 1: High level selected
12 R/W POR_VBAT_HIGH_ Disable por_vbat_high circuit 0x0
DISABLE
11 R/W POR_VBAT_LOW_ 0: Hysteresis enabled 0x0
HYST_DIS 1: Hysteresis disabled
10 R/W POR_VBAT_LOW_ 0: Low level selected 0x0
HYST_SEL 1: High level selected
9 R/W POR_VBAT_LOW_ Disable por_vbat_low circuit 0x0
DISABLE
8 R/W CP_DISABLE Disables LDO_CORE charge-pump circuit 0x0
7 R/W LDO_VREF_HOLD_ Forces LDO references in HOLD mode 0x0
FORCE
6:5 R/W LDO_LOW_CTRL_ 00: High-current mode in active, LDO_LOW OFF 0x0
REG in sleep
01: LDO_LOW OFF
10: Low-current mode in active, Low-current mode
in sleep
11: High-current mode in active, Low-current
mode in sleep
4 R/W LDO_CORE_DISAB Disables LDO_CORE 0x0
LE
3 R/W LDO_CORE_RET_ LDO_CORE_RETENTION 0x0
ENABLE 0: Disabled
1: Enabled
2 R/W VBAT_HL_CONNE Switch between VBAT_HIGH and VBAT_LOW 0x0
CT 0: Open
1: Closed
1 R/W CMP_VBAT_HIGH_ Enable cmp_vbat_high_ok 0x0
OK_ENABLE

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0 R/W CMP_VBAT_HIGH_ Enable cmp_vbat_high_nok 0x0
NOK_ENABLE
Table 143: POWER_LEVEL_REG (0x50000054)

13:11 R/W DCDC_TRIM Delta from DCDC_LEVEL nominal value 0x3
000: -75 mV
001: -50 mV
010: -25 mV
011: 0 (default)
100: +25 mV
101: +50 mV
110: +75 mV
111: +100 mV
10:9 R/W DCDC_LEVEL 00: 1.1 V 0x1
01: 1.8 V (default)
10: 2.5 V
11: 3.0 V
8:7 - - 0x0
6:4 R/W LDO_XTAL_TRIM Delta from 0.9 V nominal value 0x3
000: -75 mV
001: -50 mV
010: -25 mV
011: 0 (default)
100: +25 mV
101: +50 mV
110: +75 mV
111: +100 mV
3:1 R/W LDO_LOW_TRIM Delta from 1.1 V nominal value 0x7
000: -75 mV
001: -50 mV
010: -25 mV
011: 0 (default)
100: +25 mV
101: +50 mV
110: +75 mV
111: +100 mV (coldboot)
0 - - 0x0
Table 144: XTAL32M_TRSTAT_REG (0x50000032)

7:0 R XTAL32M_TRSTAT Reads value of the current XTAL trimming 0x0

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Table 145: Register map crg2632_preg_tim_00

0x5000424C CLK_RTCDIV_REG Divisor for RTC 100Hz clock
Table 146: CLK_RTCDIV_REG (0x5000424C)

21 R/W RTC_RESET_REQ Reset request for the RTC module 0x0
20 R/W RTC_DIV_ENABLE Enable for the 100 Hz generation for the RTC 0x0
block
19 R/W RTC_DIV_DENOM Selects the denominator for the fractional division: 0x0
0b0: 1000
0b1: 1024
18:10 R/W RTC_DIV_INT Integer divisor part for RTC 100Hz generation 0x147
9:0 R/W RTC_DIV_FRAC Fractional divisor part for RTC 100Hz generation. 0x2A8
if RTC_DIV_DENOM=1, <RTC_DIV_FRAC> out
of 1024 cycles will divide by <RTC_DIV_INT+1>,
the rest is <RTC_DIV_INT>
If RTC_DIV_DENOM=0, <RTC_DIV_FRAC> out
of 1000 cycles will divide by <RTC_DIV_INT+1>,
the rest is <RTC_DIV_INT>

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31.4 DCDC Converter Registers
Table 147: Register map crg2632_dcdc_dig_00

0x50000080 DCDC_CTRL_REG
Table 148: DCDC_CTRL_REG (0x50000080)

15:12 R/W DCDC_ILIM_MAX Maximum value for automatic inductor peak 0x8
current limit control.
0x0: 6 mA
0x1: 12 mA
0x2: 18 mA
0x3: 24 mA
0x4: 30 mA
0x5: 36 mA
0x6: 42 mA
0x7: 48 mA
0x8: 54 mA (default, limits inrush current)
0x9: 60 mA
0xA: 66 mA
0xB: 72 mA
0xC: 78 mA
0xD: 84 mA
0xE: 90 mA
0xF: 96 mA (set as default for low-ohmic batteries)
11:8 R/W DCDC_ILIM_MIN Minimum value for automatic inductor peak 0x4
current limit control.
0x0: 6 mA
0x1: 12 mA
0x2: 18 mA
0x3: 24 mA
0x4: 30 mA (default)
0x5: 36 mA
0x6: 42 mA
0x7: 48 mA
0x8: 54 mA
0x9: 60 mA
0xA: 66 mA
0xB: 72 mA
0xC: 78 mA
0xD: 84 mA
0xE: 90 mA
0xF: 96 mA

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7:6 R/W DCDC_OK_CLR_C Number of subsequent V_NOK events needed to 0x2
NT reset VDCD_OK.
0x0: 2
0x1: 4
0x2: 8 (deafult)
0x3: 15
5:3 R/W DCDC_TIMEOUT Switch timeout, go to next state if either switch is 0x4
active for longer than this setting.
0x0: Disabled
0x1: 0.25 μs
0x2: 0.50 μs
0x3: 0. 5 μs
0x4: 1.00 μs (default)
0x5: 1.25 μs
0x6: 1.50 μs
0x : 1. 5 μs
2:1 R/W DCDC_CLK_DIV Idle clock divider, sets rate at which the output is 0x1
monitored when the converter is idle.
0x0: Divide by 4
0x1: Divide by 8
0x2: Divide by 16
0x3: Divide by 32
0 R/W DCDC_ENABLE Enables hardware control of the DCDC converter. 0x0
0: DCDC converter disabled
1: DCDC converter under hardware control

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31.5 DMA Controller Registers
Table 149: Register map DMA

0x50003600 DMA0_A_STARTL_R Start address Low A of DMA channel 0
EG
0x50003602 DMA0_A_STARTH_R Start address High A of DMA channel 0
EG
0x50003604 DMA0_B_STARTL_R Start address Low B of DMA channel 0
EG
0x50003606 DMA0_B_STARTH_R Start address High B of DMA channel 0
EG
0x50003608 DMA0_INT_REG DMA receive interrupt register channel 0
0x5000360A DMA0_LEN_REG DMA receive length register channel 0
0x5000360C DMA0_CTRL_REG Control register for the DMA channel 0
0x5000360E DMA0_IDX_REG Index value of DMA channel 0
EG
EG
EG
EG
EG
EG
EG
EG
EG
EG

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EG
EG
0x50003680 DMA_REQ_MUX_RE DMA channel assignments
G
0x50003682 DMA_INT_STATUS_R DMA interrupt status register
EG
0x50003684 DMA_CLEAR_INT_RE DMA clear interrupt register
G
Table 150: DMA0_A_STARTL_REG (0x50003600)

15:0 R/W DMA0_A_STARTL Source start address, lower 16 bits 0x0
Table 151: DMA0_A_STARTH_REG (0x50003602)

15:0 R/W DMA0_A_STARTH Source start address, upper 16 bits 0x0
Table 152: DMA0_B_STARTL_REG (0x50003604)

15:0 R/W DMA0_B_STARTL Destination start address, lower 16 bits 0x0
Table 153: DMA0_B_STARTH_REG (0x50003606)

15:0 R/W DMA0_B_STARTH Destination start address, upper 16 bits 0x0

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Table 154: DMA0_INT_REG (0x50003608)

15:0 R/W DMA0_INT Number of transfers until an interrupt is generated. 0x0
The interrupt is generated after a transfer, if
DMAx_INT_REG is equal to DMAx_IDX_REG and
before DMAx_IDX_REG is incremented. The bit-
field IRQ_ENABLE of DMAx_CTRL_REG must be
set to '1' to let the controller generate the interrupt.
Table 155: DMA0_LEN_REG (0x5000360A)

15:0 R/W DMA0_LEN DMA channel's transfer length. DMAx_LEN of 0x0
value 0, 1, 2, ... results into an actual transfer
length of 1, 2, 3, ...
Table 156: DMA0_CTRL_REG (0x5000360C)

15:14 R - 0x0
13 R/W REQ_SENSE 0 = DMA operates with level-sensitive peripheral 0x0
requests (default)
1 = DMA operates with (positive) edge-sensitive
peripheral requests
12 R/W DMA_INIT 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 0x0
1 = DMA performs copy of A1 to B1, B2, etc ...
This feature is useful for memory initialization to
any value. Thus, BINC must be set to '1', while
AINC is don't care, as only one fetch from A is
done. This process cannot be interrupted by other
DMA channels. It is also noted that DMA_INIT
should not be used when DREQ_MODE='1'.
11 R/W DMA_IDLE 0 = Blocking mode, the DMA performs a fast back- 0x0
to-back copy, disabling bus access for any bus
master with lower priority.
1 = Interrupting mode, the DMA inserts a wait
cycle after each store allowing the CPU to steal
cycles or cache to perform a burst read. If
DREQ_MODE='1', DMA_IDLE is don't care.

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10:8 R/W DMA_PRIO The priority level determines which DMA channel 0x0
will be granted access for transferring data, in
case more than one channels are active and
request the bus at the same time. The greater the
value, the higher the priority. In specific:
000 = lowest priority
111 = highest priority
If different channels with equal priority level values
request the bus at the same time, an inherent
priority mechanism is applied. According to this
mechanism, if, for example, both the DMA0 and
DMA1 channels have the same priority level, then
DMA0 will first be granted access to the bus.
7 R/W CIRCULAR 0 = Normal mode. The DMA channel stops after 0x0
having completed the transfer of length
determined by DMAx_LEN_REG. DMA_ON
automatically deasserts when the transfer is
completed.
1 = Circular mode (applicable only if
DREQ_MODE = '1'). In this mode, DMA_ON
never deasserts, as the DMA channel
automatically resets DMAx_IDX_REG and starts a
new transfer.
6 R/W AINC Enable increment of source address. 0x0
0 = do not increment (source address stays the
same during the transfer)
1 = increment according to the value of BW bit-
field (by 1, when BW="00" ; by 2, when BW="01" ;
by 4, when BW="10")
5 R/W BINC Enable increment of destination address. 0x0
0 = do not increment (destination address stays
the same during the transfer)
by 4, when BW="10")
4 R/W DREQ_MODE 0 = DMA channel starts immediately 0x0
1 = DMA channel must be triggered by peripheral
DMA request (see also the description of
DMA_REQ_MUX_REG)
3 R/W IRQ_ENABLE 0 = disable interrupt on this channel 0x0
1 = enable interrupt on this channel
2:1 R/W BW Bus transfer width: 0x0
00 = 1 Byte (suggested for peripherals like UART
and 8-bit SPI)
01 = 2 Bytes (suggested for peripherals like I2C
and 16-bit SPI)
10 = 4 Bytes (suggested for Memory-to-Memory
transfers)
11 = Reserved
0 R/W DMA_ON 0 = DMA channel is off, clocks are disabled 0x0
1 = DMA channel is enabled. This bit will be
automatically cleared after the completion of a
transfer, if circular mode is not enabled. In circular
mode, this bit stays set.

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Table 157: DMA0_IDX_REG (0x5000360E)

15:0 R DMA0_IDX This (read-only) register determines the data items 0x0
currently fetched by the DMA channel, during an
on-going transfer. When the transfer is completed,
the register is automatically reset to 0.
The DMA channel uses this register to form the
source/destination address of the next DMA cycle,
considering also AINC/BINC and BW.






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length of 1, 2, 3, ...

15:14 R - 0x0
requests (default)
peripheral requests

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completed.
new transfer.
by 4, when BW="10")
by 4, when BW="10")
DMA_REQ_MUX_REG)
and 8-bit SPI)
and 16-bit SPI)
transfers)
11 = Reserved

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length of 1, 2, 3, ...

15:14 R - 0x0
requests (default)
peripheral requests
completed.
new transfer.

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6 R/W AINC Enable increment of destination address. 0x0
by 4, when BW="10")
5 R/W BINC Enable increment of destination address 0x0
0 = do not increment
1 = increment according value of BW
DMA_REQ_MUX_REG)
and 8-bit SPI)
and 16-bit SPI)
transfers)
11 = Reserved



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length of 1, 2, 3, ...

15:14 R - 0x0
requests (default)
peripheral requests

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completed.
new transfer.
by 4, when BW="10")
by 4, when BW="10")
DMA_REQ_MUX_REG)

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and 8-bit SPI)
and 16-bit SPI)
transfers)
11 = Reserved

Table 182: DMA_REQ_MUX_REG (0x50003680)

15:12 R/W - 0xF
11:8 R/W - 0xF
7:4 R/W DMA23_SEL Select which combination of peripherals are 0xF
mapped on the DMA channels. The peripherals
are mapped as pairs on two channels.
Hence, the first DMA request (peripheral-to-
memory) is mapped on channel 2 and the second
(memory-to-peripheral) on channel 3.
See also the description of DMA01_SEL bit-field
of this register for the supported peripherals.

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3:0 R/W DMA01_SEL Select which combination of peripherals are 0xF
mapped on the DMA channels. The peripherals
are mapped as pairs on two channels.
Hence, the first DMA request (peripheral-to-
memory) is mapped on channel 0 and the second
(memory-to-peripheral) on channel 1.
0x0: SPI_rx / SPI_tx
0x1: Reserved
0x2: UART_rx / UART_tx
0x3: UART2_rx / UART2_tx
0x4: I2C_rx / I2C_tx
0x5: GP_ADC (Rx only)
0x6-0xE: Reserved
0xF: None
Note: If any of the two available peripheral

selector fields (DMA01_SEL, DMA23_SEL) have
the same value, the lesser significant selector has
higher priority and will control the dma
acknowledge. Hence, if DMA01_SEL =
DMA23_SEL, the channels 0 and 1 will generate
the DMA acknowledge signals for the selected
peripheral. Consequently, it is suggested to assign
the intended peripheral value to a unique selector
field.
Table 183: DMA_INT_STATUS_REG (0x50003682)

15:8 R - 0x0
7 R - 0x0
6 R - 0x0
5 R - 0x0
4 R - 0x0
3 R DMA_IRQ_CH3 0: IRQ on channel 3 is not set 0x0
1: IRQ on channel 3 is set

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Table 184: DMA_CLEAR_INT_REG (0x50003684)

15:8 R - 0x0
7 R - 0x0
6 R - 0x0
5 R - 0x0
4 R - 0x0
3 R0/W DMA_RST_IRQ_CH Writing a 1 will reset the status bit of 0x0
3 DMA_INT_STATUS_REG for channel 3 ; writing a
0 will have no effect

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31.6 General Purpose ADC Registers
Table 185: Register map GPADC

0x50001500 GP_ADC_CTRL_REG General Purpose ADC Control Register
0x50001502 GP_ADC_CTRL2_RE General Purpose ADC Second Control Register
G
0x50001504 GP_ADC_CTRL3_RE General Purpose ADC Third Control Register
G
0x50001506 GP_ADC_SEL_REG General Purpose ADC Input Selection Register
0x50001508 GP_ADC_OFFP_REG General Purpose ADC Positive Offset Register
0x5000150A GP_ADC_OFFN_REG General Purpose ADC Negative Offset Register
0x5000150C GP_ADC_TRIM_REG General Purpose ADC Trim Register
0x5000150E GP_ADC_CLEAR_INT General Purpose ADC Clear Interrupt Register
_REG
0x50001510 GP_ADC_RESULT_R General Purpose ADC Result Register
EG
Table 186: GP_ADC_CTRL_REG (0x50001500)

12 R/W DIE_TEMP_EN Enables the die-temperature sensor. Output can 0x0
be measured on GPADC input 4.
11 - - 0x0
10 R/W GP_ADC_LDO_HO 0: GPADC LDO tracking bandgap reference 0x0
LD 1: GPADC LDO hold sampled bandgap reference
9 R/W GP_ADC_CHOP 0: Chopper mode off 0x0
1: Chopper mode enabled. Takes two samples
with opposite GP_ADC_SIGN to cancel the
internal offset voltage of the ADC; Highly
recommended for DC-measurements.
8 R/W GP_ADC_SIGN 0: Default 0x0
1: Conversion with opposite sign at input and
output to cancel out the internal offset of the ADC
and low-frequency
7 R/W GP_ADC_MUTE 0: Normal operation 0x0
1: Mute ADC input. Takes sample at mid-scale (to
dertermine the internal offset and/or noise of the
ADC with regards to VDD_REF which is also
sampled by the ADC).
6 R/W GP_ADC_SE 0: Differential mode 0x0
1: Single ended mode
5 R/W GP_ADC_MINT 0: Disable (mask) GP_ADC_INT. 0x0
1: Enable GP_ADC_INT to ICU.

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4 R GP_ADC_INT 1: AD conversion ready and has generated an 0x0
interrupt. Must be cleared by writing any value to
GP_ADC_CLEAR_INT_REG.
3 R/W GP_ADC_DMA_EN 0: DMA functionality disabled 0x0
1: DMA functionality enabled
2 R/W GP_ADC_CONT 0: Manual ADC mode, a single result will be 0x0
generated after setting the GP_ADC_START bit.
1: Continuous ADC mode, new ADC results will be
constantly stored in GP_ADC_RESULT_REG. Still
GP_ADC_START has to be set to start the
execution. The time between conversions is
configurable with GP_ADC_INTERVAL.
1 R/W GP_ADC_START 0: ADC conversion ready. 0x0
1: If a 1 is written, the ADC starts a conversion.
After the conversion this bit will be set to 0 and the
GP_ADC_INT bit will be set. It is not allowed to
write this bit while it is not (yet) zero.
0 R/W GP_ADC_EN 0: LDO is off and ADC is disabled.. 0x0
1: LDO is turned on and afterwards the ADC is
enabled.
Table 187: GP_ADC_CTRL2_REG (0x50001502)

15:13 R/W GP_ADC_STORE_ 0: Data is stored after handshake synchronisation 0x0
DEL 1: Data is stored 2 ADC_CLK cycles after internal
start trigger
7: Data is stored 8 ADC_CLK cycles after internal
start trigger
12:9 R/W GP_ADC_SMPL_TI 0: The sample time (switch is closed) is two 0x1
ME ADC_CLK cycles
1: The sample time is 1*8 ADC_CLK cycles
8:6 R/W GP_ADC_CONV_N 0: 1 sample is taken or 2 in case ADC_CHOP is 0x0
RS active.
1: 2 samples are taken.
5:4 R/W GP_ADC_OFFS_S Common mode adjust for offset shifter. Input 0x1
H_CM range is CM +/- 450mV.
0: CM = 1.25V (Input range 0.80 - 1.70)
1: CM = 1.30V (Input range 0.85 - 1.75) (default)
2: CM = 1.35V (Input range 0.90 - 1.80)
3: CM = 1.40V (input range 0.95 - 1.85)
3 R/W GP_ADC_OFFS_S 0: Disable input shifter 0x0
H_EN 1: Enable input shifter (900mV - 1800mV shifted to
0mV - 900mV)

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2 R/W GP_ADC_I20U 1: Adds 20uA constant load current at the ADC 0x0
LDO to minimize ripple on the reference voltage of
the ADC.
1:0 R/W GP_ADC_ATTN 0: No attenuator (input voltages up to 0.9V 0x0
allowed)
1: Enabling 2x attenuator (input voltages up to
1.8V allowed)
2.7V allowed)
3.6V allowed)
Enabling the attenuator requires a longer sampling
time.
Table 188: GP_ADC_CTRL3_REG (0x50001504)

15:8 R/W GP_ADC_INTERVA Defines the interval between two ADC 0x0
L conversions in case GP_ADC_CONT is set.
0: No extra delay between two conversions.
1: 1.024 ms interval between two conversions.
7:0 R/W GP_ADC_EN_DEL Defines the delay for enabling the ADC after 0x40
enabling the LDO.
0: Not allowed
1: 4x ADC_CLK period.
n: n*4x ADC_CLK period.
Table 189: GP_ADC_OFFP_REG (0x50001508)

9:0 R/W GP_ADC_OFFP Offset adjust of 'positive' array of ADC-network 0x200
(effective if "GP_ADC_SE=0", or "GP_ADC_SE=1
AND GP_ADC_SIGN=0 OR GP_ADC_CHOP=1")
Table 190: GP_ADC_OFFN_REG (0x5000150A)

9:0 R/W GP_ADC_OFFN Offset adjust of 'negative' array of ADC-network 0x200
(effective if "GP_ADC_SE=0", or "GP_ADC_SE=1
AND GP_ADC_SIGN=1 OR GP_ADC_CHOP=1")

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Table 191: GP_ADC_TRIM_REG (0x5000150C)

6:4 R/W GP_ADC_LDO_LEV GPADC LDO level 0x3
EL 0: 825mV
1: 850mV
2: 875mV
3: 900mV (reset)
4: 925mV (default)
5: 950mV
6: 975mV
7:1000mV
3:0 R/W GP_ADC_OFFS_S Offset Shifter common-mode reference fine 0x8
H_VREF trimming: 2mV/LSB
Default = mid-scale at 1000
Table 192: GP_ADC_CLEAR_INT_REG (0x5000150E)

15:0 R0/W GP_ADC_CLR_INT Writing any value to this register will clear the 0x0
ADC_INT interrupt. Reading returns 0.
Table 193: GP_ADC_RESULT_REG (0x50001510)

15:0 R GP_ADC_VAL Returns the 10 up to 16 bits linear value of the last 0x0
AD conversion. The upper 10 bits are always
valid, the lower 6 bits are only valid in case
oversampling has been applied. Two samples
results in one extra bit and 64 samples results in
six extra bits.
Table 194: GP_ADC_SEL_REG (0x50001506)

7 - - 0x0
6:4 R/W GP_ADC_SEL_P ADC positive input selection. 0x0
0: ADC0 (P0[1])
1: ADC1 (P0[2])
2: ADC2 (P0[6])
3: ADC3 (P0[7])
4: Temperature Sensor
5: VBAT_HIGH
6: VBAT_LOW
7: VDDD

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3 - - 0x0
2:0 R/W GP_ADC_SEL_N ADC negative input selection. Differential only 0x0
(GP_ADC_SE=0).
0: ADC0 (P0[1])
1: ADC1 (P0[2])
2: ADC2 (P0[6])
3: ADC3 (P0[7])
All other combinations are reserved.

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31.7 General Purpose I/O Registers
Table 195: Register map GPIO

0x50003000 P0_DATA_REG P0 Data input/output Register
0x50003002 P0_SET_DATA_REG P0 Set port pins Register
0x50003004 P0_RESET_DATA_RE P0 Reset port pins Register
G
0x50003006 P00_MODE_REG P00 Mode Register
0x5000300A P02_MODE_REG P02 Mode Register
0x5000300C P03_MODE_REG P03 Mode Register
0x5000300E P04_MODE_REG P04 Mode Register
0x5000301A P010_MODE_REG P010 Mode Register
0x5000301C P011_MODE_REG P011 Mode Register
0x5000301E PAD_WEAK_CTRL_R Pad driving strength control Register
EG
Table 196: P0_DATA_REG (0x50003000)

15:12 - - 0x0
11:0 R/W P0_DATA Sets P0 output register when written ; Returns the 0x0
value of P0 port when read
Table 197: P0_SET_DATA_REG (0x50003002)

15:12 - - 0x0
11:0 R0/W P0_SET Writing a 1 to P0[x] sets P0[x] to 1. 0x0
Writing 0 is discarded, reading returns 0

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Table 198: P0_RESET_DATA_REG (0x50003004)

15:12 - - 0x0
11:0 R0/W P0_RESET Writing a 1 to P0[x] sets P0[x] to 0. 0x0
Writing 0 is discarded, reading returns 0.
Table 199: P00_MODE_REG (0x50003006)

15:10 - - 0x0
9:8 R/W PUPD 00 = Input, no resistors selected 0x2
01 = Input, pull-up selected
10 = Input, pull-down selected
11 = Output, no resistors selected
In ADC mode, these bits are don't care
7:5 - - 0x0

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4:0 R/W PID Function of port 0x0
0 = GPIO (pin direction determined by "PUPD"
field)
1 = UART1_RX
2 = UART1_TX
3 = UART2_RX
4 = UART2_TX
5 = SYS_CLK
6 = LP_CLK
7 = Reserved
8 = Reserved
9 = I2C_SCL
10 = I2C_SDA
11 = PWM5
12 = PWM6
13 = PWM7
14 = Reserved
15 = ADC (only for P0_1, P0_2, P0_6 and P0_7)
16 = PWM0
17 = PWM1
18 = BLE_DIAG (signals mapped to P0[3:0] are
also mapped to P0[11:8])
19 = UART1_CTSN
20 = UART1_RTSN
21 = Reserved
22 = Reserved
23 = PWM2
24 = PWM3
25 = PWM4
26 = SPI_DI
27 = SPI_DO
28 = SPI_CLK
29 = SPI_CSN0
30 = SPI_CSN1
31 = Reserved
Note: When a certain input function (like SPI_DI)
is selected on more than 1 pins, the pin of the
lowest index has the highest priority.
Table 200: P01_MODE_REG (0x50003008)

15:10 - - 0x0

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7:5 - - 0x0
4:0 R/W PID See P00_MODE_REG[PID] 0x0
Table 201: P02_MODE_REG (0x5000300A)

15:10 - - 0x0
7:5 - - 0x0
Table 202: P03_MODE_REG (0x5000300C)

15:10 - - 0x0
7:5 - - 0x0
Table 203: P04_MODE_REG (0x5000300E)

15:10 - - 0x0

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7:5 - - 0x0
Table 204: P05_MODE_REG (0x50003010)

15:10 - - 0x0
7:5 - - 0x0
Table 205: P06_MODE_REG (0x50003012)

15:10 - - 0x0
7:5 - - 0x0
Table 206: P07_MODE_REG (0x50003014)

15:10 - - 0x0
7:5 - - 0x0

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Table 207: P08_MODE_REG (0x50003016)

15:10 - - 0x0
7:5 - - 0x0
Table 208: P09_MODE_REG (0x50003018)

15:10 - - 0x0
7:5 - - 0x0
Table 209: P010_MODE_REG (0x5000301A)

15:10 - - 0x0
7:5 - - 0x0
Table 210: P011_MODE_REG (0x5000301C)

15:10 - - 0x0
7:5 - - 0x0

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Table 211: PAD_WEAK_CTRL_REG (0x5000301E)

15:12 - - 0x0
11:0 R/W PAD_LOW_DRV 0 = Normal operation 0x0
1 = Reduces the driving strength of P0_x pad.
Bit x controls the driving strength of P0_x, x=0,
1,..., 11.

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31.8 General Purpose Registers
Table 212: Register map GPREG

0x50003300 SET_FREEZE_REG Controls freezing of various timers/counters.
0x50003302 RESET_FREEZE_RE Controls unfreezing of various timers/counters.
G
0x50003304 DEBUG_REG Various debug information register.
0x50003306 GP_STATUS_REG General purpose system status register.
0x50003308 GP_CONTROL_REG General purpose system control register.
0x5000330A BLE_TIMER_REG BLE FINECNT sampled value while in deep sleep state.
Table 213: SET_FREEZE_REG (0x50003300)

15:5 - - 0x0
4 R/W FRZ_DMA If '1', the DMA is frozen, '0' is discarded. 0x0
3 R/W FRZ_WDOG If '1', the watchdog timer is frozen, '0' is discarded. 0x0
WATCHDOG_CTRL_REG[NMI_RST] must be '0'
to allow the freeze function.
2 R/W FRZ_BLETIM If '1', the BLE master clock is frozen, '0' is 0x0
discarded.
1 R/W FRZ_SWTIM If '1', the SW Timer (TIMER0) is frozen, '0' is 0x0
discarded.
0 R/W FRZ_WKUPTIM If '1', the Wake Up Timer is frozen, '0' is discarded. 0x0
Table 214: RESET_FREEZE_REG (0x50003302)

15:5 - - 0x0
4 R/W FRZ_DMA If '1', the DMA continues, '0' is discarded. 0x0
3 R/W FRZ_WDOG If '1', the watchdog timer continues, '0' is 0x0
discarded.
2 R/W FRZ_BLETIM If '1', the the BLE master clock continues, '0' is 0x0
discarded.
1 R/W FRZ_SWTIM If '1', the SW Timer (TIMER0) continues, '0' is 0x0
discarded.
0 R/W FRZ_WKUPTIM If '1', the Wake Up Timer continues, '0' is 0x0
discarded.

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Table 215: DEBUG_REG (0x50003304)

15:1 R/W - 0x0
0 R/W DEBUGS_FREEZE Default '1', freezing of the on-chip timers is 0x1
_EN enabled when the Cortex is halted in DEBUG
State.
If '0', freezing of the on-chip timers is depending
on FREEZE_REG when the Cortex is halted in
DEBUG State except the watchdog timer. The
watchdog timer is always frozen when the Cortex
is halted in DEBUG State.
Table 216: GP_STATUS_REG (0x50003306)

15:2 - - 0x0
1 R/W - 0x0
0 R/W CAL_PHASE If '1', it designates that the chip is in Calibration 0x0
Phase i.e. the OTP has been initially programmed
but no Calibration has occured.
Table 217: GP_CONTROL_REG (0x50003308)

15:7 - - 0x0
6:5 R/W BLE_TIMER_DATA Refer to BLE_TIMER_REG. 0x0
_CTRL
4 R/W CPU_DMA_BUS_P Controls the CPU DMA system bus priority: 0x0
RIO If '0', the CPU has highest priority.
If '1', the DMA has highest priority.
3 - - 0x0
2 R BLE_WAKEUP_LP_ The current value of the BLE_WAKEUP_LP_IRQ 0x0
IRQ interrupt request.
1 - - 0x0
0 R/W BLE_WAKEUP_RE If '1', the BLE wakes up. Must be kept high at least 0x0
Q for 1 low power clock period.
If the BLE is in deep sleep state, then by setting
this bit it will cause the wakeup LP IRQ to be
asserted with a delay of 3 to 4 low power cycles.
Table 218: BLE_TIMER_REG (0x5000330A)

15:10 - - 0x0

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9:0 R/W BLE_TIMER_DATA Operation depends on GP_CONTROL_REG- 0x0
>BLE_TIMER_DATA_CTRL.
If BLE_TIMER_DATA_CTRL = 0 then:
This register is located at the Always On Power
Domain and it holds the automatically sampled
value of the BLE FINECNT timer
The HW automatically samples the value into this
register during the sequence of "BLE Sleep On"
and restores automatically the value during the
BLE Wake up sequence.
The Software may read and modify the value
while the BLE is in Sleep state. While the BLE is
awake, the value of the register has no meaning,
while changing the value by writing another one
will have no effect in the operation of the BLE
core.
There is a constraint when the SW performs an
write-read sequence where it has to inject a one
cycle delay in between (e.g. write-NOP-read) in
order to read back the correct value.
If BLE_TIMER_DATA_CTRL is non 0 then write
operations have the same effect as when
BLE_TIMER_DATA_CTRL=0, while for read
operations:
BLE_TIMER_DATA_CTRL= 1: then reading
BLE_TIMER_REG returns "deepsldur[9:0]".
BLE_TIMER_REG returns
"deepsltime_samp[9:0]".
BLE_TIMER_REG returns
"{deep_sleep_stat_monitor,
deepsltime_samp[18:10]}.
.

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31.9 I2C Interface Registers
Table 219: Register map I2C

0x50001300 I2C_CON_REG I2C Control Register
0x50001304 I2C_TAR_REG I2C Target Address Register
0x50001308 I2C_SAR_REG I2C Slave Address Register
0x50001310 I2C_DATA_CMD_RE I2C Rx/Tx Data Buffer and Command Register
G
0x50001314 I2C_SS_SCL_HCNT_ Standard Speed I2C Clock SCL High Count Register
REG
0x50001318 I2C_SS_SCL_LCNT_ Standard Speed I2C Clock SCL Low Count Register
REG
0x5000131C I2C_FS_SCL_HCNT_ Fast Speed I2C Clock SCL High Count Register
REG
0x50001320 I2C_FS_SCL_LCNT_ Fast Speed I2C Clock SCL Low Count Register
REG
0x5000132C I2C_INTR_STAT_REG I2C Interrupt Status Register
0x50001330 I2C_INTR_MASK_RE I2C Interrupt Mask Register
G
0x50001334 I2C_RAW_INTR_STA I2C Raw Interrupt Status Register
T_REG
0x50001338 I2C_RX_TL_REG I2C Receive FIFO Threshold Register
0x5000133C I2C_TX_TL_REG I2C Transmit FIFO Threshold Register
0x50001340 I2C_CLR_INTR_REG Clear Combined and Individual Interrupt Register
0x50001344 I2C_CLR_RX_UNDER Clear RX_UNDER Interrupt Register
_REG
0x50001348 I2C_CLR_RX_OVER_ Clear RX_OVER Interrupt Register
REG
0x5000134C I2C_CLR_TX_OVER_ Clear TX_OVER Interrupt Register
REG
0x50001350 I2C_CLR_RD_REQ_R Clear RD_REQ Interrupt Register
EG
0x50001354 I2C_CLR_TX_ABRT_ Clear TX_ABRT Interrupt Register
REG
0x50001358 I2C_CLR_RX_DONE_ Clear RX_DONE Interrupt Register
REG
0x5000135C I2C_CLR_ACTIVITY_ Clear ACTIVITY Interrupt Register
REG
0x50001360 I2C_CLR_STOP_DET Clear STOP_DET Interrupt Register
_REG
0x50001364 I2C_CLR_START_DE Clear START_DET Interrupt Register
T_REG
0x50001368 I2C_CLR_GEN_CALL Clear GEN_CALL Interrupt Register
_REG

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0x5000136C I2C_ENABLE_REG I2C Enable Register
0x50001370 I2C_STATUS_REG I2C Status Register
0x50001374 I2C_TXFLR_REG I2C Transmit FIFO Level Register
0x50001378 I2C_RXFLR_REG I2C Receive FIFO Level Register
0x5000137C I2C_SDA_HOLD_REG I2C SDA Hold Time Length Register
0x50001380 I2C_TX_ABRT_SOUR I2C Transmit Abort Source Register
CE_REG
0x50001388 I2C_DMA_CR_REG DMA Control Register
0x5000138C I2C_DMA_TDLR_REG DMA Transmit Data Level Register
0x50001390 I2C_DMA_RDLR_RE I2C Receive Data Level Register
G
0x50001394 I2C_SDA_SETUP_RE I2C SDA Setup Register
G
0x50001398 I2C_ACK_GENERAL_ I2C ACK General Call Register
CALL_REG
0x5000139C I2C_ENABLE_STATU I2C Enable Status Register
S_REG
0x500013A0 I2C_IC_FS_SPKLEN_ I2C SS and FS spike suppression limit Size
REG
Table 220: I2C_CON_REG (0x50001300)

15:7 - - 0x0
6 R/W I2C_SLAVE_DISAB Slave enabled or disabled after reset is applied, 0x1
LE which means software does not have to configure
the slave.
0=slave is enabled
1=slave is disabled
Software should ensure that if this bit is written
with '0', then bit 0 should also be written with a '0'.
5 R/W I2C_RESTART_EN Determines whether RESTART conditions may be 0x1
sent when acting as a master
0= disable
1=enable
4 R/W I2C_10BITADDR_M Controls whether the controller starts its transfers 0x1
ASTER in 7- or 10-bit addressing mode when acting as a
master.
0= 7-bit addressing
1= 10-bit addressing
3 R/W I2C_10BITADDR_S When acting as a slave, this bit controls whether 0x1
LAVE the controller responds to 7- or 10-bit addresses.
0= 7-bit addressing
1= 10-bit addressing

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2:1 R/W I2C_SPEED These bits control at which speed the controller 0x2
operates.
1= standard mode (100 kbit/s)
2= fast mode (400 kbit/s)
Note: The actuall speed depends on the pcb
traces capacitance as well as on the values of the
external pull-up resistorts. For an exact speed
match, trimming might be required, by adjusting
the values of I2C_SS_SCL_HCNT_REG,
I2C_SS_SCL_LCNT_REG,
I2C_FS_SCL_HCNT_REG,
I2C_FS_SCL_LCNT_REG registers. The reset
values of those registers were calculated with the
assumption of 4.3kOhms external pull-up
resistors.
0 R/W I2C_MASTER_MOD This bit controls whether the controller master is 0x1
E enabled.
0= master disabled
1= master enabled
Software should ensure that if this bit is written
with '1' then bit 6 should also be written with a '1'.
Table 221: I2C_TAR_REG (0x50001304)

15:12 - - 0x0
11 R/W SPECIAL This bit indicates whether software performs a 0x0
General Call or
START BYTE command.
0: ignore bit 10 GC_OR_START and use IC_TAR
normally
1: perform special I2C command as specified in
GC_OR_START
bit
10 R/W GC_OR_START If bit 11 (SPECIAL) is set to 1, then this bit 0x0
indicates whether a General Call or START byte
command is to be performed by the controller.
0: General Call Address - after issuing a General
Call, only writes may be performed. Attempting to
issue a read command results in setting bit 6
(TX_ABRT) of the IC_RAW_INTR_STAT register.
The controller remains in General Call mode until
the SPECIAL bit value (bit 11) is cleared.
1: START BYTE

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9:0 R/W IC_TAR This is the target address for any master 0x55
transaction. When transmitting a General Call,
these bits are ignored. To generate a START
BYTE, the CPU needs to write only once into
these bits.
Note: If the IC_TAR and IC_SAR are the same,
loopback exists but the FIFOs are shared between
master and slave, so full loopback is not feasible.
Only one direction loopback mode is supported
(simplex), not duplex. A master cannot transmit to
itself; it can transmit to only a slave
Table 222: I2C_SAR_REG (0x50001308)

15:10 - - 0x0
9:0 R/W IC_SAR The IC_SAR holds the slave address when the 0x55
I2C is operating as a slave. For 7-bit addressing,
only IC_SAR[6:0] is used. This register can be
written only when the I2C interface is disabled,
which corresponds to the IC_ENABLE register
being set to 0. Writes at other times have no
effect.
Table 223: I2C_DATA_CMD_REG (0x50001310)

15:11 - - 0x0
10 R/W I2C_RESTART This bit controls whether a RESTART is issued 0x0
before the byte is sent or received. If
IC_RESTART_EN is 1, a RESTART is issued
before the data is sent/received (according to the
value of CMD), regardless of whether or not the
transfer direction is changing from the previous
command; if IC_RESTART_EN is 0, a STOP
followed by a START is issued instead. If
IC_RESTART_EN is 1, a RESTART is issued only
if the transfer direction is changing from the
previous command; if IC_RESTART_EN is 0, a
STOP followed by a START is issued instead.
Reset value: 0x0

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9 R/W I2C_STOP This bit controls whether a STOP is issued after 0x0
the byte is sent or received. STOP is issued after
this byte, regardless of whether or not the Tx FIFO
is empty. If the Tx FIFO is not empty, the master
immediately tries to start a new transfer by issuing
a START and arbitrating for the bus. STOP is not
issued after this byte, regardless of whether or not
the Tx FIFO is empty. If the Tx FIFO is not empty,
the master continues the current transfer by
sending/receiving data bytes according to the
value of the CMD bit. If the Tx FIFO is empty, the
master holds the SCL line low and stalls the bus
until a new command is available in the Tx FIFO.
Reset value: 0x0
8 R/W I2C_CMD This bit controls whether a read or a write is 0x0
performed. This bit does not control the direction
when the I2C Ctrl acts as a slave. It controls only
the direction when it acts as a master.
1 = Read
0 = Write
When a command is entered in the TX FIFO, this
bit distinguishes the write and read commands. In
slave-receiver mode, this bit is a "don't care"
because writes to this register are not required. In
slave-transmitter mode, a "0" indicates that CPU
data is to be transmitted and as DAT or
IC_DATA_CMD[7:0]. When programming this bit,
you should remember the following: attempting to
perform a read operation after a General Call
command has been sent results in a TX_ABRT
interrupt (bit 6 of the
I2C_RAW_INTR_STAT_REG), unless bit 11
(SPECIAL) in the I2C_TAR register has been
cleared.
If a "1" is written to this bit after receiving a
RD_REQ interrupt, then a TX_ABRT interrupt
occurs.
NOTE: It is possible that while attempting a
master I2C read transfer on the controller, a
RD_REQ interrupt may have occurred
simultaneously due to a remote I2C master
addressing the controller. In this type of scenario,
it ignores the I2C_DATA_CMD write, generates a
TX_ABRT interrupt, and waits to service the
RD_REQ interrupt
7:0 R/W DAT This register contains the data to be transmitted or 0x0
received on the I2C bus. If you are writing to this
register and want to perform a read, bits 7:0 (DAT)
are ignored by the controller. However, when you
read this register, these bits return the value of
data received on the controller's interface.

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Table 224: I2C_SS_SCL_HCNT_REG (0x50001314)

15:0 R/W IC_SS_SCL_HCNT This register must be set before any I2C bus 0x48
transaction can take place to ensure proper I/O
timing. This register sets the SCL clock high-
period count for standard speed. This register can
be written only when the I2C interface is disabled
being set to 0. Writes at other
times have no effect.
The minimum valid value is 6; hardware prevents
values less than this being written, and if
attempted results in 6 being set.
NOTE: This register must not be programmed to a
value higher than 65525, because the controller
uses a 16-bit counter to flag an I2C bus idle
condition when this counter reaches a value of
IC_SS_SCL_HCNT + 10.
Table 225: I2C_SS_SCL_LCNT_REG (0x50001318)

15:0 R/W IC_SS_SCL_LCNT This register must be set before any I2C bus 0x4F
timing. This register sets the SCL clock low period
count for standard speed.
This register can be written only when the I2C
interface is disabled which corresponds to the
I2C_ENABLE register being set to 0. Writes at
other times have no effect.
attempted, results in 8 being set.
Table 226: I2C_FS_SCL_HCNT_REG (0x5000131C)

15:0 R/W IC_FS_SCL_HCNT This register must be set before any I2C bus 0x8
timing. This register sets the SCL clock high-
period count for fast speed. It is used in high-
speed mode to send the Master Code and START
BYTE or General CALL. This register can be
written only when the I2C interface is disabled,
which corresponds to the I2C_ENABLE register
effect.

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Table 227: I2C_FS_SCL_LCNT_REG (0x50001320)

15:0 R/W IC_FS_SCL_LCNT This register must be set before any I2C bus 0x17
timing. This register sets the SCL clock low-period
count for fast speed. It is used in high-speed mode
to send the Master Code and START BYTE or
General CALL. This register can be written only
when the I2C interface is disabled, which
corresponds to the I2C_ENABLE register being
set to 0. Writes at other times have no effect.
attempted results in 8 being set. For designs with
APB_DATA_WIDTH = 8 the order of programming
is important to ensure the correct operation of the
controller. The lower byte must be programmed
first. Then the upper byte is programmed.
Table 228: I2C_INTR_STAT_REG (0x5000132C)

15:12 - - 0x0
11 R R_GEN_CALL Set only when a General Call address is received 0x0
and it is acknowledged. It stays set until it is
cleared either by disabling controller or when the
CPU reads bit 0 of the I2C_CLR_GEN_CALL
register. The controller stores the received data in
the Rx buffer.
10 R R_START_DET Indicates whether a START or RESTART 0x0
condition has occurred on the I2C interface
regardless of whether controller is operating in
slave or master mode.
9 R R_STOP_DET Indicates whether a STOP condition has occurred 0x0
on the I2C interface regardless of whether
controller is operating in slave or master mode.
8 R R_ACTIVITY This bit captures I2C Ctrl activity and stays set 0x0
until it is cleared. There are four ways to clear it:
=> Disabling the I2C Ctrl
=> Reading the IC_CLR_ACTIVITY register
=> Reading the IC_CLR_INTR register
=> System reset
Once this bit is set, it stays set unless one of the
four methods is used to clear it. Even if the
controller module is idle, this bit remains set until
cleared, indicating that there was activity on the
bus.
7 R R_RX_DONE When the controller is acting as a slave- 0x0
transmitter, this bit is set to 1 if the master does
not acknowledge a transmitted byte. This occurs
on the last byte of the transmission, indicating that
the transmission is done.

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6 R R_TX_ABRT This bit indicates if the controller, as an I2C 0x0
transmitter, is unable to complete the intended
actions on the contents of the transmit FIFO. This
situation can occur both as an I2C master or an
I2C slave, and is referred to as a "transmit abort".
When this bit is set to 1, the
I2C_TX_ABRT_SOURCE register indicates the
reason why the transmit abort takes places.
NOTE: The controller flushes/resets/empties the
TX FIFO whenever this bit is set. The TX FIFO
remains in this flushed state until the register
I2C_CLR_TX_ABRT is read. Once this read is
performed, the TX FIFO is then ready to accept
more data bytes from the APB interface.
5 R R_RD_REQ This bit is set to 1 when the controller is acting as 0x0
a slave and another I2C master is attempting to
read data from the controller. The controller holds
the I2C bus in a wait state (SCL=0) until this
interrupt is serviced, which means that the slave
has been addressed by a remote master that is
asking for data to be transferred. The processor
must respond to this interrupt and then write the
requested data to the I2C_DATA_CMD register.
This bit is set to 0 just after the processor reads
the I2C_CLR_RD_REQ register
4 R R_TX_EMPTY This bit is set to 1 when the transmit buffer is at or 0x0
below the threshold value set in the I2C_TX_TL
register. It is automatically cleared by hardware
when the buffer level goes above the threshold.
When the IC_ENABLE bit 0 is 0, the TX FIFO is
flushed and held in reset. There the TX FIFO
looks like it has no data within it, so this bit is set
to 1, provided there is activity in the master or
slave state machines. When there is no longer
activity, then with ic_en=0, this bit is set to 0.
3 R R_TX_OVER Set during transmit if the transmit buffer is filled to 0x0
32 and the processor attempts to issue another
I2C command by writing to the IC_DATA_CMD
register. When the module is disabled, this bit
keeps its level until the master or slave state
machines go into idle, and when ic_en goes to 0,
this interrupt is cleared
2 R R_RX_FULL Set when the receive buffer reaches or goes 0x0
above the RX_TL threshold in the I2C_RX_TL
when buffer level goes below the threshold. If the
module is disabled (I2C_ENABLE[0]=0), the RX
FIFO is flushed and held in reset; therefore the RX
FIFO is not full. So this bit is cleared once the
I2C_ENABLE bit 0 is programmed with a 0,
regardless of the activity that continues.
1 R R_RX_OVER Set if the receive buffer is completely filled to 32 0x0
and an additional byte is received from an external
I2C device. The controller acknowledges this, but
any data bytes received after the FIFO is full are
lost. If the module is disabled (I2C_ENABLE[0]=0),
this bit keeps its level until the master or slave
state machines go into idle, and when ic_en goes
to 0, this interrupt is cleared.

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0 R R_RX_UNDER Set if the processor attempts to read the receive 0x0
buffer when it is empty by reading from the
IC_DATA_CMD register. If the module is disabled
(I2C_ENABLE[0]=0), this bit keeps its level until
the master or slave state machines go into idle,
and when ic_en goes to 0, this interrupt is cleared.
Table 229: I2C_INTR_MASK_REG (0x50001330)

15:12 - - 0x0
11 R/W M_GEN_CALL These bits mask their corresponding interrupt 0x1
status bits in the I2C_INTR_STAT register.
10 R/W M_START_DET These bits mask their corresponding interrupt 0x0
9 R/W M_STOP_DET These bits mask their corresponding interrupt 0x0
8 R/W M_ACTIVITY These bits mask their corresponding interrupt 0x0
7 R/W M_RX_DONE These bits mask their corresponding interrupt 0x1
6 R/W M_TX_ABRT These bits mask their corresponding interrupt 0x1
5 R/W M_RD_REQ These bits mask their corresponding interrupt 0x1
4 R/W M_TX_EMPTY These bits mask their corresponding interrupt 0x1
3 R/W M_TX_OVER These bits mask their corresponding interrupt 0x1
2 R/W M_RX_FULL These bits mask their corresponding interrupt 0x1
1 R/W M_RX_OVER These bits mask their corresponding interrupt 0x1
0 R/W M_RX_UNDER These bits mask their corresponding interrupt 0x1
Table 230: I2C_RAW_INTR_STAT_REG (0x50001334)

15:12 - - 0x0
11 R GEN_CALL Set only when a General Call address is received 0x0
and it is acknowledged. It stays set until it is
cleared either by disabling controller or when the
CPU reads bit 0 of the I2C_CLR_GEN_CALL
register. I2C Ctrl stores the received data in the
Rx buffer.

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10 R START_DET Indicates whether a START or RESTART 0x0
condition has occurred on the I2C interface
regardless of whether controller is operating in
slave or master mode.
9 R STOP_DET Indicates whether a STOP condition has occurred 0x0
on the I2C interface regardless of whether
controller is operating in slave or master mode.
8 R ACTIVITY This bit captures I2C Ctrl activity and stays set 0x0
until it is cleared. There are four ways to clear it:
=> Disabling the I2C Ctrl
=> Reading the IC_CLR_ACTIVITY register
=> Reading the IC_CLR_INTR register
=> System reset
Once this bit is set, it stays set unless one of the
four methods is used to clear it. Even if the
controller module is idle, this bit remains set until
cleared, indicating that there was activity on the
bus.
7 R RX_DONE When the controller is acting as a slave- 0x0
transmitter, this bit is set to 1 if the master does
not acknowledge a transmitted byte. This occurs
on the last byte of the transmission, indicating that
the transmission is done.
6 R TX_ABRT This bit indicates if the controller, as an I2C 0x0
transmitter, is unable to complete the intended
actions on the contents of the transmit FIFO. This
situation can occur both as an I2C master or an
I2C slave, and is referred to as a "transmit abort".
When this bit is set to 1, the
I2C_TX_ABRT_SOURCE register indicates the
reason why the transmit abort takes places.
NOTE: The controller flushes/resets/empties the
TX FIFO whenever this bit is set. The TX FIFO
remains in this flushed state until the register
I2C_CLR_TX_ABRT is read. Once this read is
performed, the TX FIFO is then ready to accept
more data bytes from the APB interface.
5 R RD_REQ This bit is set to 1 when I2C Ctrl is acting as a 0x0
slave and another I2C master is attempting to
read data from the controller. The controller holds
the I2C bus in a wait state (SCL=0) until this
interrupt is serviced, which means that the slave
has been addressed by a remote master that is
asking for data to be transferred. The processor
must respond to this interrupt and then write the
requested data to the I2C_DATA_CMD register.
This bit is set to 0 just after the processor reads
the I2C_CLR_RD_REQ register

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4 R TX_EMPTY This bit is set to 1 when the transmit buffer is at or 0x0
below the threshold value set in the I2C_TX_TL
when the buffer level goes above the threshold.
When the IC_ENABLE bit 0 is 0, the TX FIFO is
flushed and held in reset. There the TX FIFO
looks like it has no data within it, so this bit is set
to 1, provided there is activity in the master or
slave state machines. When there is no longer
activity, then with ic_en=0, this bit is set to 0.
3 R TX_OVER Set during transmit if the transmit buffer is filled to 0x0
32 and the processor attempts to issue another
I2C command by writing to the IC_DATA_CMD
register. When the module is disabled, this bit
keeps its level until the master or slave state
machines go into idle, and when ic_en goes to 0,
this interrupt is cleared
2 R RX_FULL Set when the receive buffer reaches or goes 0x0
above the RX_TL threshold in the I2C_RX_TL
when buffer level goes below the threshold. If the
module is disabled (I2C_ENABLE[0]=0), the RX
FIFO is flushed and held in reset; therefore the RX
FIFO is not full. So this bit is cleared once the
I2C_ENABLE bit 0 is programmed with a 0,
regardless of the activity that continues.
1 R RX_OVER Set if the receive buffer is completely filled to 32 0x0
and an additional byte is received from an external
I2C device. The controller acknowledges this, but
any data bytes received after the FIFO is full are
lost. If the module is disabled (I2C_ENABLE[0]=0),
this bit keeps its level until the master or slave
state machines go into idle, and when ic_en goes
to 0, this interrupt is cleared.
0 R RX_UNDER Set if the processor attempts to read the receive 0x0
buffer when it is empty by reading from the
IC_DATA_CMD register. If the module is disabled
(I2C_ENABLE[0]=0), this bit keeps its level until
the master or slave state machines go into idle,
and when ic_en goes to 0, this interrupt is cleared.
Table 231: I2C_RX_TL_REG (0x50001338)

15:5 - - 0x0
4:0 R/W RX_TL Receive FIFO Threshold Level Controls the level 0x0
of entries (or above) that triggers the RX_FULL
interrupt (bit 2 in I2C_RAW_INTR_STAT register).
The valid range is 0-31, with the additional
restriction that hardware does not allow this value
to be set to a value larger than the depth of the
buffer. If an attempt is made to do that, the actual
value set will be the maximum depth of the buffer.
A value of 0 sets the threshold for 1 entry, and a
value of 31 sets the threshold for 32 entries.

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Table 232: I2C_TX_TL_REG (0x5000133C)

15:5 - - 0x0
4:0 R/W RX_TL Transmit FIFO Threshold Level Controls the level 0x0
of entries (or below) that trigger the TX_EMPTY
interrupt (bit 4 in I2C_RAW_INTR_STAT register).
The valid range is 0-31, with the additional
restriction that it may not be set to value larger
than the depth of the buffer. If an attempt is made
to do that, the actual value set will be the
maximum depth of the buffer. A value of 0 sets the
threshold for 0 entries, and a value of 31 sets the
threshold for 32 entries..
Table 233: I2C_CLR_INTR_REG (0x50001340)

15:1 - - 0x0
0 R CLR_INTR Read this register to clear the combined interrupt, 0x0
all individual interrupts, and the
I2C_TX_ABRT_SOURCE register. This bit does
not clear hardware clearable interrupts but
software clearable interrupts. Refer to Bit 9 of the
I2C_TX_ABRT_SOURCE register for an
exception to clearing I2C_TX_ABRT_SOURCE
Table 234: I2C_CLR_RX_UNDER_REG (0x50001344)

15:1 - - 0x0
0 R CLR_RX_UNDER Read this register to clear the RX_UNDER 0x0
interrupt (bit 0) of the
I2C_RAW_INTR_STAT register.
Table 235: I2C_CLR_RX_OVER_REG (0x50001348)

15:1 - - 0x0
0 R CLR_RX_OVER Read this register to clear the RX_OVER interrupt 0x0
(bit 1) of the

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Table 236: I2C_CLR_TX_OVER_REG (0x5000134C)

15:1 - - 0x0
0 R CLR_TX_OVER Read this register to clear the TX_OVER interrupt 0x0
(bit 3) of the I2C_RAW_INTR_STAT register.
Table 237: I2C_CLR_RD_REQ_REG (0x50001350)

15:1 - - 0x0
0 R CLR_RD_REQ Read this register to clear the RD_REQ interrupt 0x0
(bit 5) of the I2C_RAW_INTR_STAT register.
Table 238: I2C_CLR_TX_ABRT_REG (0x50001354)

15:1 - - 0x0
0 R CLR_TX_ABRT Read this register to clear the TX_ABRT interrupt 0x0
(bit 6) of the
IC_RAW_INTR_STAT register, and the
I2C_TX_ABRT_SOURCE register. This also
releases the TX FIFO from the flushed/reset state,
allowing more writes to the TX FIFO. Refer to Bit 9
of the I2C_TX_ABRT_SOURCE register for an
exception to clearing IC_TX_ABRT_SOURCE.
Table 239: I2C_CLR_RX_DONE_REG (0x50001358)

15:1 - - 0x0
0 R CLR_RX_DONE Read this register to clear the RX_DONE interrupt 0x0
(bit 7) of the
Table 240: I2C_CLR_ACTIVITY_REG (0x5000135C)

15:1 - - 0x0

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0 R CLR_ACTIVITY Reading this register clears the ACTIVITY 0x0
interrupt if the I2C is not active anymore. If the I2C
module is still active on the bus, the ACTIVITY
interrupt bit continues to be set. It is automatically
cleared by hardware if the module is disabled and
if there is no further activity on the bus. The value
read from this register to get status of the
ACTIVITY interrupt (bit 8) of the
IC_RAW_INTR_STAT register
Table 241: I2C_CLR_STOP_DET_REG (0x50001360)

15:1 - - 0x0
0 R CLR_STOP_DET Read this register to clear the STOP_DET 0x0
interrupt (bit 9) of the IC_RAW_INTR_STAT
register. Reset value: 0x0
Table 242: I2C_CLR_START_DET_REG (0x50001364)

15:1 - - 0x0
0 R CLR_START_DET Read this register to clear the START_DET 0x0
interrupt (bit 10) of the IC_RAW_INTR_STAT
register.
Table 243: I2C_CLR_GEN_CALL_REG (0x50001368)

15:1 - - 0x0
0 R CLR_GEN_CALL Read this register to clear the GEN_CALL 0x0
interrupt (bit 11) of
Table 244: I2C_ENABLE_REG (0x5000136C)

15:2 - - 0x0

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1 R/W I2C_ABORT 0= ABORT not initiated or ABORT done 0x0
1= ABORT operation in progress
The software can abort the I2C transfer in master
mode by setting this bit. The software can set this
bit only when ENABLE is already set; otherwise,
the controller ignores any write to ABORT bit. The
software cannot clear the ABORT bit once set. In
response to
an ABORT, the controller issues a STOP and
flushes the Tx FIFO after completing the current
transfer, then sets the TX_ABORT interrupt after
the abort operation. The ABORT bit is cleared
automatically after the abort operation.
0 R/W CTRL_ENABLE Controls whether the controller is enabled. 0x0
0: Disables the controller (TX and RX FIFOs are
held in an erased state)
1: Enables the controller
Software can disable the controller while it is
active. However, it is important that care be taken
to ensure that the controller is disabled properly.
When the controller is disabled, the following
occurs:
* The TX FIFO and RX FIFO get flushed.
* Status bits in the IC_INTR_STAT register are still
active until the controller goes into IDLE state.
If the module is transmitting, it stops as well as
deletes the contents of the transmit buffer after the
current transfer is complete. If the module is
receiving, the controller stops the current transfer
at the end of the current byte and does not
acknowledge the transfer.
There is a two ic_clk delay when enabling or
disabling the controller
Table 245: I2C_STATUS_REG (0x50001370)

15:7 - - 0x0
6 R SLV_ACTIVITY Slave FSM Activity Status. When the Slave Finite 0x0
State Machine (FSM) is not in the IDLE state, this
bit is set.
0: Slave FSM is in IDLE state so the Slave part of
the controller is not Active
1: Slave FSM is not in IDLE state so the Slave
part of the controller is Active
5 R MST_ACTIVITY Master FSM Activity Status. When the Master 0x0
Finite State Machine (FSM) is not in the IDLE
state, this bit is set.
0: Master FSM is in IDLE state so the Master part
of the controller is not Active
1: Master FSM is not in IDLE state so the Master
part of the controller is Active

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4 R RFF Receive FIFO Completely Full. When the receive 0x0
FIFO is completely full, this bit is set. When the
receive FIFO contains one or more empty
location, this bit is cleared.
0: Receive FIFO is not full
1: Receive FIFO is full
3 R RFNE Receive FIFO Not Empty. This bit is set when the 0x0
receive FIFO contains one or more entries; it is
cleared when the receive FIFO is empty.
0: Receive FIFO is empty
1: Receive FIFO is not empty
2 R TFE Transmit FIFO Completely Empty. When the 0x1
transmit FIFO is completely empty, this bit is set.
When it contains one or more valid entries, this bit
is cleared. This bit field does not request an
interrupt.
0: Transmit FIFO is not empty
1: Transmit FIFO is empty
1 R TFNF Transmit FIFO Not Full. Set when the transmit 0x1
FIFO contains one or more empty locations, and is
cleared when the FIFO is full.
0: Transmit FIFO is full
1: Transmit FIFO is not full
0 R I2C_ACTIVITY I2C Activity Status. 0x0
Table 246: I2C_TXFLR_REG (0x50001374)

15:6 - - 0x0
5:0 R TXFLR Transmit FIFO Level. Contains the number of valid 0x0
data entries in the transmit FIFO. Size is
constrained by the TXFLR value
Table 247: I2C_RXFLR_REG (0x50001378)

15:6 - - 0x0
5:0 R RXFLR Receive FIFO Level. Contains the number of valid 0x0
data entries in the receive FIFO. Size is
constrained by the RXFLR value
Table 248: I2C_SDA_HOLD_REG (0x5000137C)

15:0 R/W IC_SDA_HOLD SDA Hold time 0x1

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Table 249: I2C_TX_ABRT_SOURCE_REG (0x50001380)

15 R ABRT_SLVRD_INT 1: When the processor side responds to a slave 0x0
X mode request for data to be transmitted to a
remote master and user writes a 1 in CMD (bit 8)
of 2IC_DATA_CMD register
14 R ABRT_SLV_ARBLO 1: Slave lost the bus while transmitting data to a 0x0
ST remote master.
I2C_TX_ABRT_SOURCE[12] is set at the same
time. Note: Even though the slave never "owns"
the bus, something could go wrong on the bus.
This is a fail safe check. For instance, during a
data transmission at the low-to-high transition of
SCL, if what is on the data bus is not what is
supposed to be transmitted, then the controller no
longer own the bus.
13 R ABRT_SLVFLUSH_ 1: Slave has received a read command and some 0x0
TXFIFO data exists in the TX FIFO so the slave issues a
TX_ABRT interrupt to flush old data in TX FIFO.
12 R ARB_LOST 1: Master has lost arbitration, or if 0x0
I2C_TX_ABRT_SOURCE[14] is also set, then the
slave transmitter has lost arbitration. Note: I2C
can be both master and slave at the same time.
11 R ABRT_MASTER_DI 1: User tries to initiate a Master operation with the 0x0
S Master mode disabled.
10 R ABRT_10B_RD_NO 1: The restart is disabled (IC_RESTART_EN bit 0x0
RSTRT (I2C_CON[5]) = 0) and the master sends a read
command in 10-bit addressing mode.
9 R ABRT_SBYTE_NO To clear Bit 9, the source of the 0x0
RSTRT ABRT_SBYTE_NORSTRT must be fixed first;
restart must be enabled (I2C_CON[5]=1), the
SPECIAL bit must be cleared (I2C_TAR[11]), or
the GC_OR_START bit must be cleared
(I2C_TAR[10]). Once the source of the
ABRT_SBYTE_NORSTRT is fixed, then this bit
can be cleared in the same manner as other bits
in this register. If the source of the
ABRT_SBYTE_NORSTRT is not fixed before
attempting to clear this bit, bit 9 clears for one
cycle and then gets re-asserted. 1: The restart is
disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0)
and the user is trying to send a START Byte.
8 R ABRT_HS_NORST 1: The restart is disabled (IC_RESTART_EN bit 0x0
RT (I2C_CON[5]) = 0) and the user is trying to use the
master to transfer data in High Speed mode
7 R ABRT_SBYTE_ACK 1: Master has sent a START Byte and the START 0x0
DET Byte was acknowledged (wrong behavior).
6 R ABRT_HS_ACKDE 1: Master is in High Speed mode and the High 0x0
T Speed Master code was acknowledged (wrong
behavior).

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5 R ABRT_GCALL_REA 1: the controller in master mode sent a General 0x0
D Call but the user programmed the byte following
the General Call to be a read from the bus
(IC_DATA_CMD[9] is set to 1).
4 R ABRT_GCALL_NO 1: the controller in master mode sent a General 0x0
ACK Call and no slave on the bus acknowledged the
General Call.
3 R ABRT_TXDATA_N 1: This is a master-mode only bit. Master has 0x0
OACK received an acknowledgement for the address, but
when it sent data byte(s) following the address, it
did not receive an acknowledge from the remote
slave(s).
2 R ABRT_10ADDR2_N 1: Master is in 10-bit address mode and the 0x0
OACK second address byte of the 10-bit address was not
acknowledged by any slave.
1 R ABRT_10ADDR1_N 1: Master is in 10-bit address mode and the first 0x0
OACK 10-bit address byte was not acknowledged by any
slave.
0 R ABRT_7B_ADDR_N 1: Master is in 7-bit addressing mode and the 0x0
OACK address sent was not acknowledged by any slave.
Table 250: I2C_DMA_CR_REG (0x50001388)

1 R/W TDMAE Transmit DMA Enable. //This bit enables/disables 0x0
the transmit FIFO DMA channel. 0 = Transmit
DMA disabled 1 = Transmit DMA enabled
0 R/W RDMAE Receive DMA Enable. This bit enables/disables 0x0
the receive FIFO DMA channel. 0 = Receive DMA
disabled 1 = Receive DMA enabled
Table 251: I2C_DMA_TDLR_REG (0x5000138C)

4:0 R/W DMATDL Transmit Data Level. This bit field controls the 0x0
level at which a DMA request is made by the
transmit logic. It is equal to the watermark level;
that is, the dma_tx_req signal is generated when
the number of valid data entries in the transmit
FIFO is equal to or below this field value, and
TDMAE = 1.

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Table 252: I2C_DMA_RDLR_REG (0x50001390)

4:0 R/W DMARDL Receive Data Level. This bit field controls the level 0x0
at which a DMA request is made by the receive
logic. The watermark level = DMARDL+1; that is,
dma_rx_req is generated when the number of
valid data entries in the receive FIFO is equal to or
more than this field value + 1, and RDMAE =1. For
instance, when DMARDL is 0, then dma_rx_req is
asserted when 1 or more data entries are present
in the receive FIFO.
Table 253: I2C_SDA_SETUP_REG (0x50001394)

15:8 - - 0x0
7:0 R/W SDA_SETUP SDA Setup. 0x64
This register controls the amount of time delay
(number of I2C clock periods) between the rising
edge of SCL and SDA changing by holding SCL
low when I2C block services a read request while
operating as a slave-transmitter. The relevant I2C
requirement is tSU:DAT (note 4) as detailed in the
I2C Bus Specification. This register must be
programmed with a value equal to or greater than
2.
It is recommended that if the required delay is
1000ns, then for an I2C frequency of 10 MHz,
IC_SDA_SETUP should be programmed to a
value of 11.Writes to this register succeed only
when IC_ENABLE[0] = 0.
Table 254: I2C_ACK_GENERAL_CALL_REG (0x50001398)

15:1 - - 0x0
0 R/W ACK_GEN_CALL ACK General Call. When set to 1, I2C Ctrl 0x0
responds with a ACK (by asserting ic_data_oe)
when it receives a General Call. When set to 0,
the controller does not generate General Call
interrupts.
Table 255: I2C_ENABLE_STATUS_REG (0x5000139C)

15:3 - - 0x0

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2 R SLV_RX_DATA_LO Slave Received Data Lost. This bit indicates if a 0x0
ST Slave-Receiver
operation has been aborted with at least one data
byte received from an I2C transfer due to the
setting of IC_ENABLE from 1 to 0. When read as
1, the controller is deemed to have been actively
engaged in an aborted I2C transfer (with matching
address) and the data phase of the I2C transfer
has been entered, even though a data byte has
been responded with a NACK. NOTE: If the
remote I2C master terminates the transfer with a
STOP condition before the controller has a chance
to NACK a transfer, and IC_ENABLE has been set
to 0, then this bit is also set to 1.
When read as 0, the controller is deemed to have
been disabled without being actively involved in
the data phase of a Slave-Receiver transfer.
NOTE: The CPU can safely read this bit when
IC_EN (bit 0) is read as 0.
1 R SLV_DISABLED_W Slave Disabled While Busy (Transmit, Receive). 0x0
HILE_BUSY This bit indicates if a potential or active Slave
operation has been aborted due to the setting of
the IC_ENABLE register from 1 to 0. This bit is set
when the CPU writes a 0 to the IC_ENABLE
register while:
(a) I2C Ctrl is receiving the address byte of the
Slave-Transmitter operation from a remote
master; OR,
(b) address and data bytes of the Slave-Receiver
operation from a remote master. When read as 1,
the controller is deemed to have forced a NACK
during any part of an I2C transfer, irrespective of
whether the I2C address matches the slave
address set in I2C Ctrl (IC_SAR register) OR if the
transfer is completed before IC_ENABLE is set to
0 but has not taken effect.
NOTE: If the remote I2C master terminates the
transfer with a STOP condition before the the
controller has a chance to NACK a transfer, and
IC_ENABLE has been set to 0, then this bit will
also be set to 1.
When read as 0, the controller is deemed to have
been disabled when there is master activity, or
when the I2C bus is idle.
NOTE: The CPU can safely read this bit when
IC_EN (bit 0) is read as 0.
0 R IC_EN ic_en Status. This bit always reflects the value 0x0
driven on the output port ic_en. When read as 1,
the controller is deemed to be in an enabled state.
When read as 0, the controller is deemed
completely inactive.
NOTE: The CPU can safely read this bit anytime.
When this bit is read as 0, the CPU can safely
read SLV_RX_DATA_LOST (bit 2) and
SLV_DISABLED_WHILE_BUSY (bit 1).

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Table 256: I2C_IC_FS_SPKLEN_REG (0x500013A0)

15:8 - - 0x0
7:0 R/W IC_FS_SPKLEN This register must be set before any I2C bus 0x1
transaction can take place to ensure stable
operation. This register sets the duration,
measured in ic_clk cycles, of the longest spike in
the SCL or SDA lines that will be filtered out by the
spike suppression logic. This register can be
written only when the I2C interface is disabled
effect. The minimum valid value is 1; hardware
prevents values less than this being written, and if

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31.10 Keyboard Registers
Table 257: Register map KBRD

0x50001400 GPIO_IRQ0_IN_SEL_ GPIO interrupt selection for GPIO_IRQ0
REG
REG
REG
REG
REG
0x5000140C GPIO_DEBOUNCE_R debounce counter value for GPIO inputs
EG
0x5000140E GPIO_RESET_IRQ_R GPIO interrupt reset register
EG
0x50001410 GPIO_INT_LEVEL_CT high or low level select for GPIO interrupts
RL_REG
0x50001412 KBRD_IRQ_IN_SEL0_ GPIO interrupt selection for KBRD_IRQ for P0
REG
0x50001414 KBRD_CTRL_REG GPIO Kbrd control register
Table 258: GPIO_IRQ0_IN_SEL_REG (0x50001400)

15:6 - - 0x0
3:0 R/W KBRD_IRQ0_SEL input selection that can generate a GPIO interrupt 0x0
1: P0[0] is selected
all others: no input selected

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15:6 - - 0x0
3:0 R/W KBRD_IRQ1_SEL see KBRD_IRQ0_SEL 0x0

15:6 - - 0x0

15:6 - - 0x0

15:6 - - 0x0
Table 263: GPIO_DEBOUNCE_REG (0x5000140C)

11 R/W DEB_ENABLE_KBR enables the debounce counter for the KBRD 0x0
D interface
10 R/W DEB_ENABLE4 enables the debounce counter for GPIO IRQ4 0x0
5:0 R/W DEB_VALUE Keyboard debounce time if enabled. Generate 0x0
KEYB_INT after specified time.
Debounce time: N*1 ms. N =0..63

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Table 264: GPIO_RESET_IRQ_REG (0x5000140E)

15:6 - - 0x0
5 R0/W RESET_KBRD_IRQ writing a 1 to this bit will reset the KBRD IRQ. 0x0
Reading returns 0.
4 R0/W RESET_GPIO4_IR writing a 1 to this bit will reset the GPIO4 IRQ. 0x0
Q Reading returns 0.
Table 265: GPIO_INT_LEVEL_CTRL_REG (0x50001410)

9 R/W EDGE_LEVELn4 see EDGE_LEVELn0, but for GPIO IRQ4 0x0
5 R/W EDGE_LEVELn0 0: do not wait for key release after interrupt was 0x0
reset for GPIO IRQ0, so a new interrupt can be
initiated immediately
1: wait for key release after interrupt was reset for
IRQ0
4 R/W INPUT_LEVEL4 see INPUT_LEVEL0, but for GPIO IRQ4 0x0
0 R/W INPUT_LEVEL0 0 = selected input will generate GPIO IRQ0 if that 0x0
input is high.
1 = selected input will generate GPIO IRQ0 if that
input is low.
Table 266: KBRD_IRQ_IN_SEL0_REG (0x50001412)

11 R/W KBRD_P11_EN enable P0[11] for the keyboard interrupt 0x0

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Table 267: KBRD_CTRL_REG (0x50001414)

7 R/W KBRD_REL 0 = No interrupt on key release 0x0
1 = Interrupt also on key release (also debouncing
if enabled)
6 R/W KBRD_LEVEL 0 = enabled input will generate KBRD IRQ if that 0x0
input is high.
1 = enabled input will generate KBRD IRQ if that
input is low.
5:0 R/W KEY_REPEAT While key is pressed, automatically generate 0x0
repeating
KEYB_INT after specified time unequal to 0.
Repeat time: N*1 ms. N =1..63, N=0 disables the
timer.

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31.11 Miscellaneous Registers
Table 268: Register map crg2632_preg_aon_00

0x50000300 HWR_CTRL_REG Hardware Reset control register
0x50000304 RESET_STAT_REG Reset status register
0x50000308 RAM_LPMX_REG
0x5000030C PAD_LATCH_REG Control the state retention of the GPIO ports
0x50000310 HIBERN_CTRL_REG Hibernation control register
0x50000320 POWER_AON_CTRL_
REG
0x50000324 GP_DATA_REG
Table 269: HWR_CTRL_REG (0x50000300)

0 R/W DISABLE_HWR Disables the RST functionality on P00 0x0
Table 270: RESET_STAT_REG (0x50000304)

3 R/W WDOGRESET_STA Indicates that a Watchdog has happened. 0x1
T This bit is also set with a PowerOn Reset
2 R/W SWRESET_STAT Indicates that a SW Reset has been requested. 0x1
The SW reset is requested by
SYS_CTRL_REG[SW_RESET] or SCB->AIRCR
inside the Cortex.
This bit is also set with a PowerOn Reset
1 R/W HWRESET_STAT Indicates that a HW Reset has happened 0x1
This bit is also set with a PowerOn Reset
0 R/W PORESET_STAT Indicates that a PowerOn Reset has happened 0x1
Table 271: RAM_LPMX_REG (0x50000308)

2:0 R/W RAMx_LPMX RAM[3:1] Transparent Light Sleep (TLS) Core 0x7
Enable for System RAMs. Assert low to enable the
TLS core feature, which will result in lower
leakage current.
In case VDD is below 0.81V, it is necessary to
hold this pin high to maintain data retention.

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Table 272: PAD_LATCH_REG (0x5000030C)

0 R/W PAD_LATCH_EN Controls the state retention of the pads. 0x1
0: latches are closed, pads retain their state.
1: latches are open, new control values have
immediate effect
Table 273: HIBERN_CTRL_REG (0x50000310)

6:2 R/W HIBERN_WKUP_M Selects which pin to wakeup from 0x0
ASK
1 R/W HIBERN_WKUP_P Selects the polarity of the wakeup source. The 0x0
OLARITY polarity must be chosen such that the
ANA_STATUS_REG[CLKLESS_WAKEUP_STAT]
is '1'. Any change on the selected GPIOs will
make the CLKLESS_WAKEUP_STAT go to '0',
and wakeup the system from hibernation.
0 R/W HIBERNATION_EN Enables the hibernation mode when sleeping 0x0
ABLE 0: deep sleep mode, PD_SLP remains on
1: hibernation mode, PD_SLP goes off.
REMAP_ADR0 needs to be set to the correct
source to boot from before going to sleep.
Table 274: POWER_AON_CTRL_REG (0x50000320)

14 - - 0x0
13:10 R/W LDO_RET_TRIM VDD clamp level setting for hibernation mode 0x0
9 R/W CMP_VCONT_SLP Disable vcont comparator in SLP 0x0
_DISABLE
8:7 R/W BOOST_MODE_FO 0x:automatic selection of boost mode 0x0
RCE 11: force boost mode
10: force buck mode
6 R/W CHARGE_VBAT_DI Do not charge vbat high in boost mode 0x0
SABLE
5 - - 0x0
4 - - 0x0
3 R/W POR_VBAT_HIGH_ Mask rst from por_vbat_high 0x1
RST_MASK
2 R/W POR_VBAT_LOW_ Mask rst from por_vbat_low 0x0
RST_MASK

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1:0 R/W VBAT_HL_CONNE 00: OFF 0x0
CT_RES_CTRL 01: Forced ON
10: Active: automatic control, Sleep: forced ON
11: Automatic control
Table 275: GP_DATA_REG (0x50000324)

7 R/W P03_P04_FILT_DIS 0: RC filtered input enabled for P0_3 and P0_4 0x0
(e.g. when used for wakeup)
1: RC filtered input disabled for P0_3 and P0_4
(e.g. when used for external clk or XTAL32k)
6 R/W FORCE_RCX_VDD 0: RCX bias supply open (see 0x0

FORCE_RCX_VREF)
1: RCX bias supply connected to VDD (use for
sleep)
5 R/W FORCE_RCX_VRE 0: RCX bias supply connected to clamp and VDD 0x0
F via 400k resistor (old situation)
1: RCX bias supply connected to vref_0v75_0
(use for calibration)
4 - - 0x0
3:0 R/W SW_GP_DATA 0x0

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31.12 OTP Controller Registers
Table 276: Register map OTPC

0x07F40000 OTPC_MODE_REG Mode register
0x07F40004 OTPC_STAT_REG Status register
0x07F40008 OTPC_PADDR_REG The address of the word that will be programmed, when the
PROG mode is used.
0x07F4000C OTPC_PWORD_REG The 32-bit word that will be programmed, when the PROG mode
is used.
0x07F40010 OTPC_TIM1_REG Various timing parameters of the OTP cell.
0x07F40014 OTPC_TIM2_REG Various timing parameters of the OTP cell.
0x07F40018 OTPC_AHBADR_REG AHB master start address
0x07F4001C OTPC_CELADR_REG OTP cell start address
0x07F40020 OTPC_NWORDS_RE Number of words
G
Table 277: OTPC_MODE_REG (0x07F40000)

31:8 - - 0x0
7:6 R/W OTPC_MODE_PRG Defines the part of the OTP cell that is 0x0
_SEL programmed by the controller during the PROG
mode, for each program request that is applied.
0x0 : Both normal and redundancy arrays are
programmed. This is the normal way of
programming.
0x1 : Only the normal array is programmed.
0x2 : Only the redundancy array is programmed.
0x3 : Reserved
The value of this configuration field can be
modified only when the controller is in an inactive
mode (DSTBY or STBY). The setting will take
effect when will be enabled again the PROG
mode.
5 R/W OTPC_MODE_HT_ Defines the temperature condition under which is 0x0
MARG_EN performed a margin read. It affects only the initial
margin read (RINI mode) and the programming
verification margin read (PVFY).
0 : Regular temperature condition (less than 85°C)
1 : igh temperature condition (85°C or more)
mode (DSTBY or STBY). The selection will take
effect at the next PVFY or RINI mode that will be
enabled. The READ mode is not affected by the
setting of this configuration bit.

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4 R/W OTPC_MODE_USE Selects the memory area of the OTP cell that will 0x0
_TST_ROW be used.
0 - Uses the main memory area of the OTP cell
1 - Uses the test row of the OTP cell
mode (DSTBY or STBY). The selection will take
effect at the next programming or reading mode
that will be enabled.
3 - - 0x0
2:0 R/W OTPC_MODE_MO Defines the mode of operation of the OTPC 0x0
DE controller. The encoding of the modes is as
follows:
0x0: DSTBY. The OTP memory is in deep standby
mode (power supply ON and internal LDO OFF).
0x1: STBY. The OTP memory is powered (power
supply ON and internal LDO ON, but is not
selected).
0x2: READ. The OTP memory is in the normal
read mode.
0x3: PROG. The OTP memory is in programming
mode.
0x4: PVFY. The OTP memory is in programming
verification mode (margin read after
programming).
0x5: RINI. The OTP memory is in initial read mode
(initial margin read).
0x6: AREAD. Copying of data from the OTP
memory to a system RAM by using the internal
DMA. See also the registers
OTPC_AHBADR_REG, OTPC_CELADR_REG
and OTPC_NWORDS_REG.
Whenever the OTPC_MODE_REG[MODE] is

changing, the status bit
OTPC_STAT_REG[OTPC_STAT_MRDY] gets the
value zero. The new mode will be ready for use
when the OTPC_STAT_MRDY become again 1.
During the mode transition the
OTPC_MODE_REG[MODE] become read only.
Do not try to use or change any function of the
controller until the OTPC_STAT_MRDY bit to
become equal to 1.
The data transferring that is performed by using
the AREAD mode is completed when
OTPC_STAT_MRDY becomes again 1. The mode
change automatically to DSTBY with the
completion of the transfer.
Table 278: OTPC_STAT_REG (0x07F40004)

31:3 - - 0x0

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2 R OTPC_STAT_MRD Indicates the progress of the transition from a 0x1
Y mode of operation to a new mode of operation.
0 : There is a transition in progress in a new mode
of operation . Wait until the transition to be
completed.
1 : The transition to the new mode of operation
has been completed. The function that has been
enabled by the new mode can be used. A new
mode can be applied.
This status bit gets the value zero every time
where the OTPC_MODE_REG[MODE] is
changing. Do not try to use or change any function
of the controller until this status bit to become
equal to 1.
1 R OTPC_STAT_PBUF Indicates the status of the programming buffer 0x1
_EMPTY (PBUF).
0 : The PBUF contains the address and the data
of a programming request. The
OTPC_PADDR_REG and the
OTPC_PWORD_REG should not be written as
long as this status bit is zero.
1 : The PBUF is empty and a new programming
request can be registered in the PBUF by using
the OTPC_PADDR_REG and the
OTPC_PWORD_REG registers.
This status bit gets the value zero every time
where a programming is triggered by the
OTPC_PADDR_REG (only if the PROG mode is
active).
0 R OTPC_STAT_PRD Indicates the state of the programming process. 0x1
Y 0: The controller is busy. A programming is in
progress.
1: The logic which performs programming is idle.
Table 279: OTPC_PADDR_REG (0x07F40008)

31:13 - - 0x0

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12:0 R/W OTPC_PADDR The OTPC_PADDR_REG and the 0x0
OTPC_PWORD_REG consist the PBUF buffer
that keeps the information that will be
programmed in the OTP, by using the PROG
mode. The PBUF holds the address
(OTPC_PADDR_REG) and the data
(OTPC_PWORD_REG) of each of the
programming requests that are applied in the OTP
memory.
The OTPC_PADDR_REG refers to a word
address. The OTPC_PADDR_REG has to be
writen after the OTP_PWORD_REG and only if
the
OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY]
=1. The register is read only for as long the PBUF
is not empty
(OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY
]=0). A writting to the OTPC_PADDR_REG
triggers the controller to start the programming
procedure (only if the PROG mode is active).
Table 280: OTPC_PWORD_REG (0x07F4000C)

31:0 R/W OTPC_PWORD The OTPC_PADDR_REG and the 0x0
OTPC_PWORD_REG consist the PBUF buffer
that keeps the information that will be
programmed in the OTP memory, by using the
PROG mode. The PBUF holds the address
(OTPC_PADDR_REG) and the data
(OTPC_PWORD_REG) of each of the
programming requests that are applied in the OTP
memory.
The OTP_PWORD_REG must be written before
the OTPC_PADDR_REG and only if
OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY]
= 1. The register is read only for as long the PBUF
is not empty
(OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY
]=0).
Table 281: OTPC_TIM1_REG (0x07F40010)

31 - - 0x0
30:24 R/W OTPC_TIM1_US_T The number of microseconds (minus one) that are 0x9
_CSP required after the selection of the OTP memory,
until to be ready for programming. It must be :
- at least 10us
- no more than 100us

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_CS required after the selection of the OTP memory,
until to be ready for any kind of read. It must be at
least 10us.
_PL required until to be enabled the LDO of the OTP. It
must be at least 10us.
15 - - 0x0
14:12 R/W OTPC_TIM1_CC_T The number of hclk_c clock periods (minus one) 0x0
_RD that give a time interval at least higher than 60ns.
This timing parameter refers to the access time of
the OTP memory.
11:10 - - 0x0
9:8 R/W OTPC_TIM1_CC_T The number of hclk_c clock periods (minus one) 0x0
_20NS that give a time interval that is at least higher than
20 ns.
7 - - 0x0
6:0 R/W OTPC_TIM1_CC_T The number of hclk_c clock periods (minus one) 0xF
_1US that give a time interval equal to 1us. This setting
affects all the timing parameters that refer to
microseconds, due to that defines the
correspondence of a microsecond to a number of
hclk_c clock cycles.
Table 282: OTPC_TIM2_REG (0x07F40014)

31 R/W OTPC_TIM2_US_A Adds an additional hclk_c clock cycle at all the 0x1
DD_CC_EN time intervals that count in microseconds.
0 : The extra hclk_c clock cycle is not applied
1 : The extra hclk_c clock cycle is applied
_SAS required after the exit from the deep sleep standby
mode and before to become ready to enter in an
active mode (reading or programming). It must be
at least 2us.
_PPH required after the last programming pulse and
before to be disabled the programming mode in
the OTP memory. It must be:
- at least 5us
- no more than 20us
_VDS required after the enabling of the power supply of
the OTP memory and before to become ready for
the enabling of the internal LDO. It must be at
least 1us.

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_PPS required after the enabling of the programming in
the OTP memory and before to be applied the first
programming pulse. It must be :
- at least 5us
- no more than 20us
15 - - 0x0
14:8 R/W OTPC_TIM2_US_T The number of microseconds (minus one) for 0x4
_PPR recovery after a programming sequence. It must
be :
- at least 5us
- no more than 100us
7:5 R/W OTPC_TIM2_US_T The number of microseconds (minus one) 0x0
_PWI between two consecutive programming pulses. It
must be :
- at least 1us
- no more than 5us
4:0 R/W OTPC_TIM2_US_T The number of microseconds (minus one) that 0x9
_PW lasts the programming of each bit. It must be :
- at least 10us
- no more than 20us
Table 283: OTPC_AHBADR_REG (0x07F40018)

31:16 - - 0x0
15:2 R/W OTPC_AHBADR It is the AHB address used by the AHB master 0x0
interface of the controller (the bits [15:2]). The bits
[1:0] of the address are considered always as
equal to zero.
The value of the register remains unchanged, by
the internal logic of the controller.
1:0 - - 0x0
Table 284: OTPC_CELADR_REG (0x07F4001C)

31:13 - - 0x0
12:0 R/W OTPC_CELADR Defines a word address inside the OTP cell that 0x0
will be used during the AREAD mode and the OTP
mirroring.

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Table 285: OTPC_NWORDS_REG (0x07F40020)

31:13 - - 0x0
12:0 R/W OTPC_NWORDS The number of words (minus one) that will be 0x0
copied by the AREAD mode. During mirroring, this
register reflects the amount of data that will be
copied.

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31.13 Quadrature Decoder Registers
Table 286: Register map QDEC

0x50000200 QDEC_CTRL_REG Quad Decoder control register
0x50000202 QDEC_XCNT_REG Counter value of the X Axis
0x50000204 QDEC_YCNT_REG Counter value of the Y Axis
0x50000206 QDEC_CLOCKDIV_R Clock divider register
EG
0x50000208 QDEC_CTRL2_REG Quad Decoder port selection register
0x5000020A QDEC_ZCNT_REG Counter value of the Z Axis
0x5000020C QDEC_EVENT_CNT_ Event counter register
REG
Table 287: QDEC_CTRL_REG (0x50000200)

10:3 R/W QDEC_IRQ_THRES Defines the number of events on either counter (X 0x2
or Y or Z) that need to be reached before an
interrupt is generated. Events are equal to
QDEC_IRQ_THRES+1.
2 R/W QDEC_IRQ_STATU 1 = Interrupt is occured. 0x0
S 0 = No interrupt pending
Write 1 will clear the pending interrupt
1 R0/WC QDEC_EVENT_CN Writing 1 QDEC_EVENT_CNT_REG is cleared 0x0
T_CLR
0 R/W QDEC_IRQ_ENABL 0 = interrupt is masked 0x1
E 1 = interrupt is enabled
Table 288: QDEC_XCNT_REG (0x50000202)

15:0 R QDEC_X_CNT Contains a signed value of the events. Zero when 0x0
channel is disabled
Table 289: QDEC_YCNT_REG (0x50000204)

15:0 R QDEC_Y_CNT Contains a signed value of the events. Zero when 0x0
channel is disabled

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Table 290: QDEC_CLOCKDIV_REG (0x50000206)

10 R/W QDEC_PRESCALE 0 = no prescaler enabled 0x0
R_EN 1 = in sleep and active mode, quadrature clock is
divided by 2
9:0 R/W QDEC_CLOCKDIV Contains the number of the input clock cycles 0x3E7
minus one, that are required to generate one logic
clock cycle.
Clock divider is bypassed when system runs at
LP_CLK
Table 291: QDEC_CTRL2_REG (0x50000208)

11 R/W QDEC_CHZ_EVEN 0 = Normal quadrature counting 0x1
T_MODE 1 = Counts rising and falling edge of both ports (if
both ports change at the same time, counter
increases by 1)
10 R/W QDEC_CHY_EVEN 0 = Normal quadrature counting 0x1
increases by 1)
9 R/W QDEC_CHX_EVEN 0 = Normal quadrature counting 0x1
increases by 1)
8:6 R/W QDEC_CHZ_PORT Defines which GPIOs are mapped on Channel Z 3
_SEL 0: none
1: P0[2] -> CHZ_A, P0[5] -> CHZ_B
2: P0[1] -> CHZ_A, P0[4] -> CHZ_B
3: P0[3] -> CHZ_A, P0[10] -> CHZ_B
4: P0[6] -> CHZ_A, P0[7] -> CHZ_B
5: P0[8] -> CHZ_A, P0[9] -> CHZ_B
6: P0[0] -> CHZ_A, P0[11] -> CHZ_B
7: none
5:3 R/W QDEC_CHY_PORT Defines which GPIOs are mapped on Channel Y 2
_SEL 0: none
1: P0[2] -> CHY_A, P0[5] -> CHY_B
2: P0[1] -> CHY_A, P0[4] -> CHY_B
3: P0[3] -> CHY_A, P0[10] -> CHY_B
4: P0[6] -> CHY_A, P0[7] -> CHY_B
5: P0[8] -> CHY_A, P0[9] -> CHY_B
6: P0[0] -> CHY_A, P0[11] -> CHY_B
7: none

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2:0 R/W QDEC_CHX_PORT Defines which GPIOs are mapped on Channel X 1
_SEL 0: none
1: P0[2] -> CHX_A, P0[5] -> CHX_B
2: P0[1] -> CHX_A, P0[4] -> CHX_B
3: P0[3] -> CHX_A, P0[10] -> CHX_B
4: P0[6] -> CHX_A, P0[7] -> CHX_B
5: P0[8] -> CHX_A, P0[9] -> CHX_B
6: P0[0] -> CHX_A, P0[11] -> CHX_B
7: none
Table 292: QDEC_ZCNT_REG (0x5000020A)

15:0 R QDEC_Z_CNT Contains a signed value of the events. Zero when 0
channel is disabled
Table 293: QDEC_EVENT_CNT_REG (0x5000020C)

7:0 R QDEC_EVENT_CN Gives the number of events at all channels. 0x0
T

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31.14 Real Time Clock Registers
Table 294: Register map rtc2632_00

0x50004100 RTC_CONTROL_REG RTC Control Register
0x50004104 RTC_HOUR_MODE_ RTC Hour Mode Register
REG
0x50004108 RTC_TIME_REG RTC Time Register
0x5000410C RTC_CALENDAR_RE RTC Calendar Register
G
0x50004110 RTC_TIME_ALARM_R RTC Time Alarm Register
EG
0x50004114 RTC_CALENDAR_AL RTC Calendar Alram Register
ARM_REG
0x50004118 RTC_ALARM_ENABL RTC Alarm Enable Register
E_REG
0x5000411C RTC_EVENT_FLAGS RTC Event Flags Register
_REG
0x50004120 RTC_INTERRUPT_EN RTC Interrupt Enable Register
ABLE_REG
0x50004124 RTC_INTERRUPT_DI RTC Interrupt Disable Register
SABLE_REG
0x50004128 RTC_INTERRUPT_M RTC Interrupt Mask Register
ASK_REG
0x5000412C RTC_STATUS_REG RTC Status Register
0x50004130 RTC_KEEP_RTC_RE RTC Keep RTC Register
G
Table 295: RTC_CONTROL_REG (0x50004100)

1 R/W RTC_CAL_DISABL When this field is set high the RTC stops 0x1
E incrementing the calendar value.
0 R/W RTC_TIME_DISABL When this field is set high the RTC stops 0x1
E incrementing the time value.
Table 296: RTC_HOUR_MODE_REG (0x50004104)

0 R/W RTC_HMS When this field is set high the RTC operates in 12 0x0
hour clock mode; otherwise, times are in 24 hour
clock format.

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Table 297: RTC_TIME_REG (0x50004108)

31 R/W RTC_TIME_CH The value in this register has altered since last 0x0
read. Read and clear.
30 R/W RTC_TIME_PM In 12 hour clock mode, indicates PM when set. 0x0
29:28 R/W RTC_TIME_HR_T Hours tens. Represented in BCD digit (0-2). 0x0
27:24 R/W RTC_TIME_HR_U Hours units. Represented in BCD digit (0-9). 0x0
23 - - 0x0
22:20 R/W RTC_TIME_M_T Minutes tens. Represented in BCD digit (0-5). 0x0
19:16 R/W RTC_TIME_M_U Minutes units. Represented in BCD digit (0-9). 0x0
15 - - 0x0
14:12 R/W RTC_TIME_S_T Seconds tens. Represented in BCD digit (0-9). 0x0
11:8 R/W RTC_TIME_S_U Seconds units. Represented in BCD digit (0-9). 0x0
7:4 R/W RTC_TIME_H_T Hundredths of a second tens. Represented in 0x0
BCD digit (0-9).
3:0 R/W RTC_TIME_H_U Hundredths of a second units. Represented in 0x0
BCD digit (0-9).
Table 298: RTC_CALENDAR_REG (0x5000410C)

31 R/W RTC_CAL_CH The value in this register has altered since last 0x0
read. Read and clear
30 - - 0x0
29:28 R/W RTC_CAL_C_T Century tens. Represented in BCD digit (1-2). 0x2
27:24 R/W RTC_CAL_C_U Century units. Represented in BCD digit (0-9). 0x0
23:20 R/W RTC_CAL_Y_T Year tens. Represented in BCD digit (0-9). 0x0
19:16 R/W RTC_CAL_Y_U Year units. Represented in BCD digit (0-9). 0x0
15:14 - - 0x0
13:12 R/W RTC_CAL_D_T Date tens. Represented in BCD digit (0-3). 0x0
11:8 R/W RTC_CAL_D_U Date units. Represented in BCD digit (0-9). 0x1
7 R/W RTC_CAL_M_T Month tens. Represented in BCD digit (0-1). 0x0
6:3 R/W RTC_CAL_M_U Month units. Represented in BCD digit (0-9). 0x1
2:0 R/W RTC_DAY Day of the week (arbitrary) units. Represented in 0x7
BCD digit (0-7).
Table 299: RTC_TIME_ALARM_REG (0x50004110)

31 - - 0x0
30 R/W RTC_TIME_PM In 12 hour clock mode, indicates PM when set. 0x0

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29:28 R/W RTC_TIME_HR_T Hours tens. Represented in BCD digit (0-2). 0x0
27:24 R/W RTC_TIME_HR_U Hours units. Represented in BCD digit (0-9). 0x0
23 - - 0x0
22:20 R/W RTC_TIME_M_T Minutes tens. Represented in BCD digit (0-5). 0x0
19:16 R/W RTC_TIME_M_U Minutes units. Represented in BCD digit (0-9). 0x0
15 - - 0x0
14:12 R/W RTC_TIME_S_T Seconds tens. Represented in BCD digit (0-9). 0x0
11:8 R/W RTC_TIME_S_U Seconds units. Represented in BCD digit (0-9). 0x0
7:4 R/W RTC_TIME_H_T Hundredths of a second tens. Represented in 0x0
BCD digit (0-9).
3:0 R/W RTC_TIME_H_U Hundredths of a second units. Represented in 0x0
BCD digit (0-9).
Table 300: RTC_CALENDAR_ALARM_REG (0x50004114)

31:14 R/W - 0x0
13:12 R/W RTC_CAL_D_T Date tens. Represented in BCD digit (0-3). 0x0
11:8 R/W RTC_CAL_D_U Date units. Represented in BCD digit (0-9). 0x0
7 R/W RTC_CAL_M_T Month tens. Represented in BCD digit (0-1). 0x0
6:3 R/W RTC_CAL_M_U Month units. Represented in BCD digit (0-9). 0x0
2:0 - - 0x0
Table 301: RTC_ALARM_ENABLE_REG (0x50004118)

5 R/W RTC_ALARM_MNT Alarm on month enable. Enable to trigger alarm 0x0
H_EN when data specified in Calendar Alarm Register
(M_T and M_U) has been reached.
4 R/W RTC_ALARM_DAT Alarm on date enable. Enable to trigger alarm 0x0
E_EN when data specified in Calendar Alarm Register
(D_T and D_U) has been reached.
3 R/W RTC_ALARM_HOU Alarm on hour enable. Enable to trigger alarm 0x0
R_EN when data specified in Time Alarm Register (PM,
HR_T and HR_U) has been reached.
2 R/W RTC_ALARM_MIN_ Alarm on minute enable. Enable to trigger alarm 0x0
EN when data specified in Time Alarm Register (M_T
and M_U) has been reached.
1 R/W RTC_ALARM_SEC Alarm on second enable. Enable to trigger alarm 0x0
_EN when data specified in Time Alarm Register (S_T
and S_U) has been reached.

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0 R/W RTC_ALARM_HOS Alarm on hundredths of a second enable. Enable 0x0
_EN to trigger alarm when data specified in Time Alarm
Register (H_T and H_U) has been reached.
Table 302: RTC_EVENT_FLAGS_REG (0x5000411C)

6 R RTC_EVENT_ALR Alarm event flag. Indicate that alarm event 0x0
M occurred since the last reset.
5 R RTC_EVENT_MNT Month rolls over event flag. Indicate that month 0x0
H rolls over event occurred since the last reset.
4 R RTC_EVENT_DATE Date rolls over event flag. Indicate that date rolls 0x0
over event occurred since the last reset.
3 R RTC_EVENT_HOU Hour rolls over event flag. Indicate that hour rolls 0x0
R over event occurred since the last reset.
2 R RTC_EVENT_MIN Minute rolls over event flag. Indicate that minute 0x0
rolls over event occurred since the last reset.
1 R RTC_EVENT_SEC Second rolls over event flag. Indicate that second 0x0
rolls over event occurred since the last reset.
0 R RTC_EVENT_HOS Hundredths of a second event flag. Indicate that 0x0
hundredths of a second rolls over event occurred
since the last reset.
Table 303: RTC_INTERRUPT_ENABLE_REG (0x50004120)

6 W RTC_ALRM_INT_E Interrupt on alarm enable. Enable to issue the 0x0
N interrupt when alarm event occurred.
5 W RTC_MNTH_INT_E Interrupt on month enable. Enable to issue the 0x0
N interrupt when month event occurred.
4 W RTC_DATE_INT_E Interrupt on date enable. Enable to issue the 0x0
N interrupt when date event occurred.
3 W RTC_HOUR_INT_E Interrupt on hour enable. Enable to issue the 0x0
N interrupt when hour event occurred.
2 W RTC_MIN_INT_EN Interrupt on minute enable. Enable to issue the 0x0
interrupt when minute event occurred.
1 W RTC_SEC_INT_EN Interrupt on second enable. Enable to issue the 0x0
interrupt when second event occurred.
0 W RTC_HOS_INT_EN Interrupt on hundredths of a second enable. 0x0
Enable to issue the interrupt when hundredths of a
second event occurred.

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Table 304: RTC_INTERRUPT_DISABLE_REG (0x50004124)

6 W RTC_ALRM_INT_DI Interrupt on alarm disable. Disable to issue the 0x0
S interrupt when alarm event occurred.
5 W RTC_MNTH_INT_D Interrupt on month disable. Disable to issue the 0x0
IS interrupt when month event occurred.
4 W RTC_DATE_INT_DI Interrupt on date disable. Disable to issue the 0x0
S interrupt when date event occurred.
3 W RTC_HOUR_INT_D IInterrupt on hour disable. Disable to issue the 0x0
IS interrupt when hour event occurred.
2 W RTC_MIN_INT_DIS Interrupt on minute disable. Disable to issue the 0x0
interrupt when minute event occurred.
1 W RTC_SEC_INT_DIS Interrupt on second disable. Disable to issue the 0x0
interrupt when second event occurred.
0 W RTC_HOS_INT_DIS Interrupt on hundredths of a second disable. 0x0
Disable to issue the interrupt when hundredths of
a second event occurred.
Table 305: RTC_INTERRUPT_MASK_REG (0x50004128)

6 R RTC_ALRM_INT_M Mask alarm interrupt. It can be cleared (set) by 0x1
SK setting corresponding bit (ALRM) in Interrupt
Enable Register (Interrupt Disable Register).
5 R RTC_MNTH_INT_M Mask month interrupt. It can be cleared (set) by 0x1
SK setting corresponding bit (MNTH) in Interrupt
4 R RTC_DATE_INT_M Mask date interrupt. It can be cleared (set) by 0x1
SK setting corresponding bit (DATE) in Interrupt
3 R RTC_HOUR_INT_M Mask hour interrupt. It can be cleared (set) by 0x1
SK setting corresponding bit (HOUR) in Interrupt
2 R RTC_MIN_INT_MS Mask minute interrupt. It can be cleared (set) by 0x1
K setting corresponding bit (MIN) in Interrupt Enable
Register (Interrupt Disable Register).
1 R RTC_SEC_INT_MS Mask second interrupt. It can be cleared (set) by 0x1
K setting corresponding bit (SEC) in Interrupt Enable
Register (Interrupt Disable Register).
0 R RTC_HOS_INT_MS Mask hundredths of a second interrupt. It can be 0x1
K cleared (set) by setting corresponding bit (HOS) in
Interrupt Enable Register (Interrupt Disable
Register).

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Table 306: RTC_STATUS_REG (0x5000412C)

3 R RTC_VALID_CAL_ Valid Calendar Alarm. If cleared then indicates 0x1
ALM that invalid entry occurred when writing to
Calendar Alarm Register.
2 R RTC_VALID_TIME_ Valid Time Alarm. If cleared then indicates that 0x1
ALM invalid entry occurred when writing to Time Alarm
Register.
1 R RTC_VALID_CAL Valid Calendar. If cleared then indicates that 0x1
invalid entry occurred when writing to Calendar
Register.
0 R RTC_VALID_TIME Valid Time. If cleared then indicates that invalid 0x1
entry occurred when writing to Time Register.
Table 307: RTC_KEEP_RTC_REG (0x50004130)

0 R/W RTC_KEEP Keep RTC. When high, the time and calendar 0x1
registers and any other registers which directly
affect or are affected by the time and calendar
registers are NOT reset when software reset is
applied. When low, the software reset will reset
every register except the keep RTC and control
registers.

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31.15 SPI Interface Registers
Table 308: Register map SPI

0x50001200 SPI_CTRL_REG Spi control register
0x50001204 SPI_CONFIG_REG Spi control register
0x50001208 SPI_CLOCK_REG Spi clock register
0x5000120C SPI_FIFO_CONFIG_R Spi fifo configuration register
EG
0x50001210 SPI_IRQ_MASK_REG Spi interrupt mask register
0x50001214 SPI_STATUS_REG Spi status register
0x50001218 SPI_FIFO_STATUS_R SPI RX/TX fifo status register
EG
0x5000121C SPI_FIFO_READ_RE Spi RX fifo read register
G
0x50001220 SPI_FIFO_WRITE_RE Spi TX fifo wtite register
G
0x50001224 SPI_CS_CONFIG_RE Spi cs configuration register
G
0x50001228 SPI_FIFO_HIGH_REG Spi TX/RX High 16bit word
0x5000122C SPI_TXBUFFER_FOR SPI TX buffer force low value
CE_L_REG
0x50001230 SPI_TXBUFFER_FOR SPI TX buffer force high value
CE_H_REG
Table 309: SPI_CTRL_REG (0x50001200)

7 R/W SPI_SWAP_BYTES 0 = normal operation 0x0
1 = LSB and MSB are swaped in APB interface
In case of 8bit spi interface, DMA/SPI can be
configured in 16bit mode to off load the bus.
Enabling SPI_SWAP_BYTES bytes will read/wrte
correctly
6 R/W SPI_CAPTURE_AT 0 = SPI captures data at correct clock edge 0x0
_NEXT_EDGE 1 = SPI captures data at next clock edge. (only for
Master mode and high clock)
5 R/W SPI_FIFO_RESET 0 = Fifo normal operation 0x0
1 = Fifo in reset state
4 R/W SPI_DMA_RX_EN applicable only when SPI_RX_EN=1 0x0

0 = No DMA request for RX
1 = DMA request when
SPI_STATUS_RX_FULL='1'

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3 R/W SPI_DMA_TX_EN applicable only when SPI_TX_EN=1 0x0
0 = No DMA request for TX
1 = DMA request when
SPI_STATUS_TX_EMPTY='1'
2 R/W SPI_RX_EN 0 = RX path is disabled 0x0

1 = RX path is enabled
Note: if master clk async or spi mode=1 or spi
mode=3 readonly is not supported
1 R/W SPI_TX_EN 0 = TX path is disabled 0x0
1 = TX path is enabled
0 R/W SPI_EN 0 = SPI module is disable 0x0

1 = SPI module is enable
Table 310: SPI_CONFIG_REG (0x50001204)

7 R/W SPI_SLAVE_EN 0 = SPI module master mode 0x0
1 = SPI module slave mode
6:2 R/W SPI_WORD_LENG Define the spi word length = 1+ 0x0

TH SPI_WORD_LENGTH (range 4 to 32)
1:0 R/W SPI_MODE Define the spi mode (CPOL, CPHA) 0x0
0 = new data on falling, capture on rising, clk low
in idle state
1 = new data on rising, capture on falling, Clk low
in idle state
2 = new data on rising, capture on falling, Clk high
in idle state
3 = new data on falling, capture on rising Clk high
in idle state
Table 311: SPI_CLOCK_REG (0x50001208)

7 R/W SPI_MASTER_CLK Should be always 1 0x0
_MODE

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6:0 R/W SPI_CLK_DIV Applicable only in master mode 0x0
Defines the spi clock frequency in master only
mode
SPI_CLK = module_clk / 2*(SPI_CLK_DIV+1)
when SPI_CLK_DIV not 0x7F
if SPI_CLK_DIV=0x7F then SPI_CLK=module_clk
Table 312: SPI_FIFO_CONFIG_REG (0x5000120C)

7:4 R/W SPI_RX_TL Receive FIFO threshold level in bytes. Control the 0x0
level of bytes in fifo that triggers the RX_FULL
interrupt. IRQ is occurred when fifo level is more
or equal to SPI_RX_TL+1. Fifo level is from 0 to 4
3:0 R/W SPI_TX_TL Transmit FIFO threshold level in bytes. Control the 0x0
level of bytes in fifo that triggers the TX_EMPTY
interrupt. IRQ is occurred when fifo level is less or
equal to SPI_TX_TL. Fifo level is from 0 to 4
Table 313: SPI_IRQ_MASK_REG (0x50001210)

1 R/W SPI_IRQ_MASK_R 0 = FIFO RX full irq is masked 0x0
X_FULL 1 = FIFO RX full irq is enabled
0 R/W SPI_IRQ_MASK_TX 0 = FIFO TX empty irq is masked 0x0

_EMPTY 1 = FIFO TX empy irq is enabled
Table 314: SPI_STATUS_REG (0x50001214)

1 R SPI_STATUS_RX_ Auto clear 0x0
FULL 0 = RX fifo level is less than SPI_RX_TL+1
1 = RX fifo level is more or equal to SPI_RX_TL+1
0 R SPI_STATUS_TX_E Auto clear 0x1

MPTY 0 = TX fifo level is larger than SPI_TX_TL
1 = TX fifo level is less or equal to SPI_TX_TL

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Table 315: SPI_FIFO_STATUS_REG (0x50001218)

15 R SPI_TRANSACTIO In master mode 0x0
N_ACTIVE 0 = spi transaction is inactive
1 = spi transaction is active
14 R SPI_RX_FIFO_OVF When 1, receive data is not written to fifo because 0x0
L fifo was full and interrupt is generated. It clears
with SPI_CTRL_REG.SPI_FIFO_RESET
13 R SPI_STATUS_TX_F 0 = TX fifo is not full 0x0

ULL 1 = TX fifo is full
12 R SPI_STATUS_RX_ 0 = RX fifo is not empty 0x1

EMPTY 1 = RX fifo is empty
11:6 R SPI_TX_FIFO_LEV Gives the number of bytes in TX fifo 0x0

EL
5:0 R SPI_RX_FIFO_LEV Gives the number of bytes in RX fifo 0x0
EL
Table 316: SPI_FIFO_READ_REG (0x5000121C)

15:0 R SPI_FIFO_READ Read from RX fifo. Read access is permit only if 0x0
SPI_STATUS_RX_EMPTY=0. Returns the 16 LSb
Table 317: SPI_FIFO_WRITE_REG (0x50001220)

15:0 R0/W SPI_FIFO_WRITE Write to TX fifo. Write access is permit only if 0x0
SPI_STATUS_TX_FULL is 0
Table 318: SPI_CS_CONFIG_REG (0x50001224)

2:0 R/W SPI_CS_SELECT Control the cs output in master mode 0x0
0 = none slave device selected
1 = selected slave device connected to GPIO with
FUNC_MODE=SPI_CS0
FUNC_MODE=SPI_CS1
FUNC_MODE=GPIO

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Table 319: SPI_FIFO_HIGH_REG (0x50001228)

15:0 R/W SPI_FIFO_HIGH RX/TX fifo data. 16 MSb when spi word is larger 0x0
than 16bits
This register has to be written before the
SPI_FIFO_WRITE_REG
This register has to be read after the
SPI_FIFO_READ_REG
Table 320: SPI_TXBUFFER_FORCE_L_REG (0x5000122C)

15:0 W SPI_TXBUFFER_F Write directly the tx buffer (2 LSB). It must to be 0x0
ORCE_L used only in slave mode
Table 321: SPI_TXBUFFER_FORCE_H_REG (0x50001230)

15:0 W SPI_TXBUFFER_F Write directly the tx buffer (2 MSB). It must to be 0x0
ORCE_H used only in slave mode.
This register has to be written before the
SPI_FIFO_WRITE_REG

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31.16 Timer and Triple PWM Registers
Table 322: Register map Timer+3PWM

0x50003400 TIMER0_CTRL_REG Timer0 control register
0x50003402 TIMER0_ON_REG Timer0 on control register
0x50003404 TIMER0_RELOAD_M_ 16 bits reload value for Timer0
REG
0x50003406 TIMER0_RELOAD_N_ 16 bits reload value for Timer0
REG
0x50003408 TRIPLE_PWM_FREQ Frequency for PWM 2,3,4,5,6 and 7
UENCY
0x5000340A PWM2_START_CYCL Defines start Cycle for PWM2
E
0x5000340C PWM3_START_CYCL Defines start Cycle for PWM3
E
0x5000340E PWM4_START_CYCL Defines start Cycle for PWM4
E
0x50003410 PWM5_START_CYCL Defines start Cycle for PWM5
E
E
E
0x50003416 PWM2_END_CYCLE Defines end Cycle for PWM2
0x5000341A PWM4_END_CYCLE Defines end Cycle for PWM4
0x5000341C PWM5_END_CYCLE Defines end Cycle for PWM5
0x5000341E PWM6_END_CYCLE Defines end Cycle for PWM6
0x50003422 TRIPLE_PWM_CTRL_ PWM 2,3,4,5,6,7 Control
REG
Table 323: TIMER0_CTRL_REG (0x50003400)

15:4 - - 0x0
3 R/W PWM_MODE 0 = PWM signals are '1' during high time. 0x0
1 = PWM signals send out the (fast) clock divided
by 2 during high time. So it will be in the range of 1
to 8 MHz.

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2 R/W TIM0_CLK_DIV 1 = Timer0 uses selected clock frequency as is. 0x0
0 = Timer0 uses selected clock frequency divided
by 10.
Note that this applies only to the ON-counter.
1 R/W TIM0_CLK_SEL 1 = Timer0 uses 16, 8, 4 or 2 MHz (fast) clock 0x0
frequency.
0 = Timer0 uses LP clock
0 R/W TIM0_CTRL 0 = Timer0 is off and in reset state. 0x0
1 = Timer0 is running.
Table 324: TIMER0_ON_REG (0x50003402)

15:0 R/W TIM0_ON Timer0 On reload value: 0x0
If read the actual ON-counter value is returned
Table 325: TIMER0_RELOAD_M_REG (0x50003404)

15:0 R/W TIM0_M Timer0 'high' reload value 0x0
If read the actual T0-counter value is returned
Table 326: TIMER0_RELOAD_N_REG (0x50003406)

15:0 R/W TIM0_N Timer0 'low' reload value: 0x0
If read the actual T0-counter value is returned
Table 327: TRIPLE_PWM_FREQUENCY (0x50003408)

13:0 R/W PWM_FREQ Defines the frequeancy of PWM 2,3,4,5,,6 and 7. 0x0
pwm freq = module Frequency / (value+1)
module frequency is the LP_CLK when
TRIPLE_PWM_CLK_SEL=0 else is the sys_clk
divided by TMR_DIV

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Table 328: PWM2_START_CYCLE (0x5000340A)

13:0 R/W START_CYCLE Defines the cycle in which the PWM becomes 0x0
high. if start_cycle is larger than freq or end_cycle
is equal to start_cycle, pwm out is always 0
Table 329: PWM3_START_CYCLE (0x5000340C)

Table 330: PWM4_START_CYCLE (0x5000340E)

Table 331: PWM5_START_CYCLE (0x50003410)




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Table 334: PWM2_END_CYCLE (0x50003416)

13:0 R/W END_CYCLE Defines the cycle in which the PWM becomes low. 0x0
If end_cycle is larger then freq and start_cycle is
not larger then freq, output is always 1

Table 336: PWM4_END_CYCLE (0x5000341A)

Table 337: PWM5_END_CYCLE (0x5000341C)

Table 338: PWM6_END_CYCLE (0x5000341E)



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Table 340: TRIPLE_PWM_CTRL_REG (0x50003422)

3 R/W TRIPLE_PWM_CLK 1 = Timer2 uses 16, 8, 4 or 2 MHz (fast) clock 0x0
_SEL frequency.
0 = Timer2 uses LP clock
2 R/W HW_PAUSE_EN '1' = HW can pause PWM 2,3,4,5,6,7 0x1
1 R/W SW_PAUSE_EN '1' = PWM 2 3 4 5 6 7 are paused 0x0
0 R/W TRIPLE_PWM_ENA '1' = enable PWM 2 3 4 5 6 7 0x0
BLE

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31.17 Timer1 Registers
Table 341: Register map Timer1

0x50004000 TIMER1_CTRL_REG Timer1 control register
0x50004004 TIMER1_CAPTURE_R Timer1 Capture control register
EG
0x50004008 TIMER1_STATUS_RE Timer1 counter value
G
0x5000400C TIMER1_CAPCNT1_V Timer1 value for event on GPIO1
ALUE_REG
0x50004010 TIMER1_CAPCNT2_V Timer1 value for event on GPIO2
ALUE_REG
0x50004014 TIMER1_CLR_EVENT Clear event register
_REG
Table 342: TIMER1_CTRL_REG (0x50004000)

16 R/W TIMER1_CLK_EN 0 = timer1 clock is disabled 0x0
1 = timer1 clock is enabled
15 R/W TIMER1_USE_SYS 0 = Timer1 use the clock LP clock 0x0
_CLK 1 = Timer1 use the system clock
14 R/W TIMER1_FREE_RU Applicable when timer counts up 0x0
N_MODE_EN 1 = timer1 goes to zero when it reaches the max
value.
0 = timer1 goes to zero when it reaches the reload
value.
13 R/W TIMER1_IRQ_EN 0 = timer1 IRQ masked 0x0
1 = timer1 IRQ unmasked
12 R/W TIMER1_COUNT_D 0 = timer1 counts up 0x0
OWN_EN 1 = timer1 counts down
11 R/W TIMER1_ENABLE 0 = Timer1 disabled 0x0
1 = Timer1 enabled
10:0 R/W TIMER1_RELOAD Reload or max value in timer mode. Actual delay 0x0
is the register value plus synchronization time (3
clock cycles)
Table 343: TIMER1_CAPTURE_REG (0x50004004)

27 R/W TIMER1_IN2_STAM 0 = On each event store the counter value 0x0
P_TYPE 1 = On each event store the RTC time stamp

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26:21 R/W TIMER1_IN2_PERI Gives the number of periods +1 of IN2, in which 0x0
OD_MAX module counts
20 R/W TIMER1_IN2_IRQ_ 1 = Interrupt is generated when capture is 0x0
EN occurred or was counted
TIMER1_IN2_PERIOD_MAX
0 = Interrupt is masked
19 R/W TIMER1_IN2_COU 0 = Capture mode 0x0
NT_EN 1 = Count mode
18 R/W TIMER1_IN2_EVEN 0 = Rising edge event 0x0
T_FALL_EN 1 = Falling edge event
it should be written when
TIMER1_GPIO2_CONF=0 to prevent false events
17:14 R/W TIMER1_GPIO2_C 0,13,14,15 = IN2 is not used 0x0
ONF 1..12 = Defines the P0 pin (0..11) module will use
as IN2
13 R/W TIMER1_IN1_STAM 0 = On each event store the counter value 0x0
P_TYPE 1 = On each event store the RTC time stamp
12:7 R/W TIMER1_IN1_PERI Gives the number of periods +1 of IN1, in which 0x0
OD_MAX module counts
6 R/W TIMER1_IN1_IRQ_ 1 = Interrupt is generated when capture is 0x0
EN occurred or was counted
TIMER1_IN1_PERIOD_MAX
0 = Interrupt is masked
5 R/W TIMER1_IN1_COU 0 = Capture mode 0x0
NT_EN 1 = Count mode
4 R/W TIMER1_IN1_EVEN 0 = Rising edge event 0x0
T_FALL_EN 1 = Falling edge event
it should be written when
TIMER1_GPIO1_CONF=0 to prevent false events
3:0 R/W TIMER1_GPIO1_C 0,13,14,15 = IN1 is not used 0x0
ONF 1..12 = Defines the P0 pin (0..11) module will use
as IN1
Table 344: TIMER1_STATUS_REG (0x50004008)

15 R TIMER1_IN2_OVRF 1 = New IN2 event occurred while Interrupt was 0x0
LW pending.
TIMER1_CAPCNT2_VALUE_REG gives the time
stamp of the first event.
14 R TIMER1_IN1_OVRF 1 = New IN1 event occurred while Interrupt was 0x0
LW pending.
TIMER1_CAPCNT1_VALUE_REG gives the time
stamp of the first event.
13 R TIMER1_IN2_EVEN 1 = Pending Capture 2 interrupt. It has be clear 0x0
T writing 1 to TIMER1_CLR_IN2_EVENT

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12 R TIMER1_IN1_EVEN 1 = Pending Capture 1 interrupt. It has be clear 0x0
T writing 1 to TIMER1_CLR_IN1_EVENT
11 R TIMER1_TIMER_E 1 = Pending Timer interrupt. it has be clear writing 0x0
VENT 1' to TIMER1_CLR_TIMER_EVENT
10:0 R TIMER1_TIMER_V Gives the current timer value 0x0
ALUE
Table 345: TIMER1_CAPCNT1_VALUE_REG (0x5000400C)

21:11 R TIMER1_CAPCNT1 In Counter mode : Not used 0x0
_RTC_HIGH In Capture mode: Gives the RTC time stamp (high
part) when an IN1 event was occurred
10:0 R TIMER1_CAPCNT1 In Counter mode : Gives the number of timer clock 0x0
_VALUE cycles minus 1 which was measured during
TIMER1_IN1_PERIOD_MAX periods of IN1
In Capture mode
(TIMER1_IN1_STAMP_TYPE=0) : Gives the
Counter value when an IN1 event was occurred
In Capture mode
(TIMER1_IN1_STAMP_TYPE=1) : Gives the RTC
time stamp (low part) when an IN1 event was
occurred
Table 346: TIMER1_CAPCNT2_VALUE_REG (0x50004010)

21:11 R TIMER1_CAPCNT2 In Counter mode : Not used 0x0
_RTC_HIGH In Capture mode: Gives the RTC time stamp (high
part) when an IN2 event was occurred
10:0 R TIMER1_CAPCNT2 In Counter mode : Gives the number of timer clock 0x0
_VALUE cycles minus 1 which was measured during
TIMER1_IN2_PERIOD_MAX periods of IN2
In Capture mode
(TIMER1_IN2_STAMP_TYPE=0) : Gives the
Counter value when an IN2 event was occurred
In Capture mode
(TIMER1_IN2_STAMP_TYPE=1) : Gives the RTC
time stamp (low part) when an IN2 event was
occurred
Table 347: TIMER1_CLR_EVENT_REG (0x50004014)

2 R0/WC TIMER1_CLR_IN2_ Write 1 to clear the TIMER1_IN2_EVENT and 0x0
EVENT TIMER1_IN2_OVRFLW

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1 R0/WC TIMER1_CLR_IN1_ Write 1 to clear the TIMER1_IN1_EVENT and 0x0
EVENT TIMER1_IN1_OVRFLW
0 R0/WC TIMER1_CLR_TIME Write 1 to clear the TIMER1_TIMER_EVENT 0x0
R_EVENT

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31.18 UART Interface Registers
Table 348: Register map UART

0x50001000 UART_RBR_THR_DL Receive Buffer Register/Transmit Holding Register/Divisor Latch
L_REG Low
0x50001004 UART_IER_DLH_REG Interrupt Enable Register/Divisor Latch High
0x50001008 UART_IIR_FCR_REG Interrupt Identification Register/FIFO Control Register
0x5000100C UART_LCR_REG Line Control Register
0x50001010 UART_MCR_REG Modem Control Register
0x50001014 UART_LSR_REG Line Status Register
0x50001018 UART_MSR_REG Modem Status Register
0x5000101C UART_SCR_REG Scratchpad Register
0x50001030 UART_SRBR_STHR0 Shadow Receive/Transmit Buffer Register
_REG
_REG
_REG
0x5000103C UART_SRBR_STHR3 Shadow Receive/Transmit Buffer Register
_REG
_REG
_REG
_REG
_REG
_REG
_REG
0_REG
1_REG
2_REG
3_REG
4_REG
5_REG

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0x50001070 UART_FAR_REG FIFO Access Register
0x5000107C UART_USR_REG UART Status Register
0x50001080 UART_TFL_REG Transmit FIFO Level
0x50001084 UART_RFL_REG Receive FIFO Level
0x50001088 UART_SRR_REG Software Reset Register.
0x5000108C UART_SRTS_REG Shadow Request to Send
0x50001090 UART_SBCR_REG Shadow Break Control Register
0x50001094 UART_SDMAM_REG Shadow DMA Mode
0x50001098 UART_SFE_REG Shadow FIFO Enable
0x5000109C UART_SRT_REG Shadow RCVR Trigger
0x500010A0 UART_STET_REG Shadow TX Empty Trigger
0x500010A4 UART_HTX_REG Halt TX
0x500010A8 UART_DMASA_REG DMA Software Acknowledge
0x500010C0 UART_DLF_REG Divisor Latch Fraction Register
0x500010F8 UART_UCV_REG Component Version
0x500010FA UART_UCV_HIGH_R Component Version
EG
0x500010FC UART_CTR_REG Component Type Register
0x500010FE UART_CTR_HIGH_R Component Type Register
EG
0x50001100 UART2_RBR_THR_D Receive Buffer Register/Transmit Holding Register/Divisor Latch
LL_REG Low
0x50001104 UART2_IER_DLH_RE Interrupt Enable Register/Divisor Latch High
G
0x50001108 UART2_IIR_FCR_RE Interrupt Identification Register/FIFO Control Register
G
0x5000110C UART2_LCR_REG Line Control Register
0x50001110 UART2_MCR_REG Modem Control Register
0x50001114 UART2_LSR_REG Line Status Register
0x5000111C UART2_SCR_REG Scratchpad Register
0x50001130 UART2_SRBR_STHR Shadow Receive/Transmit Buffer Register
0_REG
1_REG
2_REG
0x5000113C UART2_SRBR_STHR Shadow Receive/Transmit Buffer Register
3_REG
4_REG
5_REG

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6_REG
7_REG
8_REG
9_REG
10_REG
11_REG
12_REG
13_REG
14_REG
15_REG
0x50001170 UART2_FAR_REG FIFO Access Register
0x5000117C UART2_USR_REG UART Status Register
0x50001180 UART2_TFL_REG Transmit FIFO Level
0x50001184 UART2_RFL_REG Receive FIFO Level
0x50001188 UART2_SRR_REG Software Reset Register.
0x50001190 UART2_SBCR_REG Shadow Break Control Register
0x50001194 UART2_SDMAM_REG Shadow DMA Mode
0x50001198 UART2_SFE_REG Shadow FIFO Enable
0x5000119C UART2_SRT_REG Shadow RCVR Trigger
0x500011A0 UART2_STET_REG Shadow TX Empty Trigger
0x500011A4 UART2_HTX_REG Halt TX
0x500011A8 UART2_DMASA_REG DMA Software Acknowledge
0x500011C0 UART2_DLF_REG Divisor Latch Fraction Register
0x500011F8 UART2_UCV_REG Component Version
0x500011FA UART2_UCV_HIGH_R Component Version
EG
0x500011FC UART2_CTR_REG Component Type Register
0x500011FE UART2_CTR_HIGH_R Component Type Register
EG

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Table 349: UART_RBR_THR_DLL_REG (0x50001000)

15:8 - - 0x0
7:0 R/W RBR_THR_DLL Receive Buffer Register: (RBR). 0x0
This register contains the data byte received on
the serial input port (sin) in UART mode. The data
in this register is valid only if the Data Ready (DR)
bit in the Line status Register (LSR) is set. If
FIFOs are disabled (FCR[0] set to zero), the data
in the RBR must be read before the next data
arrives, otherwise it will be overwritten, resulting in
an overrun error. If FIFOs are enabled (FCR[0] set
to one), this register accesses the head of the
receive FIFO. If the receive FIFO is full and this
register is not read before the next data character
arrives, then the data already in the FIFO will be
preserved but any incoming data will be lost. An
overrun error will also occur.
Transmit Holding Register: (THR)
This register contains data to be transmitted on
the serial output port (sout) in UART mode. Data
should only be written to the THR when the THR
Empty (THRE) bit (LSR[5]) is set. If FIFO's are
disabled (FCR[0] set to zero) and THRE is set,
writing a single character to the THR clears the
THRE. Any additional writes to the THR before the
THRE is set again causes the THR data to be
overwritten. If FIFO's are enabled (FCR[0] set to
one) and THRE is set, 16 number of characters of
data may be written to the THR before the FIFO is
full. Any attempt to write data when the FIFO is full
results in the write data being lost.
Divisor Latch (Low): (DLL)
This register makes up the lower 8-bits of a 16-bit,
read/write, Divisor Latch register that contains the
baud rate divisor for the UART. This register may
only be accessed when the DLAB bit (LCR[7]) is
set. The output baud rate is equal to the serial
clock (sclk) frequency divided by sixteen times the
value of the baud rate divisor, as follows:
baud rate = (serial clock freq) / (16 * divisor)
Note that with the Divisor Latch Registers (DLL
and DLH) set to zero, the baud clock is disabled
and no serial communications will occur. Also,
once the Divisor Latch is set, at least 8 clock
cycles of the slowest UART clock should be
allowed to pass before transmitting or receiving
data.
For the Divisor Latch (High) bits, see register
UART_IER_DLH_REG.
Table 350: UART_IER_DLH_REG (0x50001004)

15:8 - - 0x0

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7 R/W PTIME_dlh7 Interrupt Enable Register: PTIME, 0x0
Programmable THRE Interrupt Mode Enable. This
is used to enable/disable the generation of THRE
Interrupt. 0 = disabled 1 = enabled.
Divisor Latch (High): DLH7, Bit 7 of the upper
part of a 16-bit, read/write, Divisor Latch register
that contains the baud rate divisor for the UART.
This register may be accessed only when the
DLAB bit (LCR[7]) is set. See register
UART_RBR_THR_DLL_REG.
6:4 R/W dlh6_4 Divisor Latch (High): DLH6 to DLH4, Bits 6 to 4 0x0
of the upper part of a 16-bit, read/write, Divisor
Latch register that contains the baud rate divisor
for the UART. This register may be accessed only
when the DLAB bit (LCR[7]) is set, otherwise, this
field is reserved. See register
3 R/W EDSSI_dlh3 Interrupt Enable Register: EDSSI, Enable 0x0
Modem Status Interrupt. This is used to
enable/disable the generation of Modem Status
Interrupt. This is the fourth highest priority
interrupt. 0 = disabled 1 = enabled
2 R/W ELSI_dhl2 Interrupt Enable Register: ELSI, Enable 0x0
Receiver Line Status Interrupt. This is used to
enable/disable the generation of Receiver Line
Status Interrupt. This is the highest priority
1 R/W ETBEI_dlh1 Interrupt Enable Register: ETBEI, Enable 0x0
Transmit Holding Register Empty Interrupt. This is
used to enable/disable the generation of
Transmitter Holding Register Empty Interrupt. This
is the third highest priority interrupt. 0 = disabled 1
= enabled

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0 R/W ERBFI_dlh0 Interrupt Enable Register: ERBFI, Enable 0x0
Received Data Available Interrupt. This is used to
enable/disable the generation of Received Data
Available Interrupt and the Character Timeout
Interrupt (if in FIFO mode and FIFO's enabled).
These are the second highest priority interrupts. 0
= disabled 1 = enabled
Table 351: UART_IIR_FCR_REG (0x50001008)

7:6 R/W UART_FIFOSE_RT On read 0x0
FIFO's Enabled (or FIFOSE): This is used to
indicate whether the FIFO's are enabled or
disabled. 00 = disabled. 11 = enabled.
On write
RCVR Trigger (or RT):. This is used to select the
trigger level in the receiver FIFO at which the
Received Data Available Interrupt will be
generated. In auto flow control mode it is used to
determine when the rts_n signal will be de-
asserted. It also determines when the
dma_rx_req_n signal will be asserted when in
certain modes of operation. The following trigger
levels are supported: 00 = 1 character in the FIFO
01 = FIFO 1/4 full 10 = FIFO 1/2 full 11 = FIFO 2
less than full
5:4 R0/W UART_TET On read 0x0
reserved
On Write
TX Empty Trigger (or TET): This is used to select
the empty threshold level at which the THRE
Interrupts will be generated when the mode is
active. It also determines when the dma_tx_req_n
signal will be asserted when in certain modes of
operation. The following trigger levels are
supported: 00 = FIFO empty 01 = 2 characters in
the FIFO 10 = FIFO 1/4 full 11 = FIFO 1/2 full

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3 R/W UART_IID3_DMAM On Read (Bit3) 0x0
Interrupt ID (or IID): This indicates the highest
priority pending interrupt which can be one of the
following types:
0001 = no interrupt pending.
0010 = THR empty.
0100 = received data available.
0110 = receiver line status.
0111 = busy detect.
1100 = character timeout.
On Write
DMA Mode (or DMAM): This determines the DMA
signalling mode used for the dma_tx_req_n and
dma_rx_req_n output signals. 0 = mode 0 1 =
mode 1
2 R/W UART_IID2_XFIFO On Read (Bit2) 0x0
R Interrupt ID (or IID): This indicates the highest
following types:
0010 = THR empty.
0111 = busy detect.
On Write
XMIT FIFO Reset (or XFIFOR): This resets the
control portion of the transmit FIFO and treats the
FIFO as empty. Note that this bit is 'self-clearing'
and it is not necessary to clear this bit.
1 R/W UART_IID1_RFIFO On Read (Bit1) 0x0
E Interrupt ID (or IID): This indicates the highest
following types:
0010 = THR empty.
0111 = busy detect.
On Write
RCVR FIFO Reset (or RFIFOR): This resets the
control portion of the receive FIFO and treats the

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0 R/W UART_IID0_FIFOE On Read (Bit0) 0x1
following types:
0010 = THR empty.
0111 = busy detect.
On Write
FIFO Enable (or FIFOE): This enables/disables
the transmit (XMIT) and receive (RCVR) FIFO's.
Whenever the value of this bit is changed both the
XMIT and RCVR controller portion of FIFO's will
be reset
Table 352: UART_LCR_REG (0x5000100C)

15:8 - - 0x0
7 R/W UART_DLAB Divisor Latch Access Bit. Writeable only when 0x0
UART is not busy (USR[0] is zero).
This bit is used to enable reading and writing of
the Divisor Latch register (DLL and DLH) to set
the baud rate of the UART.
This bit must be cleared after initial baud rate
setup in order to access other registers.
6 R/W UART_BC Break Control Bit. 0x0
This is used to cause a break condition to be
transmitted to the receiving device. If set to one
the serial output is forced to the spacing (logic 0)
state. When not in Loopback Mode, as determined
by MCR[4], the sout line is forced low until the
Break bit is cleared. If active (MCR[6] set to one)
the sir_out_n line is continuously pulsed. When in
Loopback Mode, the break condition is internally
looped back to the receiver and the sir_out_n line
is forced low.
5 - - 0x0
4 R/W UART_EPS Even Parity Select. Writeable only when UART is 0x0
not busy (USR[0] is zero).
This is used to select between even and odd
parity, when parity is enabled (PEN set to one). If
set to one, an even number of logic 1s is
transmitted or checked. If set to zero, an odd
number of logic 1s is transmitted or checked.

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3 R/W UART_PEN Parity Enable. Writeable only when UART is not 0x0
busy (USR[0] is zero)
This bit is used to enable and disable parity
generation and detection in transmitted and
received serial character respectively.
0 = parity disabled
1 = parity enabled
2 R/W UART_STOP Number of stop bits.Writeable only when UART is 0x0
This is used to select the number of stop bits per
character that the peripheral transmits and
receives. If set to zero, one stop bit is transmitted
in the serial data.
If set to one and the data bits are set to 5
(LCR[1:0] set to zero) one and a half stop bits is
transmitted. Otherwise, two stop bits are
transmitted. Note that regardless of the number of
stop bits selected, the receiver checks only the
first stop bit.
0 = 1 stop bit
1 = 1.5 stop bits when DLS (LCR[1:0]) is zero,
else 2 stop bit
1:0 R/W UART_DLS Data Length Select.Writeable only when UART is 0x0
This is used to select the number of data bits per
receives. The number of bit that may be selected
areas follows:
00 = 5 bits
01 = 6 bits
10 = 7 bits
11 = 8 bits
Table 353: UART_MCR_REG (0x50001010)

15:7 - - 0x0
6 - - 0x0
5 R/W UART_AFCE Auto Flow Control Enable. 0x0
When FIFOs are enabled and the Auto Flow
Control Enable (AFCE) bit is set, Auto Flow
Control features are enabled.
0 = Auto Flow Control Mode disabled
1 = Auto Flow Control Mode enabled

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4 R/W UART_LB LoopBack Bit. 0x0
This is used to put the UART into a diagnostic
mode for test purposes.
If operating in UART mode (SIR_MODE not
active, MCR[6] set to zero), data on the sout line is
held high, while serial data output is looped back
to the sin line, internally. In this mode all the
interrupts are fully functional. Also, in loopback
mode, the modem control inputs (dsr_n, cts_n,
ri_n, dcd_n) are disconnected and the modem
control outputs (dtr_n, rts_n, out1_n, out2_n) are
looped back to the inputs, internally.
If operating in infrared mode (SIR_MODE active,
MCR[6] set to one), data on the sir_out_n line is
held low, while serial data output is inverted and
looped back to the sir_in line.
3 - - 0x0
2 - - 0x0
1 R/W UART_RTS Request to Send. 0x0
This is used to directly control the Request to
Send (rts_n) output. The Request To Send (rts_n)
output is used to inform the modem or data set
that the UART is ready to exchange data.
When Auto RTS Flow Control is not enabled
(MCR[5] set to zero), the rts_n signal is set low by
programming MCR[1] (RTS) to a high.In Auto
Flow Control, AFCE_MODE == Enabled and
active (MCR[5] set to one) and FIFOs enable
(FCR[0] set to one), the rts_n output is controlled
in the same way, but is also gated with the
receiver FIFO threshold trigger (rts_n is inactive
high when above the threshold). The rts_n signal
is de-asserted when MCR[1] is set low.
Note that in Loopback mode (MCR[4] set to one),
the rts_n output is held inactive high while the
value of this location is internally looped back to
an input.
0 - - 0x0
Table 354: UART_LSR_REG (0x50001014)

15:8 - - 0x0

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7 R UART_RFE Receiver FIFO Error bit. 0x0
This bit is only relevant when FIFOs are enabled
(FCR[0] set to one). This is used to indicate if
there is at least one parity error, framing error, or
break indication in the FIFO.
0 = no error in RX FIFO
1 = error in RX FIFO
This bit is cleared when the LSR is read and the
character with the error is at the top of the receiver
FIFO and there are no subsequent errors in the
FIFO.
6 R UART_TEMT Transmitter Empty bit. 0x1
If FIFOs enabled (FCR[0] set to one), this bit is set
whenever the Transmitter Shift Register and the
FIFO are both empty. If FIFOs are disabled, this
bit is set whenever the Transmitter Holding
Register(THR) and the Transmitter Shift Register
are both empty.
5 R UART_THRE Transmit Holding Register Empty bit. 0x1
If THRE mode is disabled (IER[7] set to zero) and
regardless of FIFO's being implemented/enabled
or not, this bit indicates that the THR or TX FIFO
is empty.
This bit is set whenever data is transferred from
the THR or TX FIFO to the transmitter shift
register and no new data has been written to the
THR or TX FIFO. This also causes a THRE
Interrupt to occur, if the THRE Interrupt is enabled.
If both modes are active (IER[7] set to one and
FCR[0] set to one respectively), the functionality is
switched to indicate the transmitter FIFO is full,
and no longer controls THRE interrupts, which are
then controlled by the FCR[5:4] threshold setting.
4 R UART_BI Break Interrupt bit. 0x0
This is used to indicate the detection of a break
sequence on the serial input data.
If in UART mode (SIR_MODE == Disabled), it is
set whenever the serial input, sin, is held in a logic
'0' state for longer than the sum of start time +
data bits + parity + stop bits.
If in infrared mode (SIR_MODE == Enabled), it is
set whenever the serial input, sir_in, is
continuously pulsed to logic '0' for longer than the
sum of start time + data bits + parity + stop bits. A
break condition on serial input causes one and
only one character, consisting of all zeros, to be
received by the UART.
In the FIFO mode, the character associated with
the break condition is carried through the FIFO
and is revealed when the character is at the top of
the FIFO.
Reading the LSR clears the BI bit. In the non-FIFO
mode, the BI indication occurs immediately and
persists until the LSR is read.

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3 R UART_FE Framing Error bit. 0x0
This is used to indicate the occurrence of a
framing error in the receiver. A framing error
occurs when the receiver does not detect a valid
STOP bit in the received data.
In the FIFO mode, since the framing error is
associated with a character received, it is revealed
when the character with the framing error is at the
top of the FIFO.
When a framing error occurs, the UART tries to
resynchronize. It does this by assuming that the
error was due to the start bit of the next character
and then continues receiving the other bit i.e. data,
and/or parity and stop. It should be noted that the
Framing Error (FE) bit (LSR[3]) is set if a break
interrupt has occurred, as indicated by Break
Interrupt (BI) bit (LSR[4]).
0 = no framing error
1 = framing error
Reading the LSR clears the FE bit.
2 R UART_PE Parity Error bit. 0x0
This is used to indicate the occurrence of a parity
error in the receiver if the Parity Enable (PEN) bit
(LCR[3]) is set.
In the FIFO mode, since the parity error is
when the character with the parity error arrives at
the top of the FIFO.
It should be noted that the Parity Error (PE) bit
(LSR[2]) is set if a break interrupt has occurred, as
indicated by Break Interrupt (BI) bit (LSR[4]).
0 = no parity error
1 = parity error
Reading the LSR clears the PE bit.
1 R UART_OE Overrun error bit. 0x0
This is used to indicate the occurrence of an
overrun error.
This occurs if a new data character was received
before the previous data was read.
In the non-FIFO mode, the OE bit is set when a
new character arrives in the receiver before the
previous character was read from the RBR. When
this happens, the data in the RBR is overwritten.
In the FIFO mode, an overrun error occurs when
the FIFO is full and a new character arrives at the
receiver. The data in the FIFO is retained and the
data in the receive shift register is lost.
0 = no overrun error
1 = overrun error
Reading the LSR clears the OE bit.

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0 R UART_DR Data Ready bit. 0x0
This is used to indicate that the receiver contains
at least one character in the RBR or the receiver
FIFO.
0 = no data ready
1 = data ready
This bit is cleared when the RBR is read in non-
FIFO mode, or when the receiver FIFO is empty,
in FIFO mode.
Table 355: UART_MSR_REG (0x50001018)

15:5 - - 0x0
4 R UART_CTS Clear to Send. 0x1
This is used to indicate the current state of the
modem control line cts_n. This bit is the
complement of cts_n. When the Clear to Send
input (cts_n) is asserted it is an indication that the
modem or data set is ready to exchange data with
the UART Ctrl.
0 = cts_n input is de-asserted (logic 1)
1 = cts_n input is asserted (logic 0)
In Loopback Mode (MCR[4] = 1), CTS is the same
as MCR[1] (RTS).
3:1 - - 0x0
0 - - 0x0
Table 356: UART_SCR_REG (0x5000101C)

15:8 - - 0x0
7:0 R/W UART_SCRATCH_ This register is for programmers to use as a 0x0
PAD temporary storage space. It has no defined
purpose in the UART Ctrl.
Table 357: UART_SRBR_STHR0_REG (0x50001030)

15:8 - - 0x0

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7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a 0x0
shadow register for the RBR and has been
allocated sixteen 32-bit locations so as to
accommodate burst accesses from the master.
the serial input port (sin) in UART mode or the
serial infrared input (sir_in) in infrared mode. The
data in this register is valid only if the Data Ready
(DR) bit in the Line status Register (LSR) is set. If
overrun error will also occur. Shadow Transmit
Holding Register 0: This is a shadow register for
the THR and has been allocated sixteen 32-bit
locations so as to accommodate burst accesses
from the master. This register contains data to be
transmitted on the serial output port (sout) in
UART mode or the serial infrared output
(sir_out_n) in infrared mode. Data should only be
written to the THR when the THR Empty (THRE)
bit (LSR[5]) is set. If FIFO's are disabled (FCR[0]
set to zero) and THRE is set, writing a single
character to the THR clears the THRE. Any
additional writes to the THR before the THRE is
set again causes the THR data to be overwritten.
If FIFO's are enabled (FCR[0] set to one) and
THRE is set, x number of characters of data may
be written to the THR before the FIFO is full. The
number x (default=16) is determined by the value
of FIFO Depth that you set during configuration.
Any attempt to write data when the FIFO is full

15:8 - - 0x0

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15:8 - - 0x0

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Table 360: UART_SRBR_STHR3_REG (0x5000103C)

15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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Table 373: UART_FAR_REG (0x50001070)

0 R UART_FAR Description: Writes will have no effect when 0x0
FIFO_ACCESS == No, always readable. This
register is use to enable a FIFO access mode for
testing, so that the receive FIFO can be written by
the master and the transmit FIFO can be read by
the master when FIFO's are implemented and
enabled. When FIFO's are not implemented or not
enabled it allows the RBR to be written by the
master and the THR to be read by the master. 0 =
FIFO access mode disabled 1 = FIFO access
mode enabled Note, that when the FIFO access
mode is enabled/disabled, the control portion of
the receive FIFO and transmit FIFO is reset and
the FIFO's are treated as empty.

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Table 374: UART_USR_REG (0x5000107C)

15:5 - - 0x0
4 R UART_RFF Receive FIFO Full. 0x0
This is used to indicate that the receive FIFO is
completely full.
0 = Receive FIFO not full
1 = Receive FIFO Full
This bit is cleared when the RX FIFO is no longer
full.
3 R UART_RFNE Receive FIFO Not Empty. 0x0
This is used to indicate that the receive FIFO
contains one or more entries.
0 = Receive FIFO is empty
1 = Receive FIFO is not empty
This bit is cleared when the RX FIFO is empty.
2 R UART_TFE Transmit FIFO Empty. 0x1
This is used to indicate that the transmit FIFO is
completely empty.
0 = Transmit FIFO is not empty
1 = Transmit FIFO is empty
This bit is cleared when the TX FIFO is no longer
empty.
1 R UART_TFNF Transmit FIFO Not Full. 0x1
This is used to indicate that the transmit FIFO in
not full.
0 = Transmit FIFO is full
1 = Transmit FIFO is not full
This bit is cleared when the TX FIFO is full.
0 R UART_BUSY UART Busy. This indicates that a serial transfer is 0x0
in progress, when cleared indicates that the
DW_apb_uart is idle or inactive. 0 - DW_apb_uart
is idle or inactive 1 - DW_apb_uart is busy
(actively transferring data) Note that it is possible
for the UART Busy bit to be cleared even though a
new character may have been sent from another
device. That is, if the DW_apb_uart has no data in
the THR and RBR and there is no transmission in
progress and a start bit of a new character has
just reached the DW_apb_uart. This is due to the
fact that a valid start is not seen until the middle of
the bit period and this duration is dependent on
the baud divisor that has been programmed. If a
second system clock has been implemented
(CLOCK_MODE == Enabled) the assertion of this
bit will also be delayed by several cycles of the
slower clock.

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Table 375: UART_TFL_REG (0x50001080)

4:0 R UART_TRANSMIT_ Transmit FIFO Level. 0x0
FIFO_LEVEL This is indicates the number of data entries in the
transmit FIFO.
Table 376: UART_RFL_REG (0x50001084)

4:0 R UART_RECEIVE_FI Receive FIFO Level. 0x0
FO_LEVEL This is indicates the number of data entries in the
receive FIFO.
Table 377: UART_SRR_REG (0x50001088)

15:3 - - 0x0
2 W UART_XFR XMIT FIFO Reset. 0x0
This is a shadow register for the XMIT FIFO Reset
bit (FCR[2]). This can be used to remove the
burden on software having to store previously
written FCR values (which are pretty static) just to
reset the transmit FIFO. This resets the control
portion of the transmit FIFO and treats the FIFO
as empty. Note that this bit is 'self-clearing'. It is
not necessary to clear this bit.
1 W UART_RFR RCVR FIFO Reset. 0x0
This is a shadow register for the RCVR FIFO
Reset bit (FCR[1]). This can be used to remove
the burden on software having to store previously
reset the receive FIFO This resets the control
portion of the receive FIFO and treats the FIFO as
empty.
Note that this bit is 'self-clearing'. It is not
necessary to clear this bit.
0 W UART_UR UART Reset. This asynchronously resets the 0x0
UART Ctrl and synchronously removes the reset
assertion. For a two clock implementation both
pclk and sclk domains are reset.
Table 378: UART_SRTS_REG (0x5000108C)

15:1 - - 0x0

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0 R/W UART_SHADOW_R Shadow Request to Send. 0x0
EQUEST_TO_SEN This is a shadow register for the RTS bit (MCR[1]),
D this can be used to remove the burden of having
to
performing a read-modify-write on the MCR. This
is used to directly control the Request to Send
(rts_n) output. The Request To Send (rts_n)
output is used to inform the modem or data set
that the UART Ctrl is ready to exchange data.
When Auto RTS Flow Control is not enabled
(MCR[5] = 0), the rts_n signal is set low by
programming MCR[1] (RTS) to a high.
In Auto Flow Control, AFCE_MODE == Enabled
and active (MCR[5] = 1) and FIFOs enable
(FCR[0] = 1), the rts_n output is controlled in the
same way, but is also gated with the receiver
FIFO threshold trigger (rts_n is inactive high when
above the threshold).
Note that in Loopback mode (MCR[4] = 1), the
rts_n output is held inactive-high while the value of
this location is internally looped back to an input.
Table 379: UART_SBCR_REG (0x50001090)

15:1 - - 0x0
0 R/W UART_SHADOW_B Shadow Break Control Bit. 0x0
REAK_CONTROL This is a shadow register for the Break bit
(LCR[6]), this can be used to remove the burden
of having to performing a read modify write on the
LCR. This is used to cause a break condition to be
transmitted to the receiving device.
If set to one the serial output is forced to the
spacing (logic 0) state. When not in Loopback
Mode, as determined by MCR[4], the sout line is
forced low until the Break bit is cleared.
If SIR_MODE active (MCR[6] = 1) the sir_out_n
line is continuously pulsed. When in Loopback
Mode, the break condition is internally looped
back to the receiver.
Table 380: UART_SDMAM_REG (0x50001094)

15:1 - - 0x0

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0 R/W UART_SHADOW_D Shadow DMA Mode. 0x0
MA_MODE This is a shadow register for the DMA mode bit
(FCR[3]). This can be used to remove the burden
of having to store the previously written value to
the FCR in memory and having to mask this value
so that only the DMA Mode bit gets updated. This
determines the DMA signalling mode used for the
dma_tx_req_n and dma_rx_req_n output signals.
0 = mode 0
1 = mode 1
Table 381: UART_SFE_REG (0x50001098)

15:1 - - 0x0
0 R/W UART_SHADOW_F Shadow FIFO Enable. 0x0
IFO_ENABLE This is a shadow register for the FIFO enable bit
so that only the FIFO enable bit gets updated.This
enables/disables the transmit (XMIT) and receive
(RCVR) FIFOs. If this bit is set to zero (disabled)
after being enabled then both the XMIT and RCVR
controller portion of FIFOs are reset.
Table 382: UART_SRT_REG (0x5000109C)

15:2 - - 0x0
1:0 R/W UART_SHADOW_R Shadow RCVR Trigger. 0x0
CVR_TRIGGER This is a shadow register for the RCVR trigger bits
(FCR[7:6]). This can be used to remove the
burden of having to store the previously written
value to the FCR in memory and having to mask
this value so that only the RCVR trigger bit gets
updated.
This is used to select the trigger level in the
receiver FIFO at which the Received Data
Available Interrupt is generated. It also determines
when the dma_rx_req_n signal is asserted when
DMA Mode (FCR[3]) = 1. The following trigger
levels are supported:
00 = 1 character in the FIFO
01 = I ¼ full
10 = I ½ full
11 = FIFO 2 less than full

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Table 383: UART_STET_REG (0x500010A0)

15:2 - - 0x0
1:0 R/W UART_SHADOW_T Shadow TX Empty Trigger. 0x0
X_EMPTY_TRIGGE This is a shadow register for the TX empty trigger
R bits (FCR[5:4]). This can be used to remove the
this value so that only the TX empty trigger bit
gets updated.
This is used to select the empty threshold level at
which the THRE Interrupts are generated when
the mode is active. The following trigger levels are
supported:
00 = FIFO empty
01 = 2 characters in the FIFO
10 = I ¼ full
11 = I ½ full
Table 384: UART_HTX_REG (0x500010A4)

15:1 - - 0x0
0 R/W UART_HALT_TX This register is use to halt transmissions for 0x0
testing, so that the transmit FIFO can be filled by
the master when FIFOs are implemented and
enabled.
0 = Halt TX disabled
1 = Halt TX enabled
Note, if FIFOs are implemented and not enabled,
the setting of the halt TX register has no effect on
operation.
Table 385: UART_DMASA_REG (0x500010A8)

0 W DMASA This register is use to perform DMA software 0x0
acknowledge if a transfer needs to be terminated
due to an error condition. For example, if the DMA
disables the channel, then the DW_apb_uart
should clear its request. This will cause the TX
request, TX single, RX request and RX single
signals to de-assert. Note that this bit is 'self-
clearing' and it is not necessary to clear this bit.

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Table 386: UART_DLF_REG (0x500010C0)

3:0 R/W UART_DLF The fractional value is added to integer value set 0x0
by DLH, DLL. Fractional value is equal
UART_DLF/16
Table 387: UART_UCV_REG (0x500010F8)

15:0 R UCV Component Version 0x352A
Table 388: UART_UCV_HIGH_REG (0x500010FA)

15:0 R UCV Component Version 0x3331
Table 389: UART_CTR_REG (0x500010FC)

15:0 R CTR Component Type Register 0x110
Table 390: UART_CTR_HIGH_REG (0x500010FE)

Table 391: UART2_RBR_THR_DLL_REG (0x50001100)

15:8 - - 0x0

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7:0 R/W RBR_THR_DLL Receive Buffer Register: (RBR). 0x0
the serial input port (sin) in UART mode. The data
in this register is valid only if the Data Ready (DR)
bit in the Line status Register (LSR) is set. If
overrun error will also occur.
Transmit Holding Register: (THR)
This register contains data to be transmitted on
the serial output port (sout) in UART mode. Data
should only be written to the THR when the THR
Empty (THRE) bit (LSR[5]) is set. If FIFO's are
disabled (FCR[0] set to zero) and THRE is set,
writing a single character to the THR clears the
THRE. Any additional writes to the THR before the
THRE is set again causes the THR data to be
overwritten. If FIFO's are enabled (FCR[0] set to
one) and THRE is set, 16 number of characters of
data may be written to the THR before the FIFO is
full. Any attempt to write data when the FIFO is full
Divisor Latch (Low): (DLL)
This register makes up the lower 8-bits of a 16-bit,
read/write, Divisor Latch register that contains the
baud rate divisor for the UART. This register may
only be accessed when the DLAB bit (LCR[7]) is
set. The output baud rate is equal to the serial
clock (sclk) frequency divided by sixteen times the
value of the baud rate divisor, as follows:
baud rate = (serial clock freq) / (16 * divisor)
Note that with the Divisor Latch Registers (DLL
and DLH) set to zero, the baud clock is disabled
and no serial communications will occur. Also,
once the Divisor Latch is set, at least 8 clock
cycles of the slowest UART clock should be
allowed to pass before transmitting or receiving
data.
For the Divisor Latch (High) bits, see register
UART_IER_DLH_REG.
Table 392: UART2_IER_DLH_REG (0x50001104)

15:8 - - 0x0

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7 R/W PTIME_dlh7 Interrupt Enable Register: PTIME, 0x0
Programmable THRE Interrupt Mode Enable. This
is used to enable/disable the generation of THRE
Interrupt. 0 = disabled 1 = enabled.
6:4 R/W dlh6_4 Divisor Latch (High): DLH6 to DLH4, Bits 6 to 4 0x0
of the upper part of a 16-bit, read/write, Divisor
Latch register that contains the baud rate divisor
for the UART. This register may be accessed only
when the DLAB bit (LCR[7]) is set, otherwise, this
field is reserved. See register
3 R/W EDSSI_dlh3 Interrupt Enable Register: EDSSI, Enable 0x0
Modem Status Interrupt. This is used to
enable/disable the generation of Modem Status
Interrupt. This is the fourth highest priority
2 R/W ELSI_dhl2 Interrupt Enable Register: ELSI, Enable 0x0
Receiver Line Status Interrupt. This is used to
enable/disable the generation of Receiver Line
Status Interrupt. This is the highest priority
1 R/W ETBEI_dlh1 Interrupt Enable Register: ETBEI, Enable 0x0
Transmit Holding Register Empty Interrupt. This is
used to enable/disable the generation of
Transmitter Holding Register Empty Interrupt. This
is the third highest priority interrupt. 0 = disabled 1
= enabled

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0 R/W ERBFI_dlh0 Interrupt Enable Register: ERBFI, Enable 0x0
Received Data Available Interrupt. This is used to
enable/disable the generation of Received Data
Available Interrupt and the Character Timeout
Interrupt (if in FIFO mode and FIFO's enabled).
These are the second highest priority interrupts. 0
= disabled 1 = enabled
Table 393: UART2_IIR_FCR_REG (0x50001108)

7:6 R/W UART_FIFOSE_RT On read 0x0
FIFO's Enabled (or FIFOSE): This is used to
indicate whether the FIFO's are enabled or
disabled. 00 = disabled. 11 = enabled.
On write
RCVR Trigger (or RT):. This is used to select the
trigger level in the receiver FIFO at which the
Received Data Available Interrupt will be
generated. In auto flow control mode it is used to
determine when the rts_n signal will be de-
asserted. It also determines when the
dma_rx_req_n signal will be asserted when in
certain modes of operation. The following trigger
levels are supported: 00 = 1 character in the FIFO
01 = FIFO 1/4 full 10 = FIFO 1/2 full 11 = FIFO 2
less than full
5:4 R0/W UART_TET On read 0x0
reserved
On Write
TX Empty Trigger (or TET): This is used to select
the empty threshold level at which the THRE
Interrupts will be generated when the mode is
active. It also determines when the dma_tx_req_n
signal will be asserted when in certain modes of
operation. The following trigger levels are
supported: 00 = FIFO empty 01 = 2 characters in
the FIFO 10 = FIFO 1/4 full 11 = FIFO 1/2 full

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3 R/W UART_IID3_DMAM On Read (Bit3) 0x0
following types:
0010 = THR empty.
0111 = busy detect.
On Write
DMA Mode (or DMAM): This determines the DMA
signalling mode used for the dma_tx_req_n and
dma_rx_req_n output signals. 0 = mode 0 1 =
mode 1
2 R/W UART_IID2_XFIFO On Read (Bit2) 0x0
R Interrupt ID (or IID): This indicates the highest
following types:
0010 = THR empty.
0111 = busy detect.
On Write
XMIT FIFO Reset (or XFIFOR): This resets the
control portion of the transmit FIFO and treats the
1 R/W UART_IID1_RFIFO On Read (Bit1) 0x0
E Interrupt ID (or IID): This indicates the highest
following types:
0010 = THR empty.
0111 = busy detect.
On Write
RCVR FIFO Reset (or RFIFOR): This resets the
control portion of the receive FIFO and treats the

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0 R/W UART_IID0_FIFOE On Read (Bit0) 0x1
following types:
0010 = THR empty.
0111 = busy detect.
On Write
FIFO Enable (or FIFOE): This enables/disables
the transmit (XMIT) and receive (RCVR) FIFO's.
Whenever the value of this bit is changed both the
XMIT and RCVR controller portion of FIFO's will
be reset
Table 394: UART2_LCR_REG (0x5000110C)

15:8 - - 0x0
7 R/W UART_DLAB Divisor Latch Access Bit.Writeable only when 0x0
UART is not busy (USR[0] is zero).
This bit is used to enable reading and writing of
the Divisor Latch register (DLL and DLH) to set
the baud rate of the UART.
This bit must be cleared after initial baud rate
setup in order to access other registers.
6 R/W UART_BC Break Control Bit. 0x0
This is used to cause a break condition to be
transmitted to the receiving device. If set to one
the serial output is forced to the spacing (logic 0)
state. When not in Loopback Mode, as determined
by MCR[4], the sout line is forced low until the
Break bit is cleared. If active (MCR[6] set to one)
the sir_out_n line is continuously pulsed. When in
Loopback Mode, the break condition is internally
looped back to the receiver and the sir_out_n line
is forced low.
5 - - 0x0
4 R/W UART_EPS Even Parity Select. Writeable only when UART is 0x0
This is used to select between even and odd
parity, when parity is enabled (PEN set to one). If
set to one, an even number of logic 1s is
transmitted or checked. If set to zero, an odd
number of logic 1s is transmitted or checked.

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3 R/W UART_PEN Parity Enable. Writeable only when UART is not 0x0
busy (USR[0] is zero)
This bit is used to enable and disable parity
generation and detection in transmitted and
received serial character respectively.
0 = parity disabled
1 = parity enabled
2 R/W UART_STOP Number of stop bits. Writeable only when UART is 0x0
This is used to select the number of stop bits per
receives. If set to zero, one stop bit is transmitted
in the serial data.
If set to one and the data bits are set to 5
(LCR[1:0] set to zero) one and a half stop bits is
transmitted. Otherwise, two stop bits are
transmitted. Note that regardless of the number of
stop bits selected, the receiver checks only the
first stop bit.
0 = 1 stop bit
1 = 1.5 stop bits when DLS (LCR[1:0]) is zero,
else 2 stop bit
1:0 R/W UART_DLS Data Length Select.Writeable only when UART is 0x0
This is used to select the number of data bits per
receives. The number of bit that may be selected
areas follows:
00 = 5 bits
01 = 6 bits
10 = 7 bits
11 = 8 bits
Table 395: UART2_MCR_REG (0x50001110)

15:5 - - 0x0

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4 R/W UART_LB LoopBack Bit. 0x0
This is used to put the UART into a diagnostic
mode for test purposes.
If operating in UART mode (SIR_MODE not
active, MCR[6] set to zero), data on the sout line is
held high, while serial data output is looped back
to the sin line, internally. In this mode all the
interrupts are fully functional. Also, in loopback
mode, the modem control inputs (dsr_n, cts_n,
ri_n, dcd_n) are disconnected and the modem
control outputs (dtr_n, rts_n, out1_n, out2_n) are
looped back to the inputs, internally.
If operating in infrared mode (SIR_MODE active,
MCR[6] set to one), data on the sir_out_n line is
held low, while serial data output is inverted and
looped back to the sir_in line.
3:0 - - 0x0
Table 396: UART2_LSR_REG (0x50001114)

15:8 - - 0x0
7 R UART_RFE Receiver FIFO Error bit. 0x0
This bit is only relevant when FIFOs are enabled
(FCR[0] set to one). This is used to indicate if
there is at least one parity error, framing error, or
break indication in the FIFO.
0 = no error in RX FIFO
1 = error in RX FIFO
This bit is cleared when the LSR is read and the
character with the error is at the top of the receiver
FIFO and there are no subsequent errors in the
FIFO.
6 R UART_TEMT Transmitter Empty bit. 0x1
If FIFOs enabled (FCR[0] set to one), this bit is set
whenever the Transmitter Shift Register and the
FIFO are both empty. If FIFOs are disabled, this
bit is set whenever the Transmitter Holding
Register(THR) and the Transmitter Shift Register
are both empty.

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5 R UART_THRE Transmit Holding Register Empty bit. 0x1
If THRE mode is disabled (IER[7] set to zero) and
regardless of FIFO's being implemented/enabled
or not, this bit indicates that the THR or TX FIFO
is empty.
This bit is set whenever data is transferred from
the THR or TX FIFO to the transmitter shift
register and no new data has been written to the
THR or TX FIFO. This also causes a THRE
Interrupt to occur, if the THRE Interrupt is enabled.
If both modes are active (IER[7] set to one and
FCR[0] set to one respectively), the functionality is
switched to indicate the transmitter FIFO is full,
and no longer controls THRE interrupts, which are
then controlled by the FCR[5:4] threshold setting.
4 R UART_BI Break Interrupt bit. 0x0
This is used to indicate the detection of a break
sequence on the serial input data.
If in UART mode (SIR_MODE == Disabled), it is
set whenever the serial input, sin, is held in a logic
'0' state for longer than the sum of start time +
data bits + parity + stop bits.
If in infrared mode (SIR_MODE == Enabled), it is
set whenever the serial input, sir_in, is
continuously pulsed to logic '0' for longer than the
sum of start time + data bits + parity + stop bits. A
break condition on serial input causes one and
only one character, consisting of all zeros, to be
received by the UART.
In the FIFO mode, the character associated with
the break condition is carried through the FIFO
and is revealed when the character is at the top of
the FIFO.
Reading the LSR clears the BI bit. In the non-FIFO
mode, the BI indication occurs immediately and
persists until the LSR is read.
3 R UART_FE Framing Error bit. 0x0
This is used to indicate the occurrence of a
framing error in the receiver. A framing error
occurs when the receiver does not detect a valid
STOP bit in the received data.
In the FIFO mode, since the framing error is
when the character with the framing error is at the
top of the FIFO.
When a framing error occurs, the UART tries to
resynchronize. It does this by assuming that the
error was due to the start bit of the next character
and then continues receiving the other bit i.e. data,
and/or parity and stop. It should be noted that the
Framing Error (FE) bit (LSR[3]) is set if a break
interrupt has occurred, as indicated by Break
Interrupt (BI) bit (LSR[4]).
0 = no framing error
1 = framing error
Reading the LSR clears the FE bit.

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2 R UART_PE Parity Error bit. 0x0
This is used to indicate the occurrence of a parity
error in the receiver if the Parity Enable (PEN) bit
(LCR[3]) is set.
In the FIFO mode, since the parity error is
when the character with the parity error arrives at
the top of the FIFO.
It should be noted that the Parity Error (PE) bit
(LSR[2]) is set if a break interrupt has occurred, as
indicated by Break Interrupt (BI) bit (LSR[4]).
0 = no parity error
1 = parity error
Reading the LSR clears the PE bit.
1 R UART_OE Overrun error bit. 0x0
This is used to indicate the occurrence of an
overrun error.
This occurs if a new data character was received
before the previous data was read.
In the non-FIFO mode, the OE bit is set when a
new character arrives in the receiver before the
previous character was read from the RBR. When
this happens, the data in the RBR is overwritten.
In the FIFO mode, an overrun error occurs when
the FIFO is full and a new character arrives at the
receiver. The data in the FIFO is retained and the
data in the receive shift register is lost.
0 = no overrun error
1 = overrun error
Reading the LSR clears the OE bit.
0 R UART_DR Data Ready bit. 0x0
This is used to indicate that the receiver contains
at least one character in the RBR or the receiver
FIFO.
0 = no data ready
1 = data ready
This bit is cleared when the RBR is read in non-
FIFO mode, or when the receiver FIFO is empty,
in FIFO mode.
Table 397: UART2_SCR_REG (0x5000111C)

15:8 - - 0x0
7:0 R/W UART_SCRATCH_ This register is for programmers to use as a 0x0
PAD temporary storage space. It has no defined
purpose in the UART Ctrl.

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Table 398: UART2_SRBR_STHR0_REG (0x50001130)

15:8 - - 0x0

15:8 - - 0x0

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15:8 - - 0x0

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Table 401: UART2_SRBR_STHR3_REG (0x5000113C)

15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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15:8 - - 0x0

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Table 414: UART2_FAR_REG (0x50001170)

0 R UART_FAR Description: Writes will have no effect when 0x0
FIFO_ACCESS == No, always readable. This
register is use to enable a FIFO access mode for
testing, so that the receive FIFO can be written by
the master and the transmit FIFO can be read by
the master when FIFO's are implemented and
enabled. When FIFO's are not implemented or not
enabled it allows the RBR to be written by the
master and the THR to be read by the master. 0 =
FIFO access mode disabled 1 = FIFO access
mode enabled Note, that when the FIFO access
mode is enabled/disabled, the control portion of
the receive FIFO and transmit FIFO is reset and
the FIFO's are treated as empty.

DA14531
Table 415: UART2_USR_REG (0x5000117C)

15:5 - - 0x0
4 R UART_RFF Receive FIFO Full. 0x0
This is used to indicate that the receive FIFO is
completely full.
0 = Receive FIFO not full
1 = Receive FIFO Full
This bit is cleared when the RX FIFO is no longer
full.
3 R UART_RFNE Receive FIFO Not Empty. 0x0
This is used to indicate that the receive FIFO
contains one or more entries.
0 = Receive FIFO is empty
1 = Receive FIFO is not empty
This bit is cleared when the RX FIFO is empty.
2 R UART_TFE Transmit FIFO Empty. 0x1
This is used to indicate that the transmit FIFO is
completely empty.
0 = Transmit FIFO is not empty
1 = Transmit FIFO is empty
This bit is cleared when the TX FIFO is no longer
empty.
1 R UART_TFNF Transmit FIFO Not Full. 0x1
This is used to indicate that the transmit FIFO in
not full.
0 = Transmit FIFO is full
1 = Transmit FIFO is not full
This bit is cleared when the TX FIFO is full.
0 R UART_BUSY UART Busy. This indicates that a serial transfer is 0x0
in progress, when cleared indicates that the
DW_apb_uart is idle or inactive. 0 - DW_apb_uart
is idle or inactive 1 - DW_apb_uart is busy
(actively transferring data) Note that it is possible
for the UART Busy bit to be cleared even though a
new character may have been sent from another
device. That is, if the DW_apb_uart has no data in
the THR and RBR and there is no transmission in
progress and a start bit of a new character has
just reached the DW_apb_uart. This is due to the
fact that a valid start is not seen until the middle of
the bit period and this duration is dependent on
the baud divisor that has been programmed. If a
second system clock has been implemented
(CLOCK_MODE == Enabled) the assertion of this
bit will also be delayed by several cycles of the
slower clock.

DA14531
Table 416: UART2_TFL_REG (0x50001180)

4:0 R UART_TRANSMIT_ Transmit FIFO Level. 0x0
FIFO_LEVEL This is indicates the number of data entries in the
transmit FIFO.
Table 417: UART2_RFL_REG (0x50001184)

4:0 R UART_RECEIVE_FI Receive FIFO Level. 0x0
FO_LEVEL This is indicates the number of data entries in the
receive FIFO.
Table 418: UART2_SRR_REG (0x50001188)

15:3 - - 0x0
2 W UART_XFR XMIT FIFO Reset. 0x0
This is a shadow register for the XMIT FIFO Reset
bit (FCR[2]). This can be used to remove the
burden on software having to store previously
reset the transmit FIFO. This resets the control
portion of the transmit FIFO and treats the FIFO
as empty. Note that this bit is 'self-clearing'. It is
not necessary to clear this bit.
1 W UART_RFR RCVR FIFO Reset. 0x0
This is a shadow register for the RCVR FIFO
Reset bit (FCR[1]). This can be used to remove
the burden on software having to store previously
reset the receive FIFO This resets the control
portion of the receive FIFO and treats the FIFO as
empty.
Note that this bit is 'self-clearing'. It is not
necessary to clear this bit.
0 W UART_UR UART Reset. This asynchronously resets the 0x0
UART Ctrl and synchronously removes the reset
assertion. For a two clock implementation both
pclk and sclk domains are reset.
Table 419: UART2_SBCR_REG (0x50001190)

15:1 - - 0x0

DA14531

0 R/W UART_SHADOW_B Shadow Break Control Bit. 0x0
REAK_CONTROL This is a shadow register for the Break bit
(LCR[6]), this can be used to remove the burden
of having to performing a read modify write on the
LCR. This is used to cause a break condition to be
transmitted to the receiving device.
If set to one the serial output is forced to the
spacing (logic 0) state. When not in Loopback
Mode, as determined by MCR[4], the sout line is
forced low until the Break bit is cleared.
If SIR_MODE active (MCR[6] = 1) the sir_out_n
line is continuously pulsed. When in Loopback
Mode, the break condition is internally looped
back to the receiver.
Table 420: UART2_SDMAM_REG (0x50001194)

15:1 - - 0x0
0 R/W UART_SHADOW_D Shadow DMA Mode. 0x0
MA_MODE This is a shadow register for the DMA mode bit
so that only the DMA Mode bit gets updated. This
determines the DMA signalling mode used for the
dma_tx_req_n and dma_rx_req_n output signals.
0 = mode 0
1 = mode 1
Table 421: UART2_SFE_REG (0x50001198)

15:1 - - 0x0
0 R/W UART_SHADOW_F Shadow FIFO Enable. 0x0
IFO_ENABLE This is a shadow register for the FIFO enable bit
so that only the FIFO enable bit gets updated.This
enables/disables the transmit (XMIT) and receive
(RCVR) FIFOs. If this bit is set to zero (disabled)
after being enabled then both the XMIT and RCVR
controller portion of FIFOs are reset.

DA14531
Table 422: UART2_SRT_REG (0x5000119C)

15:2 - - 0x0
1:0 R/W UART_SHADOW_R Shadow RCVR Trigger. 0x0
CVR_TRIGGER This is a shadow register for the RCVR trigger bits
(FCR[7:6]). This can be used to remove the
this value so that only the RCVR trigger bit gets
updated.
This is used to select the trigger level in the
receiver FIFO at which the Received Data
Available Interrupt is generated. It also determines
when the dma_rx_req_n signal is asserted when
DMA Mode (FCR[3]) = 1. The following trigger
levels are supported:
00 = 1 character in the FIFO
01 = I ¼ full
10 = I ½ full
11 = FIFO 2 less than full
Table 423: UART2_STET_REG (0x500011A0)

15:2 - - 0x0
1:0 R/W UART_SHADOW_T Shadow TX Empty Trigger. 0x0
X_EMPTY_TRIGGE This is a shadow register for the TX empty trigger
R bits (FCR[5:4]). This can be used to remove the
this value so that only the TX empty trigger bit
gets updated.
This is used to select the empty threshold level at
which the THRE Interrupts are generated when
the mode is active. The following trigger levels are
supported:
00 = FIFO empty
01 = 2 characters in the FIFO
10 = I ¼ full
11 = I ½ full
Table 424: UART2_HTX_REG (0x500011A4)

15:1 - - 0x0

DA14531

0 R/W UART_HALT_TX This register is use to halt transmissions for 0x0
testing, so that the transmit FIFO can be filled by
the master when FIFOs are implemented and
enabled.
0 = Halt TX disabled
1 = Halt TX enabled
Note, if FIFOs are implemented and not enabled,
the setting of the halt TX register has no effect on
operation.
Table 425: UART2_DMASA_REG (0x500011A8)

0 W DMASA This register is use to perform DMA software 0x0
acknowledge if a transfer needs to be terminated
due to an error condition. For example, if the DMA
disables the channel, then the DW_apb_uart
should clear its request. This will cause the TX
request, TX single, RX request and RX single
signals to de-assert. Note that this bit is 'self-
clearing' and it is not necessary to clear this bit.
Table 426: UART2_DLF_REG (0x500011C0)

3:0 R/W UART_DLF The fractional value is added to integer value set 0x0
by DLH, DLL. Fractional value is equal
UART_DLF/16
Table 427: UART2_UCV_REG (0x500011F8)

15:0 R UCV Component Version 0x352A
Table 428: UART2_UCV_HIGH_REG (0x500011FA)

15:0 R UCV Component Version 0x3331
Table 429: UART2_CTR_REG (0x500011FC)


DA14531
Table 430: UART2_CTR_HIGH_REG (0x500011FE)


DA14531
31.19 Chip Version Registers
Table 431: Register map Version

0x50003200 CHIP_ID1_REG Chip identification register 1.
0x5000320C CHIP_ID4_REG Chip identification register 4.
Table 432: CHIP_ID1_REG (0x50003200)

7:0 R CHIP_ID1 First character of device type "2632" in ASCII. 0x32

7:0 R CHIP_ID2 Second character of device type "2632" in ASCII. 0x36

7:0 R CHIP_ID3 Third character of device type "2632" in ASCII. 0x33
Table 435: CHIP_ID4_REG (0x5000320C)

7:0 R CHIP_ID4 Fourth character of device type "2632" in ASCII. 0x32

DA14531
31.20 Wake-Up Registers
Table 436: Register map WKUP

0x50000100 WKUP_CTRL_REG Control register for the wakeup counter
0x50000102 WKUP_COMPARE_R Number of events before wakeup interrupt
EG
0x50000104 WKUP_IRQ_STATUS Reset wakeup interrupt
_REG
0x50000106 WKUP_COUNTER_R Actual number of events of the wakeup counter
EG
0x50000108 WKUP_SELECT_GPI Select which inputs from P0 port can trigger wkup counter
O_REG
0x5000010A WKUP2_SELECT_GPI Select which inputs from P1 port can trigger wkup counter
O_REG
0x5000010C WKUP_POL_GPIO_R Select the sensitivity polarity for each P0 input
EG
0x5000010E WKUP2_POL_GPIO_ Select the sensitivity polarity for each P1 input
REG
Table 437: WKUP_CTRL_REG (0x50000100)

8 R/W WKUP2_ENABLE_I 0 = no interrupt will be generated 0x0
RQ 1 = if the event counter2 reaches the value set by
WKUP_COMPARE_REG an IRQ will be
generated
7 R/W WKUP_ENABLE_IR 0 = no interrupt will be generated 0x0
Q 1 = if the event counter reaches the value set by
WKUP_COMPARE_REG an IRQ will be
generated
6 R/W WKUP_SFT_KEYHI 0 = no effect 0x0
T 1 = emulate key hit. The event counter and
counter2 will increment by 1 (after debouncing if
enabled). First make this bit 0 before any new key
hit can be sensed.
5:0 R/W WKUP_DEB_VALU Keyboard debounce time (N*1 ms with N = 1 to 0x0
E 63).
0x0: no debouncing
0x1 to 0x3F: 1 ms to 63 ms debounce time

DA14531
Table 438: WKUP_COMPARE_REG (0x50000102)

7:0 R/W WKUP_COMPARE Defines the number of events -1 that have to be 0x0
counted before the wakeup interrupt will be given.
value 0 means one event.
Table 439: WKUP_IRQ_STATUS_REG (0x50000104)

3 R0/W WKUP2_CNTR_RS writing 1 will reset the event2 counter 0x0
T
2 R0/W WKUP_CNTR_RST writing 1 will reset the event counter 0x0
1 R/W WKUP2_IRQ_STAT Gives 1 when there is a wkup2 pending IRQ. 0x0
US Writing 1 will reset the interrupt.
0 R/W WKUP_IRQ_STATU Gives 1 when there is a wkup pending IRQ. 0x0
S Writing 1 will reset the interrupt.
Table 440: WKUP_COUNTER_REG (0x50000106)

15:8 R EVENT2_VALUE This value represents the number of events that 0x0
have been counted so far. It will be reset by
writting to the WKUP_CNTR_RST bit field of the
WKUP_IRQ_STATUS_REG
7:0 R EVENT_VALUE This value represents the number of events that 0x0
have been counted so far. It will be reset by
writting to the WKUP_CNTR_RST bit field of the
WKUP_IRQ_STATUS_REG.
Table 441: WKUP_SELECT_GPIO_REG (0x50000108)

11:0 R/W WKUP_SELECT_G 0 = input P0x is not enabled for wakeup event 0x0
PIO counter
1 = input P0x is enabled for wakeup event counter
Table 442: WKUP2_SELECT_GPIO_REG (0x5000010A)

11:0 R/W WKUP2_SELECT_ 0 = input P0x is not enabled for wakeup event 0x0
GPIO counter
1 = input P0x is enabled for wakeup event counter

DA14531
Table 443: WKUP_POL_GPIO_REG (0x5000010C)

11:0 R/W WKUP_POL_GPIO 0 = the enabled input P0x increments the event 0x0
counter if that input goes high
1 = the enabled input P0x increments the event
counter if that input goes low
Table 444: WKUP2_POL_GPIO_REG (0x5000010E)

11:0 R/W WKUP2_POL_GPIO 0 = the enabled input P0x increments the event2 0x0
counter if that input goes high
1 = the enabled input P0x increments the event2
counter if that input goes low

DA14531
31.21 Watchdog Registers
Table 445: Register map WDOG

0x50003100 WATCHDOG_REG Watchdog timer register.
0x50003102 WATCHDOG_CTRL_ Watchdog control register.
REG
Table 446: WATCHDOG_REG (0x50003100)

15:9 R0/W WDOG_WEN 0000.000 = Write enable for Watchdog timer 0x0
else Write disable. This filter prevents
unintentional presetting the watchdog with a SW
run-away.
8 R/W WDOG_VAL_NEG 0 = Watchdog timer value is positive. 0x0
1 = Watchdog timer value is negative.
7:0 R/W WDOG_VAL Write: Watchdog timer reload value. Note that all 0xFF
bits 15-9 must be 0 to reload this register.
Read: Actual Watchdog timer value. Decremented
by 1 every 10.24 msec. Bit 8 indicates a negative
counter value. 2, 1, 0, 1FF16, 1FE16 etc. An NMI or
WDOG (SYS) reset is generated under the
following conditions:
If WATCHDOG_CTRL_REG[NMI_RST] = 0 then
If WDOG_VAL = 0 -> NMI (Non Maskable
Interrupt)
if WDOG_VAL = 1F016 -> WDOG reset ->
reload FF16
If WATCHDOG_CTRL_REG[NMI_RST] = 1 then
if WDOG_VAL <= 0 -> WDOG reset -> reload
FF16
Table 447: WATCHDOG_CTRL_REG (0x50003102)

15:2 - - 0x0
1 R/W - 0x0

DA14531

0 R/W NMI_RST 0 = Watchdog timer generates NMI at value 0, and 0x0
WDOG (SYS) reset at <=-16. Timer can be frozen
/resumed using
SET_FREEZE_REG[FRZ_WDOG]/
RESET_FREEZE_REG[FRZ_WDOG].
1 = Watchdog timer generates a WDOG (SYS)
reset at value 0 and can not be frozen by
Software.
Note that this bit can only be set to 1 by SW and
only be reset with a WDOG (SYS) reset or SW
reset.
The watchdog is always frozen when the Cortex-
M0 is halted in DEBUG State.

DA14531
32 Ordering Information
Table 448: Ordering Information (Samples)
Part Number Package Size (mm) Shipment Form Pack Quantity
DA14531-00000FX2 FCGQFN24 2.2 × 3.0 Reel 100/1000
DA14531-00000OG2 WLCSP17 1.6 4 × 2.032 Reel 100/1000
Table 449: Ordering Information (Production)

Part Number Package Size (mm) Shipment Form Pack Quantity
DA14531-00000FX2 FCGQFN24 2.2 × 3.0 Reel 4000
DA14531-00000OG2 WLCSP17 1.6 4 × 2.032 Reel 4000
Part Number Legend:

DA14531-RRXXXYYZ
RR: chip revision number
XXX: variant (000: No Flash)
YY: package code (FX: FCGQFN24, OG: WLCSP17)
Z: packing method (1: Tray, 2: Reel, A: Mini-Reel)

DA14531
33 Package Information
33.1 Moisture Sensitivity Level (MSL)

The MSL is an indicator for the maximum allowable time period (floor life time) in which a moisture
sensitive plastic device, once removed from the dry bag, can be exposed to an environment with a
maximum temperature of 30°C and a maximum relative humidity of 60% relative humidity (R .)
before the solder reflow process.
WLCSP packages are qualified for MSL 1.
FCGQFN packages are qualified for MSL 1.
Table 450: MSL Classification

MSL Level Floor Lifetime Conditions
MSL 4 72 hours 30°C 60% R
MSL 3 168 hours 30°C 60% R
MSL 2A 4 weeks 30°C 60% R
MSL 2 1 year 30°C 60% R
MSL 1 Unlimited 30°C 85% R
33.2 WLCSP Handling

Manual handling of WLCSP packages should be reduced to the absolute minimum. In cases where it
is still necessary, a vacuum pick-up tool should be used. In extreme cases plastic tweezers could be
used, but metal tweezers are not acceptable, since contact may easily damage the silicon chip.
Removal will cause damage to the solder balls and therefore a removed sample cannot be reused.
The WLCSP package has been coated to reduce exposure to ambient light, however WLCSP
packages can remain sensitive to visible and infrared light. It is recommended to take precautions to
properly shield the chip in the final product.
33.3 Soldering Information

Refer to the JEDEC standard J-STD-020 for relevant soldering information. This document can be
downloaded from http://www.jedec.org.
33.4 Package Outlines

DA14531
Figure 85: WLCSP17 Package Outline Drawing


DA14531
Figure 86: FCGQFN24 Package Outline Drawing


DA14531
Revision History
Revision Date Description
3.1 09-Jul-2020 Datasheet status: Final. Product status: Production
Changelog:
● WLCSP17 and FCGQFN24 Package Outline Diagram updated
● VBAT_X, GPADC, Temperature Sensor and XTAL32K specification parameters updated
● SPI Chapter: Features updated
● Buck, Boost and Bypass PMU figures updated
3.0 12-Mar-2020 Datasheet status: Final.
Changelog:
● Various updates in figures and text
● Electrical characteristics updates
2.1 17-Oct-2019 Datasheet status: Preliminary.
Changelog:
● Product status update and Datasheet status update
● VDD_Clamp recommended setting across temperature added
2.0 13-Oct-2019 Datasheet status: Preliminary.
Changelog:
● Specifications
1.5 03-Jun-2019 Datasheet status: Target
Changelog:
● Ordering Information (Production): Pack Quantity
● Complies with BLE 5.1
Changelog:
● BooterROM Sequence
● PMU Programming
● Temperature Sensor: routine for TS reading
● PMU: Buck, Boost, By-pass block diagram updated: SWs added, LDO_LOW_RET renamed to LDO_LOW
● RCX programming
● CLC filter at RFIOp
1.3 25-Jan-2019 Datasheet status: Target
Changelog:
● Various Updates
1.2 02-Oct-2018 Datasheet status: Target
Changelog:
● FCGQFN24 Package Outline updated
1.1 30-Aug-2018 Datasheet status: Target

DA14531
Status Definitions
Revision Datasheet Status Product Status Definition
1.<n> Target Development This datasheet contains the design specifications for product development.
Specifications may be changed in any manner without notice.
2.<n> Preliminary Qualification This datasheet contains the specifications and preliminary characterization
data for products in pre-production. Specifications may be changed at any
time without notice in order to improve the design.
3.<n> Final Production This datasheet contains the final specifications for products in volume
production. The specifications may be changed at any time in order to
improve the design, manufacturing and supply. Major specification changes
are communicated via Customer Product Notifications. Datasheet changes
are communicated via www.dialog-semiconductor.com.
4.<n> Obsolete Archived This datasheet contains the specifications for discontinued products. The
information is provided for reference only.
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DA14531

Ultra Low Power Bluetooth 5.1 SoC Final

Datasheet Revision 3.1 09-Jul-2020

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Figure 1: System Diagram

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4.3.1 Power-up/Wake-up in Buck Configuration........................................................... 56

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11.2.1 OTP Accessing Considerations ........................................................................... 89

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16 Quadrature Decoder .................................................................................................................. 116

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24.2.1 Keyboard Scanner ............................................................................................. 138

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29 BLE Core .................................................................................................................................... 158

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33.4 Package Outlines .............................................................................................................. 370

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Figure 53: Moving Backwards on Axis X ........................................................................................... 117

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Table 20: POR VBAT_LOW - DC Characteristics ............................................................................... 39

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Table 78: BLE_DEEPSLSTAT_REG (0x40000038) ......................................................................... 177

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Table 136: XTAL32M_START_REG (0x50000030) ......................................................................... 202

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Table 194: GP_ADC_SEL_REG (0x50001506) ................................................................................ 227

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Table 252: I2C_DMA_RDLR_REG (0x50001390) ............................................................................ 257

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Table 310: SPI_CONFIG_REG (0x50001204).................................................................................. 284

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Table 368: UART_SRBR_STHR11_REG (0x5000105C) ................................................................. 320

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Table 426: UART2_DLF_REG (0x500011C0) .................................................................................. 361

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Arm Cortex-M0+ DCDC RC

Figure 2: DA14531 Block Diagram

CFR0011-120-00 19 of 374 © 2020 Dialog Semiconductor

2 Packages and Pinout

2.1 WLCSP17 DA14531

C GNDRF2 GNDRF1 P0_2

E XTAL32Mm VSS P0_1

Switching signal, Static signal, Analog signal Quiet ground