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OpenRISC Basics

The OpenRISC project aims to create a free and open RISC processor for embedded systems. This includes an open instruction set architecture with DSP features, open source processor implementations like OR1200 and mor1kx, and tools to develop software and systems. Hardware implementations provide processor cores, while system simulators like or1ksim and QEMU allow simulating complete OpenRISC systems at the instruction level. The project also develops system-on-chips and has ports of operating systems like Linux to run on OpenRISC processors.

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55 views

OpenRISC Basics

The OpenRISC project aims to create a free and open RISC processor for embedded systems. This includes an open instruction set architecture with DSP features, open source processor implementations like OR1200 and mor1kx, and tools to develop software and systems. Hardware implementations provide processor cores, while system simulators like or1ksim and QEMU allow simulating complete OpenRISC systems at the instruction level. The project also develops system-on-chips and has ports of operating systems like Linux to run on OpenRISC processors.

Uploaded by

Rama Devi
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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OpenRISC 

Project Overview
Welcome to the project overview of the OpenRISC project. The major goal of the
project it to create a free and open processor for embedded systems. This
includes:
 a free and open RISC instruction set architecture with DSP features
 a set of free, open source implementations of the architecture
 a complete set of free, open source software development tools, libraries,
operating systems and applications
 a variety of system-on-chip and system simulators
The project is driven by a very active community and has a long history. This
unfortunately lead to scattered and partly outdated information. The goal of this
page is to provide an overview over active parts of the project and the current
development to ease the entry for newcomers or people seeking basic
information. The information is collected from the following sites where you can
find more information (which can be partly outdated):
 The OpenRISC pages at opencores.org
 The github projects

Quick start

The very quick start: jor1k


There is an interesting project in case you just want to try out the OpenRISC in
your browser: jor1k is an instruction set simulator written in javascript that boots
Linux inside your browser. You can play a game, watch some demos or surf the
internet using this emulator.
If that’s not enough, feel free to compile your own code and run it in the
simulator. There also is a demo where you can edit, compile and run inside the
browser, so that you don’t even need a cross-compiler toolchain!
Processor cores
There are two mainline processor core implementations:
 OR1200 is the original first implementation of the processor in Verilog. It
implements the basic features and is still widely used, although not actively
developed.
 mor1kx is a novel implementation which is more sophisticated and has
different variants with respect to the number of pipeline stages, tightly
coupled memory or the presence of a delay slot. It has also been recently
extended to support atomic operations and multicore features.
 marocchino an implementation with all of the advanced features of mor1kx
but uses an out-of-order pipeline implementing the Tomasulo algorithm and a
64-bit FPU.
System simulators
If you want to start with simulating the processor core to just try it out, you have
the following options:
 or1ksim is an instruction accurate simulator with a lot of features including
flexible configuration and gdb debugging.
 qemu has a patch to support the OpenRISC processor
System-on-Chip
While a processor core is still the heart of every system, the peripherals, memory
etc. are of course equally important. There are a number of system-on-chip
available that you can use to perform RTL simulations, SystemC simulations or
perform an FPGA synthesis of an OpenRISC-powered entire system:
 fusesoc is a new SoC generator that not only supports OpenRISC. It also
manages the available peripheral cores and allows you to easily configure
and generate your system-on-chip.
 minsoc is a minimal OpenRISC-based system-on-chip, that is easy to
configure and implement, but still uses the OR1200 processor
implementation.
 OpTiMSoC is a flexible multicore system-on-chip that is based on a network-
on-chip and connects a configurable number of OpenRISC (mor1kx)
processors to arbitrarily large platforms.
 MiSoC is an SoC generator using the Python based Migen which can use the
mor1kx processor. Both high performance and optimized for small FPGA
footprint, it supports a large number of development boards out the box.
 LiteX is an SoC generator like MiSoC also using Python base Migen. It can
be used to create mor1kx and marocchino SoC’s that boot Linux.
Operating Systems
If you want to run an operating system on your OpenRISC you have a few
options:
 Linux has been ported and is now upstream in the standard Linux
repositories (upstream is the term that denotes that you submitted your
changes to an open source project and they have been accepted and are
now part of this software)
 RTEMS has been ported during a Google Summer of Code project and is
also upstream.
Toolchains
A few toolchains are generally supported. A C library is an essential part of your
toolchain as it provides you the basic features. The following toolchains with
different C libraries are available:
 newlib is a small library mainly used for baremetal usage. We also maintain a
port of it for the baremetal toolchain or1k-elf-gcc
 musl is a C library with a strong emphasis on being light-weight and
correctness. The Linux toolchain is or1k-linux-musl-gcc.
 uClibc-ng a reboot of the uClibc project, is a similar small library and primarily
used for Linux applications. The Linux toolchain is or1k-linux-uclibc-gcc.
 glibc is a fully featured C Library for Linux. The Linux toolchain is or1k-linux-
gnu-gcc.

Applications
Cross compiling applications to your OpenRISC embedded target and packaging
them up into a root filesystem image could be tedious. There are a few options to
smooth the process:
 Buildroot has support for building applications using the uClibc-ng toolchain.
 OpenADK from the maintainers of uClibc-ng has support for building using
both uClibc-ng and musl toolchains.

Latest news
 19 Feb 2022 » OpenRISC support added to GLIBC 2.35
(Stafford Horne) We would like to announce that GLIBC 2.35 released in
February 2022 has support for OpenRISC. Read more about GLIBC
toolchain support support over on our software page. .. more
 28 May 2021 » Google Summer of Code 2021
(Stafford Horne) The Google Summer of Code is a yearly event which teams
open source projects with college students. Students learn about technology
and the open source community and projects benefit from new contributions.
As in previous years this year OpenRISC is participating as part of the FOSSi
foundation project. This year..... more
 04 Jun 2019 » Announcing Architecture Version 1.3
(Stafford Horne) It has been been a few years since the release of
OpenRISC version 1.2. But, it’s been a busy few years of getting GDB and
GCC ports upstream. Now with the GCC port upstream we are able to make
progress and this new architecture revision does just that bringing in..... more
 27 May 2019 » Google Summer of Code 2019
(Stafford Horne) The Google Summer of Code is a yearly event which teams
open source projects with college students. Students learn about technology
and the open source community and projects benefit from new contributions.
As in previous years this year OpenRISC is participating as part of the FOSSi
foundation project. We have..... more
 09 Nov 2018 » GCC Upstream for 9.0.0
(Stafford Horne) We are proud to announce that the OpenRISC port for gcc
has been committed to upstream. Mainline OpenRISC support will be
available in the upcoming 9.0.0 release of GCC. Note, this has been a clean
room rewrite of the OpenRISC gcc port. The old port can still be found
in..... more

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Hardware Implementations
The hardware implementations are full processor implementations written in
an Hardware Description Language. Such a description is either the input to a
hardware synthesis, such as for an ASIC or an FPGA, or for an RTL simulation.
Nevertheless, the processor cores are for themselves not running on their own,
but are complex IP blocks that at least need a clock and reset signal and some
memories connected to them. You can use one of the popular system-on-chip to
try out the processor cores.
OR1200
OR1200 is the original implementation of the OpenRISC 1000 architecture.
The source code can be found on github at openrisc/or1200.
mor1kx
The mor1kx is pretty much a drop in replacement for the original or1200
processor but it has its advantages.

 It follows, in our opinion, better coding standards compared to the or1200


 It is licensed under the CERN Open Hardware Licence Version 2 which is
suited for open hardware
 It’s implementation is highly reconfigurable allowing to be resized to meet
target size and performance requirements.
 It has docs that explain the overall design.

In 2014 the author, Julius Baxter, gave the following presentation about mor1kx
which goes into detail about the motivation for the processor rewrite and
architecture.
The source code can be found on github at openrisc/mor1kx
To build a system with mor1kx have a look at the some of the
hardware tutorials or have a look at some of the systems available in orpsoc-
cores which can be built with FuseSoC.
marocchino
The marocchino OpenRISC implementation also has the advanced features of
the mor1kx. The marocchino then expands on this with more advanced features:

 A 64-bit FPU implementing OpenRISC’s ORFPX64A32 extension.


 It implements an Out-of-order pipeline which helps to avoid pipeline stall’s
providing higher execution performance.

The source code can be found on github at openrisc/or1k_marocchino


Stafford Horne has written a few blog articles on how to use marocchino and it’s
design. Check them out:

 Marocchino in Action - how to boot up the marocchino processor.


 Marocchino Pipeline - an overview of the marocchino architecture.
 Marocchino a Tomasulo Implementation - a deep dive into the marocchino
Tomasulo algorithm implementation.

System Simulators
or1ksim
Or1ksim is a generic OpenRISC 1000 architecture simulator capable of
emulating OpenRISC based computer systems at the instruction level. It includes
models of a range of peripherals, allowing complete systems to be modeled.
Links

 openrisc/or1ksim - github repo

qemu
QEMU is a cpu emulator that supports many cpu targets. OpenRISC has been
supported since version 1.2.
Links

 qemu.org - QEMU home

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