k

I1
I • n,r, M•r~fd "' 1 hHrt·t urr hu• llf1 1tr1vAn4w (,I ttnu,.,,, tn.afru1'tlntU i t,
t·vrf<'I thrin Prtru•rfm1 tV11n Nt·1HnNttll) ttH hfln httt, "ftu• f.t beatHt" A rtm• h ..c,r. thir •m,,,urt
I of 1n~tr,1ttllon r,nu,Urlt~t,1 t'.flf1 1,,. Adil( ivt"1 tn th,. ff•rvMtl nrehtt,.rh1rt. du.- ftl stipnr ttA
mtrnory bnnki.
1,4. l Dtffer-ence b etw-een Von Neunt1nn 111d ff 1,-.ud At-c'tthutvre ,

,. Data bua and addrCB8 b ua nrr not eer,a, 111~. •

ilffli!l?INllll
D"ta boa nnd nd,tru, bu. ltt Mparat~.
So greater now of doto Is not poAKllJlc. so gC3Cf!r now of da:ta Lt poNtb&~#
• It fs called CtSC mlcroconlrollcr . (CJSC • fl ,. called RISC nuooeontroltcr. (RISC ~
Contplcx hHJtr1i1ct10n Set Computer) Reduced hut,uction kt Coffl.puteTi.
f
I • 11 has more num ber of tnatructlona. • It ha.a leu number or t ~ n a.
I •
• Otvtston and m ulUp'lexJng ls required t.o
use program and data .
• No d l vt&lon and rnulttpltxtng 11 requlttd
because oddreu b\11, Uld data bus are
f
I
separated.
01t1 but
I 0~
I
t CPU
Program: 0 111
l
b\ll

LW
P,og m.tm
mlm , mlm O~mlm

Add 11
-Control bu1
__ J L _J
Aoor11t &. control oin
f
Figure 1,8 Control Bu•
i ....._-:,,-----------------------L____ Figure 1·9 Add,••• aJ1d Conuol Bu•
--- ---
lA.2 A.dvantagea and Dh1adva.ntages of Vo n Neuman
and Harvard Arch ,tecture :
Advantagea of Von Neuman :
I I
 I
I l\ticropro«&Sor Based S3istems
f nstructlons In fewer 1·nstrucU01
• fhe Harvard architecture has an advantage of executing
Is because a much greater amou
!' _cycles than Princeton (Von Neumann) architecture. This
f of instruction parallelism can be achieved In
the Harvard architecture due to separa
j memory banks.
f
ard Architecture :
! 1.4-.1 Difference between Von Neumann and Harv

i
f Data bus and address bus are separate.
i
• Data bus and addr~ss bus are not separate. •
So greater flow of data is possible.
♦

;
tr So greater flow of data is not possible.
• It is called RISC microcontroller. (RISC ·
I
I , It ts called CISC microcontroller. (CISC - Reduced Instruction Set Computer).
I
Com plex Inst ruct ion Set Computer)
It has less number of instructions .
•
• It has mor e num ber of instructions . No diVisfon and multiplexing is requ ired
•
i' • Division and multiplexing Is requ ired to because address bus and data bus are
'f'
use prog ram and data . separated.
i
! Instruction Data
! Data bus bus bus
f
I
Data m/m
l CPU Program: Data
Prog m/m

i m/m I m/m

!i Address & Address & control bus

Control bus
' Figure 1.8 Control Bus
Figure 1.9 Address and Control Bus

I
I
j
1.4.2 Advantages and Disadvantages o
f Von Neuman and Harvard Architecture :

Advantages of Von Neuman

I
1. Less complex

2• Simple construction
.3 . Bus structure 1s not complex
not be used simultaneously.
Disadvantages of Von Neuman : e not separate, it can
I As the data and address bus arl becomes difficult.
I .
2. The Implementation of pipe Un ng .
I

Advantages of Harvard : d ta and address bus.

- _, ... ,.rfnr man ce due to separate . a , ,. , ,,.nrv. .
•
►
~
I
I
i
Microptocessor Based Systems 9

i • The Harvard architecture has an advantage of executing Instructions In fewer Jnstructlons

I

I _cycles than Princeton (Von Neumann) architecture; This Is because a much greater amount
f of instruction parallelism can be achieved In the Harvard architecture due to separate
i' memory banks.
I
i
I 1.4.1 Difference between Von Neumann and Harvard Architecture :
I
!
f
I
I
!
I
i
'
I
• Data bus and address bus are not separate. • Data bus and address bus are separate.
'
I
l
r So greater flow of data is not possible. So greater flow of data is possible.
;
I

• It is called RISC microcontroller. (RISC -

I • It is called CISC microcontroller. (CISC -
Reduced Instruction Set Computer).
Complex Instruction Set Computer)
• It has less number of instructions .
• It has more number of instructions.
' • No division and multiplexing is required
''
i • Division and multiplexing is required to
;
l because address bus and data bus are
!I use program and data.
i separated.
i
I Instruction Data
I Data bus
I
l I Prog m/m
bus
l
CPU
bus

Data m/m

I
I
!
CPU Program, Data
m/m , m/m

'i Address &

I Control bus Address & control bus

I Figure 1.8 Control Bus Figure 1.9 Address and Control Bus
'
I
! · d Di dvanta.ges of Von Neuman and Harvard Architecture :
I.4.2 Advantages an sa

I Advantages of Von Neuman

1. Less complex
2. Simple construction
3. Bus structure is not complex
Disadvantages of Von Neuman :
rate It cannot be used simultaneously.
I. As the data and address bus are not sepa '
i g· becomes difficult.
2. The implementation of pipe Un n ·
Advantages of Harvard :
 • RJSC proces sors uses s imple Instruc tion formats with fixed lnstruc
l lnetruc tton length Is al igned on the word bounda ries . The opcode
tlon length. The
j s are Oxed fo r an
tn1truct 1on. As word kngtll unlls are fetched , the fetching operaU
i on Is optimiz ed .-
r Table 1.1 Ditferc11ce berw-cen RJ6C end CI8C process or
'
I - ~ ~ ... ~ ... ~ . . ' l .., . ,I ,, - • l ..
I
}
1. It has few Instruc tions. I. h has large numbe r of tnstrucU ons.
2. E~ecuUon time for an ln s trucuon may take 2. Enc utlon time for an Instruc tion may
f small clock p~rlods .
j take several clock cycles.
3 . Chlps require le-&ser cost of product ion.
. 4. Chlps require less hardwa re lmplem en -
3. Chtps require higher cost of product ion.
t 4. ChJps require hLgher hardwa re lmplem en•

r'
tatlon, taUon.

5. Very few addres sing modes . 5. A large numbe r of addres sing mode.s.
f
i
I ► QuestJ on.s :
I I. Explain wtth block d~am of ciJgital cornpute-r.

I 2.
S.
Write dl!ferencc between Microp rocesso r & Microcontroller.
Wnte short notes about Micro Com.pute:r.

I 4. Write difference betwee n Von Neumann and Hanrar d Archite cture.

s. Explain difference betwee n RISC and CISC process or.
I
t ***
'
 8085 MlcroproccMnt ts nn 8-·bH g-cnttal putpoge trt lcroproce.~sot. ft IS suitable fo r a wide
range or appUcauans. Jt -1~ cA11:ed 8-btt mtcroprotessM hecausc ft has 8 bit Internal data bus and 4

can rtad, wrne nnd proceM 8-..blt data at a ume. The tnttrn.af arcfHttcture of 8085 mtcroprocessor
ts shuwn tn Figure 2.'11 . Thi~ includes the foJlowtng bfocks:
(l) ~egtst-er Stock (ff) Arfthrnettc and Logi c Unit (ALU} Block.
Ott} Control Unit Block {fv) tnterru pt. block

fvl Sertal I/O Control Block

INTA RST6.5 TRAP

SID SOD
IN'TR RSI 5.5 RSI 7.5
t
.__ _,Inr-re_rru
~ pt_c_on_tr_ol_
}
__,JI
:,, 8 Bit internal data bus
'\
/
'
Serial I/O control j

I I
' >
\J 1
\J
I, . ., I \J ,;
j Accumulator! Temporary IFlag Register I Instruction
1

i-
WReg ZReg
1

register register
B Reg C Reg
D Reg E Reg
,_, .. r--- \)
-,)i Arithmetic H Reg L Reg
Instruction
-
f-
Logic
Unit
- decoder Stack Pointer
and Program
) ALU
y machine Counter

Power
Supply
C GND
+5V T cycle
encoder Incrementer/
Decrememer
Address latch
___ .J___ _ _ _ _ _ _ _ ~•J_)~ -
CLK x,_ r Timing and Conirol
,..,
-
IN X2- CLK
CONTROL STATUS DMA RESET Address Addr~'i-'i/Dalll
GEN ~ ~ ~ ~ buffer buffer
l
CLKOUT RD
RE.ADY WR
I t
ALE
So
l
SI
JO/M
I
HOLD RESET IN
RESET
I
V
A, 5 - Ag
Adur~s~bus
I

)
e
AD1 - AD 0
Datu / Add~s
OUT bus

Figure 2.11 8086 Mlcroproceuor Arc hitecture

\ 32
\ I

\ Mlcropr.ocessors and Microcontrolle

th is operaUon . lt rs
ls referred as re
The blts of an y gister A In the pr
regtster arc refe ogram. \ D7 \ Da \ D5 \ 0~
tn ~ ur c 2.1 2 . rr ed ns D 7 - Do as \ 03 \ 02 \ o, \ Do
sh~wn· \
{l l) Temporary Figure 2.12 Bits
Register {TR) : of any reglaler
Temporary regi
ster ts an 8-blt .
ar ithm etic and lo wide reglster. It
gtc Instructions ls mostly us ed
. It ls not access to st or e te m po ra
ible to the us er ry da ta In
(ii i) Flag Reg .
ister {FR) :

~ D6 D5 D4 Flag register ls
D3 D2 a gr ou p of eigh
I II I I I I I
s \ z X AC X
p
D1 D0

X CY
ou t of which five
Information ab ou
fllp-flops ar e us
ed
t lndlvidual flip
-flop ,
to st or e si gn if ic
t th e re su lt of th an t
X-Don't Care op er at io ns : T he e ar it hm et ic an
ot he r th re e fl ip d logic
Figure 2.13 Flag -f lo ps ha ve un
Re gi st er values . The bi ts de
of th e flag re gi fi ne d
st er an d th ei r
• Carry Flag {CY)
it ls re se t (0)
: If an arithmetic
. The ca rr y flag
al so
op
se
codes ar e show
eration results In
n ln figure 2. 13
carry, a th e ca rr
.
y flag ls se t ( l );
co nd it io n
\
th e dual pu rp os rv es as a borrow fla otherwise
e of showing carr g for su bt ra ct io
y an d borrow in case of n. T he ca rr y flag solves
It is re pr es en te ad dl ti on an d su
d by D bi t of fla bt ra ct io n respec
0 g register. tively.
• Pa ri ty Fl ag {P)
: T hi s nag bi t
nu m be r of on es (D 2 ) shows the
re su lt of th e ar it
or od d. Si nc e 80 hm et ic op er at io
nu m be r of ones 85 m ic ro pr oc es so r follo n is having even
in ac cu m ul at or ws even pa ri ty
It is cleared (0) af ter arithmetic op sy st em so lf th
. eration Is even, e
th is flag is se t (
l ), ot he rw is e
• A ux ili ar y C ar
ry Fl ag (AC)
: In an ar it hm
nibb le an d pa ss et ic op er at io n w
ed to up pe r ni hen a ca rr y Is
in te rn al ly for bb le, th e auxiliar ge ne ra te d by lo
BCD (B in ar y C y ca rr y fl ag (AC) ls se t. wer
programmer. D od ed Decimal) T hl s flag ls us
bl op er at io ns . A C ed
4 t of fllp-flop re pr es en fl ag ca n no t be us ed
• t th e au xiliary ca rr y fla by th e
Zero Flag (Z) g.
: T he zero flag
ze ro or non-zero sh ow s th at the re su lt
. T he zero flag of any ar lt hr ne tl
Is se t ( l) when th c or logtc op er
_Zero flag ls re pr e re su lt ls zero at io n ls
es en te d by D : ot he rw
6 bi t of flag register. is e it ls re se t {0).
• Si gn Flag (S) :
T he sign flag Is
D7 of th e re se t re pl ic a of th e D
is l; ot he rw is e 7 bl t of th e re su lt .
It Is re se t (0) . Si T he sign flag ls
N ot e : Flags gn flag ts re pr es se t ( \} If bi t
ar e m od if le d on en te d by D bl t
ly af te r the exec 7 of flag register.
E u m p lc 2. 1 : ution o f an ar
lth m et lc or lo gi
Add tw o he xa c operatton.
{l ag re gi st er fo de ci m al nu m be
r th is op er at io rs 93 H an d 15 H. D et
n. er m tn e the st at
us o f the
So lu ti on :

100 l 000 l (93H)

+ 0001 0101 (1 5H )
1010
1000
T he re ls no ca
rr y in th e re su
lt of ad dl tl on ,
he nc e ca rr y flag
ls re se t CY = o.
 90 Mlcroprocesson and Microcoutrollm
From the discussion so far, we con
clude that In sys teIlUI b a.8,;..d on 8751 , 89O S 1, or DSSOOO
mlcrocontrollcrs, we have thre
e ports, PO, Pl, and P2, for 1/0
enough · for moat mtcrocontroll ope rati ons . Thi s sho uld be
cr applications. Tha t leaves por
oth er slgna.15, as we will see nex t 3 for inte rru pts as well as
t.
3.1 2.4 Port 3 pin con fitu rat
lon :
Por t 3 occupies a total of 8 pin
s, pins 10 through 17. It can be
Although por t 3 ts configured as lnp ut of out put port.
as an out put por t upon rese t.
com mo nly use d. Por t 3 has thJs ls not the way It ls most
the additional function of pro
sig nal s suc h as Inte rru pts . Tab vtd lng som e ext rem ely Imp orta nt
le 3.4 provides these alternate
app lies to bot h 805 1 and 8031 fun ctto ns of P3. Thi s lnformatlon
chips.
P3. 0 and P3. l are use d for
the rum and TXD serial com
and P3. 3 are set asid e for ext mu nic atio ns stgn als. Bit s P3. 2
ernal Inte rrup ts, Bits P3.4 and
Ffn ally , P3. 6 and P3. 7 are P3.5 are use d for tlm ers 0 and
use d to provide the WR and 1.
con nec ted In 803 1-b ase d sys tem RD sig nal s of ext ern al me mo ries
s. The por t 3 pin configuration
ts as sho wn In Fig. 3.1 8.
i
Read Latch bit _ _ Alternate output I
Vee I

Internal
FET
.I
I
I
pull up I
Internal bus -- -1 D I
0
Write to
latch
LATCH
CL Q
Pin
3.X I
Read Pin data
Alternate Input
Figure 3.18 Internal Circ uit of
Port 3
Th e Por t 3 alte rna te use s are
shown in the followtng table :
Table 3.4

P3. l TXD
SBUF
Serial Data Output
P3. 2 SBUF
INTO External Int err upt 0
P3. 3 INTI TCON.l
External Int err upt I
P3. 4 TO TCON.3
Ext ern al Timer 0 lnp ut
P3.5 Tl TMOO
External Timer 1 Ou tpu t
TMOD
P3. 6 WR Ext ern al Memory Write Pulse
P3. 7 RD Ext ern al Memory Read Pulse
 Vlll\.. ' J V ~ .. - .. -- - - •
• I

Serla1 110•
Tim ers/Coun ters. and a clock cfrc utt
The 51 1s one of the most popular mtcroco
80 ntrollers today. Many deri vative mic ro-controlle
rs
have stnCe been developed. that are based on compatible wtth the 805 1. Thu s, the abil ity to
program an 8051 1s an Important sklll for anyone who plans to develop products that wtll tak e
advantage of mtcrocontrollers. The fig. 3. I shows block diag
1-'~u.:~pt::F~~?
J.r '7·•;i,.
f!;.'f{~p: .
f;:~"'¢_o~~i l a'.t".cta
C , . , D .~W
~
.; oo.Uf
_uf fttt~
fnif~
1'
ram of 805 I mlcrocontroller.
l\
.
The descrtptlon of each block ts as follows :
a.4.1 CPU Registers :

• ALU:
Arithmetic & Logical Unit (ALU) ts capable of
operating on byte level and bit level. ALU
performs arithmetic functions like addition,
subtraction. multiplication and division. It ls
capable of performing logical functions normally also
called Boolean functions.
• Register A :
The A regtster ls also called as accumulator.
It ts used for many operations. particularly
mathematical and logical operations, and Boo
lean bit manipulations. The A register ls
used for all data transfers between the 8051 and also
any external memory. If stores the answer of
logical & Mathematical operation.
• Register B :
The B register ls used wtth the A register
for multJpllcatlon and division operations and
1as no other function other than data stor
age.
3,4.2 PC and DPTR :
Program Counter (PC) :

The S051 contain a 16-btt register called as Prog

ram Cou nter , which ts used to hold the
ddress of a byte In prog h
1structton byte ls fetch ram memory. T e PC ts auto matically incr
ed The PC I th eme nted after every
· s e on 1Y regtster that does not have an inte
DATA Pointer (DPTR) : rnal address.
This ls also 16-blt register d
sed when m ' ma e up of two 8-blt registers, named DPH
emory addresses for Internal d and DPL. They are
1PTR does
not ha l -
an externa code access and external data
ve a single internal addre DPH access.
ormally tt can · be used t I d
ss: an DPL are each assigned an address.
n ookup table accessing method.
,4,3 Stack Pointer (SP) :
Stack ls a part of .
> lnte RAM Ls
rnal RAM of ml~rocontr used
11
for tern
porary data storage. Stack Pointer (SP) poin
o er. When syst I ts only
· em 5 switched ON, SP 1s lnlttaltzed to 07H.
76 Microprocessors and Microcontrollers

Byte
Address Byte
AddreH
1F R7 7F . - - - - - - i
1E R6
10 R5
qi M
'lh~ 1C R4
·-Cll 111
C
Q) a) 18 R3
1A R2
19 R1
18 RO
17 R7
16 R6
,._ 15 RS
SN 14
~~ R4
Cl Ill
a: m
Q) 13 R3
12 R2
11 R1
Byte Bit

\
10 RO address address
OF R7 2F 7F 78
OE R6 2E 77 70
,._
OD RS 20 6F 68
s..- OG R4
Ill~ 2C 67 60
i'ial OB R3 28 5F 58
OA R2 2A 57 50
09 R1
29 4F 48
08 RO 28 47 40
07 R7 27 3F 38
06 RB 26 37 30
05 RS 25
~c 2F 28
- JI. 04 R4 24
ii 27 20
03 R3
" Ill 23 1F 18
02 R2 22 17 10
01 R1 21 OF 08
00 RO 20 07 00
7, .__ _ 0 30 '- '- -- -- -'
Working Registers
Bit addressable General Purpose

Figure '3.10 Internal RAM Organiz

ation
 t
8051 Microcontroller Arthitecturc 61

3.4.4 PSW :
It Is also called as Program S tatus Word . PSW contain nag ,rcglstcrs. which stores 1-blt
, r rtaln prrn,warn tnstructton 9., 'the 805 1 has four math, nags : , Carry0),(C), Auxiliary
resu It o ce · -e-· -
Carry CAC). overfl ow {OV) and Pa ri ty (P). It also contain§ user program nag (F .
s.4.8 Memory :

• Internal Memory :

'l'he 805 J has 128 bytes of Internal RAM , called data memory and 4KB of Internal ROM ,
called program memory.
Intern al RAM Is dlvtded In three categories
• Four register banks (RBO-RB3), each containing eight registers.
• 16 bytes, which may be addressed at the bit level (20h - 2Fh)
• 80 bytes of general-purpose data memory (30h - 7Fh)
Internal ROM 4KB occupies code address space 0000h to 0FFFh.
• Enernal Memory :

I Add!ttonal both RAM & ROM memory can be added up to 64 KB externally using suitable
circuits. External memory fetched by connecting the external access pin (EA pin no. 31 on
805 I chip) to ground .

3.4.6 Special Function Register (SFR) :

Special Function Register IP, IE, TMOD, TCON, SCON and PCON contain control and status
bits for the interrupt system, the Timer/Co unters, and the Serial port.
• IP, IE are used for interrupts .
• SCON ls used for serial communlc atton.
• TCON, TMOD are related with timer/cou nter .
• PCON for power saving mode.
3.4. 7 I/0 Ports :

There are 32 Input/Out put pins arranged as four 8-bit ports; each port pln has a latch bit.
Port can be configured as Input by writing Logic l and Output by writing Logic o.

Q Port O : An 8-btt port for the Input/Output (l/0) and data bus cum lower order address
bus (AD0-AD7).

• Port 1 : An 8-blt port for the Input/out put (I/0).

2 8
• Port : An ·blt port for the Input/output !1/0) and high order address bus (A8-Al5).
3 8
• Port : An -bll port for the Input/output !1/0) and alternate functions such as ·serial
interface bits (TXD, RXD). Timer TO and Tl 1 - --
and Write signals. nputs, Interrupt s INTO and INTI, Read
1(1
-- - . .... _ --------
Mlcroproou~ora n,irl Mtcrocontm)!!_ll~
or~n~ - - - -~2.:_·.:.-"~ - - - - 000 5 MloroproceStJor Arc hite ctur e
---..::::::.::.:...:..::..:.::..~.::..:.-=-- - - - - -
lNTt-: ~8T o,n Tr{AP
IN1 rt MT G.G RST 7.0 SID SOD

:t

g (~
lo

l\'

PO WE R{ - + SV
) SUPPLY -G ND

CU< OUT lffi . ALE

READY ~ So 10/fvl HLD A . RESET OUT A 15 - As AD 7 -AD o
Add ress bus Dat a I Add ress
Fig. 2.2.1 Arc hite ctu re of 8085 bus
fJ jj Re gis ter Str uc tur e
Temporary
• TI1.e Fig. 2.2.2 sho ws the register
reg iste r str uct ure of
8085. (See Fig. 2.2 .2 on nex t pag
e)
• The sha ded por tio n of this
reg iste r mo del is
called programmer's mo del of
8085. It inc lud es
six 8-bit reg iste rs - (B, C, D,
E, H and L) one
ncc wn ula tor , one flag reg iste
r and two 16-bit
reg iste rs (SP · and PC). All
these reg iste rs are
access ible to pro gra mm er and hen ce
the y are
inc lud ed in the pro gra mm er's
mo del .
• Th e rem ain ing reg iste rs -
Te mp ora ry, W and Z Fig.
2.2 .2 Re tg: ~r structure
are not accessible to the pro
gra mm ers ; the y are of
use d by mic rop roc ess or for int
ern al, int erm edi ate ope rat ion s.

TECHNICAL PUBLICATIONS®
- An up thrust for knowledge
 8085 Interrupts

MjcfOP,ocessors and Microcontro/le 3- 15

rs

; sav e hou rs cou nte r

MO VD ,A
; Che ok for 24 hou rs
CPI 24 H ; If not 24, got o disp lay
JNZ LA ST
MVI D, OOH ; Res et hou rs cou nte r
; Cal l disp lay sub rou tine
LAST : CAL L OIS PLAY
; Ena ble Inte rrup t
EI ; Ret urn to main pro gtal ll
RET

No

f-~ ·!i:ff!bttr
!41t,,,~m"#t
Fig. 3.6.6 Flowchart for Interrupt sub
routine
TECHNICAL PUBLICATIONS®
• An up thrust for knowledge
 Define T state in microprocessor and microcontroller
10:35 am ✓/

In microprocessors and microcontrollers, the T state refers

to a time period of a clock cycle. During this time, signals
on the microprocessor or microcontroller are stabilized and
data transfer takes place. The T state is a series of timings
within one machine cycle where the microprocessor
executes one machine instruction . Each instruction
cycle is divided into a number of T states, with each T
state representing a discrete step that the processor
takes to execute the instruction. The number of T states
in an instruction cycle varies depending on the specific
processor architecture, clock frequency and instruction
being executed . 10:36 am

e tv, essage
In microcontrollers, SJMP and LJMP are two differ ent
types of jump instru ctions used for contro lling the program
flow. The main differences between these two instru ctions
are as follows:

1. SJMP (Short Jump ) is an instru ctio,n that allows the

processor to jump a short distance, typica lly within a -128
to +127 byte range. LJMP (Long Jump ), on the other hand,
allows the processor to jump to a memo ry location that is
specified by a 16-bit address.

2. SJMP is used for imple menti ng loop struct ures within a

code, while LJMP is used for imple menti ng subroutines.

3. SJMP takes less memo ry space as compared to LJMP,

as it only requires a single-byte instru ction, while LJMP
requires a two-byte instru ction.

4. SJMP has a faster execution time than LJMP as it takes

a simpl e instruction format. On the other hand, LJMP
takes more time to execute, as it requires two separate
operations to fetch the 16-bit address and update the
program counter.

In summ ary, SJMP is used for short jumps within the same
code segment, while LJMP is used for jumpi ng between
differ ent code segments such as subro utines .
10:51 am
In microcontrollers, JB and JNB are two jump instructions
used for controlling the program flow. The main difference
between these two instructions is:

1. JB (Jump if Bit set): This instruction jumps to the

specified address if the specified bit is set or 1.

2. JNB (Jump if Bit not set): This instruction jumps to the

specified address if the specified bit is not set or 0.

In other words, JB checks if the specified bit is 1 before

jumping to the target address, while JNB checks if the
specified bit is O before jumping to the target address.
10:52 am
MOVX and MOVC are two instructions commonly used in
microcontroller programming. Both instructions are used
for transferring data from a memory location to a register in
the microcontroller. However, the main differences between
these two instructions are:

1. MOVX (Move External Data) - This instruction is used to

transfer data between the microcontroller and an external
memory device. It is specifically used for accessing
external data memory, i.e., RAM or RQ ;M .
2. MOVC (Move Code) - This instruction is used for
accessing program memory in the microcontroller. It
moves a byte of code from the program memory to an
internal register.

So, the main difference between MOVX and MOVC is

that MOVX is used for accessing external memory, while
MOVC is used for accessing program memory in the
microcontroller. 10:52 am
In computer programming, editors, assemblers, compilers,
and linkers are software tools that play important roles
in the development process. Here's a brief description of
each:

1. Editor: An editor is a software tool that allows developers

to create, modify, and save text files that contain program
code. It usually provides features like syntax highlighting,
auto-indentation, and code completion that help to make
programming easier.

2. Assembler: An assembler is a software tool that

takes assembly language code, written by a developer,
and converts it into machine code that can execute on
a microcontroller or microprocessor. The assembler
translates each opcode and operand into binary code,
which is stored in memory for execution.

3. Compiler: A compiler is a software tool that takes

high-level source code and translates it into low-level
machine code that a microcontroller or microprocessor can
execute. Compilers are used for languages like C, C++, and
Java.

4. Linker: A linker is a software tool that takes one or

more object files generated by the compiler or assembler
and combines them into a single executable program.
It resolves external references between different object
files and creates a final executable that can be run on a
microcontroller or microprocessor.

Overall, the editor helps developers to write code, the

assembler and compiler generate executable code, and the
linker turns that code into a single program that can be run
on a microcontroller or microprocessor.
 Explain assembler directives
1 ORG
2 EQU
3 END 10:54 am ✓/

1 Unread Message

In assembly language programming for microprocessors

and microcontrollers, assembler directives are special
commands used to give instructions to the assembler,
which is a program used to convert assembly code into
machine code. Here is a brief overview of each directive:

1. ORG (Origin): The ORG directive is used to specify the

starting address for the code segment in memory. This
directive sets the value of the program counter (PC) to the
specified address.

2. EQU (Equation) : The EQU directive is used to define a

symbolic name for a constant or value. The EQU directive
assigns a value to a symbolic name that can be used
throughout the assembly code.

3. END (End): The END directive is used to indicate the

end of the program. It typically appears at the end of the
source code file and tells the assembler to stop reading the
file. The END directive is also used to specify the starting
address of a program with a parameter that specifies the
address where the program execution should start.
10:55 am

e ~ essage