8-Channel DAS with 14-Bit, Bipolar Input,

Simultaneous Sampling ADC

Data Sheet AD7607
FEATURES APPLICATIONS
8 simultaneously sampled inputs Power-line monitoring and protection systems
True bipolar analog input ranges: ±10 V, ±5 V Multiphase motor control
Single 5 V analog supply and 2.3 V to 5.25 V VDRIVE Instrumentation and control systems
Fully integrated data acquisition solution Multiaxis positioning systems
Analog input clamp protection Data acquisition systems (DAS)
Input buffer with 1 MΩ analog input impedance
Second-order antialiasing analog filter Table 1. High Resolution, Bipolar Input, Simultaneous
On-chip accurate reference and reference buffer Sampling DAS Solutions
14-bit ADC with 200 kSPS on all channels Single-Ended Number of Simultaneous
Flexible parallel/serial interface Resolution Inputs Sampling Channels
SPI/QSPI™/MICROWIRE™/DSP compatible 18 Bits AD7608 8
Pin-compatible solutions from 14 bits to 18 bits 16 Bits AD7606 8
Performance AD7606-6 6
7 kV ESD rating on analog input channels AD7606-4 4
Fast throughput rate: 200 kSPS for all channels 14 Bits AD7607 8
85.5 dB SNR at 50 kSPS
INL ±0.25 LSB, DNL ±0.25 LSB
Low power: 100 mW at 200 kSPS
Standby mode: 25 mW typical
64-lead LQFP package

FUNCTIONAL BLOCK DIAGRAM

AVCC AVCC REGCAP REGCAP REFCAPB REFCAPA

1MΩ RFB
V1 CLAMP
SECOND- T/H
V1GND CLAMP ORDER LPF 2.5V 2.5V
1MΩ RFB
LDO LDO

1MΩ RFB REFIN/REFOUT

V2 CLAMP
SECOND- T/H
V2GND CLAMP ORDER LPF
1MΩ RFB REF SELECT
2.5V
REF AGND
1MΩ RFB
V3 CLAMP
SECOND- T/H OS 2
V3GND CLAMP ORDER LPF
1MΩ RFB OS 1
OS 0
1MΩ RFB
V4 CLAMP
SECOND- T/H DOUTA
V4GND CLAMP ORDER LPF SERIAL
1MΩ RFB DOUTB
8:1
1MΩ RFB MUX PARALLEL/ RD/SCLK
14-BIT DIGITAL
V5 CLAMP FILTER SERIAL
T/H SAR INTERFACE CS
SECOND-
V5GND CLAMP ORDER LPF
1MΩ RFB
PAR/SER/BYTE SEL

1MΩ RFB VDRIVE

V6 CLAMP
SECOND- T/H
V6GND CLAMP ORDER LPF PARALLEL DB[15:0]
1MΩ RFB

1MΩ RFB AD7607

V7 CLAMP
SECOND- T/H
V7GND CLAMP ORDER LPF CLK OSC
1MΩ RFB

1MΩ RFB BUSY

V8 CLAMP CONTROL
SECOND- T/H INPUTS FRSTDATA
V8GND CLAMP ORDER LPF
1MΩ RFB
08096-001

AGND CONVST A CONVST B RESET RANGE

Figure 1.

Rev. D Document Feedback

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AD7607 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 ADC Transfer Function ............................................................. 20
Applications ....................................................................................... 1 Internal/External Reference ...................................................... 21
Functional Block Diagram .............................................................. 1 Typical Connection Diagram ................................................... 22
Revision History ............................................................................... 2 Power-Down Modes .................................................................. 22
General Description ......................................................................... 3 Conversion Control ................................................................... 23
Specifications..................................................................................... 4 Digital Interface .............................................................................. 24
Timing Specifications .................................................................. 6 Parallel Interface (PAR/SER/BYTE SEL = 0).......................... 24
Absolute Maximum Ratings.......................................................... 10 Parallel Byte Interface (PAR/SER/BYTE SEL = 1, DB15 = 1) .. 24
Thermal Resistance .................................................................... 10 Serial Interface (PAR/SER/BYTE SEL = 1) ............................. 24
ESD Caution ................................................................................ 10 Reading During Conversion ..................................................... 25
Pin Configuration and Function Descriptions ........................... 11 Digital Filter ................................................................................ 26
Typical Performance Characteristics ........................................... 14 Layout Guidelines ........................................................................... 29
Terminology .................................................................................... 18 Outline Dimensions ....................................................................... 31
Theory of Operation ...................................................................... 19 Ordering Guide .......................................................................... 31
Converter Details........................................................................ 19
Analog Input ............................................................................... 19

REVISION HISTORY
5/2018—Rev. C to Rev. D 1/2012—Rev. A to Rev. B
Changes to Patent Note, Note 1 ...................................................... 3 Changes to Analog Input Ranges Section ................................... 19
Change to tCONV Parameter, Table 3 ................................................ 6
7/2010—Rev. 0 to Rev. A
2/2016—Rev. B to Rev. C Change to Table 1 ..............................................................................1
Changes to Patent Note, Note 1 ...................................................... 3
Changes to Figure 35 ...................................................................... 20 7/2010—Revision 0: Initial Version
Change to Figure 36 ....................................................................... 21
Changes to Ordering Guide .......................................................... 31

Rev. D | Page 2 of 32
Data Sheet AD7607

GENERAL DESCRIPTION
The AD76071 is a 14-bit, simultaneous sampling, analog-to- The input clamp protection circuitry can tolerate voltages of up
digital data acquisition system (DAS). The part contains analog to ±16.5 V. The AD7607 has 1 MΩ analog input impedance,
input clamp protection; a second-order antialiasing filter; a track- regardless of sampling frequency. The single supply operation, on-
and-hold amplifier; a 14-bit charge redistribution, successive chip filtering, and high input impedance eliminate the need for
approximation analog-to-digital converter (ADC); a flexible driver op amps and external bipolar supplies. The AD7607
digital filter; a 2.5 V reference and reference buffer; and high antialiasing filter has a 3 dB cutoff frequency of 22 kHz and
speed serial and parallel interfaces. provides 40 dB antialias rejection when sampling at 200 kSPS.
The AD7607 operates from a single 5 V supply and can accom- The flexible digital filter is pin driven and can be used to simplify
modate ±10 V and ±5 V true bipolar input signals while sampling external filtering.
at throughput rates of up to 200 kSPS for all channels. 1
Protected by US Patent Number 8,072,360.

Rev. D | Page 3 of 32
AD7607 Data Sheet

SPECIFICATIONS
VREF = 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, fSAMPLE = 200 kSPS, TA = TMIN to TMAX, unless otherwise noted.1

Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE fIN = 1 kHz sine wave, unless otherwise noted
Signal-to-(Noise + Distortion) (SINAD)2, 3 No oversampling; ±10 V range 84 84.5 dB
No oversampling; ±5 V range 83.5 84.5 dB
Signal-to-Noise Ratio (SNR)2 Oversampling by 4, fIN = 130 Hz 85.5 dB
No oversampling 84.5 dB
Total Harmonic Distortion (THD)2 −107 −95 dB
Peak Harmonic or Spurious Noise (SFDR)2 −108 dB
Intermodulation Distortion (IMD)2 fa = 1 kHz, fb = 1.1 kHz
Second-Order Terms −110 dB
Third-Order Terms −106 dB
Channel-to-Channel Isolation2 fIN on unselected channels up to 160 kHz −95 dB
ANALOG INPUT FILTER
Full Power Bandwidth −3 dB, ±10 V range 23 kHz
−3 dB, ±5 V range 15 kHz
−0.1 dB, ±10 V range 10 kHz
−0.1 dB, ±5 V range 5 kHz
tGROUP DELAY ±10 V Range 11 µs
±5 V Range 15 µs
DC ACCURACY
Resolution No missing codes 14 Bits
Differential Nonlinearity2 ±0.25 ±0.95 LSB4
Integral Nonlinearity2 ±0.25 ±0.5 LSB
Positive/Negative Full-Scale Error2, 5 External reference ±2 ±9 LSB
Internal reference ±2 LSB
Positive Full-Scale Error Drift2 External reference ±2 ppm/°C
Internal reference ±7 ppm/°C
Negative Full-Scale Error Drift External reference ±4 ppm/°C
Internal reference ±8 ppm/°C
Positive/Negative Full-Scale Error ±10 V range 2 8 LSB
Matching2
±5 V range 4 10 LSB
Bipolar Zero Code Error2, 6 ±10 V range ±0.5 ±2 LSB
±5 V range ±1 ±3.5 LSB
Bipolar Zero Code Error Drift2 ±10 V range 10 µV/°C
±5 V range 5 µV/°C
Bipolar Zero Code Error Matching ±10 V range 1 2.5 LSB
±5 V range 3 6 LSB
Total Unadjusted Error (TUE) ±10 V range ±0.5 LSB
±5 V range ±1 LSB
ANALOG INPUT
Input Voltage Ranges RANGE = 1 ±10 V
RANGE = 0 ±5 V
Input Current +10 V 5.4 µA
+5 V 2.5 µA
Input Capacitance7 5 pF
Input Impedance See the Analog Input section 1 MΩ

Rev. D | Page 4 of 32
Data Sheet AD7607
Parameter Test Conditions/Comments Min Typ Max Unit
REFERENCE INPUT/OUTPUT
Reference Input Voltage Range 2.475 2.5 2.525 V
DC Leakage Current ±1 µA
Input Capacitance7 REF SELECT = 1 7.5 pF
Reference Output Voltage REFIN/REFOUT 2.49/ V
2.505
Reference Temperature Coefficient ±10 ppm/°C
LOGIC INPUTS
Input High Voltage (VINH) 0.9 × VDRIVE V
Input Low Voltage (VINL) 0.1 × VDRIVE V
Input Current (IIN) ±2 µA
Input Capacitance (CIN)7 5 pF
LOGIC OUTPUTS
Output High Voltage (VOH) ISOURCE = 100 µA VDRIVE − 0.2 V
Output Low Voltage (VOL) ISINK = 100 µA 0.2 V
Floating-State Leakage Current ±1 ±20 µA
Floating-State Output Capacitance7 5 pF
Output Coding Twos complement
CONVERSION RATE
Conversion Time All eight channels included; see Table 3 4 µs
Track-and-Hold Acquisition Time 1 µs
Throughput Rate All eight channels included 200 kSPS
POWER REQUIREMENTS
AVCC 4.75 5.25 V
VDRIVE 2.3 5.25 V
ITOTAL Digital inputs = 0 V or VDRIVE
Normal Mode (Static) 16 22 mA
Normal Mode (Operational)8 20 27 mA
Standby Mode 5 8 mA
Shutdown Mode 2 6 µA
Power Dissipation8
Normal Mode (Static) 80 115.5 mW
Normal Mode (Operational) 100 142 mW
Standby Mode 25 42 mW
Shutdown Mode 10 31.5 µW
1
Temperature range for the B version is −40°C to +85°C.
2
See the Terminology section.
3
This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel mode with VDRIVE = 5 V, SNR typically reduces by 1.5 dB
and THD typically reduces by 3 dB.
4
LSB means least significant bit. With ±5 V input range, 1 LSB = 610.35 µV. With ±10 V input range, 1 LSB = 1.22 mV.
5
This specification includes the full temperature range variation and contribution from the internal reference buffer but does not include the error contribution from
the external reference.
6
Bipolar zero code error is calculated with respect to the analog input voltage.
7
Sample tested during initial release to ensure compliance.
8
Operational power/current figure includes contribution when running in oversampling mode.

Rev. D | Page 5 of 32
AD7607 Data Sheet
TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted.1

Table 3.
Limit at TMIN, TMAX
Parameter Min Typ Max Unit Description
PARALLEL/SERIAL/BYTE MODE
tCYCLE 1/throughput rate
5 µs Parallel mode, reading during or after conversion; or serial mode (VDRIVE =
3.3 V to 5.25 V), reading during a conversion using DOUTA and DOUTB lines
5 µs Serial mode reading during conversion; VDRIVE = 2.7 V
9.1 µs Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines
tCONV Conversion time
3.45 4 4.2 µs Oversampling off
7.87 9.1 µs Oversampling by 2
16.05 18.8 µs Oversampling by 4
33 39 µs Oversampling by 8
66 78 µs Oversampling by 16
133 158 µs Oversampling by 32
257 315 µs Oversampling by 64
tWAKE-UP STANDBY 100 µs STBY rising edge to CONVST x rising edge; power-up time from
standby mode
tWAKE-UP SHUTDOWN
Internal Reference 30 ms STBY rising edge to CONVST x rising edge; power-up time from
shutdown mode
External Reference 13 ms STBY rising edge to CONVST x rising edge; power-up time from
shutdown mode
tRESET 50 ns RESET high pulse width
tOS_SETUP 20 ns BUSY to OS x pin setup time
tOS_HOLD 20 ns BUSY to OS x pin hold time
t1 40 ns CONVST x high to BUSY high
t2 25 ns Minimum CONVST x low pulse
t3 25 ns Minimum CONVST x high pulse
t4 0 ns BUSY falling edge to CS falling edge setup time
t52 0.5 ms Maximum delay allowed between CONVST A, CONVST B rising edges
t6 25 ns Maximum time between last CS rising edge and BUSY falling edge
t7 25 ns Minimum delay between RESET low to CONVST x high
PARALLEL/BYTE READ
OPERATION
t8 0 ns CS to RD setup time
t9 0 ns CS to RD hold time
t10 RD low pulse width
16 ns VDRIVE above 4.75 V
21 ns VDRIVE above 3.3 V
25 ns VDRIVE above 2.7 V
32 ns VDRIVE above 2.3 V
t11 15 ns RD high pulse width
t12 22 ns CS high pulse width (see Figure 5); CS and RD linked

Rev. D | Page 6 of 32
Data Sheet AD7607
Limit at TMIN, TMAX
Parameter Min Typ Max Unit Description
t13 Delay from CS until DB[15:0] three-state disabled
16 ns VDRIVE above 4.75 V
20 ns VDRIVE above 3.3 V
25 ns VDRIVE above 2.7 V
30 ns VDRIVE above 2.3 V
t143 Data access time after RD falling edge
16 ns VDRIVE above 4.75 V
21 ns VDRIVE above 3.3 V
25 ns VDRIVE above 2.7 V
32 ns VDRIVE above 2.3 V
t15 6 ns Data hold time after RD falling edge
t16 6 ns CS to DB[15:0] hold time
t17 22 ns Delay from CS rising edge to DB[15:0] three-state enabled
SERIAL READ OPERATION
fSCLK Frequency of serial read clock
23.5 MHz VDRIVE above 4.75 V
17 MHz VDRIVE above 3.3 V
14.5 MHz VDRIVE above 2.7 V
11.5 MHz VDRIVE above 2.3 V
t18 Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS
until MSB valid
15 ns VDRIVE above 4.75 V
20 ns VDRIVE above 3.3 V
30 ns VDRIVE = 2.3 V to 2.7 V
t193 Data access time after SCLK rising edge
17 ns VDRIVE above 4.75 V
23 ns VDRIVE above 3.3 V
27 ns VDRIVE above 2.7 V
34 ns VDRIVE above 2.3 V
t20 0.4 tSCLK ns SCLK low pulse width
t21 0.4 tSCLK ns SCLK high pulse width
t22 7 SCLK rising edge to DOUTA/DOUTB valid hold time
t23 22 ns CS rising edge to DOUTA/DOUTB three-state enabled
FRSTDATA OPERATION
t24 Delay from CS falling edge until FRSTDATA three-state disabled
15 ns VDRIVE above 4.75 V
20 ns VDRIVE above 3.3 V
25 ns VDRIVE above 2.7 V
30 ns VDRIVE above 2.3 V
t25 ns Delay from CS falling edge until FRSTDATA high, serial mode
15 ns VDRIVE above 4.75 V
20 ns VDRIVE above 3.3 V
25 ns VDRIVE above 2.7 V
30 ns VDRIVE above 2.3 V
t26 Delay from RD falling edge to FRSTDATA high
16 ns VDRIVE above 4.75 V
20 ns VDRIVE above 3.3 V
25 ns VDRIVE above 2.7 V
30 ns VDRIVE above 2.3 V

Rev. D | Page 7 of 32
AD7607 Data Sheet
Limit at TMIN, TMAX
Parameter Min Typ Max Unit Description
t27 Delay from RD falling edge to FRSTDATA low
19 ns VDRIVE = 3.3 V to 5.25 V
24 ns VDRIVE = 2.3 V to 2.7 V
t28 Delay from 16th SCLK falling edge to FRSTDATA low
17 ns VDRIVE = 3.3 V to 5.25 V
22 ns VDRIVE = 2.3 V to 2.7 V
t29 24 ns Delay from CS rising edge until FRSTDATA three-state enabled
1
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
2
The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <3 LSB performance matching between channel sets.
3
A buffer, which is equivalent to a load of 20 pF on the output pins, is used on the data output pins for these measurements.

Timing Diagrams
t5
CONVST A,
CONVST B
tCYCLE
t2
CONVST A,
CONVST B t3
tCONV
t1
BUSY

t4
CS
t7
tRESET

08096-002
RESET

Figure 2. CONVST Timing—Reading After a Conversion

t5
CONVST A,
CONVST B
tCYCLE
t2
CONVST A,
CONVST B t3
tCONV

t1
BUSY
t6

CS t7

tRESET
08096-003

RESET

Figure 3. CONVST Timing—Reading During a Conversion

CS

t9
t8 t10 t11

RD t16
t13
t14 t15 t17

DATA:
DB[15:0] INVALID V1 V2 V3 V4 V7 V8

t26 t27 t29

08096-004

t24
FRSTDATA

Figure 4. Parallel Mode, Separate CS and RD Pulses

Rev. D | Page 8 of 32
Data Sheet AD7607

t12

CS AND RD
t13 t16
t17
DATA: V1 V2 V3 V4 V5 V6 V7 V8
DB[15:0]

08096-005
FRSTDATA

Figure 5. Linked Parallel Mode, CS and RD

CS

SCLK t21 t20

t19 t22 t23

t18
DOUTA,
DB13 DB12 DB11 DB1 DB0
DOUTB
t29
t25 t28

08096-006
FRSTDATA

Figure 6. Serial Read Operation (Channel 1)

CS
t8 t9
t10 t11
RD t16
t13
t14 t15 t17

DATA: DB[7:0] HIGH LOW HIGH LOW

INVALID BYTE V1 BYTE V1 BYTE V8 BYTE V8
t26 t27 t29
08096-007

t24
FRSTDATA

Figure 7. BYTE Mode Read Operation

Rev. D | Page 9 of 32
AD7607 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. THERMAL RESISTANCE
Table 4. θJA is specified for the worst-case conditions, that is, a device
Parameter Rating soldered in a circuit board for surface-mount packages. These
specifications apply to a 4-layer board.
AVCC to AGND −0.3 V to +7 V
VDRIVE to AGND −0.3 V to AVCC + 0.3 V Table 5. Thermal Resistance
Analog Input Voltage to AGND1 ±16.5 V Package Type θJA θJC Unit
Digital Input Voltage to AGND −0.3 V to VDRIVE + 0.3 V 64-Lead LQFP 45 11 °C/W
Digital Output Voltage to AGND −0.3 V to VDRIVE + 0.3 V
REFIN to AGND −0.3 V to AVCC + 0.3 V
Input Current to Any Pin Except Supplies1 ±10 mA ESD CAUTION
Operating Temperature Range
B Version −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Pb/SN Temperature, Soldering
Reflow (10 sec to 30 sec) 240 (+ 0)°C
Pb-Free Temperature, Soldering Reflow 260 (+ 0)°C
ESD (All Pins Except Analog Inputs) 2 kV
ESD (Analog Input Pins Only) 7 kV
1
Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. D | Page 10 of 32
Data Sheet AD7607

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V8GND

V7GND

V6GND

V5GND

V4GND

V3GND

V2GND

V1GND
V8

V7

V6

V5

V4

V3

V2

V1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

AVCC 1 48 AVCC
ANALOG INPUT PIN 1
AGND 2 47 AGND
DECOUPLING CAP PIN
OS 0 3 46 REFGND
POWER SUPPLY OS 1 4 45 REFCAPB
GROUND PIN OS 2 5 44 REFCAPA

DATA OUTPUT PAR/SER/BYTE SEL 6 43 REFGND

AD7607
DIGITAL OUTPUT STBY 7 TOP VIEW 42 REFIN/REFOUT
(Not to Scale) 41 AGND
DIGITAL INPUT RANGE 8
CONVST A 9 40 AGND
REFERENCE INPUT/OUTPUT
CONVST B 10 39 REGCAP

RESET 11 38 AVCC

RD/SCLK 12 37 AVCC

CS 13 36 REGCAP

BUSY 14 35 AGND

FRSTDATA 15 34 REF SELECT

DB0 16 33 DB15/BYTE SEL

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

DB7/DOUTA
DB8/DOUTB
AGND
DB1
DB2
DB3
DB4
DB5
DB6

DB9
VDRIVE

DB10
DB11
DB12
DB13
DB14/HBEN

08096-008
Figure 8. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Type1 Mnemonic Description
1, 37, 38, 48 P AVCC Analog Supply Voltage, 4.75 V to 5.25 V. This supply voltage is applied to the internal front-end
amplifiers and to the ADC core. These supply pins should be decoupled to AGND.
2, 26, 35, 40, P AGND Analog Ground. These pins are the ground reference points for all analog circuitry on the AD7607.
41, 47 All analog input signals and external reference signals should be referred to these pins. All six of
these AGND pins should connect to the AGND plane of a system.
5, 4, 3 DI OS[2:0] Oversampling Mode Pins. Logic inputs. These inputs are used to select the oversampling ratio. OS
2 is the MSB control bit, and OS 0 is the LSB control bit. See the Digital Filter section for more
details about the oversampling mode of operation and Table 9 for oversampling bit decoding.
6 DI PAR/SER/ Parallel/Serial/Byte Interface Selection Input. Logic input. If this pin is tied to a logic low, the parallel
BYTE SEL interface is selected. If this pin is tied to a logic high, the serial interface is selected. Parallel byte
interface mode is selected when this pin is logic high and DB15/BYTE SEL is logic high (see Table 8).
In serial mode, the RD/SCLK pin functions as the serial clock input. The DB7/DOUTA pin and the
DB8/DOUTB pin function as serial data outputs. When the serial interface is selected, the DB[15:9] and
DB[6:0] pins should be tied to ground.
In byte mode, DB15, in conjunction with PAR/SER/BYTE SEL, is used to select the parallel byte mode
of operation (see Table 8). DB14 is used as the HBEN pin. DB[7:0] transfer the 16-bit conversion
results in two RD operations, with DB0 as the LSB of the data transfers.
7 DI STBY Standby Mode Input. This pin is used to place the AD7607 into one of two power-down modes:
standby mode or shutdown mode. The power-down mode entered depends on the state of the
RANGE pin, as shown in Table 7. When in standby mode, all circuitry, except the on-chip reference,
regulators, and regulator buffers, is powered down. When in shutdown mode, all circuitry is powered
down.
8 DI RANGE Analog Input Range Selection. Logic input. The polarity on this pin determines the input range
of the analog input channels. If this pin is tied to a logic high, the analog input range is ±10 V for all
channels. If this pin is tied to a logic low, the analog input range is ±5 V for all channels. A logic
change on this pin has an immediate effect on the analog input range. Changing this pin during
a conversion is not recommended. See the Analog Input section for more information.

Rev. D | Page 11 of 32
AD7607 Data Sheet
Pin No. Type1 Mnemonic Description
9, 10 DI CONVST A, Conversion Start Input A, Conversion Start Input B. Logic inputs. These logic inputs are used to
CONVST B initiate conversions on the analog input channels. For simultaneous sampling of all 8 input channels
CONVST A and CONVST B can be shorted together and a single convert start signal applied.
Alternatively, CONVST A can be used to initiate simultaneous sampling for V1, V2, V3, and V4; and
CONVST B can be used to initiate simultaneous sampling on the other analog inputs (V5, V6, V7,
and V8). This is possible only when oversampling is not switched on.
When the CONVST A or CONVST B pin transitions from low to high, the front-end track-and-hold
circuitry for their respective analog inputs is set to hold.
11 DI RESET Reset Input. When set to logic high, the rising edge of RESET resets the AD7607. The part should
receive a RESET pulse after power-up. The RESET high pulse should typically be 50 ns wide. If a
RESET pulse is applied during a conversion, the conversion is aborted. If a RESET pulse is applied
during a read, the contents of the output registers reset to all zeros.
12 DI RD/SCLK Parallel Data Read Control Input When the Parallel Interface Is Selected (RD)/Serial Clock Input
When the Serial Interface is Selected (SCLK). When both CS and RD are logic low in parallel mode,
the output bus is enabled. In serial mode, this pin acts as the serial clock input for data transfers.
The CS falling edge takes the DOUTA and DOUTB data output lines out of tristate and clocks out the
MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the
DOUTA and DOUTB serial data outputs. For more information, see the Conversion Control section.
13 DI CS Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic
low in parallel mode, the DB[15:0] output bus is enabled and the conversion result is output on
the parallel data bus lines. In serial mode, CS is used to frame the serial read transfer and clock
out the MSB of the serial output data.
14 DO BUSY Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges
and indicates that the conversion process has started. The BUSY output remains high until the
conversion process for all channels is complete. The falling edge of BUSY signals that the
conversion data is being latched into the output data registers and is available to read after a
Time t4. Any data read while BUSY is high must be completed before the falling edge of BUSY
occurs. Rising edges on CONVST A or CONVST B have no effect while the BUSY signal is high.
15 DO FRSTDATA Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read
back on the parallel, parallel byte, or serial interface. When the CS input is high, the FRSTDATA
output pin is in three-state. The falling edge of CS takes FRSTDATA out of three-state. In parallel
mode, the falling edge of RD corresponding to the result of V1 then sets the FRSTDATA pin high,
which indicates that the result from V1 is available on the output data bus. The FRSTDATA output
returns to a logic low following the next falling edge of RD. In serial mode, FRSTDATA goes high on
the falling edge of CS because this clocks out the MSB of V1 on DOUTA. It returns low on the 14th
SCLK falling edge after the CS falling edge. See the Conversion Control section for more details.
22 to 16 DO DB[6:0] Parallel Output Data Bits, DB6 to DB0. When PAR/SER/BYTE SEL = 0, these pins act as three-state
parallel digital input/output pins. When CS and RD are low, these pins are used to output DB6 to DB0
of the conversion result. When PAR/SER/BYTE SEL = 1, these pins should be tied to DGND. When
operating in parallel byte interface mode, DB[7:0] outputs the 14-bit conversion result in two RD
operations. DB7 is the MSB, and DB0 is the LSB.
23 P VDRIVE Logic Power Supply Input. The voltage (2.3 V to 5.25 V) supplied at this pin determines the
operating voltage of the interface. This pin is nominally at the same supply as the supply of the host
interface (that is, DSP and FPGA).
24 DO DB7/DOUTA Parallel Output Data Bit 7 (DB7)/Serial Interface Data Output Pin (DOUTA). When PAR/SER/BYTE SEL = 0,
this pins acts as a three-state parallel digital input/ output pin. When CS and RD are low, this pin is
used to output DB7 of the conversion result. When PAR/SER/BYTE SEL = 1, this pin functions as
DOUTA and outputs serial conversion data (see the Conversion Control section for more details).
When operating in parallel byte mode, DB7 is the MSB of the byte.
25 DO DB8/DOUTB Parallel Output Data Bit 8 (DB8)/Serial Interface Data Output Pin (DOUTB). When PAR/SER/BYTE SEL = 0,
this pin acts as a three-state parallel digital input/output pin. When CS and RD are low, this pin is
used to output DB8 of the conversion result. When PAR/ SER/BYTE SEL = 1, this pin functions
as DOUTB and outputs serial conversion data (see the Conversion Control section for more details).
31 to 27 DO DB[13:9] Parallel Output Data Bits, DB13 to DB9. When PAR/SER/BYTE SEL = 0, these pins act as three-state
parallel digital input/output pins. When CS and RD are low, these pins are used to output DB13 to
DB9 of the conversion result. When PAR/SER/BYTE SEL = 1, these pins should be tied to DGND.

Rev. D | Page 12 of 32
Data Sheet AD7607
Pin No. Type1 Mnemonic Description
32 DO/DI DB14/HBEN Parallel Output Data Bit 14 (DB14)/High Byte Enable (HBEN). When PAR/SER/BYTE SEL = 0, this pin
acts as a three-state parallel digital output pin. When CS and RD are low, this pin is used to output
DB14 of the conversion result, which is a sign extended bit of the MSB, DB13. When PAR/SER/BYTE
SEL = 1 and DB15/BYTE SEL = 1, the AD7607 operates in parallel byte interface mode, in which the
HBEN pin is used to select if the most significant byte (MSB) or the least significant byte (LSB) of the
conversion result is output first. When HBEN = 1, the MSB byte is output first, followed by the LSB
byte. When HBEN = 0, the LSB byte is output first, followed by the MSB byte.
33 DO/DI DB15/ Parallel Output Data Bit 15 (DB15)/Parallel Byte Mode Select (BYTE SEL). When PAR/SER/BYTE SEL =
BYTE SEL 0, this pin acts as a three-state parallel digital output pin. When CS and RD are low, this pin is used to
output DB15, which is a sign extended bit of the MSB, DB13, of the conversion result. When PAR/
SER/BYTE SEL = 1, the BYTE SEL pin is used to select between serial interface mode or parallel byte
interface mode (see Table 8). When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0, the AD7607
operates in serial interface mode. When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1, the AD7607
operates in parallel byte interface mode.
34 DI REF SELECT Internal/External Reference Selection Input. Logic input. If this pin is set to logic high, the internal
reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled and
an external reference voltage must be applied to the REFIN/REFOUT pin.
36, 39 P REGCAP Decoupling Capacitor Pin for Voltage Output from Internal Regulator. These output pins should be
decoupled separately to AGND using a 1 μF capacitor. The voltage on these pins is in the range of
2.5 V to 2.7 V.
42 REF REFIN/ Reference Input (REFIN)/Reference Output (REFOUT). The gained up on-chip reference of 2.5 V
REFOUT is available on this pin for external use if the REF SELECT pin is set to a logic high. Alternatively, the
internal reference can be disabled by setting the REF SELECT pin to a logic low, and an external
reference of 2.5 V can be applied to this input (see the Internal/External Reference section).
Decoupling is required on this pin for both the internal or external reference options. A 10 µF
capacitor should be applied from this pin to ground close to the REFGND pins.
43, 46 REF REFGND Reference Ground Pins. These pins should be connected to AGND.
44, 45 REF REFCAPA, Reference Buffer Output Force/Sense Pins. These pins must be connected together and
REFCAPB decoupled to AGND using a low ESR 10 μF ceramic capacitor.
49, 51, 53, AI V1 to V8 Analog Inputs. These pins are single-ended analog inputs. The analog input range of these
55, 57, 59, channels is determined by the RANGE pin.
61, 63
50, 52, 54, AI GND V1GND to Analog Input Ground Pins. These pins correspond to Analog Input Pin V1 to Analog Input Pin V8.
56, 58, 60, V8GND All analog input AGND pins should connect to the AGND plane of a system.
62, 64
1
P = power supply, DI = digital input, DO = digital output, REF = reference input/output, AI = analog input, GND = ground.

Rev. D | Page 13 of 32
AD7607 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

0 0.5
AVCC = VDRIVE = 5V AVCC = VDRIVE = 5V
INTERNAL REFERENCE 0.4 INTERNAL REFERENCE
–20 fSAMPLE = 200kSPS fSAMPLE = 200kSPS
TA = 25°C 0.3 TA = 25°C
–40 ±10V RANGE ±10V RANGE
SNR: 85.07dB
THD: –107.33dB 0.2
–60 16,384 POINT FFT
fIN = 1kHz 0.1

DNL (LSB)
SNR (dB)

–80 0

–100 –0.1

–0.2
–120
–0.3
–140
–0.4

–160 –0.5

08096-020
0 10 20 30 40 50 60 70 80 90 100

08096-018
0 2000 4000 6000 8000 10,000 12,000 14,000 16,000
INPUT FREQUENCY (kHz) CODE

Figure 9. FFT ± 10 V Range Figure 12. Typical DNL ± 10 V Range

0 0.5
AVCC = VDRIVE = 5V AVCC = VDRIVE = 5V
INTERNAL REFERENCE 0.4 INTERNAL REFERENCE
–20 fSAMPLE = 200kSPS fSAMPLE = 200kSPS
TA = 25°C 0.3 TA = 25°C
–40 ±5V RANGE ±5V RANGE
SNR: 84.82dB 0.2
THD: –107.51dB
–60 16,384 POINT FFT
fIN = 1kHz 0.1
INL (LSB)
SNR (dB)

–80 0

–0.1
–100
–0.2
–120
–0.3
–140
–0.4

–160 –0.5

08096-010
0 10 20 30 40 50 60 70 80 90 100
08096-017

0 2000 4000 6000 8000 10,000 12,000 14,000 16,000

INPUT FEQUENCY (kHz) CODE

Figure 10. FFT Plot ± 5 V Range Figure 13. Typical INL ± 5 V Range

0.5 0.5
AVCC = VDRIVE = 5V AVCC = VDRIVE = 5V
0.4 INTERNAL REFERENCE 0.4 INTERNAL REFERENCE
fSAMPLE = 200kSPS fSAMPLE = 200kSPS
TA = 25°C TA = 25°C
0.3 0.3
±10V RANGE ±5V RANGE
0.2 0.2

0.1 0.1
DNL (LSB)
INL (LSB)

0 0

–0.1 –0.1

–0.2 –0.2

–0.3 –0.3

–0.4 –0.4

–0.5 –0.5
08096-009
08096-019

0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000
CODE CODE

Figure 11. Typical INL ± 10 V Range Figure 14. Typical DNL ± 5 V Range

Rev. D | Page 14 of 32
Data Sheet AD7607
5.00 10

3.75
8
2.50

PFS/NFS ERROR (%FS)

±10V RANGE
NFS ERROR (LSB)

6
1.25
±5V RANGE
0 4

–1.25
2 AVCC, VDRIVE = 5V
FSAMPLE = 200 kSPS
–2.50 TA = 25°C
0 EXTERNAL REFERENCE
–3.75 200kSPS SOURCE RESISTANCE IS MATCHED ON
AVCC, VDRIVE = 5V THE VxGND INPUT
EXTERNAL REFERENCE ±10V AND ±5V RANGE
–5.00 –2

08096-115

08096-118
–40 –25 –10 5 20 35 50 65 80 0 20k 40k 60k 80k 100k 120k
TEMPERATURE (°C) SOURCE RESISTANCE (Ω)

Figure 15. NFS Error vs. Temperature Figure 18. PFS and NFS Error vs. Source Resistance

5.00 86

3.75
85
2.50
PFS ERROR (LSB)

84
1.25

SNR (dB)
0 83
±5V RANGE
–1.25
±10V RANGE 82
AVCC = VDRIVE = 5V
–2.50 INTERNAL REFERENCE
81
fSAMPLE = 200kSPS
–3.75 200kSPS TA = 25°C
AVCC, VDRIVE = 5V ±5V RANGE
EXTERNAL REFERENCE ALL 8 CHANNELS
–5.00 80

08096-022
08096-116

–40 –25 –10 5 20 35 50 65 80 10 100 1k 10k 100k

TEMPERATURE (°C) INPUT FREQUENCY (Hz)

Figure 16. PFS Error vs. Temperature Figure 19. SNR vs. Input Frequency ± 5 V Range

86
2.5

2.0
85
NFS/PFS CHANNEL MATCHING (LSB)

PFS ERROR
1.5

1.0 84
NFS ERROR
SNR (dB)

0.5
83
0

–0.5
82
–1.0 AVCC = VDRIVE = 5V
INTERNAL REFERENCE
fSAMPLE = 200kSPS
–1.5 81 TA = 25°C
10V RANGE ±10V RANGE
–2.0 AVCC, VDRIVE = 5V ALL 8 CHANNELS
EXTERNAL REFERENCE 80
08096-023

–2.5 10 100 1k 10k 100k

08096-117

–40 –25 –10 5 20 35 50 65 80

INPUT FREQUENCY (Hz)
TEMPERATURE (°C)

Figure 17. PFS and NFS Error Matching vs. Temperature Figure 20. SNR vs. Input Frequency ± 10 V Range

Rev. D | Page 15 of 32
AD7607 Data Sheet
0.25 –40
±5V RANGE
0.20 AVCC, VDRIVE = +5V
–50 fSAMPLE = 200kSPS
BIPOLAR ZERO CODE ERROR (LSB)

0.15 RSOURCE MATCHED ON Vx AND VxGND INPUTS

–60
0.10
–70
0.05

THD (dB)
0 –80
5V RANGE
–0.05 105kΩ
–90 48.7kΩ
–0.10 23.7kΩ
10V RANGE –100 10kΩ
–0.15 5kΩ
1.2kΩ
200kSPS –110 100Ω
–0.20 AVCC, VDRIVE = 5V 51Ω
EXTERNAL REFERENCE 0Ω
–0.25 –120

08096-122
08096-119
–40 –25 –10 5 20 35 50 65 80 1k 10k 100k
TEMPERATURE (°C) INPUT FREQUENCY (Hz)

Figure 21. Bipolar Zero Code Error vs. Temperature Figure 24. THD vs. Input Frequency for Various Source Impedances,
±5 V Range

1.00 2.5010
BIPOLAR ZERO CODE ERROR MATCHING (LSB)

0.75
2.5005 AVCC = 5.25V
5V RANGE AVCC = 5V
0.50
REFOUT VOLTAGE (V) 2.5000
0.25
10V RANGE
0 2.4995
AVCC = 4.75V
–0.25
2.4990

–0.50
2.4985
–0.75 200kSPS
AVCC, VDRIVE = 5V
EXTERNAL REFERENCE
–1.00 2.4980

08096-125
08096-120

–40 –25 –10 5 20 35 50 65 80 –40 –25 –10 5 20 35 50 65 80

TEMPERATURE (°C) TEMPERATURE (°C)

Figure 22. Bipolar Zero Code Error Matching vs. Temperature Figure 25. Reference Output Voltage vs. Temperature for
Different Supply Voltages
–40 8
±10V RANGE AVCC, VDRIVE = 5V
AVCC, VDRIVE = +5V fSAMPLE = 200kSPS
–50 fSAMPLE = 200kSPS 6
RSOURCE MATCHED ON Vx AND VxGND INPUTS
4
–60
INPUT CURRENT (µA)

2
–70
THD (dB)

0
–80
–2
105kΩ
–90 48.7kΩ –4
23.7kΩ
–100 10kΩ
5kΩ –6
1.2kΩ
–110 100Ω +85°C
–8 +25°C
51Ω
0Ω –40°C
–120 –10
08096-126
08096-121

1k 10k 100k –10 –8 –6 –4 –2 0 2 4 6 8 10

INPUT FREQUENCY (Hz) INPUT VOLTAGE (V)

Figure 23. THD vs. Input Frequency for Various Source Impedances, Figure 26. Analog Input Current vs. Input Voltage for Various Temperatures
±10 V Range

Rev. D | Page 16 of 32
Data Sheet AD7607
22 –50
AVCC, VDRIVE = 5V
INTERNAL REFERENCE

CHANNEL-TO-CHANNEL ISOLATION (dB)

–60
20 AD7607 RECOMMENDED DECOUPLING USED
fSAMPLE = 150kSPS
AVCC SUPPLY CURRENT (mA)

–70 TA = 25°C
18 INTERFERER ON ALL UNSELECTED CHANNELS
–80

16 –90
±10V RANGE

14 –100
±5V RANGE
–110
12
AVCC, VDRIVE = 5V –120
10 TA = 25°C
INTERNAL REFERENCE –130
fSAMPLE VARIES WITH OS RATE
8 –140

08096-127

08096-129
NO OS OS2 OS4 OS8 OS16 OS32 OS64 0 20 40 60 80 100 120 140 160
OVERSAMPLING RATIO NOISE FREQUENCY (kHz)

Figure 27. Supply Current vs. Oversampling Rate Figure 29. Channel-to-Channel Isolation
140
POWER SUPPLY REJECTION RATIO (dB)

130

120
±10V RANGE
110
±5V RANGE
100

90

80 AVCC, VDRIVE = 5V
INTERNAL REFERENCE
AD7607 RECOMMENDED DECOUPLING USED
70
fSAMPLE = 200kSPS
TA = 25°C
60
08096-128

0 100 200 300 400 500 600 700 800 900 1000 1100
AVCC NOISE FREQUENCY (kHz)

Figure 28. PSRR

Rev. D | Page 17 of 32
AD7607 Data Sheet

TERMINOLOGY
Integral Nonlinearity Total Harmonic Distortion (THD)
The maximum deviation from a straight line passing through The ratio of the rms sum of the harmonics to the fundamental.
the endpoints of the ADC transfer function. The endpoints of For the AD7607, it is defined as
the transfer function are zero scale, at ½ LSB below the first THD (dB) =
code transition; and full scale, at ½ LSB above the last code
V2 2 + V32 + V4 2 + V5 2 + V6 2 + V72 + V82 + V92
transition. 20log
V1
Differential Nonlinearity
The difference between the measured and the ideal 1 LSB where:
change between any two adjacent codes in the ADC. V1 is the rms amplitude of the fundamental.
V2 to V9 are the rms amplitudes of the second through ninth
Bipolar Zero Code Error
harmonics.
The deviation of the midscale transition (all 1s to all 0s) from
the ideal, which is 0 V – ½ LSB. Peak Harmonic or Spurious Noise
The ratio of the rms value of the next largest component in the
Bipolar Zero Code Error Match
ADC output spectrum (up to fS/2, excluding dc) to the rms value
The absolute difference in bipolar zero code error between any
of the fundamental. Normally, the value of this specification is
two input channels.
determined by the largest harmonic in the spectrum, but for
Positive Full-Scale Error ADCs where the harmonics are buried in the noise floor, it is
The deviation of the actual last code transition from the ideal determined by a noise peak.
last code transition (10 V − 1½ LSB (9.998) and 5 V − 1½ LSB Intermodulation Distortion
(4.99908)) after bipolar zero code error is adjusted out. The With inputs consisting of sine waves at two frequencies, fa and fb,
positive full-scale error includes the contribution from the any active device with nonlinearities create distortion products
internal reference buffer. at sum and difference frequencies of mfa ± nfb, where m, n = 0,
Positive Full-Scale Error Match 1, 2, 3. Intermodulation distortion terms are those for which
The absolute difference in positive full-scale error between any neither m nor n is equal to 0. For example, the second-order
two input channels. terms include (fa + fb) and (fa − fb), and the third-order terms
include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).
Negative Full-Scale Error
The calculation of the intermodulation distortion is per the THD
The deviation of the first code transition from the ideal first
specification, where it is the ratio of the rms sum of the individual
code transition (−10 V + ½ LSB (−9.9993) and −5 V + ½ LSB
distortion products to the rms amplitude of the sum of the
(−4.99969)) after the bipolar zero code error is adjusted out.
fundamentals expressed in decibels (dB).
The negative full-scale error includes the contribution from
the internal reference buffer. Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but not
Negative Full-Scale Error Match
the linearity of the converter. PSR is the maximum change in
The absolute difference in negative full-scale error between any
full-scale transition point due to a change in power supply voltage
two input channels.
from the nominal value. The PSR ratio (PSRR) is defined as the
Signal-to-(Noise + Distortion) Ratio ratio of the power in the ADC output at full-scale frequency, f,
The measured ratio of signal-to-(noise + distortion) at the to the power of a 200 mV p-p sine wave applied to the ADC’s
output of the ADC. The signal is the rms amplitude of the VDD and VSS supplies of frequency, fS.
fundamental. Noise is the sum of all nonfundamental signals
PSRR (dB) = 10log (Pf/PfS)
up to half the sampling frequency (fS/2, excluding dc).
where:
The ratio depends on the number of quantization levels in
Pf is equal to the power at Frequency f in the ADC output.
the digitization process: the more levels, the smaller the
PfS is equal to the power at Frequency fS coupled onto the AVCC
quantization noise.
supplies.
The theoretical signal-to-(noise + distortion) ratio for an ideal
Channel-to-Channel Isolation
N-bit converter with a sine wave input is given by
Channel-to-channel isolation is a measure of the level of crosstalk
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB between any two channels. It is measured by applying a full-scale
Thus, for a 14-bit converter, the signal-to-(noise + distortion) sine wave signal of up to 160 kHz to all unselected input channels,
is 86.04 dB. and then determining the degree to which the signal attenuates
in the selected channel with a 1 kHz sine wave signal applied (see
Figure 29).

Rev. D | Page 18 of 32
Data Sheet AD7607

THEORY OF OPERATION
CONVERTER DETAILS Analog Input Clamp Protection
The AD7607 is a data acquisition system that employs a high Figure 30 shows the analog input structure of the AD7607.
speed, low power, charge redistribution, successive approxi- Each AD7607 analog input contains clamp protection circuitry.
mation analog-to-digital converter (ADC) and allows the Despite single 5 V supply operation, this analog input clamp
simultaneous sampling of eight analog input channels. The analog protection allows for an input overvoltage of up to ±16.5 V.
inputs on the AD7607 can accept true bipolar input signals. The RFB

RANGE pin is used to select either ±10 V or ±5 V as the input 1MΩ

Vx CLAMP
range. The AD7607 operates from a single 5 V supply.
1MΩ
VxGND CLAMP
The AD7607 contains input clamp protection, input signal scaling

08096-032
SECOND-
ORDER
amplifiers, a second-order antialiasing filter, track-and-hold RFB LPF
amplifiers, an on-chip reference, reference buffers, a high speed Figure 30. Analog Input Circuitry
ADC, a digital filter, and high speed parallel and serial interfaces.
Sampling on the AD7607 is controlled using the CONVST signals. Figure 31 shows the voltage vs. current characteristic of the
clamp circuit. For input voltages of up to ±16.5 V, no current
ANALOG INPUT flows in the clamp circuit. For input voltages that are above ±16.5 V,
Analog Input Ranges the AD7607 clamp circuitry turns on and clamps the analog
The AD7607 can handle true bipolar input voltages. The logic input to ±16.5 V.
level on the RANGE pin determines the analog input range of AV , VDRIVE = 5V
30 T CC
all analog input channels. If this pin is tied to a logic high, the A = 25°C

analog input range is ±10 V for all channels. If this pin is tied INPUT CLAMP CURRENT (mA)
20
to a logic low, the analog input range is ±5 V for all channels.
10
A logic change on this pin has an immediate effect on the analog
input range; however, there is a typical settling time of ~80 μs, 0

in addition to the normal acquisition time requirement. –10

Recommended practice is to hardwire the RANGE pin
–20
according to the desired input range for the system signals.
–30
During normal operation, the applied analog input voltage should
remain within the analog input range selected via the range pin. –40

A RESET pulse must be applied after power-up to ensure the –50

08096-051
analog input channels are configured for the range selected. –20 –15 –10 –5 0 5 10 15 20
SOURCE VOLTAGE (V)
When in a power-down mode, it is recommended to tie the Figure 31. Input Protection Clamp Profile
analog inputs to GND. As per the Analog Input Clamp
Protection section, the overvoltage clamp protection is A series resistor should be placed on the analog input channels
recommended for use in transient overvoltage conditions and to limit the current to ±10 mA for input voltages above ±16.5 V.
should not remain active for extended periods. Stressing the In an application where there is a series resistance on an analog
analog inputs outside of the conditions mentioned here may input channel, Vx, a corresponding resistance is required on the
degrade the Bipolar Zero Code error and THD performance of analog input GND channel, VxGND (see Figure 32). If there is
the AD7607. no corresponding resistor on the VxGND channel, an offset
error occurs on that channel.
Analog Input Impedance
RFB
The analog input impedance of the AD7607 is 1 MΩ. This is AD7607
a fixed input impedance that does not vary with the AD7607 ANALOG R VINx 1MΩ
INPUT CLAMP
SIGNAL
sampling frequency. This high analog input impedance elimi- R C VxGND 1MΩ
CLAMP
nates the need for a driver amplifier in front of the AD7607,
08096-032

allowing for direct connection to the source or sensor. With the RFB
need for a driver amplifier eliminated, bipolar supplies (which
are often a source of noise in a system) can be removed from Figure 32. Input Resistance Matching on the Analog Input
the signal chain.

Rev. D | Page 19 of 32
AD7607 Data Sheet
Analog Input Antialiasing Filter The end of the conversion process across all eight channels is
An analog antialiasing filter (a second-order Butterworth) is indicated by the falling edge of BUSY, and it is at this point that the
also provided on the AD7607. Figure 33 and Figure 34 show track-and-holds return to track mode and the acquisition time
the frequency and phase response, respectively, of the analog for the next set of conversions begins.
antialiasing filter. In the ±5 V range, the −3 dB frequency is The conversion clock for the part is internally generated, and
typically 15 kHz. In the ±10 V range, the −3 dB frequency is the conversion time for all channels is 4 μs. On the AD7607, the
typically 23 kHz. BUSY signal returns low after all eight conversions to indicate the
5 end of the conversion process. On the falling edge of BUSY, the
0
track-and-hold amplifiers return to track mode. New data can
±10V RANGE
AV , V = 5V
be read from the output register via the parallel, parallel byte, or
–5 f CC DRIVE
SAMPLE = 200kSPS
±5V RANGE serial interface after BUSY goes low; or, alternatively, data from
TA = 25°C
ATTENUATION (dB)

–10 the previous conversion can be read while BUSY is high. Reading
–15 data from the AD7607 while a conversion is in progress has little
effect on performance and allows a faster throughput to be
–20 ±10V RANGE 0.1dB 3dB
–40 10,303 24,365Hz
achieved. In parallel mode at VDRIVE > 3.3 V, the SNR is reduced
–25 +25 9619 23,389Hz by ~1.5 dB when reading during a conversion.
+85 9326 22,607Hz
–30
±5V RANGE 0.1dB 3dB ADC TRANSFER FUNCTION
–40 5225 16,162Hz
–35 +25 5225 15,478Hz The output coding of the AD7607 is twos complement. The
+85 4932 14,990Hz
–40 designed code transitions occur midway between successive
08096-053

100 1k 10k 100k

integer LSB values, that is, 1/2 LSB, 3/2 LSB. The LSB size is
INPUT FREQUENCY (Hz)
FSR/16,384. The ideal transfer characteristic is shown in Figure 35.
Figure 33. Analog Antialiasing Filter Frequency Response
VIN REF
±10V CODE = × 8192 ×
10V 2.5V
VIN REF
18 ±5V CODE = × 8192 ×
5V 2.5V
16 011...111
±5V RANGE 011...110
14
ADC CODE

12 +FS – (–FS)
000...001 LSB =
000...000 214
10 ±10V RANGE
PHASE DELAY (µs)

111...111
8
6 100...010
4 100...001
100...000
2 –FS + 1/2LSB 0V – 1LSB +FS – 3/2LSB
0 ANALOG INPUT

–2 +FS MIDSCALE –FS LSB

08096-035
–4 AVCC, VDRIVE = 5V ±10V RANGE +10V 0V –10V 1.22mV
f = 200kSPS ±5V RANGE +5V 0V –5V 610µV
–6 SAMPLE
TA = 25°C
–8 Figure 35. Transfer Characteristics
08096-052

10 1k 10k 100k
INPUT FREQUENCY (Hz) The LSB size is dependent on the analog input range selected.
Figure 34. Analog Antialiasing Filter Phase Response

Track-and-Hold Amplifiers
The track-and-hold amplifiers on the AD7607 let the ADC
accurately acquire an input sine wave of full-scale amplitude to
14-bit resolution. The track-and-hold amplifiers sample their
respective inputs simultaneously on the rising edge of CONVST x.
The aperture time for the track-and-hold (that is, the delay time
between the external CONVST x signal and the track-and-hold
actually going into hold) is well matched, by design, across all eight
track-and-holds on one device and from device to device. This
matching allows more than one AD7607 device to be sampled
simultaneously in a system.

Rev. D | Page 20 of 32
Data Sheet AD7607
INTERNAL/EXTERNAL REFERENCE Internal Reference Mode
The AD7607 contains an on-chip 2.5 V band gap reference. The One AD7607 device, configured to operate in the internal
REFIN/REFOUT pin allows access to the 2.5 V reference that reference mode, can be used to drive the remaining AD7607
generates the on-chip 4.5 V reference internally, or it allows devices, which are configured to operate in external reference
an external reference of 2.5 V to be applied to the AD7607. An mode (see Figure 38). The REFIN/REFOUT pin of the AD7607,
externally applied reference of 2.5 V is also gained up to 4.5 V, using configured in internal reference mode, should be decoupled
the internal buffer. This 4.5 V buffered reference is the reference using a 10 μF ceramic decoupling capacitor. The other AD7607
used by the SAR ADC. devices, configured in external reference mode, should use a
100 nF decoupling capacitor on their REFIN/REFOUT pins.
The REF SELECT pin is a logic input pin that allows the user to
select between the internal reference or an external reference. REFIN/REFOUT

If this pin is set to logic high, the internal reference is selected SAR
and enabled. If this pin is set to logic low, the internal reference BUF
REFCAPB

is disabled and an external reference voltage must be applied 10µF

to the REFIN/REFOUT pin. The internal reference buffer is REFCAPA

always enabled. After a reset, the AD7607 operates in the 2.5V

REF

08096-036
reference mode selected by the REF SELECT pin. Decoupling is
required on the REFIN/REFOUT pin for both the internal and
external reference options. A 10 μF ceramic capacitor is Figure 36. Reference Circuitry
required on the REFIN/REFOUT pin.
The AD7607 contains a reference buffer configured to gain the AD7607 AD7607 AD7607
REF voltage up to ~4.5 V, as shown in Figure 36. The REFCAPA REF SELECT REF SELECT REF SELECT
and REFCAPB pins must be shorted together externally, and REFIN/REFOUT REFIN/REFOUT REFIN/REFOUT
a ceramic capacitor of 10 μF applied to REFGND, to ensure that
the reference buffer is in closed-loop operation. The reference 100nF 100nF 100nF

voltage available at the REFIN/REFOUT pin is 2.5 V.

ADR421

08096-038
When the AD7607 is configured in external reference mode, 0.1µF

the REFIN/REFOUT pin is a high input impedance pin. For Figure 37. Single External Reference Driving Multiple AD7607 REFIN Pins
applications using multiple AD7607 devices, the following
configurations are recommended, depending on the application
requirements. VDRIVE

External Reference Mode AD7607 AD7607 AD7607

REF SELECT REF SELECT REF SELECT
One ADR421 external reference can be used to drive the
REFIN/REFOUT REFIN/REFOUT REFIN/REFOUT
REFIN/REFOUT pins of all AD7607 devices (see Figure 37).
In this configuration, each REFIN/REFOUT pin of the AD7607 +
10µF 100nF 100nF
should be decoupled with a 100 nF decoupling capacitor.

08096-037
Figure 38. Internal Reference Driving Multiple AD7607 REFIN Pins.

Rev. D | Page 21 of 32
AD7607 Data Sheet
TYPICAL CONNECTION DIAGRAM The power-down mode is selected through the state of the RANGE
Figure 39 shows the typical connection diagram for the AD7607. pin when the STBY pin is low. Table 7 shows the configurations
There are four AVCC supply pins on the part, and each of the required to choose the desired power-down mode. When the
four pins should be decoupled using a 100 nF capacitor at each AD7607 is placed in standby mode, current consumption is 8 mA
supply pin and a 10 µF capacitor at the supply source. The AD7607 maximum and power-up time is approximately 100 µs because
can operate with the internal reference or an externally applied the capacitor on the REFCAPA and REFCAPB pins must charge
reference. In this configuration, the AD7607 is configured to up. In standby mode, the on-chip reference and regulators
operate with the internal reference. When using a single AD7607 remain powered up, and the amplifiers and ADC core are
device on the board, the REFIN/REFOUT pin should be decoupled powered down.
with a 10 µF capacitor. When using an application with multiple When the AD7607 is placed in shutdown mode, current
AD7607 devices, refer to the Internal/External Reference section. consumption is 6 µA maximum and power-up time is
The REFCAPA and REFCAPB pins are shorted together and approximately 13 ms (external reference mode). In shutdown
decoupled with a 10 µF ceramic capacitor. mode, all circuitry is powered down. When the AD7607 is
The VDRIVE supply is connected to the same supply as the powered up from shutdown mode, a RESET signal must be
processor. The VDRIVE voltage controls the voltage value of the applied to the AD7607 after the required power-up time has
output logic signals. For layout, decoupling, and grounding elapsed.
hints, see the Layout Guidelines section. Table 7. Power-Down Mode Selection
POWER-DOWN MODES Power-Down Mode STBY RANGE
Two power-down modes are available on the AD7607: standby Standby 0 1
mode and shutdown mode. The STBY pin controls whether Shutdown 0 0
the AD7607 is in normal mode or in one of the two power-
down modes.
ANALOG SUPPLY DIGITAL SUPPLY
VOLTAGE 5V1 VOLTAGE +2.3V TO +5V

+
10µF 1µF 100nF
100nF

REFIN/REFOUT REGCAP2 AVCC VDRIVE

MICROPROCESSOR/
MICROCONVERTER/
REFCAPA
PARALLEL
+ DB0 TO DB15 INTERFACE
10µF
DSP

REFCAPB
REFGND CONVST A, CONVST B
CS
V1
RD
V1GND
V2 AD7607 BUSY
V2GND RESET
V3
V3GND OS 2
OS 1 OVERSAMPLING
V4 OS 0
EIGHT ANALOG V4GND
INPUTS V1 TO V8 V5 REF SELECT VDRIVE
V5GND
V6 PAR/SER SEL
V6GND
V7 RANGE
V7GND VDRIVE
STBY
V8
V8GND AGND

1DECOUPLING SHOWN ON THE AV

CC PIN APPLIES TO EACH AVCC PIN (PIN 1, PIN 37, PIN 38, PIN 48).
08096-039

DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV CC PIN 37 AND PIN 38.

2DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39).

Figure 39. Typical Connection Diagram

Rev. D | Page 22 of 32
Data Sheet AD7607
CONVERSION CONTROL This is accomplished by pulsing the two CONVST pins
Simultaneous Sampling on All Analog Input Channels independently and is possible only if oversampling is not in
use. CONVST A is used to initiate simultaneous sampling of
The AD7607 allows simultaneous sampling of all analog input
the first set of channels (V1 to V4), and CONVST B is used
channels. All channels are sampled simultaneously when both
to initiate simultaneous sampling on the second set of analog
CONVST pins (CONVST A, CONVST B) are tied together. A
input channels (V5 to V8), as illustrated in Figure 40.
single CONVST signal is used to control both CONVST x inputs.
The rising edge of this common CONVST signal initiates On the rising edge of CONVST A, the track-and-hold
simultaneous sampling on all analog input channels. amplifiers for the first set of channels are placed into hold
mode. On the rising edge of CONVST B, the track-and-hold
The AD7607 contains an on-chip oscillator that is used to
amplifiers for the second set of channels are placed into hold
perform the conversions. The conversion time for all ADC
mode. The conversion process begins when both rising edges
channels is tCONV. The BUSY signal indicates to the user when
of CONVST x have occurred; therefore, BUSY goes high on the
conversions are in progress, so when the rising edge of CONVST
rising edge of the later CONVST x signal. In Table 3, Time t5
is applied, BUSY goes logic high and transitions low at the end
indicates the maximum allowable time between CONVST x
of the entire conversion process. The falling edge of the BUSY
sampling points.
signal is used to place all eight track-and-hold amplifiers back
into track mode. The falling edge of BUSY also indicates that There is no change to the data read process when using two
the new data can now be read from the parallel bus (DB[15:0]), separate CONVST x signals.
the DOUTA and DOUTB serial data lines, or the parallel byte bus Connect all unused analog input channels to AGND. The results
(DB[7:0]). for any unused channels are still included in the data read because
Simultaneously Sampling Two Sets of Channels all channels are always converted.
The AD7607 also allows the analog input channels to be sampled
simultaneously in two sets. This can be used in power-line
protection and measurement systems to compensate for phase
differences between current and voltage sensors. In a 50 Hz
system, this allows for up to 9° of phase compensation; and in a
60 Hz system, it allows for up to 10° of phase compensation.

V1 TO V4 TRACK-AND-HOLD
ENTER HOLD
V5 TO V8 TRACK-AND-HOLD
ENTER HOLD

CONVST A
t5

CONVST B
AD7607 CONVERTS
ON ALL 8 CHANNELS
BUSY
tCONV

CS/RD

DATA: DB[15:0] V1 V2 V3 V7 V8
08096-040

FRSTDATA

Figure 40. Simultaneous Sampling on Channel Sets While Using Independent CONVST A and CONVST B Signals—Parallel Interface Mode

Rev. D | Page 23 of 32
AD7607 Data Sheet

DIGITAL INTERFACE
The AD7607 provides three interface options: a parallel inter- When there is only one AD7607 in a system/board and it does not
face, a high speed serial interface, and a parallel byte interface. share the parallel bus, data can be read using just one control
The required interface mode is selected via the PAR/SER/BYTE signal from the digital host. The CS and RD signals can be tied
SEL and the DB15/BYTE SEL pins. together, as shown in Figure 5. In this case, the data bus comes
out of three-state on the falling edge of CS/RD. The combined CS
Table 8. Interface Mode Selection
and RD signal allows the data to be clocked out of the AD7607
PAR/SER/BYTE SEL DB15 Interface Mode
and to be read by the digital host. In this case, CS is used to
0 0 Parallel interface mode
frame the data transfer of each data channel.
1 0 Serial interface mode
1 1 Parallel byte interface mode PARALLEL BYTE INTERFACE (PAR/SER/BYTE SEL = 1,
Interface mode operation is discussed in the following sections.
DB15 = 1)
Parallel byte interface mode operates much like the parallel
PARALLEL INTERFACE (PAR/SER/BYTE SEL = 0) interface mode, except that each channel conversion result is read
Data can be read from the AD7607 via the parallel data bus with out in two 8-bit transfers. Therefore, 16 RD pulses are required to
standard CS and RD signals. To read the data over the parallel bus, read all eight conversion results from the AD7607. To configure
the PAR/SER/BYTE SEL pin should be tied low. The CS and RD the AD7607 to operate in parallel byte interface mode, the PAR/
input signals are internally gated to enable the conversion result SER/BYTE SEL and BYTE SEL/DB15 pins should be tied to logic
onto the data bus. The data lines, DB15 to DB0, leave their high high (see Table 8). DB[7:0] are used to transfer the data to the
impedance state when both CS and RD are logic low. When CS digital host. DB0 is the LSB of the data transfer, and DB7 is the
and RD are low, DB15 and DB14 are used to output a sign MSB of the data transfer. In parallel byte mode, DB14 acts as an
extended bit of the MSB (DB13) of the conversion result. HBEN pin. When the DB14/HBEN pin is tied to logic high, the
most significant byte (MSB) of the conversion result is output
AD7607
INTERRUPT
first, followed by the LSB byte of the conversion result. When
BUSY 14 DB14/HBEN is tied to logic low, the LSB byte of the conversion
CS 13 result is output first, followed by the MSB byte of the conversion
RD 12 DIGITAL
result. The FRSTDATA pin remains high until the entire 14 bits
08096-041

HOST
DB[15:0] 33:16
of the conversion result from V1 is read. If the MSB byte is always
Figure 41. Interface Diagram—One AD7607 Using the Parallel Bus, to be read first, the HBEN pin should be set high and remain
with CS and RD Shorted Together high. If the LSB byte is always to be read first, the HBEN pin
should be set low and remain low. In this circumstance, the
The rising edge of the CS input signal tristates the bus, and the
MSB byte contains two sign extended bits in the two MSB
falling edge of the CS input signal takes the bus out of the high positions.
impedance state. CS is the control signal that enables the data
lines; it is the function that allows multiple AD7607 devices to SERIAL INTERFACE (PAR/SER/BYTE SEL = 1)
share the same parallel data bus. To read data back from the AD7607 over the serial interface,
The CS signal can be permanently tied low, and the RD signal the PAR/SER/BYTE SEL pin must be tied high. The CS and
can be used to access the conversion results as shown in Figure 4. SCLK signals are used to transfer data from the AD7607. The
A read operation of new data can take place after the BUSY AD7607 has two serial data output pins, DOUTA and DOUTB.
signal goes low (see Figure 2); or, alternatively, a read operation Data can be read back from the AD7607 using one or both of
of data from the previous conversion process can take place these DOUT lines. For the AD7607, conversion results from
while BUSY is high (see Figure 3). Channel V1 to Channel V4 first appear on DOUTA, and
conversion results from Channel V5 to Channel V8 first appear
The RD pin is used to read data from the output conversion results on DOUTB.
register. Applying a sequence of RD pulses to the RD pin of the
The CS falling edge takes the data output lines, DOUTA and DOUTB,
AD7607 clocks the conversion results out from each channel
out of three-state and clocks out the MSB of the conversion result.
onto the parallel output bus, DB[15:0], in ascending order.
The rising edge of SCLK clocks all subsequent data bits onto the
The first RD falling edge after BUSY goes low clocks out the
serial data outputs, DOUTA and DOUTB. The CS input can be held
conversion result from Channel V1. The next RD falling edge
low for the entire serial read, or it can be pulsed to frame each
updates the bus with the V2 conversion result, and so on. The
channel read of 14 SCLK cycles.
eighth falling edge of RD clocks out the conversion result for
Channel V8. When the RD signal is logic low, it enables the data
conversion result from each channel to be transferred to the
digital host (DSP, FPGA).
Rev. D | Page 24 of 32
Data Sheet AD7607
Figure 42 shows a read of eight simultaneous conversion results The subsequent 13 data bits are clocked out of the AD7607 on the
using two DOUT lines on the AD7607. In this case, a 56 SCLK SCLK rising edge. Data is valid on the SCLK falling edge. To access
transfer is used to access data from the AD7607, and CS is held each conversion result, 14 clock cycles must be provided.
low to frame the entire 56 SCLK cycles. Data can also be clocked The FRSTDATA output signal indicates when the first channel,
out using just one DOUT line; in which case, it is recommended V1, is being read back. When the CS input is high, the FRSTDATA
that DOUTA be used to access all conversion data because the output pin is in three-state. In serial mode, the falling edge of CS
channel data is output in ascending order. For the AD7607 to
takes FRSTDATA out of three-state and sets the FRSTDATA pin
access all eight conversion results on one DOUT line, a total of
high, indicating that the result from V1 is available on the DOUTA
112 SCLK cycles are required. These 112 SCLK cycles can be
output data line. The FRSTDATA output returns to a logic low
framed by one CS signal, or each group of 14 SCLK cycles can be following the 14th SCLK falling edge. If all channels are read on
individually framed by the CS signal. The disadvantage of using DOUTB, the FRSTDATA output does not go high when V1 is output
just one DOUT line is that the throughput rate is reduced if reading on this serial data output pin. It goes high only when V1 is available
occurs after conversion. The unused DOUT line should be left on DOUTA (and this is when V5 is available on DOUTB).
unconnected in serial mode. If DOUTB is to be used as a single
DOUT line, the channel results are output in the following order: READING DURING CONVERSION
V5, V6, V7, V8, V1, V2, V3, and V4; however, the FRSTDATA Data can be read from the AD7607 while BUSY is high and the
indicator returns low after V5 is read on DOUTB. conversions are in progress. This has little effect the performance
Figure 6 shows the timing diagram for reading one channel of of the converter, and it allows a faster throughput rate to be
achieved. A parallel, parallel byte, or serial read can be performed
data, framed by the CS signal, from the AD7607 in serial mode.
during conversions and when oversampling is or is not enabled.
The SCLK input signal provides the clock source for the serial
Figure 3 shows the timing diagram for reading while BUSY is
read operation. The CS goes low to access the data from the
high in parallel or serial mode. Reading during conversions
AD7607. The falling edge of CS takes the bus out of three-state
allows the full throughput rate to be achieved when using the
and clocks out the MSB of the 14-bit conversion result. This serial interface with VDRIVE above 3.3 V.
MSB is valid on the first falling edge of the SCLK after the CS
falling edge. Data can be read from the AD7607 at any time other than on
the falling edge of BUSY because this is when the output data
registers get updated with the new conversion data. Time t6, as
outlined in Table 3, should be observed in this condition.

CS

56
SCLK

DOUTA V1 V2 V3 V4
08096-042

DOUTB
V5 V6 V7 V8

Figure 42. Serial Interface with Two DOUT Lines

Rev. D | Page 25 of 32
AD7607 Data Sheet
DIGITAL FILTER different oversample rates. The OS pins are latched on the falling
The AD7607 contains an optional first-order digital sinc filter that edge of BUSY. This sets the oversampling rate for the next
should be used in applications where slower throughput rates are conversion (see Figure 43).
used and digital filtering is required. The oversampling ratio of Selection of the oversampling mode has the effect of adding
the digital filter is controlled using the oversampling pins, OS[2:0] a digital filter function after the ADC. The different oversampling
(see Table 9). OS 2 is the MSB control bit, and OS 0 is the LSB rates and the CONVST x sampling frequency produce different
control bit. Table 9 lists the oversampling bit decoding to select the digital filter frequency profiles.

Table 9. Oversample Bit Decoding

Maximum Throughput,
OS[2:0] Oversampling Ratio 3 dB BW, 5 V Range (kHz) 3 dB BW, 10 V Range (kHz) CONVST Frequency (kHz)
000 No oversampling 15 22 200
001 2 15 22 100
010 4 13.7 18.5 50
011 8 10.3 11.9 25
100 16 6 6 12.5
101 32 3 3 6.25
110 64 1.5 1.5 3.125
111 Invalid

CONVST A
AND
CONVST B
OVERSAMPLE RATE
LATCHED FOR CONVERSION N + 1
CONVERSION N CONVERSION N + 1

BUSY

tOS_HOLD
tOS_SETUP

08096-043
OS x

Figure 43. OS x Pin Timing

Rev. D | Page 26 of 32
Data Sheet AD7607
0
Figure 44 to Figure 49 show the digital filter frequency profiles for
the different oversampling ratios. The combination of the analog –10

antialiasing filter and the oversampling digital filter helps to reduce –20
the complexity of the design of the filter before the AD7607. The

ATTENUATION (dB)
–30
digital filtering combines steep roll-off and linear phase response.
0 –40

–10 –50

–20 –60
ATTENUATION (dB)

–30 –70
AVCC = VDRIVE = 5V
TA = 25°C
–40 –80
±10V RANGE
OS BY 16
–50 –90

08096-014
100 1k 10k 100k 1M 10M

–60 FREQUENCY (Hz)

–70
Figure 47. Digital Filter Response for Oversampling by 16
AVCC = VDRIVE = 5V
T = 25°C
–80 A
±10V RANGE
OS BY 2 0
–90
08096-011

100 1k 10k 100k 1M 10M

–10
FREQUENCY (Hz)
–20
Figure 44. Digital Filter Response for Oversampling by 2

ATTENUATION (dB)
–30

0 –40

–10 –50

–20 –60
ATTENUATION (dB)

–30 –70
AVCC = VDRIVE = 5V
TA = 25°C
–40 –80
±10V RANGE
OS BY 32
–50 –90

08096-015
100 1k 10k 100k 1M 10M
–60 FREQUENCY (Hz)

–70 Figure 48. Digital Filter Response for Oversampling by 32

AVCC = VDRIVE = 5V
T = 25°C
–80 A
±10V RANGE
OS BY 4 0
–90
08096-012

100 1k 10k 100k 1M 10M

–10
FREQUENCY (Hz)
–20
Figure 45. Digital Filter Response for Oversampling by 4
ATTENUATION (dB)

–30

0 –40

–10 –50

–20 –60
ATTENUATION (dB)

–30 –70
AVCC = VDRIVE = 5V
TA = 25°C
–40 –80
±10V RANGE
OS BY 64
–50 –90
08096-016

100 1k 10k 100k 1M 10M

–60 FREQUENCY (Hz)

–70 Figure 49. Digital Filter Response for Oversampling by 64

AVCC = VDRIVE = 5V
T = 25°C
–80 A
±10V RANGE
OS BY 8
–90
08096-013

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 46. Digital Filter Response for Oversampling by 8

Rev. D | Page 27 of 32
AD7607 Data Sheet
2000
AVCC = 5V process extends. The actual BUSY high time depends on the over-
1800 VDRIVE = 5V
TA = 25°C sampling rate that is selected: the higher the oversampling rate,
1600 10V RANGE
OS64
the longer the BUSY high or total conversion time (see Table 3).
NUMBER OF OCCURANCES

1400 Figure 51 shows that the conversion time extends as the over-
1200 sampling rate is increased. To achieve the fastest throughput
1000 rate possible when oversampling is turned on, the read can be
800
performed during the BUSY high time. The falling edge of BUSY
is used to update the output data registers with the new conversion
600
data; therefore, the reading of conversion data should not occur on
400 this edge.
200 tCYCLE
0

08096-130
–2 –1 0 1 2 CONVST A tCONV
AND
CODE CONVST B 39µs
Figure 50. Histogram of Codes, Oversampling by 64 19µs

If the OS[2:0] pins are set to select an oversampling ratio of 8, 4µs

for example, the next CONVST x rising edge takes the first sample BUSY OS = 0 OS = 4 OS = 8

for each channel. The remaining seven samples for all channels t4
t4
t4
are taken with an internally generated sampling signal. As the
oversampling ratio is increased, the 3 dB frequency is reduced and CS
the allowed sampling frequency is also reduced (see Table 9). The
OS[2:0] pins should be configured to suit the filtering requirements RD
of the application.

08096-044
DATA:
The CONVST A and CONVST B pins must be tied/driven DB[15:0]

together when oversampling is turned on. When the oversampling Figure 51. No Oversampling, Oversampling by 4, and Oversampling by 8
function is turned on, the BUSY high time for the conversion Using Read After Conversion

Rev. D | Page 28 of 32
Data Sheet AD7607

LAYOUT GUIDELINES
The printed circuit board that houses the AD7607 should be Figure 52 shows the recommended decoupling on the top layer
designed so that the analog and digital sections are separated of the AD7607 board. Figure 53 shows bottom layer decoupling,
and confined to different areas of the board. which is used for the four AVCC pins and the VDRIVE pin.
At least one ground plane should be used. It can be common or
split between the digital and analog sections. In the case of the
split plane, the digital and analog ground planes should be joined
in only one place, preferably as close as possible to the AD7607.
If the AD7607 is in a system where multiple devices require
analog-to-digital ground connections, the connection should
still be made at only one point: a star ground point that should be
established as close as possible to the AD7607. Good connections
should be made to the ground plane. Avoid sharing one connection
for multiple ground pins. Use individual vias or multiple vias to
the ground plane for each ground pin.
Avoid running digital lines under the devices because doing so
couples noise onto the die. The analog ground plane should be

08096-048
allowed to run under the AD7607 to avoid noise coupling. Fast
switching signals like CONVST A, CONVST B, or clocks should Figure 52. Top Layer Decoupling REFIN/REFOUT,
be shielded with digital ground to avoid radiating noise to other REFCAPA, REFCAPB, and REGCAP Pins
sections of the board, and they should never run near analog
signal paths. Avoid crossover of digital and analog signals. Traces
on layers in close proximity on the board should run at right angles
to each other to reduce the effect of feedthrough through the board.
The power supply lines to the AVCC and VDRIVE pins should use
as large a trace as possible to provide low impedance paths and
reduce the effect of glitches on the power supply lines. Where
possible, use supply planes and make good connections between
the AD7607 supply pins and the power tracks on the board.
Use a single via or multiple vias for each supply pin.
Good decoupling is also important in lowering the supply
impedance presented to the AD7607 and in reducing the
magnitude of the supply spikes. The decoupling capacitors should
be placed close to (ideally, right up against) these pins and their
corresponding ground pins. Place the decoupling capacitors for 08096-049

the REFIN/REFOUT pin and the REFCAPA and REFCAPB

pins as close as possible to their respective AD7607 pins; and, Figure 53. Bottom Layer Decoupling
where possible, they should be placed on the same side of the
board as the AD7607 device.

Rev. D | Page 29 of 32
AD7607 Data Sheet
To ensure good device-to-device performance matching in AVCC
a system that contains multiple AD7607 devices, a symmetrical
layout between the devices is important.
Figure 54 shows a layout with two AD7607 devices. The AVCC
supply plane runs to the right of both devices. The VDRIVE supply
U2
track runs to the left of the two AD7607 devices. The reference
chip is positioned between the two AD7607 devices, and the
reference voltage track runs north to Pin 42 of U1 and south to
Pin 42 of U2. A solid ground plane is used. These symmetrical
layout principles can also be applied to a system that contains
more than two AD7607 devices. The AD7607 devices can be
placed in a north-south direction with the reference voltage
located midway between the AD7607 devices and the reference
track running in the north-south direction, similar to Figure 54.

U1

08096-050
Figure 54. Layout for Multiple AD7607 Devices—Top Layer and
Supply Plane Layer

Rev. D | Page 30 of 32
Data Sheet AD7607

OUTLINE DIMENSIONS
12.20
0.75 12.00 SQ
0.60 1.60 11.80
0.45 MAX
64 49
1 48

PIN 1

10.20
TOP VIEW 10.00 SQ
(PINS DOWN)
9.80
1.45
0.20
1.40
0.09
1.35
7°
3.5°
0.15 16 33
0°
0.05 SEATING 17 32
PLANE 0.08
COPLANARITY VIEW A 0.27
0.50
BSC 0.22
VIEW A LEAD PITCH 0.17
ROTATED 90° CCW

051706-A
COMPLIANT TO JEDEC STANDARDS MS-026-BCD

Figure 55. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD7607BSTZ −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2
AD7607BSTZ-RL −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2
EVAL-AD7607SDZ −40°C to +85°C Evaluation Board
EVAL-SDP-CB1Z Evaluation Controller Board
1
Z = RoHS Compliant Part.

Rev. D | Page 31 of 32
AD7607 Data Sheet

NOTES

©2010–2018 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D08096-0-5/18(D)

Rev. D | Page 32 of 32